M34280M1-155GP

M34280M1 MITSUBISHI | Alldatasheet

Document overview

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Technical content

(× 4 bits) 32 words 32 words 32 words 32 words PIN CONFIGURATION (TOP VIEW) M34280M1-XXXFP/GP ROM (PROM) size (× 9 bits) 1024 words 1024 words 1024 words 1024 words Product M34280M1-XXXFP M34280M1-XXXGP M34280E1FP M34280E1GP

DESCRIPTION

The 4280 Group is a 4-bit single-chip microcomputer designed with CMOS technology for remote control transmitters. The 4280 Group has 7 carrier waves and enables fabrication of 8 × 7 key matrix.

FEATURES

µs (at f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD =3.0 V)

Timer with a reload register and carrier wave output auto-control function
Carrier wave output function (port CARR) f(X IN), f(XIN)/4, f(XIN)/8, f(XIN)/12 f(XIN)/64, f(XIN)/96, “H” output fixed
Logic operation function (XOR, OR, AND)
RAM back-up function
Key-on wakeup function (ports D
Watchdog timer
Power-on reset circuit APPLICATION Various remote control transmitters

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS VSS D D 2 D 3 D 4 D 5 D 1 D 0 CARR VDD D 6 G 3 G 2 XIN XOUT G 0 G 1 M34280M1-XXXFP/GP Outline 20P2N-A 20P2E/F-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS BLOCK DIAGRAM XIN–XOUT 142 71 I/O port Internal peripheral functions Timer System clock generating circuit Remote control carrier wave output Memory ROM (Note) 1024 words · 9 bits RAM 32 words · 4 bits

720 Series

ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (4 levels) Port E Port G Port D Timer 1 (8 bits) Note: PROM 1024 words · 9 bits

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PERFORMANCE OVERVIEW Function 8.0 µs (at 4.0 MHz system clock frequency) (f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) 1024 words 5 9 bits 32 words 5 4 bits Seven independent output ports 1-bit I/O port with the pull-down function 3-bit input port with the pull-down function 2-bit output port (E0, E1) 4-bit I/O port with the pull-down function 1-bit output port; CMOS output 8-bit timer with a reload register 4 levels (However, only 3 levels can be used when the TABP p instruction is executed) CMOS silicon gate 20-pin plastic molded SOP (20P2N-A)/SSOP (20P2E/F-A) –20 °C to 85 °C 1.8 V to 3.6 V 400 µA (f(X IN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V) 0.1 µA (at room temperature, VDD = 3 V) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timer 1 Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 6 D 7 E0–E2 E0, E1 G 0–G 3 CARR Active mode RAM back-up mode M34280M1/ Output I/O Input Output I/O Output PIN DESCRIPTION Name Power supply Ground System clock input System clock output Output port D I/O port D I/O port E I/O port G Carrier wave output for remote control Input/Output Input Output Output I/O Output Input I/O Output Function Connected to a plus power supply. Connected to a 0 V power supply. I/O pins of the system clock generating circuit. Connect a ceramic resonator between pins X IN and XOUT . The feedback resistor is built-in between pins XIN and XOUT . Each pin of port D has an independent 1-bit wide output function. The output structure is P-channel open-drain. 1-bit I/O port. For input use, turn on the built-in pull-down transistor and set the latch of the specified bit to “0.” In addition, key-on wakeup function using “H” level sense becomes valid. The output structure is P-channel open-drain. 2-bit (E 0, E1) output port. The output structure is P-channel open-drain. 3-bit input port. For input use (E0, E1), turn on the built-in pull-down transistor and set the latch of the specified bit to “0.” In addition, key-on wakeup function using “H” level sense becomes valid. Port E2 has an input-only port and has a key-on wakeup function using “H” level sense and pull-down transistor. 4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure is P-channel open-drain. Port G has a key-on wakeup function using “H” level sense and pull-down transistor. Carrier wave output pin for remote control. The output structure is CMOS circuit. Pin VDD VSS XIN XOUT D 0–D 6 D 7 E0–E2 G 0–G 3 CARR

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CONNECTIONS OF UNUSED PINS Pin D 0–D 7 E 0, E1 E 2 G 0–G 3 Connection Open or connect to VDD pin (Note 1). Set the output latch to “1” and open, or connect to VDD pin (Note 2). Open or connect to VSS pin. Set the output latch to “0” and open, or connect to VSS pin. Notes 1: Port D7: Set the bit 2 (PU02) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. 2: Set the corresponding bits (PU00, PU01) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF. (Note in order to set the output latch to “0” to make pins open)

After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD )
Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise. PORT FUNCTION Control bits 1 bit Output: 2 bits Input: 3 bits 4 bits 1 bit Control instructions SD RD CLD SD RD CLD SZD OEA IAE IAE OGA IAG OCRA Control registers PU0 PU0 C Output structure P-channel open-drain P-channel open-drain P-channel open-drain CMOS Input/ Output Output (7) I/O (1) I/O (2) Input (1) I/O (4) Output (1) Remark Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function (programmable) Pull-down function and key-on wakeup function Pin D 0–D 6 D 7 G 0–G 3 CARR Port Port D Port E Port G Port CARR DEFINITION OF CLOCK AND CYCLE
System clock (STCK) The system clock is the source clock for controlling this product. It can be selected as shown below whether to use the CCK instruction. CCK instruction When not using When using Instruction clock f(XIN)/32 f(XIN)/4 System clock f(XIN)/8 f(XIN)
Instruction clock (INSTCK) The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling CPU. The one instruction clock cycle is equivalent to one machine cycle.
Machine cycle The machine cycle is the cycle required to execute the instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PORT BLOCK DIAGRAMS CLD instruction SD instruction RD instruction S R Q S R Q PU0 2 Ai Ai D T Q (Note 2) V12 A3 D T Q R V10 CARRY QD T R D T Q PU0 0 D T Q PU0 1 CLD instruction SD instruction RD instruction Register Y Decoder Register Y Decoder (Note 1) (Note 1) (Note 1) (Note 1) Ports D0–D 6 Port D7 (Note 4) Pull-down transistor Port E0 (Note 4) Port E1 (Note 4) Port E2 (Note 4) (Note 1) (Note 1) Pull-down transistor Pull-down transistor Pull-down transistor Pull-down transistor (Note 1) To timer 1 Ports G0–G 3 (Note 4) Port CARR Carrier wave output control signal TCA instructionOCRA instruction Carrier wave output circuit Register A Timer 1 underflow signal Skip decision (SZD instruction) Key-on wakeup input Key-on wakeup input Aj(Note 3) TCA instruction Register C Register ATAC instruction OEA instruction IAE instruction Register A Register A Key-on wakeup input Key-on wakeup input Register A OEA instruction IAE instruction IAE instruction Register A Key-on wakeup input OGA instruction IAG instruction Notes 1: This symbol represents a parasitic diode. i represents bits 0 to 3. j represents bits 0 to 2. Applied voltage must be less than V DD . Aj(Note 3) Register A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). A3 A2 A1 A0B3 B2 B1 B0 ER 7ER 6ER 5ER 4ER 3ER 2ER 1ER 0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Fig. 4 TABP p instruction execution example Specifying address p3 p2 p1 p0 PC H DR 2 DR 1 DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D The contents of register A ROM 8 40 TABP p instruction Low-order 4 bits Middle-order 4 bits Most significant 1 bit URS flag (1) URSC instruction Register A (4) Register B (4) Carry flag CY (1)

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f or INFRARED REMO TE CONTROL TRANSMITTERS Fig. 5Stack registers (SKs) structure Fig. 6Example of operation at subroutine call SK 0 SK 1 SK 2 SK 3 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 Program counter (PC) Executing RT instruction Executing BM instruction Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. (SP) 0 (SK0) 000116 (PC) SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) (SK0) (SP) 3 Note: (5) Most significant ROM code reference enable flag (URS) URS flag controls whether to refer to the contents of the most significant 1 bit (bit 8) of ROM code when executing the TABP p instruction. If URS flag is “0,” the contents of the most significant 1 bit of ROM code is not referred even when executing the TABP p instruction. However, if URS flag is “1,” the contents of the most significant 1 bit of ROM code is set to flag CY when executing the TABP p instruction (Figure 4). URS flag is “0” after system is released from reset and returned from RAM back-up mode. It can be set to “1” with the URSC instruction, but cannot be cleared to “0.” (6) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

performing a subroutine call, or
executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used when executing a table reference instruction. Accordingly, be careful not to over the stack. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. Note : The 4280 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter (PC) PC H Specifying page PC L Specifying address X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register X (2) Register Y (4)Specifying RAM digit Specifying RAM file (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). 0 1 01 D 5D 7 D 0 Specifying bit position Set Register Y (4) Port D output latch

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 10 ROM map of M34280M1 PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 ROM size and pages Fig. 11 RAM map Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern of all addresses can be used as data areas with the TABP p instruction. DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Product M34280M1 M34280E1 ROM size (5 9 bits) 1024 words Pages 8 (0 to 7) Product M34280M1 M34280E1 RAM size 32 words 5 4 bits (128 bits) Table 2 RAM size Register Y Register X 0 1 RAM 32 words × 4 bits (128 bits) 32 words 087654321 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 03FF16 018016 Page 1 Page 2 Page 0 Page 3 Page 7

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 12 Auto-reload function TIMERS The 4280 Group has the programmable timer.

Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer 1 underflow flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function). FF16 n 0016 n : Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time A skip instruction is executed. Timer 1 underflow flag The contents of counter

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS The 4280 Group timer consists of the following circuit.

Timer 1 : 8-bit programmable timer This timer can be controlled with the timer control register V1. Timer 1 function is described below. Table 3 Function related timer Circuit Timer 1 Structure 8-bit programmable binary down counter Count source
Carrier generating circuit output (CARRY)
Bit 5 of watchdog timer Frequency dividing ratio 1 to 256 Use of output signal
Carrier wave output control Control register Fig. 13 Timers structure XIN INSTCK (Instruction clock) STCK (System clock) INSTCK QS R 130 5 WDF1 WDF2 (Note 1) V10 CARRY V11 (T1AB) (TAB1) T1F D T Q R V10 SNZT1 instruction V12 Timer 1 (8) Reload register R1 (8) (Note 2) Register BRegister A CCK instruction Initializing signal (Note 3) Synchronous circuit Carrier wave output control signal Frequency divider (divided by 4) Frequency divider (divided by 8) WRST instruction Initializing signal (Note 3) Initializing signal(Note 3) 14-bit timer (WDT) System reset Notes 1: Counting is stopped by clearing to “0.” 2: When the T1AB instruction is executed after V1 0 is set to “1,” writing is performed only to reload register R1. 3: The initializing signal is output at reset or RAM back-up mode. : Data is automatically set from a reload register when timer 1 underflows (auto-reload function).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Table 4 Control registers related to timer V12 V11 V10 Timer control register V1 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit at reset : 0002 Wat RAM back-up : 0002 Note: “W” represents write enabled. (4) Timer 1 underflow flag (T1F) Timer 1 underflow flag is set to “1” when the timer 1 underflows. The state of this flag can be examined with the skip instruction (SNZT1). T1F flag is cleared to “0” when the next instruction is skipped with a skip instruction. (1) Control register related to timer

Timer control register V1 Register V1 controls the timer 1 count source and auto- control function of carrier wave output from port CARR by timer 1. Set the contents of this register through register A with the TV1A instruction. (2) Precautions Note the following for the use of timers.
Count source Stop timer 1 counting to change its count source.
Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently.
Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. (3) Timer 1 Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). When timer is stopped, data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. When timer is operating, data can be set to only reload register R1 with the T1AB instruction. When setting the next count data to reload register R1 at operating, set data before timer 1 underflows. Timer 1 starts counting after the following process; À set data in timer 1, \` select the count source with the bit 1 of register V1, and ´ set the bit 0 of register V1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 underflow flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 to registers A and B. When reading the data, stop the counter and then execute the TAB1 instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS WATCHDOG TIMER Watchdog timer provides a method to reset and restart the system when a program runs wild. Watchdog timer consists of 14-bit timer (WDT) and watchdog timer flags (WDF1, WDF2). Watchdog timer downcounts the instruction clock (INSTCK) as the count source. When the timer WDT count value becomes 0000 16 and underflow occurs, the WDF1 flag is set to “1.” Then, when the WRST instruction is not executed before the timer WDT counts 16383, WDF2 flag is set to “1” and internal reset signal is generated and system reset is performed. When using the watchdog timer, execute the WRST instruction at period of 16383 machine cycle or less to keep the microcomputer operation normal. Timer WDT is also used for generation of oscillation stabilization time. When system is returned from reset and from RAM back- up mode by key-input, software starts after the stabilization oscillation time until timer WDT downcounts to 3E00 16 elapses. Fig. 14 Watchdog timer function 3E0016 0000 16 3FFF 16 Value of timer WDT WDF1 flag WDF2 flag Internal reset signal “1” “0” “1” “0” “H” “L” System reset Return POF instruction execution WRST instruction execution System reset Software start Software start Software start

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CARRIER GENERATING CIRCUIT The 4280 Group can output the various carrier waveforms by the carrier wave selection register C. Set the contents of this register through register A with the TCA instruction. The TAC instruction can be used to transfer the contents of register C to register A. When the TCA instruction is executed, the output latch of port CARR is cleared to “0.” The carrier waveform selected by setting register C can be output from port CARR by setting port CARR output latch to “1.” When the CARR output latch is cleared to “0,” carrier wave output is stopped and port CARR output is fixed to “L” level. The CARR output latch can be set through bit 3 (A 3) of register A with the OCRA instruction. The relationship between the setting value of register C and selected waveform is described below. Also, timer 1 can auto-control the carrier wave output from port CARR by setting the timer control register V1. Fig. 15 Carrier wave selection register No carrier wave C 2 OCRA LA 0LA 8 OCRA (TCA) f(XIN)/4 1/2 (Note) Carrier wave selection register C (at reset: 1112, at RAM back-up: 1112) Register C setting value C 1 C 0 “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” “H” “L” Output waveform Carrier wave Frequency Duty System clock/ System clock/ System clock “L” level fixed Note: This carrier wave can be used only when system clock f(X IN)/8 is selected. The carrier wave output is fixed to “L” level when system clock f(XIN) is selected.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LOGIC OPERATION FUNCTION The 4280 Group has the 4-bit logic operation function. The logic operation between the contents of register A and the low-order 4 bits of register E is performed and its result is stored in register Each logic operation can be selected by setting logic operation selection register LO. Set the contents of this register through register A with the TLOA instruction. The logic operation selected by register LO is executed with the LGOP instruction. Table 5 shows the logic operation selection register LO. Table 5 Logic operation selection register LO at reset : 002 at RAM back-up : 002 W LO 1 LO 0 LO 1 LO 0 Logic operation selection bits Logic operation selection register LO Logic operation function Exclusive logic OR operation (XOR) OR operation (OR) AND operation (AND) Not available Fig. 16 Port CARR output auto-control by timer 1 Note: “W” represents write enabled. a b c d (V11)← 0 CARRY a b cd Timer 1 start Timer 1 underflow Port CARR output “1” “0” “H” “L” Set the interval “a” to timer 1. Select count source CARRY Set the interval “b” to reload register R1. Set the interval “c” to reload register R1. Set the interval “d” to reload register R1. Carrier wave output start Timer 1 underflow Port CARR output “1” “0” “H” “L” “1” “0”Register V12 Carrier wave output start (V12)← 1 (V10)← 1 Auto-control valid “H” “L” Auto-control invalid Auto-control invalid Carrier wave output stop (Note) Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1. Timer 1 stop (V10)← 0

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 17 Reset release timing RESET FUNCTION The 4280 Group has the power-on reset circuit, though it does not have RESET pin. System reset is performed automatically at power-on, and software starts program from address 0 in page In order to make the built-in power-on reset circuit operate efficiently, set the voltage rising time until V DD = 0 to 2.2 V is obtained at power-on 1ms or less. Fig. 18 Power-on reset circuit example VDD Internal reset signal Power-on reset circuit Voltage drop detection circuit Watchdog timer output Power-on reset circuit output voltage Reset state Internal reset signal Reset released Power-on f(XIN) f(XIN) 16384 pulses Internal reset signal “H” “L” Software starts (address 0 in page 0)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (1) Internal state at reset Table 6 shows port state at reset, and Figure 19 shows internal state at reset (they are retained after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 19 are undefined, so set the initial value to them. Address 0 in page 0 is set to program counter.

Most significant ROM code reference enable flag (URS) 0000000000 000 111 000 1111 1111 Fig. 19 Internal state at reset Table 6 Port state at reset Name D 0–D 6 D 7 G 0–G 3, E2 E0, E1 State at reset “H” output “H” output Input port (Pull-down transistor ON) Input circuit OFF (Pull-down transistor OFF) State after system is released from reset High impedance state Input circuit OFF (Pull-down transistor OFF) Input port (Pull-down transistor ON) Input port (Pull-down transistor OFF) Note: The contents of all output latch is initialized to “0.” VOLTAGE DROP DETECTION CIRCUIT The built-in drop detection circuit is designed to detect a drop in voltage at operating and to reset the microcomputer if the supply voltage drops below the specified value (Typ. 1.50 V) or less. Fig. 20 Voltage drop detection circuit operation waveform VDD Reset voltage Internal reset signal Microcomputer starts operation after f(XIN) is counted to 16384 times. The voltage drop detection circuit is stopped and power dissipation is reduced at the RAM back-up mode, when the functions except the RAM and pull-down control register (PU0) are initialized.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS RAM BACK-UP MODE The 4280 Group has the RAM back-up mode. When the POF instruction is executed, system enters the RAM back-up state. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, power dissipation can be reduced without losing the contents of RAM. Table 7 shows the function and states retained at RAM back-up. Figure 21 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the software from address 0 in page 0 when any of the following conditions is satisfied .

reset by power-on reset circuit is performed
reset by watchdog timer is performed
reset by voltage drop detection circuit is performed In this case, the P flag is “0.” Table 7 Functions and states retained at RAM back-up RAM back-up O 5 (“H” output) 5 (“H” output) 5 (input) 5 (input cut-off) 5 (input) 5 (input cut-off) 5 (input) 5 (input) O Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Ports D 0–D 6 (Note 3) Port D7 Port E0 Port E1 Port G Timer control register V1 Pull-down control register PU0 Logic operation selection register LO Timer 1 function Timer 1 underflow flag (T1F) Watchdog timer (WDT) Watchdog timer flag 1 (WDF1) Watchdog timer flag 2 (WDF2) Most significant ROM code reference enable flag (URS) (PU02)=0 (Note 3) (PU02)=1 (PU00)=0 (Note 4) (PU00)=1 (PU01)=0 (Note 4) (PU01)=1 Notes 1: “O” represents that the function can be retained, and “5 ” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to “11 2” at RAM back-up. 3: The contents of port output latch is initialized to “0.” However, port continues to output “H” level. 4: The state of this bit is equal to the state at reset.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 8 shows the return condition for each return source. Remarks Only key-on wakeup function of the port whose pull-down transistor is turned ON is valid. Key-on wakeup function is always valid. Return source Ports D7, E0, E1 Ports G, E2 Return condition Return by an external “H” level input. Return by an external “H” level input. Table 8 Return source and return condition (5) Pull-down control register PU0

Pull-down control register PU0 Register PU0 controls the ON/OFF of pull-down transistor, input, key-on wakeup function of ports E 0, E1 and D7. Table 9 Pull-down control register PU0 2 PU0 1 PU0 0 Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid Pull-down transistor ON, input circuit ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Port D 7 pull-down control bit Port E1 pull-down control bit Port E0 pull-down control bit Pull-down control register PU0 at reset : 000 2 at RAM back-up : state retained W Note: “W” represents write enabled. Fig. 21 State transition Fig. 22 Set source and clear source of the P flag Fig. 23 Start condition identified example using the SNZP instruction S R Q Power down flag P POF instruction Reset input l Set source POF instruction is executed l Clear source Reset input Software start P = “1” Yes Warm startCold start No Set the contents of this register through register A with the TPU0A instruction. : Microcomputer starts its operation after f(XIN) is counted to16384 times.Stabilizing time a POF instruction is executed A f(XIN) oscillationReturn input B (RAM back-up mode) f(XIN) stop Reset (Stabilizing time a ) (Stabilizing time a )

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 24 Clock control circuit structure Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and XOUT at the shortest distance as shown Figure 26. A feedback resistor is built-in between X IN pin and XOUT pin. ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (three sets containing the identical data) Fig. 25 Ceramic resonator external circuit CLOCK CONTROL The clock control circuit consists of the following circuits.

System clock generating circuit
Control circuit to stop the clock oscillation
Control circuit to return from the RAM back-up state OSC R S Q POF instruction XIN XOUT CCK instruction STCK INSTCK Frequency divider (divided by 8)Multi- plexer Internal clock generating circuit (divided by 4) Internal power-on reset circuit Pull-down control register PU0 Port D Ports E0, E1 Ports E2, G0–G 3 4280 XIN XOUT C IN C OUT Use the resonator manufacturer’s recommended value because constants such as capacitance depend on the resonator.

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f or INFRARED REMO TE CONTROL TRANSMITTERS LIST OF PRECAUTIONS À Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

connect a bypass capacitor (approx. 0.01 µF) between pins V DD and VSS at the shortest distance,
equalize its wiring in width and length, and
use the thickest wire. In the One Time PROM version, port E2 is also used as VPP pin. Connect this pin to VSS through the resistor about 5 kΩ which is assigned to E2/VPP pin as close as possible at the shortest distance. \` Notes on unused pins (Note in order to set the output latch to “0” to make pins open)
After system is released from reset, a port is in a high- impedance state until the output latch of the port is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to VSS and VDD )
Connect the unused pins to VSS and VDD at the shortest distance and use the thick wire against noise. ´ Timer
Count source Stop timer 1 counting to change its count source.
Watchdog timer Be sure that the timing to execute the WRST instruction in order to operate WDT efficiently.
Writing to reload register R1 When writing data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. ˆ Program counter Make sure that the program counter does not specify after the last page of the built-in ROM.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR ER C PU0 LO X Y DP PC PC H PC L SK SP CY T1F WDT WDF1 WDF2 URS P STCK INSTCK

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Carrier wave selection register C (3 bits) Timer control register V1 (3 bits) Pull-down control register PU0 (3 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (10 bits) High-order 3 bits of program counter Low-order 7 bits of program counter Stack register (10 bits 5 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 underflow flag Watchdog timer Watchdog timer flag 1 Watchdog timer flag 2 Most significant ROM code reference enable flag Power down flag System clock Instruction clock Port D (8 bits) Port E (3 bits) Port G (4 bits) Port CARR (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p3 p2 p1 p0 Hex. number C + Hex. number x (also same for others) Symbol D E G CARR x y p n j A 3A 2A1A0 ( ) M(DP) a p, a C x Note :The 4280 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Function (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p=0 to 7 (PC L) ← (DR 2–DR 0, A 3–A0) When URS=0 (B) ← (ROM(PC)) 7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1 (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A 1A 0 Logic operation instruction XOR, OR, AND (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 LIST OF INSTRUCTION FUNCTION Arithmetic operation Register to register transfer GroupingMnemonic TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY TAM j XAM j XAMD j XAMI j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER 7–ER 4) ← (B) (ER3–ER 0) ← (A) (B) ← (ER7–ER 4) (A) ← (ER3–ER 0) (DR 2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 GroupingMnemonic LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP SB j RB j SZB j RAM to register transfer RAM addresses Comparison operation GroupingMnemonic SEAM SEA n B a BL p, a BA a BLA p, a BM a BML p, a BMLA p, a RT RTS Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCL) ← (a6–a4, A 3–A0) (PCH ) ← p (PCL) ← (a6–a4, A 3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p= 0 to 7 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p p= 0 to 7 (PCL) ← (a6–a4, A 3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Subroutine operationReturn operation Branch operation Bit operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LIST OF INSTRUCTION FUNCTION (CONTINUED) GroupingMnemonic TV1A TAB1 T1AB SNZ1 TCA TAC OCRA CLD RD SD SZD OEA IAE OGA IAG Function (V1 2–V1 0) ← (A2–A0) (B) ← (T17–T14) (A) ← (T13–T10) at timer 1 stop (V10=0): (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) at timer 1 operating: (V10=1) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (C2–C 0) ← (A2–A0) (CARR) ← 0 (CARR) ← (A3) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 7 (A2–A 0) ← (E2–E0) (G) ← (A) (A) ← (G) Timer operationInput/Output operation GroupingMnemonic NOP POF SNZP CCK TLOA URSC TPU0A WRST Function (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU0 2–PU0 0) ← (A2–A0) (WDF1) ← 0 Other operation Carrier wave control operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS INSTRUCTION CODE TABLE D 3– D 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F XAM D 8–D 4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10000 11000 10111 11111 10–17 NOP RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY TEAB CMA RAR TAB TAY SZB SZB SZB SZB SEAn SEAM TDA TABE SZC RT RTS RB RB RB RB IAE SB SB SB SB TABP TABP TABP TABP OEA BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BA BL BL BL BL TAC TCA BMLA XAM XAM XAM TAM TAM TAM TAM XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD BML BML BML BML A LA A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 18–1F LXY 0,0 LXY 1,0 LXY 2,0 LXY 0,1 LXY 1,1 LXY 2,1 LXY 0,2 LXY 1,2 LXY 2,2 LXY 0,3 LXY 1,3 LXY 2,3 LXY 0,4 LXY 1,4 LXY 2,4 LXY 0,5 LXY 1,5 LXY 2,5 LXY 0,6 LXY 1,6 LXY 2,6 LXY 0,7 LXY 1,7 LXY 2,7 SNZP OGA IAG OCRA POF LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 CCK TPU0A LXY 0,8 LXY 1,8 LXY 2,8 LXY 0,9 LXY 1,9 LXY 2,9 LXY 0,10 LXY 1,10 LXY 2,10 LXY 011 LXY 1,11 LXY 2,11 LXY 0,12 LXY 1,12 LXY 2,12 LXY 0,13 LXY 1,13 LXY 2,13 LXY 0,14 LXY 1,14 LXY 2,14 LXY 0,15 LXY 1,15 LXY 2,15 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15 TABP TABP TABP TABP 7BL BL BL BL BML BML BML BML LGOP SZD SNZT1 TV1A WRST BL BML BLA BMLA SEA 1 1 a a a a a a a 1 0 a a a a a a a 1 1 a a a 0 p p p 1 0 a a a 0 p p p 0 1 0 1 1 n n n n BA 1 1 a a a a a a a 0 0 0 1 0 1 0 1 1 SZD TLOA T1AB TAB1 URSC Hex. notation The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D8–D 4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. The codes for the second word of a two-word instruction are described below. Do not use the code marked “–.” The second word

Skip conditionDetailed description Carry flag CY MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC 27 26 Instruction code Function MnemonicHexadecimal notation Number of words Number of cycles Parameter Type of instructions D8D7D6D5D4D3D2D1D0 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (ER7–ER4) ← (B) (ER3–ER0) ← (A) (B) ← (ER7–ER4) (A) ← (ER3–ER0) (DR2–DR0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY TAM j XAM j XAMD j XAMI j Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Continuous (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0 Register to register transfer 01 E 00 E 01 F 00 C 01 A 02 A 02 9 0Cy 01 3 017 06 4 06 j 06 C 06 8 RAM addresses 000011110 000001110 000011111 000001100 000011010 000101010 000101001 011x 1x0y3y2y1y0 000010011 000010111 0011001j1j0 0011000j1j0 0011011j1j0 0011010j1j0 MACHINE INSTRUCTIONS RAM to register transfer

Skip conditionDetailed description Carry flag CY MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC 29 28 Instruction code Function MnemonicHexadecimal notation Number of words Number of cycles Parameter Type of instructions D8D7D6D5D4D3D2D1D0 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP (A) ← n n = 0 to 15 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H) ← p, p=0 to 7 (PCL) ← (DR2–DR0, A3–A0) When URS=0, (B) ← (ROM(PC)) 7 to 4 (A) ← (ROM(PC))3 to 0 When URS=1, (CY) ← (ROM(PC))8 (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1 (PC) ← (SK(SP)) (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A3A2A1A0 Logic operation instruction XOR, OR, AND Continuous Overflow = 0 (CY) = 0 Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits 7 to 0 are the ROM pattern in address (DR

2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in

page p. When this instruction is executed, 1 stage of stack register is used. Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC instruction is executed). One of stack is used when the TABP p instruction is executed. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one‘s complement for register A‘s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Execute the logic operation selected by logic operation selection register LO between the contents of register A and register E, and stores the result in register A. Arithmetic operation 0B n 09 p 00 A 00 B 0A n 00 7 00 6 02 F 01 C 01 D 04 1 01011n 3n2n1n0 010010p2p1p0 000001010 000001011 01010n 3n2n1n0 000000111 000000110 000101111 000011100 000011101 001000001 MACHINE INSTRUCTIONS (CONTINUED)

Skip conditionDetailed description Carry flag CY MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC 31 30 Instruction code Function MnemonicHexadecimal notation Number of words Number of cycles Parameter Type of instructions D8D7D6D5D4D3D2D1D0 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch within a page : Branches to address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a in the identical page with register A. Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a in page p with register A. SB j RB j SZB j SEAM SEA n B a BL p, a BA a BLA p, a (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH) ← p (PCL) ← a6–a0 (Note) (PCL) ← (a6–a4, A3–A0) (PCH) ← p (PCL) ← (a6–a4, A3–A0) (Note) (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15 0010111j 1j0 0010011j1j0 0001000j1j0 000100110 000100101 01011n3n2n1n0 11a6a5a4a3a2a1a0 00011p3p2p1p0 11a6a5a4a3a2a1a0 000000001 11a 6a5a4a3a2a1a0 000010000 11a 6a5a4p3p2p1p0 05 C 04 C 02 j 02 6 02 5 0B n 18 a 03 p 18 a 00 1 18 a 01 0 18 p Bit operationComparison operation Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1. Branch operation MACHINE INSTRUCTIONS (CONTINUED)

Skip conditionDetailed description Carry flag CY MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC 33 32 Instruction code Function MnemonicHexadecimal notation Number of words Number of cycles Parameter Type of instructions D8D7D6D5D4D3D2D1D0 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS BM a BML p, a BMLA p, a RT RTS TAB1 T1AB TV1A SNZ1 TAC TCA OCRA 1a a 07 p 1aa 05 0 1a p 04 4 04 5 057 047 05B 042 040 05A 086 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H) ← 2 (PCL) ← a6–a0 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← a6–a0 (Note) (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH) ← p (PCL) ← (a6–a4, A3–A0) (Note) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (B) ← (T17–T14) (A) ← (T13–T10) at timer 1 stop (V10=0) at timer 1 operating (V10=1) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 (A2–A0) ← (C2–C0) (C2–C0) ← (A2–A0), (CARR) ← 0 (CARR) ← (A3) Skip at uncondition (T1F) = 1 Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a in page p with register A. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Transfers the contents of timer 1 to registers A and B. Transfers the contents of registers A and B to timer 1. Transfers the contents of register A to registers V1. Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. Transfers the contents of register A to register C. Transfers the contents of register C to register A. In this case, port CARR output latch is cleared to “0.” Transfers the contents of bit 3 (A 3) of register A to port CARR output latch. 10a6a5a4a3a2a1a0 00111p3p2p1p0 10a6a5a4a3a2a1a0 001010000 10a6a5a4p3p2p1p0 001000100 001000101 001010111 001000111 001011011 001000010 001000000 001011010 010000110 Subroutine operationReturn operation MACHINE INSTRUCTIONS (CONTINUED) Note : p is 0 to 7 for M34280E1, and p is 0 to 7 for M34280M1. Timer operationCarrier wave control operation

Skip conditionDetailed description Carry flag CY MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC 35 34 Instruction code Function MnemonicHexadecimal notation Number of words Number of cycles Parameter Type of instructions D8D7D6D5D4D3D2D1D0 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS MACHINE INSTRUCTIONS (CONTINUED) Input/Output operation 011 014 015 024 02B 084 056 080 028 00 0 00 D 00 3 05 9 05 8 08 2 08 F 00 F CLD RD SD SZD OEA IAE OGA IAG NOP POF SNZP CCK TLOA URSC TPU0A WRST 000010001 000010100 000010101 000100100 000101011 010000100 001010110 010000000 000101000 000000000 000001101 000000011 001011001 001011000 010000010 010001111 000001111 (D) ← 0 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 7 1, E0) ← (A1, A0) (A2–A0) ← (E2–E0) (G) ← (A) (A) ← (G) (PC) ← (PC) + 1 RAM back-up (P) = 1 ? STCK changes to f(XIN) (LO1, LO0) ← (A1, A0) (URS) ← 1 (PU02–PU00) ← (A2–A0) (WDF1) ← 0 (D(Y)) = 0 (Y) = 7 (P) = 1 Clears (0) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y (high-impedance state). Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is “0.” Outputs the contents of register A to port E. Transfers the contents of port E to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A. No operation Puts the system in RAM back-up state. Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. System clock (STCK) changes to f(X IN) from f(XIN)/8. Execute this CCK instruction at address 0 in page Transfers the contents of register A to the logic operation selection register LO. Sets the most significant ROM code reference enable flag (URS) to “1.” Transfers the contents of register A to register PU0. Initializes the watchdog timer flag (WDF1). Other operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS CONTROL REGISTERS V12 V11 V10 Timer control register V1 Auto-control output by timer 1 is invalid Auto-control output by timer 1 is valid Carrier output (CARRY) Bit 5 of watchdog timer (WDT) Stop (Timer 1 state retained) Operating Carrier wave output auto-control bit Timer 1 count source selection bit Timer 1 control bit at reset : 0002 Wat RAM back-up : 0002 PU0 2 PU0 1 PU0 0 Pull-down transistor OFF, input circuit OFF, key-on wakeup invalid Pull-down transistor ON, input circuit ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Pull-down transistor OFF, key-on wakeup invalid Pull-down transistor ON, key-on wakeup valid Port D 7 pull-down control bit Port E1 pull-down control bit Port E0 pull-down control bit Pull-down control register PU0 at reset : 000 2 at RAM back-up : state retained W Carrier wave selection register C at reset : 111 2 at RAM back-up : 1112 R/W C 2 C 1 C Frequency System clock/12 System clock/12 System clock/8 System clock/8 System clock f(X IN)/4 (Note 2) Duty Carrier wave at reset : 002 at RAM back-up : 002 W LO 1 LO 0 LO 1 LO 0 Logic operation selection bits Logic operation selection register LO Logic operation function Exclusive logic OR operation (XOR) OR operation (OR) AND operation (AND) Not available Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: f(X IN) is valid only when f(XIN)/8 is selected as the system clock. No carrier wave “L” level fixed Carrier wave selection bits C 2 C 1 C 0

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Conditions Ta = 25 °C Unit V V V m W Ratings –0.3 to 5 –0.3 to VDD +0.3 –0.3 to VDD +0.3 300 –20 to 85 –40 to 125 Symbol V DD VI VO Pd Topr Tstg RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted) Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage Ports D7, E, G “H” level input voltage XIN “L” level input voltage Ports D7, E, G “L” level input voltage XIN “H” level peak output current Ports D, E1, G “H” level peak output current Port E0 “H” level peak output current CARR “L” level peak output current CARR “H” level average output current Ports D, E1, G “H” level average output current Port E0 “H” level average output current CARR “L” level average output current CARR System clock frequency Voltage drop detection circuit detection voltage Voltage drop detection circuit low voltage determination time Power-on reset circuit valid power source rising time Limits Max. 3.6 3.6 V DD VDD 0.2VDD 0.2VDD –24 –20 –12 –10 500 1.80 1.56 1.2 Typ. 1.50 0.16 Min. 1.8 1.4 0.7VDD 0.8VDD 1.10 1.40 Symbol VDD VRAM VSS VIH VIH VIL VIL IOH (peak) IOH (peak) IOH (peak) IOL(peak) IOH (avg) IOH (avg) IOH (avg) IOL (avg) f(XIN) VDET TDET TPON Unit V V V V V V V mA mA mA mA mA mA mA mA MHz kHz V ms ms when STCK = f(XIN)/8 selected when STCK = f(XIN) selected Note: The average output current ratings are the average current value during 100 ms. Conditions VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V Ceramic resonance Ceramic resonance Ta=25 °C Supply voltage is -10V/s and drops under detected voltage. V DD = 0 to 2.2 V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Parameter “L” level output voltage Port CARR “H” level output voltage Ports D, E1, G “H” level output voltage Port E0 “H” level output voltage CARR “L” level input current Ports D 7, E, G “H” level input current Ports E0, E1 Output current at off-state Ports D, E0, E1 Supply current (when operating) Supply current (at RAM back-up) Pull-down resistor value Ports D7, E, G Feedback resistor value between XIN–X OUT Test conditions IOL = 2 mA IOH = –2 mA IOH = –12 mA IOH = –10 mA V I = VSS V I = VDD Pull-down transistor in off-state V O = VSS f(XIN) = 4.0 MHz f(XIN) = 500 kHz Ta = 25 °C V DD = 3 V, VI = 3 V LimitsSymbol V OL V OH V OH V OH IIL IIH IOZ IDD R PH R OSC Unit V V V V µA µA µA µA µA µA kΩ kΩ Max. 0.9 800 700 0.5 300 3200 Typ. 400 350 0.1 150 Min. 2.1 1.5 1.0 700

ELECTRICAL CHARACTERISTICS

(Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted) BASIC TIMING DIAGRAM STCK Mi Mi+1 D 0–D 7,E0,E1 G 0–G 3 D 7 E0–E2 G 0–G 3 Machine cycle Parameter Pin name System clock Ports D, E0, E1, G output Ports D7, E, G input

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Table 10 Product of built-in PROM version PROM size (5 9 bits) 1024 words 1024 words RAM size (5 4 bits) 32 words 32 words Product M34280E1FP M34280E1GP ROM type One Time PROM [shipped in blank] One Time PROM [shipped in blank] Package 20P2N-A 20P2E/F-A BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4280 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 10 shows the product of built-in PROM version. Figure 26 and 27 show the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. Fig. 26 Pin configuration of built-in PROM version PIN CONFIGURATION (TOP VIEW) VSS D D 2 D 3 D 4 D 5 D 1 D 0 CARR VDD D 6 G 3 G 2 XIN XOUT G 0 G 1 M34280E1FP/GP Outline 20P2N-A 20P2E/F-A

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f or INFRARED REMO TE CONTROL TRANSMITTERS (1) PROM mode (serial input/output) The M34280E1FP/GP has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), SCLK (serial clock input), PGM and VPP to “H” after connecting wires as shown in Figure 1 and powering on the VDD pin, and then applying 12.5V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Refer to the Mitsubishi Data Book “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” about the serial programmer for the Mitsubishi single-chip microcomputers. Fig. 27 Pin configuration of built-in PROM version (continued) SDA SCLK PGM Vpp Vss VDD D 0 D 1 D 2 D 3 VDD CARR D 7 D 6 D 5 D 4 20VSS G 1 G 2 G 3 G 0 XIN XOUT M34280E1FP/GP Outline 20P2N-A : connected to the ceramic resonance circuit Note: The state of disconnected pins are the same as that at reset. 20P2E/F-A PIN CONFIGURATION (TOP VIEW)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Number of transfer In the first transfer, the command code is input. Then, address input or data input/output is performed according to the contents of the command code. Table 11 shows the software command used in the PROM mode. The following explains each software command. (2) Functional outline In the PROM mode, data is transferred with the clock- synchronous serial input/output. The input data is read through the SDA pin into the internal circuit synchronously with the rising edge of the serial clock pulse. The output data is output from the SDA pin synchronously with the falling edge of the serial clock pulse. Data is transferred in units of 8 bits. Table 11 Software command Command Read Program Program verify First command code input 1516 2516 3516 Second Read address L (input) Program address L (input) Program address L (input) Fourth Read data L (output) Program data L (input) Program data L (input) Third Read address H (input) Program address H (input) Program address H (input) Number of transfer Command Read Program Program verify Fifth Read data H (output) Program data H (input) Program data H (input) Seventh Verify data H (output) Sixth Verify data L (output) (3) Read Input the command code 1516 in the first transfer. Proceed and input the low-order 8 bits and the high-order 8 bits of the address and pull the PGM pin to “L.” When this is done, the contents of input address is read and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the low-order 8 bits and high-order 8 bits of read data which have been stored into the data latch, are serially output from the SDA pin. Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). Fig. 28 Timing at reading tCR tRC 10 1 01 00 0 A0 A7 SCLK SDA PGM Read tWR tCH D0 D7 tCH tCH 00 00 00 0 A8 A9 00 00 00 Command code input (1516) Read address input (L) Read address input (H) Read data output (L) Read data output (H)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 30 Timing at program verifying and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. (4) Program Input command code 2516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, Fig. 29 Timing at programming (5) Program verify Input command code 3516 in the first transfer. Proceed and input the low-order 8 bits and high-order 8 bits of the address and the low-order 8 bits and high-order 8 bits of program data, and pull the PGM pin to “L.” When this is done, the program data is programmed to the specified address. Then, when the PGM pin is pulled to “L” again after it is released back to “H,” the address programmed with the program command is read and verified and stored into the internal data latch. When the PGM pin is released back to “H” and serial clock is input to the SCLK pin, the verify data that has been stored into the data latch is serially output from the SDA pin. Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit). 10 10 01 00 A0 A7 SCLK SDA PGM tCH D0 D7 tCP tWP tCH tCH 0 000 000 tCH A8 A9 00 00 00 Command code input (2516) Program address input (L) Program address input (H) Program data input (L) Program data input (H) Program 1 0101 1 00 A0 A7 SCLK SDA PGM tCH D0 D7 tCP tWP tCH tCH 0 000 00 0 tCH A8 A9 00 00 00 tCR tRC SCLK SDA PGM tWR D0 D7 D8 tCH 00 00 00 0 Command code input (3516) Program address input (L) Program address input (H) Program data input (L) Program data input (H) Program Verify data output (L) Verify data output (H) Verify

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PROGRAM ALGORITHM FLOW CHART START VDD = 4V,VPP = 12.5V ADRS = first location X=0 WRITE PROGRAM DATA X = X + 1 PROGRAM ONE PULSE OF 0.2ms X = 25? VERIFY BYTE? YES NO FAIL PASS LAST ADRS? NO YES READ COMMAND DEVICE PASSED VERIFY BYTE? PASS FAIL DEVICE FAILED INC ADRS 3516 DIN WRITE PROGRAM-VERIFY COMMAND VERIFY ALL BYTE? FAIL PASS 1516 PROGRAM PULSE OF 0.2Xms DURATION WRITE PROGRAM COMMAND 2516 WRITE PROGRAM DATA DIN VDD = 4V,VPP = 4V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS (Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V) Max. 0.21 5.25 180 TIMING DIAGRAM Symbol tCH tCR tWR tRC tCP tWP tOWP tC(CK) tW(CKH) tW(CKL) tr(CK) tf(CK) td(C–Q) th(C–Q) th(C–E) tsu(D–C) th(C–D) Parameter Serial transfer width time Read wait time after transfer Read pulse width Transfer wait time after read Program wait time after transfer Program pulse width Added program pulse width SCLK input cycle time SCLK “H” pulse width SCLK “L” pulse width SCLK rising time SCLK falling time SDA output delay time SDA output hold time SDA output hold time (only for 16th bit) SDA input set-up time SDA input hold time Unit µs µs ns µs µs ms ms µs ns ns ns ns ns ns ns ns ns Min. 2.0 2.0 500 2.0 2.0 0.19 0.19 1.0 450 450 100 180 Limits tC(CK) tW(CKH)tW(CKL) td(C-Q) th(C-E) tf(CK) tr(CK) tsu(D-C) th(C-D) SCLK SDA output SDA input th(C-Q) Measurement condition Output timing voltage: VOL = 0.8 V, VOH = 2.0 V Input timing voltage: VIL = 0.2 VDD , VIH = 0.8 VDD

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Fig. 31 Flow of writing and test of the product shipped in blank Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Note: (6) Notes on handling À A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. \` For the M34280E1FP/GP, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 31 before using is recommended.

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f or INFRARED REMO TE CONTROL TRANSMITTERS GZZ-SH54-86B <91A0>

720 SERIES MASK ROM ORDER CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP MITSUBISHI ELECTRIC Please fill in all items marked . TE L ( ) Company name Date issued Date: Customer Issuance signature Receipt Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor 27C64 27C128 Low-order 8-bit data Most significant bit data 1.00K 1.00K 27C51227C256 Low-order 8-bit data Most significant bit data 1.00K 1.00K Low-order 8-bit data Most significant bit data 1.00K 1.00K Low-order 8-bit data Most significant bit data 1.00K 1.00K 0000 16 03FF 16 1000 16 13FF 16 3FFF 16 0000 16 03FF 16 1000 16 13FF 16 1FFF 16 000016 03FF 16 100016 13FF 16 7FFF 16 000016 03FF 16 100016 13FF 16 FFFF 16 1. Confirmation Specify the name of the product being ordered (check in the approximate box). Three sets of EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by floppy disk. Microcomputer name: M34280M1-XXXFP M34280M1-XXXGP Ordering by the EPROMs Specify the type of EPROMs submitted (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Set “FF16” in the shaded area.

MITSUBISHI MICR OCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f or INFRARED REMO TE CONTROL TRANSMITTERS GZZ-SH54-86B <91A0> SINGLE-CHIP MICROCOMPUTER M34280M1-XXXFP/GP MITSUBISHI ELECTRIC Mask ROM number Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code (hexadecimal notation) Mask file name .MSK (equal or less than eight characters) 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (20P2N-A for M34280M1-XXXFP, 20P2E/F-A for M34280M1-XXXGP) and attach to the Mask ROM Order Confirmation Form. 3. Comments]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS PACKAGE OUTLINE SOP20-P-300-1.27 Weight(g) JEDEC Code 0.26 Cu Alloy 20P2N-A Plastic 20pin 300mil SOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .180 .512 .25 .57 .40 .271 .10 .81 .40 .20 .612 .35 .271 .87 .60 .251 .627 .20 .12 .50 .250 .712 .45 .18 .80 .10 b2 –. 7 6 0– 0° –8 ° e 20 11 101 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail FDetail G z x –Z1 0.585 0.735 0.25 z b x M G SSOP20-P-225-0.65 Weight(g) JEDEC Code 0.08 Alloy 42/Cu Alloy 20P2E/F-A Plastic 20pin 225mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .170 .130 .46 .34 .26 .30 .01 .10 .151 .220 .150 .56 .44 .650 .46 .50 .01 .85 .20 .451 .320 .20 .66 .54 .66 .70 .10 b2 –. 3 5 0– 0° –1 0 ° e 20 11 101 H E E D e y F A A2 A1 L c e b2 Recommended Mount Pad Detail F x –Z1 0.325 0.475 0.13 z G b x M Detail G z

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Customer’s Parts Number Note: The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 13 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 4 : If the Mitsubishi logo is not required, check the box be- low. Mitsubishi logo is not required 20P2N-A (20-PIN SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s Parts Number + Mitsubishi IC Catalog Name Mitsubishi IC catalog name Mitsubishi IC catalog name Note 1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be du- plicated as close as possible. Mitsubishi lot number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special logo required 20 11 101 Mitsubishi lot number (6-digit or 7-digit) 20 11 101 Mask ROM number (3-digit) Mitsubishi lot number (6-digit or 7-digit) Special Mark (Customer’s Trade Mark) Mitsubishi IC catalog name 20 11 101 Mask ROM number (3-digit) Mitsubishi lot number (6-digit or 7-digit)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS Customer’s Parts Number Note: The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Mitsubishi IC catalog name and Mitsubishi lot number Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 4 characters: Only 0 to 9, A to Z, +, -, /, (, ), &, ©, . (period), and , (comma) are usable. 20P2E/F-A (20-PIN SSOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark B. Customer’s Parts Number + Mitsubishi IC Catalog Name Mitsubishi IC catalog name Mitsubishi IC catalog name 20 11 101 Mitsubishi lot number (4-digit or 5-digit) 20 11 101 Mitsubishi lot number (4-digit or 5-digit) ROM number (3-digit)

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Rev. Rev. No. date

1.0 First Edition 980420

2.0 • 20P2E/F-A package added 990611

Figure XA-2: A resistor is added REVISION DESCRIPTION LIST 4280 GROUP DATA SHEET (1/1) Revision Description

Summary

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

Description