M34250M2-086FP

M34250M2 MITSUBISHI | Alldatasheet

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Technical content

SINGLE-CHIP 4-BIT CMOS MICR OCOMPUTER ROM type Mask ROM One Time PROM Package 20P2N-A 20P2N-A RAM size 4 bits) 64 words 64 words *: Shipped after writing (shipped in blank: M34250E2FP) PIN CONFIGURATION (TOP VIEW) M34250M2-XXXFP ROM (PROM) size 9 bits) 2048 words 2048 words Product M34250M2-XXXFP M34250E2-XXXFP * V DD G S S S S D D D D G V SS G OUT G /INT R ESET X IN X OUT CNV SS F F M34250M2-XXXF P Outline 20P2N-A

DESCRIPTION

The 4250 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 720 series using a simple instruction set. The computer is equipped with one 8-bit timer which has a reload register and the interrupt function. The various microcomputers in the 4250 Group include variations of the built-in memory type as shown in the table below.

FEATURES

µ s (at 4.0 MHz system clock frequency, V DD =4.5 V to 5.5 V)

• Supply voltage 4.5 V to 5.5 V (at 4.0 MHz system clock frequency) 2.5 V to 5.5 V (at 1.0 MHz system clock frequency) 2.2 V to 5.5 V (at 1.0 MHz system clock frequency: only for Mask ROM version)
• Timer
• CR oscillation circuit (Capacitor and Resistor connected externally)
• Logic operation instruction
• RAM back-up function
• Key-on wakeup function (ports G and S, INT pin) APPLICATION Electric household appliances, consumer electronics products (mouse, etc.) MITSUBISHI MICROCOMPUTERS

4250 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER RAM (64 words 5 4 bits) ROM (2048 words 5 9 bits) 720 series CPU core Memory I/O port Internal peripheral functions Timer Timer 1 (8 bits) System clock generating circuit XIN -XOUT (Note) Note: PROM 2048 words 5 9 bits Register B (4 bits)Register A (4 bits) Register D (3 bits) Register E (8 bits) Stack register (SK) (4 levels) Interrupt stack register (SDP) (1 level) ALU (4 bits) Port D Port S Port G Port F BLOCK DIAGRAM

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PERFORMANCE OVERVIEW Function 1.0 µs (at 4.0 MHz system clock frequency) (Refer to the electrical characteristics because the minimum instruction execution time depends on the supply voltage.) 2048 words 5 9 bits 64 words 5 4 bits Four independent I/O ports; ports D2 and D3 are also used as ports C and K, respectively. 4-bit I/O port 1-bit I/O port; port C is also used as port D 1-bit I/O port; port K is also used as port D3. 2-bit I/O port 4-bit I/O port; ports G 0 and G1 are also used as pins INT and TOUT . Interrupt input; INT pin is also used as port G0. Timer output; TOUT pin is also used as port G1. 8-bit timer with a reload register 2 (one for external and one for timer) 1 level CR oscillation circuit (a capacitor and a resistor connected externally) Frequency error: ±17 % DD = 5 V ± 10 %, VDD = 3 V ± 10 %, the error of the external capacitor and resistor excluded) 4 levels CMOS silicon gate 20-pin plastic molded SOP (20P2N-A) –20 °C to 85 °C 2.2 V to 5.5 V (Refer to the electrical characteristics because the supply voltage depends on the system clock frequency.) 1.5 mA (at 4.0 MHz system clock frequency, V DD = 5 V, output transistors in the cut-off state) 0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timer Interrupt Oscillation circuit Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 3 S0–S3 C K F 0, F1 G 0–G 3 INT T OUT Timer 1 Sources Nesting Active mode RAM back-up mode M34250M2/ I/O I/O I/O I/O I/O I/O Input Output

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Name Power supply Ground CNV SS Reset input System clock input System clock output I/O port F I/O port G I/O port S I/O port D I/O port C I/O port K Timer output Interrupt input Input/Output Input Input Output I/O I/O I/O I/O I/O I/O Output Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. Reset pulse input pin I/O pins of the system clock generating circuit. Connect pins XIN and XOUT directly. Then, pull up XIN pin through a resistor and pull down XOUT pin through a capacitor. 2-bit I/O port; for input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. 4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports G 0 and G1 are also used as pins INT and TOUT , respectively. 4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function which can be switched by software. Also, it is used to perform the logic operation using register A. Each pin of port D has an independent 1-bit wide I/O function. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports D 2 and D3 are also used as ports C and K, respectively. 1-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Port C has a pull-up function which can be switched by software. It is also used as port D 1-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Port K has a pull-up function which can be switched by software. It is also used as port D TOUT pin has the function to output the timer 1 underflow signal divided by 2. It is also used as port G1. INT pin accepts an external interrupt. It also accepts the input signal to return the system from the RAM back-up state. It is also used as port G0. Pin VDD VSS CNV SS RESET XIN XOUT F0, F1 G 0–G 3 S0–S3 D 0–D 3 C K T OUT INT

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MULTIFUNCTION Pin G 0 G 1 D 2 D 3 Multifunction INT TOUT C K Multifunction G 0 G 1 D 2 D 3 Pin INT (Note 2) TOUT (Note 2) C (Note 2) K (Note 2) Notes 1: Pins except above have just single function. 2: The I/O of ports D2, D3 and G0, and the input of port G1 can be used even when ports C and K and pins INT and TOUT are selected. CONNECTIONS OF UNUSED PINS Pin F0, F1 G 0/INT, G1/TOUT G 2, G3 S0–S3 Connection Connect to VSS pin. Open or connect to VSS pin. (Note 3) Pin D 0, D1 D 2/C, D3/K Connection Connect to VSS pin. Open or connect to VSS pin. (Note 1) Connect to VSS pin. (Note 2) Notes 1: When pins G0/INT, G1/TOUT , G2 and G3 are connected to VSS pin, turn off their pull-up transistors (Pull-up control register PU0=“5 02”) and also invalidate the key-on wakeup functions of pins G1/TOUT , G2 and G3 (Key-on wakeup contorl register K0=“55 05 2”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-on wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately after going into the RAM back-up state. When these pins are open, turn on their pull-up transistors (Pull-up control register PU0=“5 1 2”) by software. 2: When ports S0–S 3 are connected to VSS pin, invalidate the key-on wakeup functions (Key-on wakeup contorl register K0=“555 02”) by software. When the POF instruction is executed while these pins are connected to VSS and the key-on wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately after going into the RAM back-up state. 3: When ports D 2/C and D3/K are connected to VSS pin, turn off their pull-up transistors (register PU0=“05 2”) by software. When these pins are open, turn on their pull-up transistors (register PU0=“15 2”) by software. (Note when connecting to VSS and VDD )

• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT FUNCTION Control bits Control instructions SD RD SZD CLD SCP RCP SNZCP OKA IAK OSA IAS LGOP OGA IAG OFA IAF Control registers PU0 LO PU0, K0 PU0, K0 PU0, K0 Output structure N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain Input/ Output I/O (4) I/O (4) I/O (4) I/O (2) Remark Pull-up function (programmable) Logic operation function (programmable) Key-on wakeup functions (programmable) Pull-up functions Key-on wakeup functions (only pull-up function is programmable) Pull-up functions (programmable) Key-on wakeup functions (programmable) Pin D 0, D1 D 2/C D 3/K S0–S3 G 0/INT G 1/TOUT G 2, G3 F0, F1 Port Port D Port S Port G Port F DEFINITION OF CLOCK AND CYCLE

• System clock This is the source clock input to the XIN pin. Connect pins XIN and XOUT directly. Then, pull up XIN pin through a resistor and pull down XOUT pin through a capacitor.
• Instruction clock The instruction clock is a signal derived by dividing the system clock by 4, and is the basic clock for controlling this product.
• Machine cycle One machine cycle is the time required to execute the minimum instruction (one-cycle instruction). The machine cycle is equivalent to the instruction clock cycle.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (3) Port K 1-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is the N-channel open-drain. The pull-up transistor of port K is turned on when the bit 1 of register PU0 is set to “1” by software. Port K is also used as port D Accordingly, when port D3/K is used as port K, set the port D3 output latch to “1.” (4) Port G (G0–G 3) 4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is the N-channel open-drain. The pull-up transistor of port G is turned on when the bit 0 of register PU0 is set to “1” by software. Ports G 0 and G1 are also used as INT pin and TOUT pin, respectively. Note: “W” represents write enabled. Pull-up control register PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Ports C and K pull-up transistor control bit Ports G 0–G 3 pull-up transistor control bit Pull-up control register PU0 at reset : 00 2 at RAM back-up : state retained W I/O PORT (1) Port D (D0–D 3) Each pin of port D has an independent 1-bit wide I/O function. Each pin has an output latch. For input/output of ports D 0–D 3, select one of port D with the register Y of data pointer first. For input use, set the latch of the specified bit to “1.” All port D output latches can be set to “1” with the CLD instruction. The output structure is the N-channel open-drain. Ports D 2 and D3 are also used as ports C and K, respectively. Accordingly, when port D2/C is used as port D2, set the port C output latch to “1.” When port D3/K is used as port D3, set the port K output latch to “1.” (2) Port C 1-bit I/O port. Port C output latch can be set to “1” with the SCP instruction. Port C output latch can be cleared to “0” with the RCP instruction. Port C input level can be examined by executing the skip (SNZCP) instruction. For input use, set the latch of the specified bit to “1.” The output structure is the N-channel open-drain. The pull-up transistor of port C is turned on when the bit 1 of register PU0 is set to “1” by software. Port C is also used as port D 2. Accordingly, when port D2/C is used as port C, set the port D2 output latch to “1.”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Functions XOR operation OR operation AND operation Not available Logic operation function selection bits Logic operation selection register LO at reset : 00 2 at RAM back-up : 002 LO 1 W LO 0 LO 1 LO 0 Note: “W” represents write enabled. Logic operation selection register (5) Port F (F0, F1) 2-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is the N-channel open-drain. (6) Port S (S 0–S3) 4-bit I/O port. Port S has the logic operation (LGOP) function. For input (logic operation included) use, set the latch of the specified bit to “1.” The output structure is the N-channel open-drain. When performing the logic operation, select the logic operation function with the logic operation selection register LO. Set the contents of register LO through register A with the TLOA instruction. When the LGOP instruction is executed, the logic operation selected with the register LO is performed between the contents of register A and the contents of port S, and its result is stored in register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS D T Q Register A Aj F0, F1 OFA instruction IAF instruction Register A Ai OSA instruction Key-on wakeup input D T Q S0–S3 K00 IAS instruction Ai LGOP instruction LO Register S RQ Skip decision (SZD instruction) D 0, D1 DecoderRegister Y SD instruction RD instruction SCP instruction RCP instruction S RQ S RQ Skip decision (SZD instruction) D 2/C Skip decision (SNZCP instruction) PU0 1 Pull-up transistor DecoderRegister Y SD instruction RD instruction (Note 1) (Note 1) (Note 1) (Note 3) (Note 2) (Note 2) (Note 1) D 3/K D T Q S RQ Skip decision (SZD instruction) OKA instruction IAK instruction Pull-up transistor PU0 1 Register A DecoderRegister Y SD instruction RD instruction (Note 1) This symbol represents a parasitic diode. Applied potential to ports D 0, D1, F0, F1, S0–S3 must be 7V or less. Applied potential to ports D 2, D3 must be VDD or less. i represents 0, 1, 2 or 3. j represents 0 or 1. CLD instruction CLD instruction CLD instruction Logic operator Notes 1:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PORT BLOCK DIAGRAMS (CONTINUED) (Note 1) (Note 1) OGA instruction D T Q IAG instruction Register A PU0 0 G 0/INT Pull-up transistor EXF0 Key-on wakeup input K02 Falling Rising External interrupt OGA instruction D T Q IAG instruction Register A Key-on wakeup input PU0 0 G 1/TOUT Timer 1 underflow signal output 1 V13 K01 This symbol represents a parasitic diode. Notes 1: OGA instruction D T Q IAG instruction Register A Ak Key-on wakeup input PU0 0 G 2, G3 K01 (Note 1) (Note 2) Pull-up transistor Pull-up transistor One-sided edge detection circuit Applied potential to ports G0–G 3 must be VDD or less. k represents 2 or 3.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Fig. 4 TABP p instruction execution example FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Specifying address TABP p instruction p3 p2 p1 p0 PC H DR 2 DR 1 DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 84 0 Middle-order 4 bits Low-order 4 bits Register A (4) Register B (4) The contents of register A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call SK 0 SK 1 SK 2 SK 3 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 Program counter (PC) Executing RT instruction Executing BM instruction Stack pointer (SP) points “3” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after four stack registers are used ((SP) = 3), (SP) = 0 and the contents of SK 0 is destroyed. Returning to the BM instruction execution address with the RT instruction, and the BM instruction is equivalent to the NOP instruction. (SP) 0 (SK0) 000116 (PC) SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) (SK0) (SP) 3 Note: (5) Stack registers (SKs) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p). Stack registers (SKs) are four identical registers, so that subroutines can be nested up to 4 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 4 levels are exceeded. The register SK nesting level is pointed automatically by 2-bit stack pointer (SP). Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag and skip flag just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter (PC) PC H Specifying page PC L Specifying address X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register X (2) Register Y (4)Specifying RAM digit Specifying RAM file 10 0 10 Set Specifying bit position Port D output latchRegister Y (4) D 2D 3 D 1 D 0 (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not exceed after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers X and Y. Register X specifies a file and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 10 ROM map of M34250M2 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Fig. 12 RAM map A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 0100 16 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers X and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Table 2 RAM size Product M34250M2 M34250E2 RAM size 64 words 5 4 bits (256 bits) 087654321 Interrupt address page 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 07FF16 018016 Page 1 Page 2 Page 0 Page 3 Page 15 087654321 External interrupt address Timer 1 interrupt address 008016 008216 00FF16 Register Y Register X RAM 64 words 5 4 bits (256 bits) 64 words PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 9 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34250M2. Table 1 ROM size and pages Product M34250M2 M34250E2 ROM size (5 9 bits) 2048 words Pages 16 (0 to 15)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 4 Interrupt request flag, interrupt enable bit and skip instruction Request flag EXF0 T1F Interrupt name External interrupt Timer 1 interrupt Enable bit V10 V11 Skip instruction SNZ0 SNZ1 Table 5 Interrupt enable bit function Occurrence of interrupt request Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each in- terrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)
• Interrupt enable bit = “1” (interrupt request occurrence enabled)
• Interrupt enable flag (INTE) = “1” (interrupt enabled) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit (V1 0, V11) Use an interrupt enable bit of interrupt control register V1 to select the corresponding interrupt or skip instruc- tion. Table 4 shows the interrupt request flag, interrupt en- able bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is sat- isfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruc- tion. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear con- dition is satisfied. Accordingly, an interrupt occurs when the interrupt dis- able state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Priority level Interrupt name External interrupt Timer 1 interrupt Interrupt address Address 0 in page 1 Address 2 in page 1 Activated condition Level change of INT pin Timer 1 underflow

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

• Stack register (SK)
• Interrupt request flag (only the flag for the current interrupt
• Data pointer, carry flag, skip flag The address of main routine to be executed when returning Fig. 14 Internal state when interrupt occurs T1F V1 1 EXF0 V1 0 Address 2 in page 1 Address 0 in page 1 Request flag (state retained) Enable bit Enable flag Activated condition INT pin (L→ H or H→ L input) Timer 1 underflow EI RTI Interrupt service routine Interrupt occurs Interrupt is enabled Main routine : Interrupt enabled state : Interrupt disabled state (4) Internal state during an interrupt The internal state of the microcomputer during an in- terrupt is as follows (Figure 14).
• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disa- bled.
• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
• Data pointer, carry flag and skip flag The contents of these pointer and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store se- quence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return to main routine. Interrupt enabled by executing the EI instruction is per- formed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI in- struction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing Fig. 15 Interrupt system diagram

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (6) Control register related to interrupt

• Timer control register V1 Interrupt enable bits of external and timer 1 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register (7) Interrupt sequence Interrupts occur only when the respective INTE flag, interrupt enable bits (V10, V11), and interrupt request flags (EXF0, T1F) are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Fig. 16 Interrupt sequence Table 6 Control register related to interrupt V13 V12 V11 V10 Timer control register V1 G 1/TOUT pin function selection bit Prescaler/timer 1 operation start bit Timer 1 interrupt enable bit External interrupt enable bit Port G1 (I/O) TOUT pin (output)/port G1(input) Prescaler stop (initial state) / timer 1 stop (state retained) Prescaler / timer 1 operation Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Note: “R” represents read enabled, and “W” represents write enabled. at reset : 00002 R/Wat RAM back-up : 00002 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 2 to 3 machine cycles (Notes 1, 2) Software starts from the interrupt address.Flag cleared Interrupt enabled state. l When an interrupt request flag is set after its interrupt is enabled f (XIN) EI instruction execution cycleInterrupt enable flag (INTE) Retaining level for 5 cycles or more of f(XIN) is necessary. Interrupt disabled state. EXF0 flag T1F flag G 0/INT pin External interrupt Timer 1 interrupt Interrupt activated condition is satisfied. 1 machine cycle The address is stacked to the last cycle. This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Notes 1:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER EXTERNAL INTERRUPTS The 4250 Group has an external interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the key-on wakeup control register K0. Table 7 External interrupt activated condition Name External interrupt Input pin G 0/INT Valid waveform Falling waveform (“H”→ “L”) Rising waveform (“L”→ “H”) Valid waveform selection bit(K02) Fig. 17 External interrupt circuit structure OGA instruction D T Q IAG instruction Register A PU0 0 G 0/INT pin Pull-up transistor EXF0 Key-on wakeup input K02 Falling Rising External interrupt (Note) This symbol represents a parasitic diode. Note: Applied potential to port G0 must be VDD or less. One-sided edge detection circuit

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER K03 K02 K01 K00 Instruction clock divided by 4 Instruction clock divided by 512 Rising waveform (“L” → “H”) Falling waveform (“H” → “L”) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Prescaler dividing ratio selection bit Interrupt valid waveform for INT pin/ key-on wakeup valid waveform selection bit (Note 2) Ports G 1–G 3 key-on wakeup control bit Ports S0–S3 key-on wakeup control bit Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. (1) External interrupt request flag (EXF0) External interrupt request flag (EXF0) is set to “1” when a valid waveform is input to G0/INT pin. The valid waveforms causing the interrupt must be retained at their level for 5 cycles or more of f(XIN) (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the timer control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

• External interrupt activated condition External interrupt activated condition is satisfied when a valid waveform is input to G 0/INT pin. The valid waveform can be selected from rising waveform or falling waveform. An example of how to use the external interrupt is as follows. À Select the valid waveform with the bit 2 of register K0. \` Clear the EXF0 flag to “0” with the SNZ0 instruction. ´ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ˆ Set both the external interrupt enable bit (V10) and the INTE flag to “1.” The external interrupt is now enabled. Now when a valid waveform is input to the G0/INT pin, the EXF0 flag is set to “1” and the external interrupt occurs. (2) Control register related to external interrupt
• Key-on wakeup control register K0 Register K0 controls the valid waveform for the external interrupt and key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. The TAK0 instruction can be used to transfer the contents of register K0 to register A. Table 8 Control register related to external interrupt

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 18 Auto-reload function FF16 n 0016 n : Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time An interrupt occurs or a skip instruction is executed. Timer 1 interrupt request flag The contents of counter TIMERS The 4250 Group has the programmable timer.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER The 4250 Group timer consists of the following circuits.

• Prescaler : frequency divider
• Timer 1 : 8-bit programmable timer with the interrupt function These timers can be controlled with the timer control register V1 and key-on wakeup control register K0. Each function is described below. Table 9 Function related timers Circuit Prescaler Timer 1 Structure Frequency divider 8-bit programmable binary down counter Count source Instruction clock Prescaler output (ORCLK) Frequency dividing ratio 4, 512 1 to 256 Use of output signal
• Timer 1 count source
• TOUT pin
• Timer 1 interrupt Fig. 19 Timers structure Control register Count source is stopped by clearing to “0.” Data is automatically set from a reload register when timer 1 underflows (auto-reload function). Timer 1 reload register R 1(8) Timer 1 (8) Register B(4) T1F Timer 1 interrupt TAB1 instruction Register A(4) TAB1 instruction Bit 7 Bit 0 V13 G 1 output G 1/TOUT T1ABinstruction G 1 input Instruction clock XIN ORCLK V12 K03 Prescaler V12(Note) Timer 1 underflow signal Internal clock generating circuit (divided by 4) Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Table 10 Control registers related to timer V13 V12 V11 V10 Timer control register V1 Port G1 (I/O) TOUT pin (output)/port G1(input) Prescaler stop (initial state) / timer 1 stop (state retained) Prescaler / timer 1 operation Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) G 1/TOUT pin function selection bit Prescaler/timer 1 operation start bit Timer 1 interrupt enable bit External interrupt enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. at reset : 00002 R/Wat RAM back-up : 00002 K03 K02 K01 K00 Instruction clock divided by 4 Instruction clock divided by 512 Rising waveform (“L” → “H”) Falling waveform (“H” → “L”) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Prescaler dividing ratio selection bit Interrupt valid waveform for INT pin/ key-on wakeup valid waveform selection bit (Note 2) Ports G 1–G 3 key-on wakeup control bit Ports S0–S3 key-on wakeup control bit Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (5) Timer output pin (G1/TOUT ) Timer output pin (G1/TOUT ) has the function to output the timer 1 underflow signal divided by 2. The selection of G1/TOUT pin function can be controlled with the bit 3 of register V1. (6) Timer interrupt request flag (T1F) Timer interrupt request flag is set to “1” when the timer underflows. The state of this flag can be examined with the skip instruction (SNZ1). Use the register V1 to select an interrupt or a skip instruction. T1F flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (1) Control registers related to timer

• Timer control register V1 G 1/TOUT pin function selection bit and prescaler/timer 1 operation start bit are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
• Key-on wakeup control register K0 Prescaler dividing ratio selection bit is assigned to register K0. Set the contents of this register through register A with the TK0A instruction. The TAK0 instruction can be used to transfer the contents of register K0 to register A. (2) Precautions Note the following for the use of timers.
• Prescaler Stop the prescaler operation to change its frequency dividing ratio.
• Reading the count value Stop timer 1 counting and then execute the TAB1 instruction to read its data. (3) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 3 of register K0 to select the prescaler dividing ratio and the bit 2 of register V1 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 2 of register V1 is cleared to “0.” (4) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Timer 1 starts counting after the following process; À set data in timer 1, and \` set the bit 2 of register V1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto- reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 to registers A and B with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from G 1/TOUT pin.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER f(XIN) RESET The number of clock cycles depends on the internal state of the microcomputer when reset is performed. Software starts (address 0 in page 0) 3584 to 3585 machine cycles Fig. 20 Reset release timing Fig. 21 RESET pin input waveform and reset operation RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied;

• the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. Keep the value of supply voltage the minimum value or more of the recommended operating conditions. RESET Software starts (address 0 in page 0) Reset input 1 machine cycle or more 0.1VDD 3584 to 3585 machine cycles (Note) Note : 0.85VDD

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 22 Power-on reset circuit example (2) Internal state at reset Table 11 shows port state at reset, and Figure 23 shows internal state at reset (they are retained after system is released from reset). Table 11 Port state at reset The contents of timers, registers, flags and RAM except shown in Figure 23 are undefined, so set the initial value to them. Name D 0, D1, D2/C, D3/K S0–S3 G 0/INT, G1/TOUT G 2, G3 F0, F1 State High impedance (Note) Function D 0, D1, D2/C, D3/K S0–S3 G 0/INT, G1 G 2, G3 F0, F1 Note: Output latch is set to “1.” (1) Power-on reset Reset can be automatically performed at power on (power-on reset) by connecting a resistor, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance. VDD VDD RESET pin voltage Internal reset signal Power-on RESET pin This symbol represents a parasitic diode. Internal reset signal Reset state Reset released Note: Applied potential to RESET pin must be 7 V or less.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Address 0 in page 0 is set to program counter. 00000000000 0 (Interrupt disabled) 0000 (Interrupt disabled, prescaler/timer 1 stopped) 0000 1111 1111 Fig. 23 Internal state at reset

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Remarks Select the return edge (rising edge or falling edge) with the bit 2 of register K0 according to the external state before going into the RAM back-up state. Set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state. Return source G 0/INT pin Ports G1–G 3 S0–S3 Return condition Return by an external rising edge input (“L”→ “H”) or falling edge The EXF0 flag is not set. Return by an external “L” level input. Table 13 Return source and return condition Note: G0/INT pin and ports G1–G 3, S0–S3 share the circuit which is used to detect the edge and to recognize “L” level. The G0/INT pin cannot be set to “no key-on wakeup.” RAM BACK-UP MODE The 4250 Group has the RAM back-up mode. When the POF instruction is executed continuously, system enters the RAM back-up state. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 12 shows the function and states retained at RAM back-up. Figure 24 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (return from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the POF instruction continuously, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the software from address 0 in page 0 when reset pulse is input to RESET pin. In this case, the P flag is “0.” (4) Return signal An external wakeup signal is used to return from the RAM back-up mode. Table 13 shows the return condition for each return source. Table 12 Functions and states retained at RAM back-up RAM back-up O O O Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port Timer control register V1 Timer 1 function Pull-up control register PU0 Key-on wakeup control register K0 Logic operation selection register LO External interrupt request flag (EXF0) Timer 1 interrupt request flag (T1F) Interrupt enable flag (INTE) Notes 1: “O” represents that the function can be retained, and “5 ” represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2:The stack pointer (SP) points the level of the stack register and is initialized to “3” at RAM back-up.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER : Microcomputer starts its operation after 3584 to 3585 machine cycles for the time required to stabilize the f(XIN) oscillation. Stabilizing time a POF instruction is executed A f(XIN) oscillationReturn input B (RAM back-up mode) f(XIN) stop Reset (Stabilizing time a ) (Stabilizing time a ) K03 K02 K01 K00 Instruction clock divided by 4 Instruction clock divided by 512 Rising waveform (“L” → “H”) Falling waveform (“H” → “L”) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Prescaler dividing ratio selection bit Interrupt valid waveform for INT pin/ key-on wakeup valid waveform selection bit (Note 2) Ports G 1–G 3 key-on wakeup control bit Ports S0–S3 key-on wakeup control bit Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag after executing at least one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Table 14 Key-on wakeup control register Fig. 24 State transition S R Q Power down flag P POF instruction Reset input l Set source POF instruction is executed l Clear source Reset input Fig. 25 Set source and clear source of the P flag Fig. 26 Start condition identified example using the SNZP instruction Software start P = “1” Yes Warm startCold start No (5) Key-on wakeup control register K0

• Key-on wakeup control register K0 The interrupt valid waveform for INT pin/key-on wakeup valid waveform selection bit, the ports G1–G 3 key-on wakeup control bit and the ports S0–S 3 key-on wakeup control bit are assigned to the register K0. Set the contents of this register through register A with the TK0A instruction. The TAK0 instruction can be used to transfer the contents of register K0 to register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 27 Clock control circuit structure Clock signal f(XIN) is obtained by connecting XIN pin and XOUT pin directly, and externally connecting a resistor to XIN and a capacitor to XOUT . Connect this external circuit to pins XIN and XOUT at the shortest distance. When an external clock signal is input, note the input waveform (refer to the list of precaution). ROM ORDERING METHOD Please submit the information described below when ordering Mask ROM. (1) M34250M2-XXXFP Mask ROM Order Confirmation Form (three sets containing the identical data) Fig. 28 Resistor and capacitor external circuit CLOCK CONTROL The clock control circuit consists of the following circuits.

• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state Internal clock generating circuit (divided by 4) Instruction clock RESET G 0/INT pin K02 Ports G1–G 3 Ports S0–S3 Key-on wakeup control register K00, K01 Counter Wait time control circuit (Note) Software start signal Note: The wait time control circuit is used to start the microcomputer operation after 3584 to 3585 machine cycles for the time required to stabilize the f(XIN) oscillation. Oscillation circuit R S QPOF instruction XIN XOUT Multiplexer Rising Falling Rising detected M34250M2-XXXFPXIN XOUT The system clock frequency is affected by a capacitor, a resistor and an LSI, So, set the constants within the range of the frequency limits.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LA 4 ; ( 555 02) LA 4 TK0A ; Change of the interrupt valid waveform SNZ0 ; The SNZ0 instruction is executed NOP ... Fig. 29 External interrupt program example ... 5 : this bit is not related to the setting of G0/INT pin. LIST OF PRECAUTIONS À Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

• connect a bypass capacitor (approx. 0.01 µF) between pins VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire. In the One Time PROM version, CNV SS pin is also used as VPP pin. Connect this pin to VSS through the resistor about 5 kΩ which is assigned to CNVSS /VPP pin as close as possible at the shortest distance. \` Prescaler Stop the prescaler operation to change its frequency dividing ratio. ´ Timer count source Stop timer 1 counting to change its count source. ˆ Program counter Make sure that the PCH does not specify after the last page of the built-in ROM. ˜ G 0/INT pin When the interrupt valid waveform of the G0/INT pin is changed with the bit 2 of register K0 in software, be careful about the following notes.
• After clear the bit 0 of register V1 to “0” (Figure 29À ), change the interrupt valid waveform of G0/INT pin with the bit 2 of register K0 .
• Set a value to bit 2 of register K0 and execute the SNZ0 instruction to clear the external interrupt request flag (EXF0) after executing at least one instruction (refer to Figure 29\` ). Depending on the input state of the G 0/INT pin, the EXF0 flag may be set when the interrupt valid waveform is changed. ¯ Notes on unused pins
• When pins G0/INT, G1/TOUT , G2 and G3 are connected to VSS pin, turn off their pull-up transistors (register PU0=“5 02”) and also invalidate the key-on wakeup functions of pins G 1/TOUT , G2 and G3 (register K0=“55 05 2”) by software. When the POF instruction is executed while these pins are connected to V SS and the key-on wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately after going into the RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0=“5 1 2”) by software.
• When ports S0–S3 are connected to VSS pin, invalidate the key-on wakeup functions (register K0=“555 02”) by software. When the POF instruction is executed while these pins are connected to V SS and the key-on wakeup functions are left valid, the system returns from RAM back-up state by recognizing the return condition immediately after going into the RAM back-up state.
• When ports D 2/C and D3/K are connected to VSS pin, turn off their pull-up transistors (register PU0=“05 2”) by software. When these pins are open, turn on their pull-up transistors (register PU0=“15 2”) by software. (Note when connecting to VSS and VDD )
• Connect the unused pins to VSS or VDD at the shortest distance (within 20 mm) and use the thick wire against noise. ˘ Multifunction
• G 0/INT pin can be also used as an I/O port G0 even when it is used as INT pin.
• G 1/TOUT pin can be also used as input port G1 even when it is used as TOUT pin.
• D 2/C pin can be also used as I/O port D2 even when it is used as port C.
• D 3/K pin can be also used as I/O port D3 even when it is used as port K.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER t/2 (S) t/2 (S) t (S) VDD (V) VSS (V) Fig. 30 External clock input waveform ˙ Key-on wakeup When system returns from RAM back-up state by using the G 0/INT pin, select the return edge (rising edge or falling edge) with the bit 2 of register K0 according to the external state before going into the RAM back-up state. When system returns from RAM back-up state by using the ports G 1–G 3 and S0–S3, set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state. G 0/INT pin and ports G1–G 3, S0–S3 share the circuit which is used to detect the edge and to recognize “L” level. The G 0/INT pin cannot be set to “no key-on wakeup.” ¨ External clock input waveform When the external clock is used, open XOUT pin, and input the clock waveform into XIN pin shown below. (Refer to Figure 30)

• Duty ratio = 50 %. H ” level input voltage=VDD (V), “L” level input voltage=VSS (V). É CR oscillation constant Use the external 30 pF capacitor and enable to change the frequency by the external resistor. Test the system sufficiently because the oscillation constant depends on the ROM type (mask ROM or PROM).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SYMBOL The symbols shown below are used in the following list of instruction function and the machine instructions. Symbol A B DR E PU0 LO X Y DP PC PC H PC L SK SP CY T1F INTE EXF0 P

Contents

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Timer control register V1 (4 bits) Key-on wakeup control register K0 (4 bits) Pull-up control register PU0 (2 bits) Logic operation selection register LO (2 bits) Register X (2 bits) Register Y (4 bits) Data pointer (6 bits) (It consists of registers X and Y) Program counter (11 bits) High-order 4 bits of program counter Low-order 7 bits of program counter Stack register (11 bits 5 4) Stack pointer (2 bits) Carry flag Timer 1 reload register Timer 1 Timer 1 interrupt request flag Interrupt enable flag External interrupt request flag Power down flag Port D (4 bits) Port F (2 bits) Port G (4 bits) Port S (4 bits) Port K (1 bit) Port C (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant which represents the immediate value Hexadecimal constant which represents the immediate value Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Symbol D F G S K C x y p n j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4250 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Function (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PC L) ← (DR 2–DR 0, A3–A0) (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) + (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 Logic operation instruction XOR, OR, AND (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 LIST OF INSTRUCTION FUNCTION Arithmetic operation Register to register transfer Grouping Mnemonic TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY TAM j XAM j XAMD j XAMI j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 Grouping Mnemonic LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP SB j RB j SZB j RAM to register transfer RAM addresses Bit operation Comparison operation Grouping Mnemonic SEAM SEA n B a BL p, a BA a BLA p, a BM a BML p, a BMLA p, a RTI RT RTS Function (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCL) ← (a6–a4, A3–A0) (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Subroutine operationReturn operation Branch operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER LIST OF INSTRUCTION FUNCTION (CONTINUED) Input/Output operation Grouping Mnemonic DI EI SNZ0 TAB1 T1AB SNZ1 Function INTE← 0 INTE ← 1 (EXF0) = 1 ? After skipping the next instruction (EXF0) ← 0 (B) ← (T1 7–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 Interrupt operation Grouping Mnemonic CLD RD SD SZD SCP RCP SNZCP OFA IAF OGA IAG OSA IAS OKA IAK Function (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 3 (D(Y)) ← 1 (Y) = 0 to 3 (D(Y)) = 0 ? (Y) = 0 to 3 (C) ← 1 (C) ← 0 (C) = 1? (F) ← (A 1, A0) (A1, A0) ← (F) (A3, A2) ← (0) (G) ← (A) (A) ← (G) (S) ← (A) (A) ← (S) (K) ← (A0) (A0) ← (K), (A3, A2, A1) ← (0) Grouping Mnemonic NOP POF SNZP TLOA TV1A TAV1 TK0A TAK0 TPU0A Function (PC) ← (PC) + 1 RAM back-up (P) = 1 ? (LO) ← (A 1, A0) (V1) ← (A) (A) ← (V1) (K0) ← (A) (A) ← (K0) (PU0) ← (A) Other operation Timer operation

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL D3– 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 XAM Hex. notation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 to 17 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D8–D 4 show the high-order 5 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. The codes for the second word of a two-word instruction are described below. BL BML BLA BMLA SEA 1 1 a a a a a a a 1 0 a a a a a a a 1 1 a a a p p p p 1 0 a a a p p p p 0 1 0 1 1 n n n n The second word BA 1 1 a a a a a a a SZD 0 0 0 1 0 1 0 1 1 NOP RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY TEAB CMA RAR TAB TAY SZB SZB SZB SZB SEAn SEAM TDA TABE SZC RT RTS RB RB RB RB IAF SB SB SB SB TABP TABP TABP TABP TABP TABP OFABML BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BM B BA BL BMLA XAM XAM XAM TAM TAM TAM TAM XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD BML BML BML BML BML A LA A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 18 to 1F LXY 0,0 LXY 1,0 LXY 2,0 LXY 0,1 LXY 1,1 LXY 2,1 LXY 0,2 LXY 1,2 LXY 2,2 LXY 0,3 LXY 1,3 LXY 2,3 LXY 0,4 LXY 1,4 LXY 2,4 LXY 0,5 LXY 1,5 LXY 2,5 LXY 0,6 LXY 1,6 LXY 2,6 LXY 0,7 LXY 1,7 LXY 2,7 SNZP OGA IAG TV1A DI EI POF LXY 3,0 LXY 3,1 LXY 3,2 LXY 3,3 LXY 3,4 LXY 3,5 LXY 3,6 LXY 3,7 SNZ1 SNZ0 LGOP TLOA LXY 0,8 LXY 1,8 LXY 2,8 LXY 0,9 LXY 1,9 LXY 2,9 LXY 0,10 LXY 1,10 LXY 2,10 LXY 0,11 LXY 1,11 LXY 2,11 LXY 0,12 LXY 1,12 LXY 2,12 LXY 0,13 LXY 1,13 LXY 2,13 LXY 0,14 LXY 1,14 LXY 2,14 LXY 0,15 LXY 1,15 LXY 2,15 LXY 3,8 LXY 3,9 LXY 3,10 LXY 3,11 LXY 3,12 LXY 3,13 LXY 3,14 LXY 3,15 OSA SZD RTI IAS IAK BML BML OKA SCP RCP T1AB TK0A TAV1 TAK0 TAB1 TPU0A SNZCP TABP TABP BML BML BML BML BML BML BML BML TABP TABP TABP TABP TABP TABP TABP TABP Do not use the code marked “–.” A B C D E F D8–D4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10111 11111 – –10000 11000 INSTRUCTION CODE TABLE

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (DR2–DR 0) ← (A2–A0) (X) ← x, x = 0 to 3 (Y) ← y, y = 0 to 15 (Y) ← (Y) + 1 (Y) ← (Y) – 1 TAB TBA TAY TYA TEAB TABE TDA LXY x, y INY DEY Register to register transfer 01 E 00 E 01 F 00 C 01 A 02 A 02 9 0C y 01 3 01 7 RAM addresses 000011110 000001110 000011111 000001100 000011010 000101010 000101001 011x 1 x0 y3 y2 y1 y0 000010011 000010111 MACHINE INSTRUCTIONS

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 37 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Loads the value x in the immediate field to register X, and the value y in the immediate field to register When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. Continuous (Y) = 0 (Y) = 15

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 RAM to register transfer TAM j XAM j XAMD j XAMI j (A) ← (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) – 1 (A) ←→ (M(DP)) (X) ← (X) EXOR(j) j = 0 to 3 (Y) ← (Y) + 1 06 4 06 j 06 C 06 8 0011001j 1 j0 0011000j 1 j0 0011011j 1 j0 0011010j 1 j0 MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 39 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (Y) = 15 (Y) = 0 After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 LA n TABP p AM AMC A n SC RC SZC CMA RAR LGOP (A) ← n n = 0 to 15 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7 to 4 (A) ← (ROM(PC))3 to 0 (SP) ← (SP) – 1 (PC) ← (SK(SP)) (Note) (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP))+ (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A3A2A1A0 Logic operation instruction XOR, OR, AND Arithmetic operation 0B n 09 p 00 A 00 B 0A n 00 7 00 6 02 F 01 C 01 D 04 1 Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2. 01011n 3 n2 n1 n0 01001p 3 p2 p1 p0 000001010 000001011 01010n 3 n2 n1 n0 000000111 000000110 000101111 000011100 000011101 010000001 MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 41 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Continuous Overflow = 0 (CY) = 0 Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR 2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one‘s complement for register A‘s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Execute the logic operation selected by logic operation selection register LO between the contents of register A and port S, and stores the result in register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SB j RB j SZB j SEAM SEA n B a BL p, a BA a BLA p, a (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (Note) (PCL) ← (a6–a4, A3–A0) (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (Note) 0010111j 1 j0 0010011j 1 j0 0001000j 1 j0 000100110 000100101 01011n 3 n2 n1 n0 11a 6 a5 a4 a3 a2 a1 a0 00011p 3 p2 p1 p0 11a 6 a5 a4 a3 a2 a1 a0 000000001 11a 6 a5 a4 a3 a2 a1 a0 000010000 11a 6 a5 a4 p3 p2 p1 p0 05 C 04 C 02 j 02 6 02 5 0B n 18 a 03 p 18 a 00 1 18 a 01 0 18 p Bit operationComparison operation Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2. Branch operation MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 43 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch within a page : Branches to address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a with register A in the identical page. Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the low- order 4 bits of the address a with register A in page p. (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n n = 0 to 15

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 BM a BML p, a BMLA p, a RTI RT RTS DI EI SNZ0 1a a 07 p 1aa 05 0 1a p 04 6 04 4 04 5 00 4 00 5 08 F (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PC H ) ← 2 (PCL) ← a6–a0 (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← a6–a0 (Note) (SK(SP)) ← (PC) (SP) ← (SP) + 1 (PCH ) ← p (PCL) ← (a6–a4, A3–A0) (Note) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping the next instruction (EXF0) ← 0 10a 6 a5 a4 a3 a2 a1 a0 00111p 3 p2 p1 p0 10a 6 a5 a4 a3 a2 a1 a0 001010000 10a 6 a5 a4 p3 p2 p1 p0 001000110 001000100 001000101 000000100 000000101 010001111 Subroutine operationReturn operationInterrupt operation MACHINE INSTRUCTIONS (CONTINUED) Note : p is 0 to 15 for M34250E2, and p is 0 to 15 for M34250M2.

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 45 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Skip at uncondition (EXF0) = 1 Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (a 6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of address a with register A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Clears (0) to the interrupt enable flag INTE, and disables the interrupt. Sets (1) to the interrupt enable flag INTE, and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is “1.” After skipping, clears the EXF0 flag.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 TAB1 T1AB SNZ1 (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (T1F) = 1 ? After skipping the next instruction (T1F) ← 0 08A 085 08C 010001010 010000101 010001100 CLD RD SD SZD 000010001 000010100 000010101 000100100 000101011 011 014 015 024 02B (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 3 (D(Y)) ← 1 (Y) = 0 to 3 (D(Y)) = 0 ? (Y) = 0 to 3 Timer operationInput/Output operation MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 47 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER (T1F) = 1 Transfers the contents of timer 1 to registers A and B. Transfers the contents of registers A and B to timer 1 and timer 1 reload register. Skips the next instruction when the contents of T1F flag is “1.” After skipping, clears (0) to T1F flag. (D(Y)) = 0 (Y) = 0 to 3 Sets (1) to port D (high-impedance state). Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y (high-impedance state). Skips the next instruction when a bit of port D specified by register Y is “0.”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Instruction code FunctionMnemonic Hexadecimal notation Number of words Number of cycles Parameter Type of instructions D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Input/Output operation (F) ← (A 1, A0) (G) ← (A) (A) ← (G) (S) ← (A) (A) ← (S) (K) ← (A0) (C) ← 1 (C) ← 0 (C) = 1 ? (PC) ← (PC) + 1 RAM back-up (P) = 1 ? (LO) ← (A 1, A0) (V1) ← (A) (A) ← (V1) (K0) ← (A) (A) ← (K0) (PU0) ← (A) 084 056 080 028 01B 055 081 057 082 083 08D 00 0 00 D 00 3 05 8 08 6 08 8 08 7 08 9 08 B 010000100 001010110 010000000 000101000 000011011 001010101 010000001 001010111 010000010 010000011 010001101 000000000 000001101 000000011 001011000 010000110 010001000 010000111 010001001 010001011 OFA IAF OGA IAG OSA IAS OKA IAK SCP RCP SNZCP NOP POF SNZP TLOA TV1A TAV1 TK0A TAK0 TPU0A Other operation MACHINE INSTRUCTIONS (CONTINUED)

Skip condition Detailed description Carry flag CY MITSUBISHI ELECTRIC 49 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Outputs the contents of register A to port F. Transfers the contents of port F to register A. Outputs the contents of register A to port G. Transfers the contents of port G to register A. Outputs the contents of register A to port S. Transfers the contents of port S to register A. Outputs the contents of register A to port K. Transfers the contents of port K to register A. Sets (1) to port C. Clears (0) to port C. Skips the next instruction when the contents of port C is “1.” No operation Puts the system in RAM back-up state. Skips the next instruction when P flag is “1.” After skipping, P flag remains unchanged. Transfers the contents of register A to the logic operation selection register LO. Transfers the contents of register A to register V1. Transfers the contents of register V1 to register A. Transfers the contents of register A to register K0. Transfers the contents of register K0 to register A. Transfers the contents of register A to register PU0. (C) = 1 (P) = 1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction. According to the input state of G0/INT pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. CONTROL REGISTERS PU0 1 PU0 0 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Ports C and K pull-up transistor control bit Ports G 0–G 3 pull-up transistor control bit Pull-up control register PU0 at reset : 00 2 at RAM back-up : state retained W V13 V12 V11 V10 Port G1 (I/O) TOUT pin (output) / port G1(input) Prescaler stop (initial state) / timer 1 stop (state retained) Prescaler/timer 1 operation Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) G 1/TOUT pin function selection bit Prescaler/timer 1 operation start bit Timer 1 interrupt enable bit External interrupt enable bit Timer control register V1 R/Wat reset : 00002 at RAM back-up : 00002 K03 K02 K01 K00 Instruction clock divided by 4 Instruction clock divided by 512 Rising waveform (“L” → “H”) Falling waveform (“H” → “L”) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Key-on wakeup not used Key-on wakeup used (“L” level recognized) Prescaler dividing ratio selection bit Interrupt valid waveform for INT pin/ key-on wakeup valid waveform selection bit (Note 2) Ports G1–G 3 key-on wakeup control bit Ports S0–S3 key-on wakeup control bit Key-on wakeup control register K0 at reset : 0000 2 at RAM back-up : state retained R/W Functions XOR operation OR operation AND operation Not available Logic operation function selection bits Logic operation selection register LO at reset : 00 2 at RAM back-up : 002 LO 1 W LO 0 LO 1 LO 0

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage XIN, G0–G 3, D2/C, D3/K Input voltage F0, F1, S0–S3, D0, D1, RESET Output voltage XOUT Output voltage F0, F1, S0–S3, D0, D1 Output voltage G0–G 3, D2/C, D3/K Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Ta = 25 °C Unit V V V V V V mW Ratings –0.3 to 7.0 –0.3 to VDD +0.3 –0.3 to 8.0 –0.3 to VDD +0.3 –0.3 to 8.0 –0.3 to V DD +0.3 300 –20 to 85 –40 to 125 Symbol V DD VI VI VO VO VO Pd Topr Tstg RECOMMENDED OPERATING CONDITIONS (Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted) Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage F0, F1, D0, D1 “H” level input voltage G0–G 3, D2, D3 “H” level input voltage INT “H” level input voltage C, K “H” level input voltage S 0–S3 “H” level input voltage RESET “L” level input voltage C, K “L” level input voltage S0–S3 “L” level input voltage F0, F1, G0–G 3, D0–D 3 “L” level input voltage INT “L” level input voltage RESET “L” level peak output current F0, F1, S0–S3, D0, D1, D2/C, D3/K “L” level peak output current G0, G1/TOUT , G2, G3 “L” level average output current F0, F1, S0–S3, D0, D1, D2/C, D3/K “L” level average output current G0, G1/TOUT , G2, G3 System clock frequency (Note 2) Frequency error (errors of external capacitor and resistor not included) Note: Use the 30 pF capacitor externally and enable the change of frequency by external resistor. Limits Conditions 0.4 MHz ≤ f(XIN) ≤ 4.4 MHz 0.4 MHz ≤ f(XIN) ≤ 1.1 MHz VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V (Note 1) (Note 1) VDD = 4.5 V to 5.5 V VDD = 2.2 V to 5.5 V VDD = 5 V ±10 % Ta = 25 °C [reference] (–20 °C to 85 °C) VDD = 3 V ±10 % Ta = 25 °C [reference] (–20 °C to 85 °C) Max. 5.5 5.5 5.5 V DD VDD VDD VDD 0.16VDD 0.2VDD 0.3VDD 0.15VDD 0.1VDD 4.4 1.1 ±17 ±17 Typ. 5.0 4.0 1.0 Min. 4.5 2.2 2.0 0.7V DD 0.7VDD 0.85VDD 0.5VDD 0.7VDD 0.4VDD 0.6VDD 0.85VDD 0.4 0.4 Symbol VDD VRAM VSS VIH VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL IOL (peak) IOL (peak) IOL (avg) IOL (avg) f(XIN) Δf(XIN) Notes 1: Keep the total currents of IOL (avg) for ports S0–S3, D0, D1, D2/C, D3/K to 50 mA or less. Keep the total currents of IOL (avg) for ports F0, F1, G0, G2, G3 and G1/TOUT pin to 30 mA or less. 2: The system clock frequency is affected by the external capacitor, resistor and LSI. Accordingly, set the constants so as not to exceed the frequency limits. Be careful about the input waveform when using the external clock. Refer to the notes on use. Unit V V V V V V V V V V V V V V V V V mA mA mA mA MHz

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Parameter “L” level output voltage F0, F1, S0–S3, D0, D1, D2/C, D3/K “L” level output voltage G 0, G1/TOUT , G2, G3 “H” level input current F0, F1, S0–S3, D0, D1, RESET “H” level input current G 0/INT, G1, G2, G3, D2/C, D3/K “L” level input current F0, F1, S0–S3, D0, D1, D2/C, D3/K, G 0/INT, G1, G2, G3, RESET Output current at off-state F 0, F1, S0–S3, D0, D1 Output current at off-state G 0, G1/TOUT , G2, G3, D2/C, D3/K Supply current Pull-up transistor G 0/INT, G1, G2, G3, D2/C, D3/K Hysteresis INT Hysteresis S0–S3 Hysteresis RESET Test conditions VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = 7 V VI = VDD VI = 0 V (Note) VO = 7 V VO = VDD VDD = 5 V VDD = 3 V Ta = 25 °C VDD = 5 V VDD = 3 V VDD = 5 V, VI = 0 V VDD = 5 V VDD = 5 V VDD = 3 V LimitsSymbol VOL VOL IIH IIH IIL IOZH IOZH IDD R PU VT+ – VT– VT+ – VT– VT+ – VT– Unit V V V V µA µA µA µA µA mA mA µA µA µA kΩ V V V V Max. 0.9 0.9 Typ. 1.5 0.3 0.1 0.3 1.8 0.7 Min. 0.1 IOL = 12 mA IOL = 6 mA IOL = 5 mA IOL = 2 mA f(XIN) = 4.0 MHz f(XIN) = 1.0 MHz at active mode at RAM back-up mode Note: In this case, the pull-up transistors for G0/INT pin and ports G1, G2, G3, D2/C and D3/K are not selected.

ELECTRICAL CHARACTERISTICS

(Ta = –20 °C to 85 °C, VDD = 2.2 V to 5.5 V, unless otherwise noted)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER BASIC TIMING DIAGRAM Clock Ports D, C, K output Ports D, C, K input Ports F, G, S output Ports F, G, S input Interrupt input X IN Parameter Pin name Machine cycle State T4 T1 T2 T3 Mi Mi+1 D 0,D1 D 0,D1 D 2/C,D3/K D 2/C,D3/K G 0/INT,G1/TOUT G 2, G3 S0–S3 F0,F1 G 0/INT,G1/TOUT G 2, G3 S0–S3 F0,F1 G 0/INT

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 31 Pin configuration of built-in PROM version Table 15 Product of built-in PROM version *: Under development PROM size (5 9 bits) 2048 words RAM size (5 4 bits) 64 words Product M34250E2-XXXFP * M34250E2FP * ROM type One Time PROM [shipped after writing] (shipped after writing and test in factory) One Time PROM [shipped in blank] Package 20P2N-A PIN CONFIGURATION (TOP VIEW) BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4250 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 15 shows the product of built-in PROM version. Figure 31 and 32 show the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version. VDD D 2/CXIN 18 G D 3/K D 1 D 0 G 3 VSS G 1/TOUT G 0/INT RESET XOUT CNV SS M34250E2-XXXFP Outline 20P2N-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Fig. 32 Pin configuration of built-in PROM version (continued) G D 3/K D 2/C D 1 D 0 G 3 VDD VSS (0V) G 1/TOUT G 0/INT RESET X IN X OUT CNV SS M34250E2-XXXFP ] : A resistor is connected to XIN pin. A capacitor is connected to XOUT pin. VPP SCLK SDA PGM VDD Note: The state of each disconnected pin is the same as that at reset. VDD VSS Outline 20P2N-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 33 Flow of writing and test of the product shipped in blank Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150°C exceeding 100 hours. Note: (1) PROM mode The 4250 Group has a function to serially input/output the command codes, addresses, and data required for operation (e.g. read and program) on the built-in PROM using only a few pins. This mode can be selected by setting pins SDA (serial data input/output), S CLK (serial clock input), and PGM to “H” after connecting wires as shown in Figure 32 and powering on the VDD pin, and then applying 12 V to the VPP pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first). Use the special-purpose serial programmer when performing serial read/program. Refer to the Mitsubishi Data Book “DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” about the serial programmer (serial programmer and control software, etc.) for the Mitsubishi single-chip microcomputers. (2) Notes on handling À A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. \` For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 33 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped)

© 1997 MITSUBISHI ELECTRIC CORP. KI-9711 Printed in Japan (ROD) II New publication, effective Nov. 1997. Specifications subject to change without notice. Notes regarding these materials

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 971130

REVISION DESCRIPTION LIST 4250 GROUP DATA SHEET (1/1) Revision Description