M34225M1

M34225M1 MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 28

Technical content

MITSUBISHICMICMPTR/MIPRC) bLE D MM 6249828 0017458 276 MENITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DESCRIPTION

The MSUZZ5M1-XXXSP/FP and M3422562-xxxSP/FP are | PIN. CONFIGURATION (TOP VIEW) single-chip 4-bit microcomputers which utilize CMOS tech- ane noe WEST 5 vectw nology. Ail are housed in ® 30-pin shrink plastic molded — | weamerega int fH Pee narvo DIP oF 36-pin shrink plastic molded SOP, and contain a 9- | Antegvotaoe 4/1! Bo oor Dit timer, two 8-bit timers/event counters, an &-bit timer, an | etrence vane v0, — Fe eT A-D converter, and a serial 1/0. The ditterences between | "niveonou | Ko~B] = E a—FyS~ oe a oe VO dunner uerecs jt | kag Be Bove. below. sere wee OBS Be rcte) oper Se ERE Bris) Tes name 7OM Se Tam oie s-G SE f-o mse226ue-1xSP|_2048wordsxsbie_ | 128wordsX4bite sO 8 & f-o! of FBO. } voor ‘The differences between M34225M1-XXSP and M34225M1- vonmo| o- fa 0. | XXXFP are the package oulline and power dissipation wow, @ fo, (absolute maximum ratings) (ovives Ol Fao, | The following explanations apply to the M34225M1-XXXSP. ‘Specification variations for other chips are noted accor Outline 30P48 ingty. reser ~C BD veo'sv: FEATURES wtf] CO) B-owe © Number of basic instructions cosenenen TT ws x0 © Memory size var > G [BD Xow ROM «+= 1024 wordsX9 bits (M34225M1-XXXSP) «GB . -g BN 2048 words 9 bits (M34225M2-XXXSP) wt - iS gs 5 ne ween RAM ==> 64 words X4 bits (M34225M1-XXXSP) neo OBS bborvse 128 words X4 bits (M34225M2-XXXSP) s-E] S8© Bq © Instruction execution time s-@ 2 x Bare sce (one word instructions, a AME frequency) s-q $§ pv © Timers Timer 1 : 9-bit timer s-G 3 3 [B-o Timer 2 : B-bit timer/event counter nc [a--o- (with 8 reload register) x @ [3-0 Timer 3 : 8-bit timer/event counter one E~ o> (with a pulse period vem, Boo measurement register) ‘Me, Fano, Timer 4: 8-bit timer (with a reload register) Outline 36P2R © Interruptes--0--6 types( external timer 1 oF serial Nc! No connecven 1/0, and timer 2), 1 level © Subroutine nesting snr tn Alevels © Analog inputs (Port K) =~ sooo © 170 ports (Ports D. F. S) 7 © Timer 170 port (CNTR) -woenrntnrnnd © "A.D converter + B-bit successive approximation © Serial /0'~ BebiIXt © Built-in feed back resistance for clock APPLICATION Washing machine, Rice cooker, Camera, Office automation equipment, Copying machine, Medical instruments, Learn- ing equipment, Toys es a

MITSUBISHIC(CMICMPTR/MIPRC) b&1E D mm 6249428 0017459 102 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 'M34225M1-XXXSP BLOCK DIAGRAM | | S| 4 | = = ; — hee =e |e} 7 | Lane sce qe ces Sota j 4 « Cs a | sal | ai ar EE M34225M2-XXXSP BLOCK DIAGRAM | uaa TI SES = con + geese) menoe Leonard fF see eee Sst Tt |e oe io a - C=| I Se ees, ee =a Ee oes Te) asses eee , A

MITSUBISHI(MICMPTR/MIPRC) bE D Ml 6249828 0017460 924 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4.BIT CMOS MICROCOMPUTER FUNCTIONS OF M34225M1-XXXSP/FP and M34225M2-XXXSP/FP Parameter Force Fiynbe! bane maveione ” 7 oe Tnsrconexecton time 1s cane word murvcnns a ts eavency: ee Yuck mquery soon ~ths : ce Fete aerating cree tuton enema connected carame enn un eee boca now {inazasinesouxserre _102twordsX908 - t | MOA229M2-0XXSP/FP MSWord XSbitS ~ oT Memory soe toe Fuca soeseiFP Simonton nl in | MOA225M2-XXXSP/FP —_17Bwords X4bits : . ~ — Te Le homed ns nn rn er an is A "0 pind” - a Inparouina pare KT trent 2 smug wpa 2-04) (Gg most TT “ont T "0 “ext ° ae _ Ser : ‘oout bot, . : srowvoupavotege iPS wien. - - apart * put wattage ‘« SV imon? ~ee crescent ae be wines. 2 . F smaterg | A-0 conener 7 Buin abacte accuracy £3158 EK aceese aogonmaton Sein VO ; ext ~ Timer | S-bM wer. xed drvis:0n - Time Tener? E-bat nner ‘event Counter woth an 8-bi reload regsier _ ~ Tene} 8:bit wmervavent couner with a pula period measurement register Timer 4 ‘8-bit timer woth an E-bit reload register 7 sone ‘ype ‘iypes ener! mer oseraO ander? J nating ; eve! — 2 Sebroin nesing Aes "Devin wn wie used TABPD inicio «Brees . sects enh. aks ons Sopmstven pastemoesO® Prcsnge azz cnt Manze KrF S6ipm shiek panne moti 80° Sepp womage sv-4 7 Foret oaupaion 1.SmW typ Lt AMM at noma! operation Se

9 MITSUBISHI 3

MITSUBISHIC(MICMPTR/MIPRC) b1E D MM 6249828 OO1L74b1 860 MIT MITSUBISH! MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER PIN DESCRIPTION mj mm | tent Yoo [swore | Connected to +5V power mpphy ve tems PT ease De-0, | vpn 1 eo | toon pn nso aoa 9-0 oop pet ad [oteteeeerstoctenertan cE | i Tha eaout arvoure a Wechaet open ere Fo~Fs | VO pon 1 VO | Thi pen tunctone ws 84-04 70 ' 1 | The port is turned to an input enabled ste when the cutput latch is et to “1° { i | Te xtour severe 8 N-channet open drain KenKy | Analog input pon Kj laput [otc oan not AD coven, ad can ane 42: rma np pa So~Ss | vO pons 5 vo | the part funetons a8 a 4-64 inp i i | ro bor ned to an inp @nuble state when the utp itch i wet to “t= : i | The auiput structure is N-channet open drain Gwin fmmre” Ye Taecononmscenne asere gO ORS UDO OUD t hom wiqnel of tmer 2 Boh ofthese functions are selected by sofware, ' _____| se ste arte tv open a iNT | Saterrpt input | Input | This is an interrupt Input pin. RESET | eset inp Input | To emer the reset state, thes mput pin must be kept at @°L" for more than one machine eyole. Kane | Clock input Input: These are 1/0 pins of mtemat clock genereting clrcult. a ee = =! Connect enter & cormmic renonstor (400KH2~4NMH2) to these pins. eee ‘CNVes am CNVes input | This is usually Connected to Vss, and suppty “L” (OV). AVoo Analog voltage impul "thus te the power supply input pin for he A-D converter. ~ AVss—_ Antlog voltage input | te me power supply inp pin fore A-O converter Vnex | Reterancevotage input: Ths he reference votage inp ine he A.D canearier wwe . ae OE aaarereeEeeEOE_—E_E_—E—EEEeeeEeee_E

MITSUBISHICMICNPTR/MIPRC) bLE D MM 6249828 OOL?4b2 777 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER FUNCTION BLOCK OPERATIONS DATA MEMORY (RAM) PROGRAM MEMORY (ROM) This is the memory in which various processing data and The memory is a mask ROM of 1024 words X 9 bits, and control data are stored. Its size is 64 words X 4 bits (256 stores user-created instruction codes, The ROM is com- bits). One word of RAM is composed of 4 bits. However, bil posed of 8 pages, each page consisting of addresses trom processing can be accomplished for the entire memory 0~127. A ROM address map Is shown in Figure 1. Page 2 area. Figure 2 shows an address map of the RAM. An Is @ special page used for subroutine calls, A page 2 sub- address in RAM can be selected by the registers Z, X, and routine can be called from an arbitrary page by using @ Y of the data pointer (OP). ‘one-word BM instruction. ‘iso, by executing a TABPp instruction (p= 4~7). pages 4 ~T can be used as data area. When executing this instruc- Lied -t Pogue? . 2. 1d ton, one of the stacks is used. End St a Se y; ESS Pe s EXIST LETSEESREEREERNURREOEEE (Gress coc eosnICODSOODSU0SUSN5000U000520: ls #1 er aaa SOeRERESE eared fey | bp peep : TT TT H i -j 4p Hitt TI pi i Dobe 7 - 7 RAM aaarese CE IS *e .° ul meni Note : The digit number in RAM of M4225M2-XXXSP. is Fig.) ROM address map composed of 16 digits ((Y)=0~18). Note : The ROM of M34225M2-XXXSP is composed of 16 pages. By executing a TABPp instruction (p=12~ | DATA POINTER (OP) 15), pages 12~15 can be used as data area. ‘This is @ register to specify a RAM address and the bit location for 1/0 port D. The data pointer (DP) is composed PROGRAM COUNTER (PC) ot 7 bits “This counter is used to specily » ROM address, and deter- Register Z, the most significant bit of the OP. specifies the mines the sequence in which instructions are read from the RAM file group, the middle 2-bit register (X) specifies the FROM. This program counter (PC) consists of 10 bits: the RAM file, and the lower 4-bit register (Y) specifies the ‘upper 3 bits (PC,,) stand for a ROM page, and the lower 7 RAM digit. Register Y also specifies the bit location for vO bits (PC,) stand for an address. The PC is @ pure binary port D. tosntor and le incremented each time an inarution is ex: ‘cuted. However, when executing @ branch instruction, 4-BIT ARITHMETIC AND LOGIC ‘subroutine call instruction or return instruction, its value UNIT (ALU) fakes that spected by that instction This 188 4-0Itathmetic unt and consists of a 4-bt acc ‘The PC takes the zero address of the next page, afer tion unit and its associated logical circuits. This unit per- address 127 of that page is reached. forms addition, comparison, bit manipulation, and so on. Note : The program counter (PC) of (M34225M2-XXXSP- consists of 11 bits ((PC,,)=4 bits, (PC,) =7 bits) REGISTER A (ACCUMULATOR) AND CARRY FLAG (CY) STACK REGISTERS (SKo, SK;, SK, SK) Register A is an accumulator exclusively used for computa~ eek Ree eS ie cio on riertpt handing tion Wt composed of 4 Bits. The processing of data such Pn ore a saserragater ere veed to temporary as computation, anslet, exchange. ransormation and 1/0 ‘save the contents of the PC belore the branch, and unt! is executed using mainly this register. The carry flag (cy) conta is relumed othe routine, stores the carry tram the most significant bit of the ALU af Since there are four 10-bit registers (SK), up to four sub- ter executing an AMC instruction. It can also be used as an routine levels can be called! one ofthe loves has been 1-bit flag used for execution of an Interrupt routine or TABP p instruc- tion, however, only 3 levels can be used for subroutines. REGISTER B AND REGISTER E ‘The address of the stack register is specified by @ stack Register B is composed of 4 bits, and can be used for stor- potter. ge of 4b date ox Wanster of B-bit data in conjunction with Note : The stack register (SK) of (M34225M2-XXXSP con- register A. Register E is composed of 8 bits, and can be slate of four 11-bit registers ned for 8-bi gata vansfer fo or om register A and © a Awe 5 pags 7 . Oe

Register D is composed of 3 bits and in conjunction with ‘saved in one of the stack registers. register is used with TABP p instruction execution. ‘The INTE fing is reset to the interrupt disable state. Table 1. Interrupt types and vector Interrupt condition is retained. oo oe ee come cone j tegister (register A), timer 2 interrupt request flag (2F). enable flag INTE Is set to “1” (INTE =1" when an El in- (500kHz for 2MHz clock frequency) reaches 500 or 20. Either interrupting trom timer 1 oF serial 1/0 is. determined ‘struction. The cause of each interrupt can be controlled by the solt- struction. calls, Afler an interrupt handling program execution is function) in order to continue counting. 1: Program counter order to continue counting.

MITSUBISHICMICMPTR/MIPRC) b61E D MM 6249828 0017464 5S7T MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER latches the contents of timer 3 when the externa inter- rupt request flag is set (“0" to “1"). The contents of register N can be read by using a TABS instruction. (4) Timer 4 Timer 4 is on B-bit binary down counter, which has a reload register (register U). The values of timer 4 and register U can be set by executing a T4AB instruction, and counts the oscillating frequency divided by four. Wnen i overtiows, timer 4 is automaticaly reloaded ftom register U and continues counting (5) Timer 1/0 (CNTR pin) This 8 normally an input pin which is selected as the count source ot timer 2 and timer 3 bythe timer control register, otherwise this becomes an output pin for a 1/2 cycle of the timer 2 overtiows. Levels of these ports ("H” or “L") can be tested by @x- ‘ecution of SNZC instruction. (6) Timer 1 interrupt request flag (1F) Timer 2 interrupt request flag (2F) ‘The timer 1 interrupt request flag (1F) is set every time timer 1 count reaches 600 or 20, and the timer 2 inter- supt request flag (2F) is set every time timer 2 over- flows. These lags con be tested by an interrupt or ex: ‘ecution of skip instruction (SNZ1 or SNZ2). Whether to fxecule on interrupt or execute a akip instruction can be determined by the timer control register, Each of these tiemrs interrupt request flags (1F and 2F) can be reset by an interrupt or execution of skp instruction (7) Timer 3 overflow flag (3F) This tag sets every overtiow of imer 3. The testing 3F fag can be determined by the execution of skip in- struction (SNZ3). The 3F flag can be reset afler skip instruction is ex: cuted and the next instruction is skipped (8) External interrupt request flag (EXF) External interrupt request flag is set when the interrupt- ing conditions are satisied This flag is tosted by the ‘execution of interrupt oF skip instruction (SNZO). Either interrupt or skip instruction is determine by the timer controt register V. This flag is reset by the execution of Intertupt or skip instruction INT pin (interrupt input) level can also be tested by ex- ‘ecuting the skip instruction (SNZO). Either testing INT pin levels oF EXF flag is determined by the timer con- trol rogister V and ©. EXF flag cannot be reset i the skip instruction is elected for the testing of INT pin levels and is ex- eouted (9) Timer control registers (V, W and Q) The timer contol registers perform the above fonctions, ‘and the data is transtered to these registers from regis- ter A by the TVA. TWA oF TOA Instruction. Figure 3 shows the structure of ese registers a fe MESH , ELECTRIC a

MITSUBISHICMICMPTR/MIPRC) 62E D M® 6249828 OO1L74bS 4Ob MENITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ou) (oa) (iy Me Lv Ve} tomer control register (Register V) | Lo eT | [0 | Saabie (5NZ0 metrecton is avalabte) | 1 Tenable (SHZ0 inatrscon unevalbla) | | TTT er ne | © [aan (SAE inavucin i evade) [i Tenable (821 wir vnaralsbie) | Timer 2 waeriupt enable be \\ “Tanabe (Sai nonocn e owes) “1 Tenable (ShZ2 maton is neraiaie) Timer | cont var ba -9_j covet sop (reset oie) 1 coun sar (ous) (oo) “er conta agit (Repater W) —_--_____- — <7. Timer 2 count source selection bit we] We [eeu owes O71 0 Tomer 2 count sap

074 Testers cock fom CNTR pin

11 [eck cncaaieg weaver wad oy

11 Leverton signs vom wer 1

(wea) (veo) Tuner controt register | Register O) TO Tope wave i [00 [aig woe (S20 noe etal orl aT pl _| 6] [sion eg 520 ntnchn rai eer WT pe 1] wg edge (Shad marucon mabe conaen of Ex og)

111 Pring edge (128 rac natal tens of EX Mg)

i ___._ Timer § couse step sotoetion bit_ 1] 29 steps ( cout the clock cnciteing Requency. ded by 4)

1 S00 saps (cout the cock enciaing hequency Gonded by 4

cane te =~. Timer 3 cour source selection OM | 0 extemal clock tom CNTR pM 1 evertow sgn tom ter 4 Fig.3. Structure of timer contro! registers (registers V, W, and Q) : one OOO ae

MITSUBISHICMICMPTR/MIPRC) 61E D MM 6249828 O0174bb 342 M@EMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER , : cma notpe ag MER ® Oo” C2 SC C8 Phe) ([Reomeraa] CI TAB? 1288 TAB? les EA tne 2 ‘Timer /0 pin CNTR pow 1 a ee | coum Ey Sore fe (iE a | (Baseaeanememen nner] GIs) | Ta | a ee > E “ fe MISESH ° ELECTRIC OOO

MITSUBISHICMICMPTR/MIPRC ) BLE D MM 6249828 00174K7 289 MENITY MITSUBISH? MICROCOMPUTERS M3422SM2-XXXSP/FP SINGLE-CHIP 4-BiT CMOS MICROCOMPUTER SERIAL 4O register H and the lower 4 bits, register L. The re- ‘The M34225M1-XXXSP houses a clock-synchronous serial ceived data is stored but by bit starting trom the high- VO which can serially receive oF send 8-bit data. This se- st bit (bit 3) of register M, and the transmitted data is tial VO is composed of serial 1/0 register (H and L), serial transmitted bit by bit starting from the lowest bit (bit 0) VO mode register (J) and a serial 1/0 counter. Each of the of register L ‘serial /0 register (H and L) are used to transmit 4-bit data. (2! Serial I/O mode register (J) The serial 1/0 mode register (J) is used to select the tunc- ‘This Is a 4-bit register used to select the clock source, tions denoted by its 4 bits. This serial 1/0 performs data ‘oF port function, and interrupt sources (interrupt from ‘ranater with the internal CPU by using the data bus, and timer 1 oF from serial 1/0) with respect to the serial with the extemal CPU by using ports Fo~F, Ports Fo~ Fa vo. ‘are not only 1/0 ports, but Fo is also a serial 1/0 receive (3) Serial I/O transmit/receive comptetion flag (SIOF) ready pin (Saoy). Fy is a synchronous clock input pin This flag is set when the serial data transmit/receive is (CLK), and F, and Fs are serial data input/output pins completed. This flag can be tested by an interrupt and (Sour. Ad Sy). The functions of these ports can be the execution of a skip instruction (SZS1), Whether to selected by the serial /O mode register. enable or disable an interrupt can be decided by the (1 Serial 1/0 regiser (H and L) serial 1/0 mode register. The serial 1/0 register is for transtorming serial data to The SIOF flag is reset. olther when an interrupt is arattel data. Each of these registers H and L consists accepted oF after the next instruction is skipped by the of 4 bits The upper 4 bits of the transmitied data uses execution of the skip instruction. (wea) teat 0? ‘Sorat 0 moge repster(Regater J) : | = ‘Sychvanove clock velcbon ba © exiorat clock : | 1 etock oxcitaing frequency divided by @ - iy i a “Seval 70 por and nerrupt selecion bt i © paranel pons (Pons F,. Fa. and F). timer ¥ temupt 1 ena V0 pons (CLK. Soy nd Si neni VO wterup i a Bao, BOA selection ba 0 puraiet pent :Pon Fy} 1" Seer port - be _ ‘Sena 1/0 interrupt enable bt 0" eaatte . . Fig Structure of serial 1/0 mode register (register J) MITSUBISH: 0 Ae OEE

R/MIPRC) b61E D MM 6249828 0017468 115 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fon ima? Xa pin Cpe Dip. — Seow Timer 1, oF FefSnor pin C4 Dl - D ‘Ser! 170 interrupt oH Toc rucux sin CSooK| [oP {_} eee EO fl Sri set

4 Sr lek

vmeve OMe | rsa © i ee 4 $3 LL a SS — fact VO mode regate J Fig® Block diagram of serial VO A-D CONVERSION 31 -A-D conversion termination lag (ADF) ‘A-D conversion can be controlled such that the A-D contro! The A-D conversion termination flag is a 1-bit flag, so sircentols those registers. etc, described below The When the A-D conversion is finished. this flag is set to start and end of A-D conversion can be recognized by soft- T ware. Figure 8 shows the A-D conversion circuit. ‘The re- This flag value can be tested by @ skip instruction solution of the A-D conversion is 8 bits, its analog input pins (SZAD). By executing @ skip instruction, the ADF tlag are Ko~K, and its conversion speed is 368 (when (Xin) is set to “0” =4MHz) 14) Successive approximation register (registers HA and (0) A-D control register (C) LA) ‘The A-D control register (C) is a 2-bit register. One of ‘The result of A-D conversion is stored in the succesive Tre tro snoiog impute is selected according 0 the approximation registers. HA and LA. Registers HA and combination of bits 0 and 1 of this register. Figure 7 LA are each composed of 4 bits, and can send their comline correspondence between the selected ane- dala 0 register A. The upper 4 bis ofthe Bit digital Jog input pin and bit O or 1 data (resulting from A-D conversion) are stored in reg- (2) The A-D conversion start instruction (ADST) ister HA, and the lower 4 bits in register LA When the ADST instruction is executed, the A-D con- version begins toe) (oa) 0 camerven conv eg (Repie C) _ oo . KD coneiben pon woecionb - © Gy Pon O18 pain ot “pen, Fig.7 Structure of A-D conversion control register (register C) 9. wrrsueiset " ELECTRIC eee

MITSUBISHI(MICHPTR/MIPRC) bLE D MM b249828 OOL74bT O51 menity MITSUBISH! MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP St iP IT CMOS MICROCOMPUTER Ce y [Te] TJ (vet J 229 Le ott

0 Tener

(m0 reais) A(T bee | a is Ave on Veer 0 Yao ia Fig.8 Block diagram of A-D conversion circuit WO PORT When the processor is reset, its status is as foliows: Mb Port 0 (De~D4) 1. Address 0 of page 0 is input into the program counter This port performs 9-bit O's (SZD, SO, and RD). ls (Po)—0 output has 2 latch which is capable of manipulating 1-2 Interrupt is disabled UINTE)~0 bit, and the 1/0 can be carried out such that register ¥ (the same as when & DI instruction ie executed) of the data pointer specilies one of the D ports “3. Registers V and W are set to“0". (V)=0. and (W)-0. For input. the output latch of the corresponding bits 4: Register Q is Set to “Fre” (Q)-Fre must be set to “1” The instruction CLD, can set all of 5. External interrupt request flag (EXF), timer 1 interrupt the port D latches to “1” request flag (1F), timer 2 interrupt request flag (2F). ‘The output structure of this port ts N-channel open and timer 3 overtiow flag (3F) are all reset drain (EXP )=(1F) = (2F)=(3F)~0 2 Pot F(Fo~Fs) 6 Output latches of ports D. F, S and CNTR, are a! set to ‘This port has a 4-bit output (OFA) and input (IAF) tune oa (D)=(F)=(8)= (CNTR) tion. For input. the output latch for the corresponding 7. A-D conversion termination flag (ADF) is set to “O- bite must be set to “1” (AQF)~0 The output structure of this port is N-channel open & Serial /O send/receive completion flag (SIOF) is set oan too. (SIOF)—0

3 Port S(S~S:) 9: Seviah VO mode register (register J) and AD control

‘This port has one 8-bit output (OSAB) and two 4-bit m- register (register C) is set 10°0" (8)=0, (0 puts (IAS) For input, the output latch tor the corresponding bits GLOCK GENERATING CIRCUIT mmust be set 10 "1". The Instuction CLS, can set all ot clock generating cicut is but nto the procatsor, so a the port $ latches to" Ceramic Tenonatar ie connected 10 the clock 1/0 pint a The output structure of this port is N-channel open clock signals can be oblained. Ifthe clock signals are input oan from an external circu, connect the clock generating s0urc0 to the Xu pin and leave the Xour pin open RESET FUNCTION Figures 9~10 show examples of the circuits, Wan “L" input is supplied to the RESET pin for longer than cone machine cycle, the processor is reset. After tha, it the RESET pin is supplied with an “H” input, the program ex- ecution starts at address 0 of page 0. a n eee OO

©) GLE D MM 6249828 0017470 873 MMITY MITSUBISHI MICROCOMPUTERS M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER tion to reset the EXF fag after the seting of he regs: MTF ero woe coc me aeramie | igor an one inaction ined bei SNZ0 2 — oscarce ceed be instruction (@) (see Figure 12), ‘canaure Ur be vont so--4" ommended by ve of $e crate menace ro sete vue orapetr 0 Nor 3 Fig’ External ceramic resonetor cout enzo (M34225M1-XXXSP- Nor Ey 7 TAL OY Oper Fig.12 Example program-2 Enteral ck gern exc me Bamp ” @ _Notes on timer 1 | gio Exava cook apa When the count value of timer 1 is changed while iis Counting, the first timing of ter 1 overtiow just afer the ranging is unsetieg. Teretore, change the count DATA REQUIRED FOR MASK ORDERING —_ “Turan umed Tree, congs.e cout vale Please send the following data tor mask orders. (1) M34225M1-XXXSP/FP or M34225M2-XXXSP/FP mask centration sheet ; (2) ROM data sree = EPROM 3 sets wo? (Submit three sets of EPROM's with the same data) vA Tomar 1 count stop a (3) Mark specification form tor 30P4B aA 6 Tos Seen vue PRECAUTION FOR_USE Los © [Notes on noise and latch-up In order to avoid noise and latch-up, connect the following A Vener cod at ‘external circuit. 1, Connect a bypass capacitor (= 0.1uF) directly be- —Fig.13_ Example program-3 twoon the Veo pin and Vos pin using # heavy wie, and ‘connect the Voo pin to the AVoo pin and Vss pin tothe @_ Notes on serial 1/0 Averpin So this microcomputer continues # serial transmission a8 @ [Notes on iNT pin] ong as an external clock inputs, when selected an external Moana crass atthe INT pin is changed by the bit ot clack as synchronous clock. it must be contlled exter the register Q (in the software program) care for the tollow- nally. ing notes: (When the SST instruction is executed and the serial 1/0 Ty ‘set the bit 0 of the register V to "0" ((D) and the bit 1 counter counts eight clocks. ine SIOF flag is set fo “1~.) of the register @ to "1" (Z) before the input polarity of | Note on register ¥ ' the INT pin is changed (see Figure 11). ‘On M34225M1-XXXSP, when the contents of register ¥ are 8~15, this microcomputer has no correlative memory area. A this time, do not use the reading memory instructions o 4 Hor009 1 (AM, AMC, SEAM, SZ8, TAM, XAM, XAMI, and XAMD). A ws goons 2 ros Fight Example program-t 2. Depending on the input state of the INT pin, the exter- nal inert request tg EXF is sel when the input polarity is changed. Therefore, execute SNZO instruc- a ate 4

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER INSTRUCTION CODE TABLE . 7 y Tp Xs e404 fo omo'a coro ores eof ovo 011 reo nif ano 121 0 sree vonifo nese vio niae vif °°," ~ : i? nr m0 i PIs inf va «Me -4.- i + deen ob. $a 4 1 t ~ anne vent =_ dno, MPa] oo! 01! oz! os}oelosjostor}oejos oni oe ec! on! oe | oF joni7~i9 * Tez ae Tp a Tie Por oR or oer] rion eer Pigg fon fete teolelzo! ao My P i ee xaié Pats foxy oe ber Tor oor 1 | eA coo Buta = | pmilaost. — | em! 8 wee fe - ed pera rpariag 4 Tee “ean Ak Poe Gor bx Px] —P wre 2 | - cis mses - ml rca: -— = * : Or) ow! ® obey 12, boyd. » fade toriveleztaa| 1” ‘ ge + enna fF TP ber ber er bo] won) 3 | — my et fezao’ — )™ emtraa! — Os mee fe 8 wpe et fo. 8 a fost usiasiss| “rant eek UN pix bay Ue oe oo 4}. no so mat — em| ofa TaBe ON eu 8 ee i ee pone eeee a4 4 4 LOA a a sat tas se kk] iy ba ba ot or 5 | et so seam a fats ms.” ™ paclreae tabe ceeued bed veer nn oe . oe S828 sfosiusiasians| O Fat Se A | br oy oy ono 6 fac - seam eu atiar *™ em eva tabe io Pe oe ne * ase . i? oo + 6.6.6 106 16 26) 36] TAM we A LAT LXV LXY LXY LXY q om 7} sc ory = a] - mx ™™ wan | twa tape Pa ee a 8 oP tt forinziag! s7/ PhP ta xan Au] boa oe wo 8 f= = wel 2 ran womltana — | od ee a8 . H . oe. ° 4 - 8) fos nec 26 a8 + kaw Pay cate ait ae ee tor 9 | ~ reap roa #m| 7 scr *™ soudrata — oui e i. ™~ 1, 79, o foe ne!2cia0|™. ° wai Aun [oe Ux Gro rook | aM reap tase #et] — tan “M oulrane — emi 8 scan 0a | ber xv Bee oe] wor @ fame ose = sel ra cenalraps — OT eww ee « : 4 Bae. : Ws 19 $0.19, 9.1122, 99 + : ne” se Xam erie? 4 UA ber ox or GT ni00 {ryan cma’ ~ 900 p1nfsnz1 om 8 a sane os ad. . Lh ee wi 12 12 12 fOse naz zazsret ne s8 AMO era kU] Gr ca not 0 | - man - om seudl'snze m8 a en heaiae 191399 fo.ra's.t3'2.19/9,19] ™ snz’ | ne” se amo ‘sag A ua | oy ny Uy ev moe ren. tas 7 om oan suze Oe OT oe eens Deane ated Bre er 4 4 ne totals. talz. salar) OM ne 0 amo emer nL] Oy ony Gr Br] 0? m+ & | = ‘rar sec oo] “| 5 ewalenzo ow! 8 aisisa 15.1535 fos 1.98295 305 Nie 1 The snow abe shows he caveapondence between machine cose an ache matocbone Oy~Dy sands fr te lower 4s he machine Cader and O}~D, forthe epper bt fhe machine codes, Ato the Pannoncial vues Wose Code ae lied Thar te tre maucvo Nes. Torend ano Se chon, bet i been the cove dhe fret word of such mabucton shown tr OSiet we cae 2: The second word or ?-wordarucons ar ted Below in sense Bui Ti Geen ceed BA 1) bese wena Os jb ieee oppo ema li oees opne sta '0.1011 nana sz0 “6 0010 tort 3 The BLOM. nd TABP codes mere wih anlersh ar nt avedbie wth he MS42Z5M1-KXKSP 4 :_The TABP caden mand win ho sine nee avaluie wh her MEN? HOO —LLLIARE cose mertegn mo anorane ms nat aalble win he MBKZZEMzXS OO EEOEOEOEEOEOEOEOOO

MITSUBISHI(MICMPT R/MIPRC) BLE D MM 6249828 0017472 G46 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SYMBOLS ‘The following notations are used for the following descriptions. Taye emtorig symett_____ convert x aap ; aaa : eoothipred ; jnoooona ce B a i gc (2-8) H eesti 2 port tren . itemtens coe me | esome 4s evonctowoonen woe | 1 wean Sa |mrictran HE eroesereereters ’ Ls epue ste) Teper ang rs | ve ower 4b sri 0 reg) - Direction in whuch cata ib wansiorred te | Peers teraaaten woe | > Set nga none ee rere 4 bacemeace ® [oA a avon ager M88 ‘ ee an tap nt cuge a ne a | Timer contro! register Q (4-bi) instruction 1 executed A reeset tens cor) Rreaben ch petit pnt OF w | Tamar control register W (2-bit) (page Pr Pe . | Kogucrnsno © me caster exe ome Y | Register ¥ (4-bit) + as for her value Zz | Regester Z (1-1) * ES beoeebair el ve ee aot oon Pow | SePuppar 3b oe program contr rs Lieued apres ceaetoeeny = edeetherhintay Fs paper oe) & Paton 2 | Tamer 2 3 | Timer 3 14 | Timer a oF | Timer 3 overiow tog Soe te tn a peteeteonreteris So, etoranne wr | et ese SIOF | Seri! 1/0 wanema/receive complevon fag D | Pot © (oa) s "Pon § (4-bit) Ce mn ns SOUND rion BB TT ICT OH Pmt OT reat papon canst caer tha poion Comte! ge egrouns waco’ ake grae ek ce Ae ' a

MITSUBISHICMICMPTR/MIPRC) bLE D MM 6249828 0017473 582 MENITY | MITSUBISHS MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-817 CMOS MICROCOMPUTER MACHINE INSTRUCTIONS — h ‘mnvon ote a 1 tinemente eee || ay | DL Dr DD DL Dy O OD, by Mmmm ig”) | Tae 00001114 1 ola 1 elili army | fm 00000111 ole 0 Eiri |e i Bitar pee e errr rey ris lane | B inva }0 0 0 0 0 1 1 0 Oj0 0 G/F 1 liyIH(A) | 2 | TESTES) | 2 tos joo oo 1 Oo 1:0 2 Bt 1 OH j 2 jae fo 0010101 0.0 2 Att |(Bmte~es) ' ux ny lo To my me vs ve we Wo 0 CV) 111 | (Xe x where xe 0~ 3 $ faeneteeeet ia i | q \\ rion] : Z iw ee ee ee . : itd TAM) 0011001 hw Ob 4) pt E@mcacoey) : FL joo tow k wnere i= 0~3 foamy (001 1 0 0 Om wo 6 Ft Lt i tareomcorn B xaMDy 00 1 1 OF 1 hy mw 0 6 CIPI T CA)e(M(OP)) H t 1) Loo-00¥) g ! t ! (Y= (V)— 1, where j= O~ 3 F] | Samy fo 0 1 1 0 1 Oh 0 6 B+ F. 4 (Al=(M(OP)? | Ti) jooeoow | ©) )SOMO4+ 1, were peo ppt cb ae ten i cee te feeb oo lo 10 1 tom mem m0 B mitt (A)= 1, where n= 0~15 i | | g | | a | | 1 | | i ! i i it | r Jae OEE EOEOEOEO_eee

MITSUBISHICMICMPTR/MIPRC) bIE D MM 6249828 OOLP474 419 MNITH MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | : ] suecmanem a! Dente soztpn ' - | — | re contents of rogister A are wanstorrad to regater & Lo | come tng ot tad ga | - |= | re cents eg Aare wate reper - |= | secon tpt Atop Be uses org - 1 = | tne cones et repaar& at uanteea to repstorO ' - = | re contents rege E ae uarsoned to eps” A and regis B | ceiovundescgton | — _Tnmadit es se cond ore X dhe anal et a's ate ores i tenon LY eupcten oe a ooo | - — The immadiaie field vaive ¢ 1s loaded to register Z | w=o | = jane content trpiter¥ are ncremenied by 1 Asa res he coment @ este Y are 07 the men marcton 6 | 1 ewwoue | oy ats nw commis leper ¥ ae acemoned by | Ae ren Re coment coir ¥ ae -15 he nec i § aiopea | - = ane vatong te covets ol MOP) 'o eget A a exci ogc OF peomadSateten egies X a ; + Fn ste ane te ep } - —_ ; Mier exchanging tne contents of MOP} to register _an exclusive logca! OR ss periormed between regisier X and the im | | pit sae jan tees sored mo ope x { (y) 15, to | Ate ‘exchanging the contenis of M(OP' to register A. an exclusive logical OR « periormed between register X and the uy | i mediate eld value | and the result is stored into regisler X i || aaa. time contents of vegiaer¥ ie ncrementes by | an me rest “O° then he next mstuchon s ipDed 1 oj ! Le ee Pate ”

MITSUBISHICMICMPTR/MIPRC) 6&1E D MM 6249828 0017475 355 MEMITY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4.RIT CMOS MICROCOMPUTER | ' Instruction code eos (8P)—(SP)—1, (PCS—(8K(SP)) t * pwhere p=d~7 g aM 0 0 0 0 0 1 0 1 OIG GB Ai1 11 KA)RCA)(MEDP)) Banc 800 80101 10 kB tt tale tareiMBe) Her) 2 (CY) carry ane) 0 01 0 01 4 hw 0 # Gt Y (MDP) I~ 0. wrere j= O~ 3 $ H 5 sz, 00 0 1 0 0 0 hk wm Oo 2 4 1-1 (MOP 0%. where i O~3 § sem 00010011002 6 1 1 tAmMIOR® ze 0 0 0 1 0 0 4 G0 4°G J F*2 2+ (Ale N?, whore n= O~15 Taga 0 1 6 0 0 1 Ot OO B A 1A (B)>-(T2:~T24), (Al-(T23~T20) 8 tam 010001 01 tw 8 BIE 1 kB} UNay~T24), (A}=(H2I=N26) Brae ee Cea i ' (T3y~T39) “FF vw a " Ae

MITSUBISHI (MICMPTR/MIP RC) BLE D MM 6249828 0017476 291 MEMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER SINGLE CHIP ¢-BIT CMOS MICROCOMPUTER | meso || — H if en i a a oo - | = | mtr ne rmcng a esate aici by reat! A and apie! D (0; Oy Ay A As A 8 omen pape 9 | {| ve wants 1egser 8and bet 30 he ROM acess are Hanne orga nan ve mance 6: i | cies oe ot ach gia i une 1 hoy — G11 | ua extn <MI0P! ne sn ep CF 8 atte ope A Bnd Rave ed tr A nd oc og | ley overiows 0 = | tee medi tot ven saan 0 ep A oa econ cay ag CY we sl changed 8 8 ont | | exon Ate the calculation, «me veut does not orton, tne next tron sioped | - 1 any tag Cv met | - 0 cory tag CY w nett00 (cy) =0 * [Wiha contents of ceny flag CY are “O°, the next mstruchon 1s skipped a = nn eth annul tte! come eed pr i - 0/1. | Regie A ncusing the cary flag CY 18 rotated 1 bi tothe righ — anny - = "The inti covtt M.OP- whch ie Beste By ne medi la) 101 ! - — The [-th bit of me contents of MOP . whch 1s the bi speciied by Ine immediate field valve | + reset to 0 i | aw (oP) #0 = "Wine jh bt the contents of MOP. winch the Bt specihed by he emmeciate Held value yo °O" he next mstrcton “where |= 0~3 is skipped (ia) =m (DP)) = econ reps Area winecones MDP even wun wake jen = tne covet pier Ae equ nae nd vue neva maton pes cere | - = The contents of register A and vegisier B are Mansteried to tumer 2 anc the reload register R i - — recom te 2 vowed teagan ete 8 | - | = | rn cnet on puke patod manttoman epee Wate bensanadio repel: hana gir 8 \\ - line contents of register A and register B are translerred to limes 4 and the reload register U And then the contents of tim | | arse rneie-FFe | - — | rn enantio oe tne coat reget ee AYE 9 ELECTRIC a

MITSUBISHICMICMPTR/MIPRC) 61E D MM 6249828 0017477 128 MBMITY MITSUBISHI MICROCOMPUTERS . M34225M1-XXXSP/FP M34225M2-XXXSP/FP | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER : ( ntact end is! i namo feo rerwererser 11) Punesons Tee BO OO DL Dy OF 0 D4| Meaedwemal | an ie ee + a jtwa fo 1 © © 6 01 ¥ sho 8 7]4 74 OW etay {Toa 19 100 0 0 OF Hho B34! 4 \\C@ecay ‘nz ie 100 6 4 1 0 0,0 & G14. 4 l CaF Im) 2, Aner enip. (IIE O B onze 181 © 001 1 04:0 8 B11 cart >, anor sup, (ate ' snz3 99 © 1 O11 1 O10 2 ©5454 i CaF mI >, anor akip. (30 nf es pe § ee ee rd (PCO ag ~ a ie p11 me te me ms ae wit 8 aw! ' i . "V1 te ae a 0 Be bw pm 1 8 (PC) 8g ~ ay Ay ~ Be ~ BMe 10 a M% 8 as om wm 1 8 8 1 (SK(SP))—(PC), (SP)~(SP)4+1 3 (PCy I= 2. (PCI 06 ~ a6 : V0 mma me wt 8 (PCB. (POLI a6 ~ a J omrperme 00101000008 © 2 2 (SKISP))—(PC), (9P)—(SP)+1 1 0 a a a 0 pp pp 1 8 Pp (PE d= p. (PC.)= 04 ~ ae Ay ~ Ao. eee ee aan ea zEe,_a_aTaTaTaTaTToTeE

MITSUBISHICMICMPTR/MIPRC) b1E D Ml 6249828 0017478 Ob4 Menity MITSUBISH! MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER vsnne |S ones - —Tpeconns agua Aw edn coanp - | = |r canta egiter Ae ealorea eter eset © ape | — | w ve tag a1, 0 next insvucton is shipped. Aner sp. 1F fag is revet() (are - |stats mmc ern er er me) - TV ans paguspee nner he oe = | = lemeranaenie sown msiom nn aatees | | | | seataonsesne cone wn cmnangea ote i |oremeencenmemerennemime cnet - | — | subroutine cain page 2 the subrovne at aaaress » of page 215 cated =| ena et eae aa aoe ce }_ 4 - | - [eran ct me narey tbs oa Amennemuegnaptng me nso a | Scone bm eccomoniy aon eer - | — | contin ten etane tam be vt handing eine ome men ovine “tne ves tut pinta (X,Y. 2). cary ag CY. aR Hats, and ne contrucus esznption of LA'LXY nsicben NOP aa aeeeeee ra nmr tnasany ioe wnat - | ses Sn vassevon ne monte me nics sate nu nope ate ” Se GQ, EEE —e— SS SSS

MITSUBISHI(MICMPTR/MIPRC) 6b1E D MM 6249828 0017479 TTO MMITY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4.BIT CMOS MICROCOMPUTER LE a? FOTOS | tanec ose | ) weemene — uu heesens | tes Se, leo vewereee er idler | las 00001001 0f0 4 2]ti1 |is4 | |s0 oo0001017 04/01 511] [C00 ware We om H |no 0 0 001 0 1 0 0/0 1 4)1)1 1010, mnare vim O~ 8 | § | seo je 00 1 0:01 0 010 2 4/2! 2|(DII— 0%, where (vim O~8 i i | ha ! 1 1 | Piet loss CoC) i ps CR i ora fe 1000.01 0 070 8 44.4 iKRMA) ; ‘ar ho 0 1 0 1 8 1 1 O10 & 6 1 1 CA=(FD ‘aK fo oy os ott 10 5 78 ttaetK? suze fo 1 0 0 0111 O10 8 E.t 4 CoNTRIMT? a ee a 19 0 0 0 001 0 110 0 Sit,3 UWE mt ‘ot fo 0 0 6 0 0 1 0 O10 O 4:41 ‘CNTE)~o § sno © 1 0 0 0 4 1 1 10 8 FT. 1 Get = (EXIST 7, Attar ekip, (EXFI= 0 = = 0, Qom 0 2 (INT) =L? i i TAL fo 0 1 0 0 0 0 oO tio 4 48 teat fim oo 1011 or te 8 Bit t HtAD irom 801011 0 0 08s BI! T Kama) g i : § | ssr [eo so to 8 tes 951-1 Lemp d,senm v0 mn Q | sxzi [oo 1 00 0 0 1 010 4 2)]1 1 (SIOF)= 1 2, AnOr ship, (SIOF)—0 | / i ti 1 | } | fyi | foray L i pt a OO EEO

HITSUBISHICMICNPTR/NIPRC) BLE D 6249828 OO1748O 72 MNITY MITSUBISH! MICROCOMPUTERS M34225M1-XXXSP/FP M3422S5M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER t i incon nT! sens saengion Bo co nce poe — Tpeto cnet movant | = re eas than mpnconc) \\ - {| ne pr pet 0 wich a pac by reguter¥ ston anpance j= — | one in pa pot 0 wneh pects by opt Y mea) ! weno =| wens ee pr par wh pati ype 0" 9 net machen moe | where (¥) =0~8 i i = tne woo pr $i tanner A 1 - — The contents of regater A are ovtout to the por F - = Ina wd won wept we watered eee 8 oe trem ram pet K re tra oreie & | curmy = 1 = tata OR pi a tn ee io ape magt na tg NTE 4H: to change ate m whch ator noe i - - " the wtertupt enable fag INTE i reset (0° fo change the slate on wich an mterrupt is ¥BDIed axe) at | evte tte (0,) 1" the B&F aug Vth vet acon mpeed Ate De he De EF Hag He ware O11 wt (wer) = = reneyie- ane neo top 0:04 8-1 Hine ene tne MT pee netnhucten ses ware "0, O11 | ann a = yen 0: 8-0" and Gy 8-9" e evel the IN pn 1" he neato espe were 1" 0, 0400 , oe = tre coun vega ae wae toregaerA i = Tren repute & Fane man apa At antes ores poe tw covet sagutr A we wooed trap | = cmt etn a f=) ame SF ae aa srs ~ “1 ' | ne BF ag he memantine monet ‘Aner te skp the SIOF ig reset 0 | Lj | | | 14 | | a a

MITSUBISHI( MICMPTR/MIPRC) BLE D Ml bL249828 0017481 655 MBNITY MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER i no ae hep Sj tnemanic ee =f i Fonction te «| Dy OF By OB, O_O O_o Meme Z ogy) a OO i i : \\ ! : ay i | | Jie fo 1 2 © 01 0 0 ole & alrit lemme & rata @ 4 9 0 0 1 0 oO 110 B 8it {1 {arnt { 2 os aosr fo 1 0 0 © 0 6 0 1] o 8 1/1) 1 | (ADF~0, AD conversion sar { i id a § noe © 0 0 0 0 0 0 0 O;0 Oo Ol 1} 1 \\(PE—(PC+T By. | i by i ‘eae Forme MOA220NE KOXP. thong we muchas Ger Wom te MOAZ2SMI DOSP (taal roto cate zo8 a } i Fonctions Tea Dy Or % Dy OO O 0 D “mssecimel f a an nn TABP p 0 1 0 0} By be & m0 9 L113 (SKISP))~(PC), (8P)-(8P)+1 : i t (PO,)—P ! i (PO, )= Dz ~ Dy Aa~ Aa i ‘ { (B)—(ROM(PC) )y—4 H fl | (A)=(ROM(PC) ane + ‘ (SP)—-(SP)—1. (PC)—(SK(SP)) . : smote peas er 000 1 1 By pe mw 0 3B 2/21CPeWHp 5. eran eee re 5 i Coa i LBLA Da 00001000 00 t 02/2 ‘(Pew p | va mm a be or Bs welt se | (PCI~ ag ~ ae Aamo ' i . . ' i : ri i, mee 59 0 1 1 1 Bs Be By pol 0 7 Pi? 2. (SKISP)IA(PC), (8PI~(SPH+ 1 ! 1 { §) jp osseaee “|! oe (PCxI~ B. (POI tg ~ to fimmrre 00 1 0 1 0 0 0 a0 & 02! e sKismniner, (orients a (Poa, (PCI ~ Be Army " ae

MITSUBISHICMICMPTR/MIPRC) bLE D MM 6249828 0017482 S5S MENITY . MITSUBISHI] MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-81 CMOS MICROCOMPUTER (-— 5 i - - Saeuwa deus kev ndmee scope > Sco Li uw contin | SEY tates detcpton - | - ‘bia 7~4 of the resicing at the adorent indicated by register A and register D, (Dy Dy Oy As Ar As Ae), OF 8 givan Page P Mecweane regu an 3°00 OM AoE we ees op A When mich | | - | pranch out of page: a beaneh it made tothe adoress auaiksArArAoky which is generated by replacing he lower 4 Os ot | satan sa 9 bye conenanding il ete A ae a TUT |~ [eae EES eee

MITSUBISHI(MICMPTR/MIPRC) b1E D Mm b249828 0017483 42] MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER ABSOLUTE MAXIMUM RATINGS Smo rae. pe SO Rings Veo, Septr vege ee S12 “Aveo Bevin voto AD TX me tage Xe -- 4. Weot 03 v Vor wate Pane Fe, Gt KERB" ST es Tv “Veo tinge Port 8,0 UTE 2 no ae Vi. mut votage Po Var To. TTD LL TSB Ave $0.5 Vo overage Kor i oo Vo Quip! volage Pon F i a — | a ae Yo. 3 Quiet vate Poe 6.0 arimehinatieae Sane Sos en siaadsuvnaa iors “~ ]Yyease 1108 Pa __jpoverceepuaee —_“naeeraayuaeee yest” 2 Tog. Serege temper M0135 © RECOMMENDED OPERATING CONDITIONS ‘1. ~-2-#c) i meee ee ie ee Ves ___ Supply vonage we nes . ae en ae ‘Aveo, Svopi woiwge a MO OT eg _A¥aa ___ Supply votiage tor AO eee ee ee. came neem nen a ee ee eee Mn pat tage Pot JIS UT DL, te aT Vee TH mow vonage Pome 8.0 ee Yow “put wotage Xn. : - 0700 Vo Vin put wattage Por K ~ - 8 No “AVoo Mex. mou vonage RESET — ee Moe Vix 7E aout vonage NTR 0 0209 Me. enol voage Pome SBC BMG wo ee lo peak“ peas ou caver Fone 0. § ae nn ons louipeak _“t peak ovtout curren Pons FONT - aoe ce focang. “Menge pu curenPomO.S ; er. lociayg -U arerage ouput cnet Ports F CTA : ne ery {en Goce encuaang Heawency aa a Mane ELECTRICAL CHARACTERISTICS (tx~-2-8C. voort5~55¥) ro Servo ten : Tet contions nS IE atm Vox 1+ eto vine Bans exh “sgn dima i ni a a Vou. “4° extout vonage Pons 8, D fo ma, oe 27 Vv” cine 1H od coeee Pore 8.0 ce WO te, AE out current Pom —— 2 Wen Aven at wnsetect a Ne 8 mow curr Pot ‘ev at ae Tua Clee Minow etre ay Ta 10 “ta on covert Pra FB. 8, et CNTR, RESET" were ern aan BO) [torn Oxtow umremt eb Pan gm aa | tom __—Outoa curent t of Pee 0.8 Spl Sr ea ST 8 Gi oa capactanes Ope Ti OE 0a too. Seep cuere OO ike ante a nme eperaton TS 2 mk Ye AT input vortage Viner - — owes _ om. pn eis cm sae 1 ma inog "Soy eurant A) 1h. coreiton sma

MITSUBISHICMICMPTR/MIPRC) bLE D MM 62459828 0017484 366 MMITY MITSUBISHI MICROCOMPUTERS M34225M1-XXXSP/FP M34225M2-XXXSP/FP SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Tato aceoacy SSC Ma oI Rurcoen | Ladder resistance vale ee ‘Keowee | Cowersion me teat Vaae___| Reterence mpi vomage a ~_.. A¥e0. Vin = Analog input vottage Voge v BASIC TIMING DIAGRAM a Parameter ~~ panama — n [ow a a oo os | | Pon © output | Be~Be ee Port © Input — Ss A Ce, Gee | Pome KS ious Ee AS SE ED GD GS | mteruptinowt | INT T™X__ XL OK KY CNTR tpt ee {Ce CNTR output centr ee >, es a JaMet! ° OO OQO)OQd)Qd CQO OO OOOO QQ OO EE EEE ————EeEa==E a aaaSVV__aQaLaaa

MITSUBISHICMICMPTR/MIPRC) 61E D MM 6249828 0017485 2T4 MENITY MITSUBISHI MICROCOMPUTERS M3422SM1-XXXSP/FP M34225M2-XXXSP/FP : SINGLE-CHIP 4.817 CMGS MICROCOMPUTER Plastic 30pin 400mil SOIP " Dimennon in ram ait} or —ere mi po | : 7 i wees Ni AN OTA LT iit i 0 sean f——) [ separ | Plastic 3@pin 4S0mil SSOP Oimensen 9 mm Fa a a (OAMNOOOOONONNNON | nce. Fe HUOULN AANA YL ) , Wes) | ssets | 2 Foe wn r bt . .--- --— i astog ier . nase OOOO eeeee