M33281GS-20 MITSUBISHI | Alldatasheet
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\\A sk 8 get P ao git? gate HSI ral CMOS FLOATING-POINT PROCESSING UNIT (M32/FPU) DESCRIPTION TA 12-05 M39281GS-20 is a high-speed floating-point arithmetic LSI PIN CONFIGURATION (BOTTOM VIEW) unit, and support the extended precision data format of PNMLKJHG@FEDCBA IEEE standard. . @00090DDODD900O0G II 2 43 44 45 46 47 48 49 «50 51 52 1 The M33281GS-20 Is designed to give maximum pertorm- 6886 bbb bb Shah 4 Iz - 3 6G 67 88 6 0 5 2 HS GS 2 ance as a coprocessor for M32 family microprocessors ce} g a 8 g a 8 8 8 ij 9 io} g 9 3 (M33220GS-20, M33230GS-20) . In addition to arithmetic 88S 9900 |4 : 7am. 8 4 operations and square roots, it has elementary function in- 000 000 {5 structions, Inner product instructions for fast matrix and vec- § § 8 8 3 6 tor calculations, area discrimination instructions for clipping &és B38 47 discrimination, graphics oriented instructions and many gas maszeics §=696 BS de more. Bo it : 28 M 690 990 |9 2 it in ao 9 : - | en we |” opera (OM ; PEEP gees |" , ertomance ( " 2 operation with M33220GS-20) 3888000000885 8 |u fon oF subtraction ous S60005005000000 |1 Multipulication 0.4548 3 B 4 a R a a a ta g s s a 8 4 Division 1.548 (7% BU B 227 ® 19 18 17 16 15 14 @ Elementary function calculation @ Graphics support - ° Outline 185S8X-A @ Conforms to IEEE754 . © Fast coprocessor interface - © Peripheral device mode specifiable (for use when MPU @ Comprehensive system functions lacks coprocessor interface) @ Softwave and system support @ Package 135 pin PGA ~ @ Variety of instruction types . : 31 arithmetic related APPLICATION + 21 control related . Sclentific and technical calculations, éngineering diagram © 16 floating point operation registers (80-bit) processing PIN ASSIGN [Pw cope] PIN | NAME [PIN cone] PIN | [Pwv cone] PIN | NAME [PIN CODE] PINT NAME [PIN CODE] PIN | NAME [PIN CODE] PIN | NAME | Pa [tf fae [ oi [107| Ow | Ho [iz] Dw | ts | aT Veo | NO | 73 Ves | [ 2) Ae | etn | ez] ean | ors [66] Ow | Ha [i] Veo | Mi | 42] Vee | nto [78 | Veo | [as [a | wack |ei2 [oa] cpste[ ore [17] Voo | Hts | 70[ Vos | wa | @7|rorsts wit | 7 Veo | aa [4 ec, [era | ot [Veo [et [49 { Voo | Hi4 | 21 [ Voo | ma [ize{ uo [wiz | 76] Veo _| [as | s| ww [ 614 | 15] Voc { e2 | o| d, [ot [45| bd, | ma |iza| crip | nia | 75 | Ves | | as | | sate | ct | if veo | es fist] oo | [oof On | ms fiz] ire | Nia | [car [7 Vea [2] 88 E12 [108] De_| [bie prat | vent _| | as | a[ Nc] co | | Aw | st2 [Ose | m7 _[i20| Ves | r2 | 39 | RESET | as_| a Ves | c4# [98] Co | { 18 si3 EE ae ee | S| Boy | rt | al oy | ta | 22] Ow | [118 | Veo [| p4 | a7 | Ves _| [Ait |W] Veo | 06 [100] Veo [Fe | 93[ oy [et [a [ Ves | mio [17 | Veo | ps | 36 sizie | [ate | 12] ves [or [ror] par, | Fs [iso , | ke | oo] de | mit |i6| Vo | pe | a5] No | | ars _[ 13] opste | 8 [102 | Veo | F12 [109] Ome [Ks [126] Ow | wiz [15] "Veo | pr [4] Voo | [ais [14] Veo | co [103] Veo | FIs | 68] Voo | Ki2 [113] Ds | mis | 74] Voo | Pa | [81 |'s2] Ves | cio [ios [meray fia | 19] Ves [72] Ou | mia | 25] Dy | Po | Ves [var [ss] veo [ent [ies] _oc | oi [a7 [23 | ves [at [rorsta| p10 | 31 | Foros | es |s4| Aw 106 ors Se | 92 ee Veo | Shae} tel Veo HS ee fe Dv | 129 | te | 8| Dw | Na | as] uo | pi2 | 2 | 85 [s6| Bs | ota [16] Vos | aie [0] Oe | ts [1a] Ves [na [a4| crib, | Pia [2] No | [86 [s7| Veo | ot [60] Ves [Gta | 60] Ou [t+ [195] Voo | NS [83] Voo | Pts [27 | Veo | e788 | BAT: [d, [ ara [20 [Des | uit [ta [rorste| Ne | e2| Voo | | [| Be _| 69] Vos Lie} tel pe | ee Pi ee fo at ss + —t+- + [so] cof ope | om [i [ves [He [si] dw | vis re [ [| ee Note. Gicro™ Ig a trademark of the G-MIGRO group for the TRON specification microprocessors. 8-12 9 MITSUBISHI ELECTRIC.
CMOS FLOATING-POINT PROCESSING UNIT (M32/F PU) - OC eee BLOCK DIAGRAM (MIGROSEQUENCER) Sewn PROTOCOL CONTROLLER . iz doninouuen MICRO ROM PIPELINE MANAGER ROM FORMAT eRe en EXPONENT PROCESSOR| DATA BUS “ee (BUS CONTROL UNIT)