M32000D3FP

M32000D3FP MITSUBISHI | Alldatasheet

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Technical content

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER

FEATURES

address bus: 24 bits control registers: 32 bits x 5

• Multiply-accumulate operation unit (DSP function instruction)
• Internal memory controller
• Programmable I/O ports /CPU sleep mode INT and SBI

APPLICATIONS

Portable equipment, Still camera, Navigation system, Digital instrument, Printer, Scanner, FA equipment

DESCRIPTION

The M32000D3FP is a new generation microcomputer with a 32-bit CPU and built-in high capacity DRAM. Using this device it is possible to implement the complex applications of the multimedia age with high performance and low power consumption. The M32000D3FP contains 1M bytes of DRAM and 4K bytes of cache memory. The CPU is implemented with a RISC architecture and has a high performance figure of 52.4 MIPS (at an internal clock rate of 66.6 MHz ). Memory for main storage is provided internally to the device eliminating external memory and associated control circuits thus reducing overall system noise and power consumption. The CPU, internal DRAM and cache memory are connected by a 128-bit, 15 ns/cycle internal bus which virtually eliminates transfer bottlenecks in between the CPU and the memory. The M32000D3FP internally multiplies the frequency of the input clock signals by four. For an internal operating frequency of 66.6 MHz the input clock fre- quency is 16.65MHz. A 16-bit data and 24-bit address bus are the M32000D3FP's exter- nal bus and the interface to external peripheral controllers. When the hold state is set, the internal DRAM can be accessed from an exter- nal device. A 3-chip basic system configuration using the M32000D3FP is the device itself plus an ASIC as a peripheral controller and a program ROM. Execution starts from the reset vector entry on the external ROM after power on, a program requiring high speed execution is then transferred to internal DRAM and this is then executed. The M32000D3FP also has a slave mode additional to its master mode. When set to slave mode the M32000D3FP can be used as a coprocessor. In this mode it does not access its external bus immediatly after reset, but waits for the master to start its operation. MITSUBISHI MICROCOMPUTERS M32000D3FP

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP PIN CONFIGURATION (TOP VIEW) 100 M3 2000D 3FP 100-pin QFP/0.65 mm pitch VC C A19 A18 A17 A16 VS S A15 A14 VC C ST BY DC BS PLLVCC PLLVSS PLLC AP VS S CL KIN PP 1 PP 0 CS A13 A12 VS S A11 A10 VC C VC C A30 A29 A28 A27 VS S A26 BC H BC L SID VC C R/W VC C VS S VS S VC C RS T M/S A25 A24 VS S A23 A22 A21 A20 VC C VS S VC C VC C VS S VS S VC C HREQ SB I INT HAC K VS S VS S D1 5 D1 4 D1 3 D1 2 VC C BURS T ST VC C VSS VC C VSS VC C WK U P VC C D1 1 D1 0 VS S Note:Connect *1 pins to VCC. Connect *2 pins to VSS.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP BLOCK DIAGRAM M 32000D3FP CLKIN DRAM (1M bytes) me mo ry controller PLL clock generating circuit 32 bits 32 bits PC ALU shift m ultiply- accumu late unit 32 x 16 bits MUL 56-bit -AC C register 32 bits x cache mem ory (4K bytes) instruction queue (128 bits x 2 stages) data selector 32 bitsÛ 128 bits instruction decoder load/ store 128 128 128 128 128 M32R CPU core PP1 program m able I/O port PP0 A8 - A30 D0 - D15 BCL BS ST R/W BURST DC HR EQ HACK CS SID external bus interface unit 128 bitsÛ 16 bits M/S RST SBI INT WK U P 128-bit internal bus STBY BCH PLLCAP PLLVCC PLLVSS

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP FUNCTIONS function block characteristics CPU core • bus specification basic bus cycle: 15 ns (internal operation at 66.6 MHz) logical address space: linear 4G bytes ____ ____ external address bus: 24 bits (external output pin: A8 to A30, BCH, BCL) external data bus: 16 bits

• implementation: 5-stage pipeline
• core internal: 32 bits
• register configuration general-purpose registers: 32 bits 5 16 control registers: 32 bits 5 5
• instruction set 16-bit/32-bit instruction format 83 instructions/6 addressing modes
• multiply-accumulate operation built in internal DRAM • 8M bits (1M bytes) cache memory • 4K bytes (internal instruction/data cache mode, instruction cache mode, cache-off mode) memory controller • cache control
• internal DRAM control, refresh control
• power management function (standby mode, CPU sleep mode selection control) programmable I/O port • two programmable I/O ports

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP PIN FUNCTION DIAGRAM CLKIN RST M32000D3FP clock system control VCC VSS 16 15 A8 - A30address bus D0 - D15data bus HREQ HACK SID bus control BCH BS DC BCL interrupt input PP0 PP1 ST R/W BURST CS M/S programmable I/O port SBI INT WKUP STBY PLLCAP PLLVCC PLLVSS

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP PIN DESCRIPTION (1/3) type pin name name I/O function power VCC power source – All power source pins should be connected to VCC. source VSS ground – All ground pins should be connected to VSS. clock CLKIN clock input input Clock input pin. The M32000D3FP has an internal PLL multiplier circuit, and an input clock which is 1/4 of the internal operating frequency (when the internal operating frequency is 66.6 MHz, the CLKIN input is 16.65 MHz). PLLCAP C connection – Connects a capacitor for the internal PLL. for PLL PLLVCC power source – Power source for the internal PLL. for PLL PLLVSS ground – Ground for the internal PLL. for PLL system ____ RST reset input Internally resets the M32000D3FP. It is also used to return from control standby mode and CPU sleep mode. M/S master/slave input Sets the M32000D3FP default operation to either system bus master (M/S = "H") or bus slave (M/S = "L"). When the M32000D3FP is set to bus slave, it does not carry out a reset vector entry fetch after a reset._ The setting of M/S cannot be changed during operation. Keep at either an "H" or an "L" level. WKUP wakeup input Input pin to request return from standby mode._____ This is only accepted when STBY is "L" level. It generates the wakeup interrupt. STBY standby output Indicates that the M32000D3FP has switched to standby mode. An "L" level is output while the device is in standby mode. address A 8 to A30 address bus I/O The M32000D3FP has a 24-bit address (A8 to A31) bus for a 16 MB bus address space. A31 is not output. During the write cycle, the____ valid byte positions on the 16-bit data bus are output as BCH or____ BCL. During the read cycle, the 16-bit data bus is read, however, only data in the valid byte positions is transferred to the M32000D3FP. Address bus pins are bidirectional. When accessing the internal DRAM from an external bus master while the M32000D3FP is in the hold state, input the address from the system bus side. data bus D0 to D15 data bus I/O 16-bit data bus for connecting to external devices. (Hi-z)* * (Hi-z): This pin goes to high-impedance in the hold state. (Hi-z)*

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP PIN DESCRIPTION (2/3) type pin name name I/O function bus SID space I/O Space identifier between user space and I/O space. control identifier (Hi-z)* SID = "L": user space SID = "H": I/O space SID is bidirectional. When accessing the internal DRAM from outside the M32000D3FP while the M32000D3FP is in the hold state, input an "L" level from the system bus side. BCH, BCL byte control I/O Indicates the valid byte positions of transferred data. (Hi-z)* BCH corresponds to the MSB side (D0 to D7), and BCL corresponds____ to the LSB side (D8 to D15). During a read bus cycle, both BCH____ During a write bus cycle, either BCH and/or BCL is an "L" level depending on the byte(s) to be written. When accessing the internal DRAM from an external bus master, the byte control signal is input from the system bus side. BS bus start output When the M32000D3FP drives an external bus cycle, BS goes to an "L" level at the start of the bus cycle.__ In burst transfer, BS goes to the "L" level for each transfer cycle. When accessing internal resources such as an internal__ DRAM or internal I/O register, BS is not output. ST bus status output Indicates whether the bus cycle that the M32000D3FP drives is an instruction fetch access cycle or an operand access cycle. ST = "L": for instruction fetch access ST = "H": for operand access ST = undefined: when idle R/W read/write I/O Outputs R/W to identify whether the external bus cycle a read or a write cycle. When accessing the internal DRAM from an external__ bus master, R/W is input from the external bus. BURST burst output The M32000D3FP drives two consecutive bus cycles to access 32-bit data allocated on the 32-bit word boundary. For instruction fetches, it drives 8 (max.) consecutive cycles (8 cycles in instruction cache mode) to data on the 128-bit boundary.______ During these consecutive bus cycles, BURST goes to "L" level. When accessing 32-bit data, an "L" level followed by an "H" level is output from address A30, because the MSB-side 16 bits are accessed prior to the LSB-side 16 bits. When accessing 128-bit data, the addresses are output from an arbitrary 16-bit aligned address and wraparound within a 128-bit aligned boundary. * (Hi-z): This pin goes to high-impedance in the hold state. (Hi-z)* (Hi-z)* (Hi-z)* (Hi-z)*

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP type pin name name I/O function bus DC* data complete I/O When the M32000D3FP drives an external bus cycle, it control automatically inserts wait cycles until DC is input by the slave (cont.) device in the system bus. When the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus master, the M32000D3FP__ outputs DC to notify to the external bus master that the bus cycle to the internal DRAM has been completed. HREQ hold input Bus right request input pin of the system bus. When HREQ is an "L" level, the M32000D3FP switches to the hold state. HACK hold output Indicates that the M32000D3FP has switched to the hold state acknowledge and releases the bus right of the system bus to the requestor. CS chip input Signal input to the M32000D3FP when it is in the hold state to select request access to the internal DRAM from an external bus master.__ When an "L" level is input to CS, the M32000D3FP accesses the internal DRAM at the address input via the address pins. interrupt ___ SBI system input ___ System break interrupt input pin. The SBI is not masked by the controller break IE bit in the PSW register. It is also used to return from CPU interrupt sleep mode and to request the start of operation in slave mode. ___ INT external input External interrupt request input pin. It is also used to return from interrupt CPU sleep mode and to request the start of operation the slave mode. programm- PP0, PP1 port I/O Two programmable I/O ports. able I/O port __ __ * The DC pin becomes an output pin when the CS signal is input to the M32000D3FP. PIN DESCRIPTION (3/3) (Hi-z)

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP FUNCTIONAL DESCRIPTION CPU The M32R CPU has 16 general-purpose registers, 5 control regis- ters, an accumulator and a program counter. The accumulator is of 64-bit width. The registers and program counter are of 32-bit width. General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain data and base addresses. R14 is used as the link register and R15 as the stack pointer (SPI or SPU). The link register is used to store the return address when executing a subroutine call instruction. The interrupt stack pointer (SPI) and the user stack pointer (SPU) are alternatively represented by R15 depending on the value of the stack mode bit (SM) in the processor status word register (PSW). Control registers There are 5 control registers which are the processor status word register (PSW), the condition bit register (CBR), the interrupt stack pointer (SPI), the user stack pointer (SPU) and the backup PC (BPC). The MVTC and MVFC instructions are used for writing and reading these control registers. 310 R10 R11 R12 R13 R14 (link register) R15 (stack pointer) 310 (see note) Note: The interrupt stack pointer (SPI) and the user stack pointer (SPU) are alternatively represented by R15 depending on the value of the stack mode bit (SM) in the PSW. Fig. 1 General-purpose registers processor status word register condition bit register interrupt stack pointer user stack pointer backup PC 310 CR0 CR1 CR2 CR3 CR6 (see notes) CRn Notes 1: CRn (n = 0 - 3, 6) denotes the control register number. 2: The MVTC and MVFC instructions are used for writing and reading these control registers. PSW CBR SPI SPU BPC Fig. 2 Control registers

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Processor status word register: PSW (CR0) The processor status word register (PSW) shows the M32R CPU status. It consists of the current PSW field, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field is made up of the stack mode bit (SM), the interrupt enable bit (IE) and the condition bit (C). The BPSW field is made up of the backup stack mode bit (BSM), the backup interrupt enable bit (BIE) and the backup condition bit (BC). Note: "init." ...initial state immediately after reset "R " .... : read enabled "W ".... : write enabled D bit name function init. R W

16 BSM (backup SM) saves value of SM bit when EIT occurs undefined

17 BIE (backup IE) saves value of IE bit when EIT occurs undefined

23 BC (backup C) saves value of C bit when EIT occurs undefined

24 SM (stack mode) 0: uses R15 as the interrupt stack pointer 0

1: uses R15 as the user stack pointer

25 IE (interrupt enable) 0: does not accept interrupt 0

1: accepts interrupt

31 C (condition bit) indicates carry, borrow and overflow resulting 0

from operations (instruction dependent) Fig. 3 Processor status word register 16 17 23 24 25 3115870 SM IE CBCBSM BIE 00000000000000000000000000PSW BPSW field PSW field

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Condition bit register The condition bit register (CBR) is a separate read-only register which contains a copy of the current the condition bit (C) in the PSW. This register is read-only. An attempt to write to the CBR with the MVTC instruction is ignored. Interrupt stack pointer, User stack pointer The interrupt stack pointer (SPI) and the user stack pointer (SPU) retain the current stack address. The SPI and SPU can be accessed as the general-purpose register R15. R15 switches between repre- senting the SPI and SPU depending on the value of the stack mode bit (SM) in the PSW. Backup PC The backup PC (BPC) is the register where a copy of the PC value is saved when EIT occurs. Bit 31 is fixed at "0". When EIT occurs, the PC value immediately before EIT occurrence or that of the next in- struction is set. The value of the BPC is reloaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC become "00" on returning (It always returns to the word boundary). 310 00000000000000000000000000CBR C00000 310 BPCBPC 0 Fig. 4 Condition bit register, interrupt stack pointer, user stack pointer and backup PC 310 SPI SPU SPU 310 SPI

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Accumulator The accumulator (ACC) is a 64-bit register used for DSP type func- tions. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The high-order 32 bits (bit 0 - bit 31) can be set with the MVTACHI instruction and the low-order 32 bits (bit 32 - bit 63) can be set with the MVTACLO instruction. Use the MVFACHI , MVFACLO and MVFACMI instructions for reading from the accumu- lator. The high-order 32 bits (bit 0 - bit 31) are read with the MVFACHI instruction, the low order 32 bits (bit 32 - bit 63) with the MVFACLO instruction and the middle 32 bits (bit 16 - bit 47) with the MVFACMI instruction. Program counter The program counter (PC) is a 32-bit counter that retains the ad- dress of the instruction being executed. Since the M32R CPU in- struction starts with even-numbered addresses, the LSB (bit 31) is always "0". Fig. 5 Accumulator 310 PCPC 0 Fig. 6 Program counter 32 48 633116150 4778 ACC (see note) read/write range with MVTACLO or MVFACLO instruction read/write range with MVTACHI or MVFACHI instruction read range with MVFACMI instruction Note: Bits 0 - 7 are always read as the sign-extended value of bit 8. An attempt to write to this area is ignored.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Data types Signed and unsigned integers of byte (8 bits), halfword (16 bits), and word (32 bits) types are supported as data in the M32R CPU instruc- tion set. A signed integer is represented in a 2's complement format. Data formats Data size of a register of the M32R CPU is always a word (32 bits). Byte (8 bits) and halfword (16 bits) data in memory are sign-extended (the LDB and LDH instructions) or zero-extended (the LDUB and LDUH instructions) to 32 bits, and loaded into the register. Word (32 bits) data in a register is stored to memory by the ST in- struction. Halfword (16 bits) data in the LSB side of a register is stored to memory by the STH instruction. Byte (8 bits) data in the LSB side of a register is stored to memory by the STB instruction. Data stored in memory can be one of these types: byte (8 bits), halfword (16 bits) or word (32 bits). Although the byte data can be located at any address, the halfword data and the word data can only be located on the halfword bound- ary and the word boundary, respectively. If an attempt is made to access data in memory which is not located on the correct boundary, an address exception occurs. signed byte (8-bit) integer unsigned byte (8-bit) integer signed halfword (16-bit) integer S S S S: sign bit unsigned halfword (16-bit) integer signed word (32-bit) integer unsigned word (32-bit) integer Rn 0 31 < load > byte Rn 0 31 halfword Rn 0 31 word sign-extention (LDB instruction) or zero-extention (LDUB instruction) from memory (LDB , LDUB instruction) < store > Rn 0 31 byte Rn 0 31 halfword Rn 0 31 word to memory (STB instruction) to memory (STH instruction) to memory (ST instruction) from memory (LDH , LDUH instruction) from memory (LD instruction) sign-extention (LDH instruction) or zero-extention (LDUH instruction) <data format in a register> <data format in memory> Fig. 7 Data type Fig. 8 Data format address byte halfword word + 0 + 1 + 2 + 3 byte byte byte byte halfword halfword word 7 8 31161515870 16 23 24

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Address space The M32000D3FP logical address is 32-bit wide and offers 4 GB linear space. The M32000D3FP has address spaces allocated as shown below. The user space is specified by SID = 0 (H'0000 0000 to H'7FFF FFFF). The area available to the user is 16 MB from address H'0000 0000 to address H'00FF FFFF. The I/O space is specified by SID = 1 (H'8000 0000 to H'FFFF FFFF). The area available to the user is 16 MB from address H’FF00 0000 to address H'FFFF FFFF. The I/O space cannot be cached. These areas below are allocated in each space.

• User space internal DRAM area external area
• I/O space user I/O area system area internal I/O area Fig. 9 Address space H'0000 0000 H'FFFF FFFF < logical space > EIT vector entry (reset interrupt)H'7FFF FFFF H'8000 0000 I/O space (SID = 1) user space (SID = 0) < physical space > internal DRAM area (1M bytes) H'0000 0000 H'000F FFFF H'0010 0000 H'00FF FFFF external area (15M bytes) logical address 0 : H'00 0000 0 : H'0F FFFF 0 : H'10 0000 0 : H'FF FFFF (16M bytes) (16M bytes) H'FF00 0000 H'FF7F FFFF H'FF80 0000 H'FFFF FFFF H'FFBF FFFF H'FFC0 0000 1 : H'00 0000 1 : H'BF FFFF 1 : H'FF FFFF 1 : H'C0 0000 1 : H'7F FFFF 1 : H'80 0000 user I/O area (8M bytes) system area (4M bytes) internal I/O area (4M bytes) physical address (24 bits) EIT vector entry (except for reset interrupt) SID physical address (24 bits)SID logical address logical address

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP The user I/O area is 8 MB from address H'FF00 0000 to address H'FF7F FFFF. When this space is accessed, the control signals to access external devices are output. The system area is 4 MB from address H'FF80 0000 to address H'FFBF FFFF. This area is reserved for development tools such as in-circuit emulators or debug moni- tors. The user cannot use this area. The internal I/O area is 4 MB from address H'FFC0 0000 to address H'FFFF FFFF. The memory controller and programmable I/O port registers are allocated in this area. The internal DRAM (1 MB) is allocated from address H'0000 0000 to address H'000F FFFF. The EIT vector entry (other than the reset interrupt) is allocated in the address H'0000 0000 to address H'0000 008F of this area. The internal DRAM is connected to the M32R CPU via a 4 KB cache memory with a 128-bit bus. When the M32000D3FP is in the hold state, the internal DRAM can be accessed from an external bus master by inputting control signals. The external area consists of 15 MB from address H'0010 0000 to address H'00FF FFFF. When this space is accessed, the control sig- nals to access external devices are output. The bottom 16 bytes in this area (H'00FF FFF0 to H'00FF FFFF) are the reset interrupt EIT vector entry. Fig. 10 Internal I/O space memory map H'FFC0 0000 H'FFFF FFE0 H'FFFF FFE4 H'FFFF FFE8 H'FFFF FFF8 H'FFFF FFFC logical address 0 31 +3 address (reserved) +2 address+1 address+0 address PPCR1 PPDR0 memory controller PPDR1 (reserved) MPMR MCCR PPCR0 H'FFFF FFEC MLCR: lock control register MPMR: power management control register MCCR: cache control register programmable I/O port PPCR0: programmable I/O port direction control register 0 PPCR1: programmable I/O port direction control register 1 PPDR0: programmable port data register 0 PPDR1: programmable port data register 1 MLCRH'FFFF FFF4

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP EIT events are shown below.

• Reserved instruction exception (RIE) The reserved instruction exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected.
• Address exception (AE) The address exception (AE) occurs if an attempt is made to access an unaligned address with either a load instruction or a store instruc- tion.
• Reset interrupt (RI) ___ The reset interrupt (RI) is always accepted when the RST signal is input. It has the highest priority.
• Wakeup interrupt (WI) The wakeup interrupt (WI) is accepted when the WKUP signal is input while the M32000D3FP is in standby mode. It is only used to return from standby mode.
• System break interrupt (SBI) ___ The system break interrupt (SBI) is an interrupt request from the SBI pin. It is used when a break in power source or an error from an external watchdog timer is detected. It is also used to return from CPU sleep mode and to start an M32000D3FP set to slave mode.
• External interrupt (EI) ___ The external interrupt (EI) is an interrupt request from the INT pin. It is used by an interrupt from the external peripheral I/O and can be masked by the IE bit in the PSW register. It is also used to return from CPU sleep mode and to start an M32000D3FP set to slave mode.
• Trap The trap (TRAP) is a software interrupt which is generated by ex- ecuting the TRAP instruction. A total of 16 EIT vector entries are available for operands 0 to 15 of the TRAP instruction. Fig. 11 EIT events EIT Exception Reserved Instruction Exception (RIE) Address Exception (AE) Interrupt Reset Interrupt (RI) Wakeup Interrupt (WI) System Break Interrupt (SBI) Trap Trap (TRAP) External Interrupt (EI) EIT While the CPU is executing a program, sometimes it is necessary to suspend execution, because a certain event occurs, and execute another program. These kinds of events are referred to as EIT (Ex- ception, Interrupt, Trap).
• Exception The event is related to the context being executed. It is generated by errors or violations that occur during instruction execution. With the M32000D3FP, the address exception (AE) and reserved instruction exception (RIE) are of this type.
• Interrupt The event is not related to the context being executed. It is gener- ated by an external hardware signal. With the M32000D3FP, the external interrupt (EI), system break interrupt (SBI), wakeup inter- rupt (WI) and reset interrupt (RI) are of this type.
• Trap This is a software interrupt which is generated by executing the TRAP instruction. It is intentionally added to the program by the program- mer, as a system call.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Internal memory system The memory system built into the M32000D3FP has the following characteristics.

• internal 8M-bit (1M-byte) DRAM
• internal 4K-byte cache memory
• CPU, cache and internal DRAM are connected by a 128-bit bus
• selectable cache memory operation mode – internal instruction/data cache mode – instruction cache mode – cache-off mode When the internal instruction/data cache mode is selected, the cache memory functions as a cache for both instruction and data from the internal DRAM, and caches all bus access to the DRAM. This mode is for a system which uses the internal DRAM as main memory. Trans- fer between the M32R CPU, cache memory and internal DRAM is always carried out in blocks of 128 bits. Caching is carried out by the direct map method. Writing is by the copy back method. When the M32000D3FP access destination is an external space, data transfer between the M32R CPU and the external device is car- ried out via the bus interface unit (BIU). The BIU has a 128-bit data buffer which converts the bus width between the 128-bit bus in the M32000D3FP and the external bus. Caching is not applicable in this case of data transfer. When accessing the internal DRAM from an external bus master, and a cache hit occurs (the accessed data is inside the cache), data transfer between the cache memory and the external bus via the BIU is carried out. When a cache miss occurs, (the accessed data is not inside the cache) data transfer is carried out between the internal DRAM and the external bus via the BIU without cache replacement. cache control register (MCCR) < address: H'FFFF FFFF> D24 D25 D26 D27 D28 D29 D30 D31 CP CM0 CM1 <at reset: H'01> D bit name function R W

24 C P 0: no purge 0

(cache purge) 1: purge 25 - 29 Not assigned. 0 30, 31 CM0, CM1 00: cache mode (cache mode) is not changed 01: cache-off mode 10: internal instruction/data cache mode 11: instruction cache mode W = ... write enabledW = : write disabled 128 external bus (16 bits) external bus interface M32000D3FP 128 128 instruction/ data cache DRAM BIUCPU Fig. 12 Cache control register Fig. 13 Internal instruction/data cache mode

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP When the instruction cache mode is selected, the cache functions as an instruction cache for the internal DRAM or the external memory, and caching is carried out for instruction fetch access. This mode is designed for use when an external ROM is used as program memory and the internal DRAM is used as data memory, or when instructions are located in the internal DRAM. Caching is carried out by the direct map method. When instruction codes in the user space are overwrit- ten by the external bus master or another source, instruction code coherency in the cache memory is not guaranteed. Furthermore, caching is not applied when accessing the internal DRAM from the external bus master. When the cache-off mode is selected, the M32000D3FP internal memory system is configured as follows. In this mode, caching is not applied, and all bus cycles are directly to the internal DRAM or exter- nal bus. external bus (16 bits) external bus interface M32000D3FP 128 instruction cache BIU 128 DRAM CPU 128 external bus (16 bits) external bus interface M32000D3FP 128 DRAM BIUCPU Fig. 14 Instruction cache mode Fig. 15 Cache-off mode

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Bus interface unit (BIU) The M32000D3FP has the following signals related to the external bus.

• Address (A8 to A30) The M32000D3FP has a 24-bit address bus (A8 to A31) correspond- ing to a 16 MB address space. Of these, A31 (the LSB) is not output externally. In write cycles, the validity of the two bytes output on the___ ___ 16-bit data bus is indicated by BCH and/or BCL. In read cycles, the 16-bit data bus is always read, however, only data in the valid byte position in the M32000D3FP is transferred. The address pins are bidirectional. If the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus master, the address signal is input from the system bus side.
• Space identifier (SID) The space identifier is used to specify user space and I/O space. user space: SID = "L" I/O space: SID = "H" If the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus master, the "L" level should be input to SID from the system bus side.___ ___
• Byte control (BCH, BCL) Byte control signals indicate the byte position of valid data trans-___ ferred of the external bus cycle. BCH corresponds to the MSB side________ (D0 to D7), and BCL corresponds to the LSB side (D8 to D15). Dur-___ ___ ing the bus read cycle, both BCH and BCL are an "L" level. During___ ___ the bus write cycle, BCH and/or BCL go to an "L" level depending on the bytes to be written. If the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus master, the byte control signal is input from the system bus side.
• Data bus (D0 to D15) The M32000D3FP has a 16-bit data bus to access external devices. If the M32000D3FP is in the hold state and the internal DRAM is accessed from an external bus master, the data bus is used as a data I/O bus from the system bus side.
• Bus start (BS) When the M32000D3FP drives the bus cycle to the system bus, an "L" level is output to BS at the start of the bus cycle. Also, for a burst __ __ transfer, the BS signal is output for each transfer cycle. The BS sig- nal is not output when accessing internal resources such as the in- ternal DRAM or internal I/O registers.
• Bus status (ST) The ST signal identifies whether the bus cycle the M32000D3FP is driving is an instruction fetch cycle or an operand access cycle. instruction fetch access: ST = "L" operand access: ST = "H" hold: ST = high-impedance idle: ST = undefined
• Read/write (R/W) The M32000D3FP outputs a R/W signal to identify whether the ex- ternal bus cycle is a read or write operation. When accessing the internal DRAM from an external bus master, a R/W signal is input from the system bus side. read bus cycle: R/W = "H" write bus cycle: R/W = "L"
• Burst (BURST) The M32000D3FP drives two consecutive bus cycles to access 32- bit data located on the 32-bit boundary. In instruction fetching, it drives a maximum of 8 (fixed to 8 cycles in instruction cache mode) con- secutive read cycles to access data located on the 128-bit boundary. While driving these consecutive bus cycles, the M32000D3FP out- puts "L" level to BURST. When accessing 32-bit data, the address of the MSB-side 16 bits are output before the address of the LSB side 16 bits. When accessing 128-bit data, the addresses are output for every access cycle from the arbitrary 16-bit aligned addresses to wraparound within the 128-bit boundary.
• Data complete (DC) When starting an external bus cycle, the M32000D3FP automati- cally inserts wait cycles until the DC signal is input from external. Wait control using the DC signal is effective also for bus cycles dur- ing burst transfer. When the M32000D3FP is in the hold state and if __ __ the CS signal is input, the M32000D3FP outputs the DC signal to notify the external bus master that internal DRAM access is com- plete.
• Hold control (HREQ, HACK) The hold state is the state when the external bus access stops and all pins go to a high-impedance state. However, the internal DRAM can be accessed while the external bus is in the hold state. To put the M32000D3FP into the hold state, input an "L" level to HREQ. When the hold request is accepted and the M32000D3FP enters the hold state, an "L" level is output from HACK.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Read and write operations of the M32000D3FP are carried out using the address bus, data bus, and the R/W, BCH, BCL and DC signals. When reading, the R/W signal goes to an "H" level, and the BCH and BCL signals go to an "L" level. The CPU reads the data in the valid ___ byte positions. When writing, an "L" level is output from R/W, and BCH and BCL are output according to the valid byte positions, so as to specify the byte positions for writing into an external device. Keep DC signal at the "H" level during idle cycles. idle read "H" "H" CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W idleread idle write idlewrite CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W "H" "Hi-z" "Hi-z" "Hi-z" "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Fig. 16 Read/write timing (two no-wait accesses)

• Internal DRAM access control (CS) The internal DRAM can be accessed when CS is driven to an "L" ____ level after the M32000D3FP enters the hold state (HACK = "L"). To access the internal DRAM from external, the following signals from the system bus side should be controlled.
• A8 to A30 Input internal DRAM addresses to be read or written.___ ___
• BCH, BCL Specify the byte position of data to be written into the internal DRAM. BCH corresponds to the MSB side (D0 to D7), and BCL corresponds to the LSB side (D8 to D15).
• R/W ___ Specify read or write operation. When reading, R/W = "H". When writing, R/W = "L".
• D0 to D15 16-bit data I/O bus.
• SID When accessing the internal DRAM from an external bus mas- ter, an "L" level is input to SID to specify user space.
• DC This signal notifies to an external bus master that the internal DRAM access is complete. When access is complete, an "L" level is output to DC. Table 1 Pin condition in hold state pin name pin condition or operation ST, R/W , BS, BURST D 0 - D15 output when internal DRAM is read__ by an external bus master (CS = "L",__ R/W = "H"), otherwise high-impedance D C output when internal DRAM is accessed by an external bus master__ (CS = "L"), otherwise high-impedance HACK output "L" other pins normal operation

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP When an "L" level is input to DC, the next bus cycle is processed and wait cycles are inserted until this point. Keep the DC signal at the "H" level, unless otherwise necessary. When a write cycle comes imme- diately after a read cycle, the M32000D3FP inserts an idle cycle to prevent a collision with data on the system bus. The same applies to write cycles (burst write access) immediately after a burst read cycle. Fig. 17 Read/write timing (two one-wait accesses) Fig. 18 Automatic idle cycle insertion between consecutive read and write cycles "H" "H" idle read CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W idleread "H" idle write idlewrite CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W "Hi-z" "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Keep DC signal at the "H" level during idle cycles. "H" idle CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W idleread write idle Note: "Hi-z" means high-impedance, and indicates sampling timing. Keep DC signal at the "H" level during idle cycles.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP The M32000D3FP outputs the BURST signal and carries out a burst transfer when reading "the word-size data aligned on the 32-bit bound- ary" or "a maximum 4 words of instructions aligned on the 128-bit boundary". The BURST signal is synchronized with the CLKIN falling edge of the first bus access cycle and output "L" level. It returns to an "H" level synchronized with the first CLKIN falling edge of the last bus access cycle. Addresses A8 to A30 are output for each cycle. When burst reading 32-bit data, the MSB-side 16-bit read bus cycle is carried out first followed by the LSB-side 16-bit read bus cycle. When the cache memory operation mode is the instruction cache mode, and burst reading of the instructions within the 128-bit bound- ary for cache replacement occurs, the bus cycle is driven a fixed 8 times from an arbitrary 32-bit boundary address and to wraparound within the 128-bit boundary. When other than the instruction cache mode is selected and burst reading a set of instructions of less than 128 bits, consecutive bus cycles are driven from an arbitrary 32-bit boundary address as the top to the 128-bit line (A28 to A30 = "111"). Fig. 20 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait) Fig. 19 1-word (32-bit) burst read timing (1-0 wait) "H" idle CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W burst read (1 word) idle "Hi-z" "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Wait cycles can be inserted even when burst transferring by setting DC = "H". Keep DC signal at the "H" level during idle cycles. Wait cycles can be inserted even when burst transferring by setting DC = "H". "H" idle CLKIN BS A8 - A30 SID, ST BCH, BCL BURST D0 - D15 DC R/W burst read ( 4 words) idle "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Keep DC signal to at the "H" level during idle cycles.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP When writing word-size data aligned on the 32-bit boundary, the M32000D3FP carries out a burst-transfer by outputting the BURST signal. When burst-writing 32-bit data, the MSB-side 16-bit write bus cycle is driven first, followed by the LSB-side 16-bit write bus cycle. The BURST signal is synchronized with the CLKIN falling edge of the first bus access cycle, and "L" level is output. It returns to "H" level in synchronization with the CLKIN falling edge of the last bus access cycle. Addresses A8 to A30 are output for each cycle. When an "L" level is input to HREQ, the M32000D3FP switches to the hold state and outputs an "L" level to HACK. While the M32000D3FP is in the hold state, bus related pins go to a high im- pedance state, and data transfer is carried out on the system bus. To return to normal operation mode from the hold state, the HREQ sig- nal should be changed to an "H" level. Fig. 21 1-word (32-bit) burst write timing (1-0 wait) Fig. 22 Bus arbitration timing idle CLKIN BS A8 - A30 SID,ST BCH, BCL BURST D0 - D15 DC R/W burst write (1 word) idle "Hi-z" "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Wait cycles can be inserted even when burst transferring by setting DC = "H". Keep DC signal at the "H" level during idle cycles. "Hi-z" "Hi-z" "Hi-z" (see note 2) "Hi-z" "Hi-z" "Hi-z" "Hi-z" Notes 1: Before switching to the hold state, an idle cycle of 1 CLKIN clock period is always inserted. After returning from the hold state, an idle cycle of 1 to 5 CLKIN clock periods is always inserted. 2: "Hi-z" means high impedance, and indicates sampling timing. 3: While the M32000D3FP is in the hold state, the DC signal is driven and output when the CS signal is input. (see note 2) (see note 3) write CLKIN HREQ BCH, BCL D0 - D15 DC R/W idle hold shift hold return idle HACK A8 - A30 SID, ST (see note 1) (see note 1) BS BURST

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP ("L" output) ("L" input) "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" HREQ BCH, BCL D0 - D15 DC R/W hold shift hold return HACK A8 - A30 CS read read read read SID Note: "Hi-z" means high impedance, and indicates sampling timing. CLKIN The value of the R/W signal that controls the data direction of the bus interface cannot be changed during CS="L". Hold this value while CS="L". Also, where marked above with ] , 3 to 7 CLKIN clock periods are necessary for the first read operation (also when reading crosses an 128-bit boundary) when reading from the internal DRAM. Hold the input value of the address or other control signals during these wait cycle periods (DC = "H"). Consecutive read operations within an 128-bit boundary are completed in 1 CLKIN clock period. During these wait cycle period, CS cannot be returned to an "H" level (the access cannot be aborted). CS can only be returned to an "H" level after DC is driven to "L". When the M32000D3FP is in the hold state and an "L" level is input to CS, the M32000D3FP interprets it as a bus access request to the internal DRAM. In this case, when the R/W signal is an "H" level, the memory controller drives a read cycle to the internal DRAM. In the read cycle, the 16-bit data for the address specified with A8 to A30, is output from D0 to D15 regardless of the BCH and BCL settings. Also the DC signal is output. The M32000D3FP reads 128 bits of data from the block on the 128- bit boundary including the requested address into the 128-bit buffer of the bus interface unit. 3 to 7 CLKIN clock periods are necessary for the first bus access, however, when reading consecutive address within the 128-bit boundary, the subsequent read bus cycles are com- pleted in 1 CLKIN clock period because a read from the internal DRAM does not take place. After DC outputs an "L" level (access complete), return CS to the "H" level between the CLKIN falling edge corre- sponding to the last read cycle and the following CLKIN falling edge. Return HREQ to the "H" level to return the M32000D3FP to the nor- mal operation mode from the hold state either at the same time as or after CS is returned to the "H" level. Fig. 23 Read bus cycle to internal DRAM

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP ("L" output) ("L" output) ("L" output) "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" CLKIN HREQ BCH, BCL D0 - D15 DC R/W hold shift hold return HACK A8 - A30 CS write write write write SID Note: "Hi-z" means high impedance, and indicates sampling timing. The value of the R/W signal that controls the data direction of the bus interface cannot be changed during CS="L". Hold this value while CS="L". Also, where marked above with ], 3 to 7 CLKIN clock periods are necessary for writing operation to internal DRAM crossing an 128-bit boundary. Hold the input value of the address or other control signals during these wait cycle periods (DC = "H"). Consecutive writing operations within an 128-bit boundary are completed in 1 CLKIN clock period. During these wait cycle period, CS cannot be returned to "H" level (the access cannot be aborted). CS can only be returned to a "H" level after DC is driven to "L". When the M32000D3FP is in the hold state and an "L" level is input to CS, the M32000D3FP interprets it as a bus access request to the internal DRAM. In this case, when the R/W signal is at an "L" level, the memory controller drives a write cycle to the internal DRAM. Byte data control is specified by the BCH and BCL signals. Only data in the byte positions for which an "L" level is input to BCH or BCL are written. When writing is complete, an "L" level DC signal is output. The M32000D3FP stores the requested data in the 128-bit data buffer of the BIU, before writing to the internal DRAM. This reduces the number of accesses to the internal DRAM when a request to writing to consecutive addresses is made, and improves bus cycle through- put. Consecutive write cycles within an 128-bit boundary are com- pleted in 1 CLKIN clock period. 3 to 7 CLKIN clock periods are nec- essary for a write access crossing an 128-bit boundary when writing to the internal DRAM. After DC outputs an "L" level (access com- plete), return CS to the "H" level between the CLKIN falling edge corresponding to the last write cycle and the following CLKIN falling edge. Return HREQ to the "H" level to return the M32000D3FP to the normal operation mode from the hold state either at the same time as or after CS is returned to the "H" level. When the external bus master makes an access, the value of the R /W signal that controls the data direction of the bus interface can- not be changed during CS="L". Therefore, read cycles and write cycles cannot be mixed while CS = "L". When starting a write cycle follow- ing after a read cycle and starting a read cycle following a write cycle, keep the CS signal at an "H" level for at least 1 CLKIN. Fig. 24 Write bus cycle to internal DRAM Fig. 25 Read/write bus cycle CLKIN HREQ BCH, BCL D0 - D15 DC R/W hold shift hold return HACK A8 - A30 CS ("L" output) read CS = "H" write ("L" output) SID ("L" input) "Hi-z" "Hi-z" "Hi-z" "Hi-z""Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" "Hi-z" Note: "Hi-z" means high-impedance, and indicates sampling timing. Also, where marked above with ], keep CS signal to "H" at least 1 CLKIN when starting a write bus cycle after a read bus cycle or a read bus cycle after a write bus cycle. "Hi-z"

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Master/slave mode_ The M32000D3FP has an M/S (master/slave) pin for multiprocessor configuration use.

• master mode (M/S = "H") This is normal operation mode. Set the M/S pin to an "H" level. It is used when the M32000D3FP is used as the main CPU in a system.
• slave mode (M/S = "L") This operation mode is for when the M32000D3FP is used as a coprocessor. Set the M/S pin to an "L" level. When set to slave mode, the M32000D3FP does not start operation even after a reset, until an interrupt request or the SBI is input. Processing is carried out by communicating with the master M32000D3FP, using the two pro- grammable I/O ports and the external interrupt signal.
• Coprocessor only configuration example The slave M32000D3FP accesses only the internal DRAM and never the external bus. M/S and HREQ are fixed at the "L" level. The slave M32000D3FP executes the instructions that the master M32000D3FP downloads to the internal DRAM. The data transfer request (process- ing complete) from the slave M32000D3FP is notified to the master M32000D3FP by inputting the interrupt request via the programmable I/O port. The data transaction is carried out when the master M32000D3FP accesses the internal DRAM in the slave M32000D3FP.
• Common bus coprocessor configuration example In this configuration, the slave M32000D3FP can also access the external bus. Communications between the master and slave CPUs is carried out using the programmable I/O ports and the interrupt request input. D24 D25 D26 D27 D28 D29 D30 D31 LM lock control register (MLCR) < address: H'FFFF FFF7> Fig. 26 Lock control register M32000D3FP (master) ROM ASIC PP0 M/SM/S HREQ INT M32000D3FP (slave) HACK HREQ HACK bus arbiter INT M32000D3FP (master) ROM ASIC INT PP0 M/SM/S HREQ INT M32000D3FP (slave) no access to external bus <coprocessor only configuration> <common bus coprocessor configuration> Fig. 27 Master/slave system configuration example 0: HREQ exclusive lock mode___ 1: CS exclusive lock mode W = ... write enabledW = : write disabled <at reset: H'00> D bit name function R W 24 - 30 N ot 0 assigned. 31 LM (lock mode)

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP In standby mode, all clock supply stops and only the contents of the internal DRAM are retained. The power requirement is only that which the internal DRAM needs for refreshing itself. When set to standby mode, the M32000D3FP waits for the current bus operation to be completed. It then purges the cache memory and switches the inter- nal DRAM to self-refresh mode. After that, the PLL and all clock sup- plies stop and the STBY signal goes to an "L" level to indicate the completion of the switch to standby mode. Input an "L" level to WKUP ___ or RST to return from standby mode to normal operation mode. The contents of the internal DRAM are retained upon return using the WKUP signal. In CPU sleep mode, clock supply to the M32R CPU stops. In this mode, the internal DRAM, cache memory, memory controller and external bus interface continue to operate and the internal DRAM can be accessed from the external bus. Input an "L" level to INT, SBI ___ or RST to return to normal operation mode from CPU sleep mode. The contents of the cache memory, internal DRAM, general-purpose registers and programmable I/O control register are retained upon return using the INT or SBI signals. Power management function The M32000D3FP has the following two low-power consumption modes.

• standby mode
• CPU sleep mode power management (MPMR) < address: H'FFFF FFFB> D24 D25 D26 D27 D28 D29 D31 PM1PM0 D30 <at reset: H'00> D bit name function R W 24 - 29 Not assigned. 0 30, 31 PM0, PM1 (low power consumption mode) 00: normal operation mode 01: (reserved) 10: CPU sleep mode 11: standby mode Fig. 28 Power management control register standby mode reset normal operation mode CPU sleep mode set to CPU sleep mode (H'02 is written to MPMR register) set to standby mode (H'03 is written to MPMR register) INT, SBI, RST input WKUP, RST input Fig. 29 State transition for low power consumption mode W = ... write enabledW = : write disabled

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Programmable I/O port The M32000D3FP has two programmable I/O ports (PP0, PP1). Each port can be set as input or output. Reset ____ When an "L" level is input to RST, the M32000D3FP switches to the reset state. The reset state is released when an "H" level is input to ____ RST, and the program is executed from the EIT vector entry of the reset interrupt. All internal resources including the internal PLL (4x clock generator) are initialized. In order to stabilize PLL oscillation, ____ the "L" input to RST should last a minimum of 2 ms after VCC stabi- lizes to the specified voltage level. <at reset: H'00> D bit name function R W 24 - 30 Not assigned. 0

31 PP0C, PP1C 0: input port

(port I/O direction)1: output port programmable I/O port direction control register 1 (PPCR1) < address: H'FFFF FFE7> D24 D25 D26 D27 D28 D29 D30 D31 PP1C programmable I/O port direction control register 0 (PPCR0) < address: H'FFFF FFE3> D24 D25 D26 D27 D28 D29 D30 D31 PP0C Fig. 30 Programmable I/O port direction control register programmable I/O port data register 0 (PPDR0) < address: H'FFFF FFEB> <at reset: B'0000 000?> D bit name function R W 24 - 30 Not assigned. 0

31 PP0D, PP1D 0: data = "0"

(port data) 1: data = "1" D24 D25 D26 D27 D28 D29 D30 D31 PP1D programmable I/O port data register 1 (PPDR1) < address: H'FFFF FFEF> D24 D25 D26 D27 D28 D29 D30 D31 PP0D Fig. 31 Programmable I/O port data register Table 2 Internal state after reset internal resources state DRAM undefined cache memory invalid (purged all) general purpose undefined registers (R0 - R15) control registersPSW (CR0) B'0000 0000 0000 0000 ??00 000? 0000 0000 (BSM, BIE, and BC are undefined) CBR (CR1) H'0000 0000 SPI (CR2) undefined SPU (CR3) undefined BPC (CR6) undefined PC master mode: execute from address H'7FFF FFF0 slave mode: wait for interrupt input at address H'7FFF FFF0

• execute from address H'0000 0010___ by inputting SBI signal
• execute from address H'0000 0080___ by inputting INT signal ACC (accumulator)undefined I/O registers PPCR0, PPCR1 H'00 (input) PPDR0, PPDR1 B'0000 000? (depends on input pin state) MLCR H'00 (HREQ exclusive lock mode) MPMR H'00 (normal operation) MCCR H'01 (cache-off mode) W = ... write enabledW = : write disabled W = ... write enabledW = : write disabled

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Clock generating circuit The M32000D3FP has a clock multiplier circuit and operates at four times the input frequency. The internal operation frequency becomes 66.6 MHz when a 16.65 MHz clock is input to CLKIN. A capacitor (C) should be connected to the PLLCAP pin, and the clock is input to the CLKIN pin. The PLLVCC and PLLVSS pins should be connected to the power source or the ground, respectively. ADDRESSING MODE M32R family supports the following addressing modes. < register direct > The general-purpose register or the control register to be processed is specified. < register indirect > The contents of the register specify the address in memory to be accessed. This mode can be used by all load/store instructions. < register relative indirect > (The contents of the register) + (16-bit immediate value which is sign- extended to 32 bits) specify the address in memory to be accessed. < register indirect and register update >

• 4 is added to the register contents (the contents of the register before update specify the address in memory to be accessed [LD instruction]
• 4 is added to the register contents (the contents of the register after update specify the address in memory to be accessed) [ST instruction]
• 4 is subtracted from the register contents (the contents of the register after update specify the address in memory to be accessed) [ST instruction] < immediate > The 4-, 5-, 8-, 16- or 24-bit immediate value. < PC relative > (The contents of PC) + (8, 16, or 24-bit displacement which is sign- extended to 32 bits and 2 bits left-shifted) specify the address in memory to be accessed. Fig. 32 Oscillation circuit M32000D3FP 18 (CLKIN) 16 (PLLCAP) 15 (PLLVSS) C 14 (PLLVCC) VCC PLL clock generating circuit clock input recommended values in circuit C : 1000 pF

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP INSTRUCTION SET A total of 83 instructions are implemented. <Load/store instructions> The load/store instructions carry out data transfers between a regis- ter and a memory. LD Load LDB Load byte LDUB Load unsigned byte LDH Load halfword LDUH Load unsigned halfword LOCK Load locked ST Store STB Store byte STH Store halfword UNLOCK Store unlocked <Transfer instructions> The transfer instructions carry out data transfers between registers or a register and an immediate value. LD24 Load 24-bit immediate LDI Load immediate MV Move register MVFC Move from control register MVTC Move to control register SETH Set high-order 16-bit <Operation instructions> Compare, arithmetic/logic operation, multiply and divide, and shift are carried out between registers.

• compare instructions CMP Compare CMPI Compare immediate CMPU Compare unsigned CMPUI Compare unsigned immediate
• arithmetic operation instructions ADD Add ADD3 Add 3-operand ADDI Add immediate ADDV Add with overflow checking ADDV3 Add 3-operand ADDX Add with carry NEG Negate SUB Subtract SUBV Subtract with overflow checking SUBX Subtract with borrow INSTRUCTION FORMAT There are two major instruction formats: two 16-bit instructions packed together within a word boundary, and a single 32-bit instruction. < 16-bit instruction > op1 R 1 R 2op2 op1 R 1 c op1 cond c op1 R 1 R 2op2 c op1 R 1 R 2op2 c op1 R 1 c op1 cond c < 32-bit instruction > R 1 = R1 op R2 R 1 = R1 op c Branch (Short Displacement) R 1 = R1 op c Branch Compare and Branch R 1 = R2 op c Fig. 33 Instruction format

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP <EIT-related instructions> The EIT-related instructions carry out the EIT events (Exception, In- terrupt and Trap). Trap initiation and return from EIT are EIT-related instructions. TRAP Trap RTE Return from EIT <DSP function instructions> The DSP function instructions carry out multiplication of 32 bits 5 16 bits and 16 bits 5 16 bits or multiply and add operation; there are also instructions to round off data in the accumulator and carry out transfer of data between the accumulator and a general-purpose reg- ister. MACHI Multiply-accumulate high-order halfwords MACLO Multiply-accumulate low-order halfwords MACWHI Multiply-accumulate word and high-order halfword MACWLO Multiply-accumulate word and low-order halfword MULHI Multiply high-order halfwords MULLO Multiply low-order halfwords MULWHI Multiply word and high-order halfword MULWLO Multiply word and low-order halfword MVFACHI Move from accumulator high-order word MVFACLO Move from accumulator low-order word MVFACMI Move from accumulator middle-order word MVTACHI Move to accumulator high-order word MVTACLO Move to accumulator low-order word RAC Round accumulator RACH Round accumulator halfword

• logic operation instructions AND AND AND3 AND 3-operand NOT Logical NOT OR OR OR3 OR 3-operand XOR Exclusive OR XOR3 Exclusive OR 3-operand
• multiply/divide instructions DIV Divide DIVU Divide unsigned MUL Multiply REM Remainder REMU Remainder unsigned
• shift instructions SLL Shift left logical SLL3 Shift left logical 3-operand SLLI Shift left logical immediate SRA Shift right arithmetic SRA3 Shift right arithmetic 3-operand SRAI Shift right arithmetic immediate SRL Shift right logical SRL3 Shift right logical 3-operand SRLI Shift right logical immediate <Branch instructions> The branch instructions are used to change the program flow. BC Branch on C-bit BEQ Branch on equal BEQZ Branch on equal zero BGEZ Branch on greater than or equal zero BGTZ Branch on greater than zero BL Branch and link BLEZ Branch on less than or equal zero BLTZ Branch on less than zero BNC Branch on not C-bit BNE Branch on not equal BNEZ Branch on not equal zero BRA Branch JL Jump and link JMP Jump NOP No operation

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Power source voltage Input voltage Output voltage Power consumption Operating temperature Storage temperature ABSOLUTE MAXIMUM RATINGS Ratings TOPR = 25 °C ConditionsParameter VCC VI VO PD TOPR TSTG Symbol Unit V V V mW Min. Max. –0.5 –0.5 –0.5 –65 4.6 4.6 4.6 1000 150 RECOMMENDED OPERATING CONDITIONS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted) VCC VIH VIL IOH (see note) IOL (see note) CL Ratings Max. 3.6 VCC+0.3 VCC+0.3 0.8 0.2VCC V V V V V mA mA pF Symbol Parameter Unit Min. 3.0 2.0 0.8VCC –0.3 –0.3 Power source voltage “H” input voltage All inputs except following ____ RST pin “L” input voltage All inputs except following ____ RST pin “H” output current “L” output current output load capacity Typ. Note: IOH and IOL represent the maximum values of DC current load. Intermittent current that is generated during output need not to be considered as long as the output load capacity is within the specified range.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP IOH = –2 mA IOL = 2 mA VO = 0 to VCC VIH = 0 to VCC +0.3 V VIH = 0 to VCC +0.3 V Average in normal operation mode VCC = 3.3 V Average in CPU sleep mode VCC = 3.3 V Average in standby mode VCC = 3.3 V All pins “H” output voltage “L” output voltage Output current in off state “H” input current “L” input current Power source current Pin capacitance VOH VOL IOZ IIH IIL ICC C DC CHARACTERISTICS ELECTRICAL CHARACTERISTICS (VCC = 3.3 V ± 0.3 V, TOPR = 0 to 70 °C unless otherwise noted) Ratings Max. 0.4 10.0 10.0 –10.0 200 150 1500 V V µA µA µA mA mA µA pF Symbol Parameter Unit Min. 2.4 –10.0 Test conditions Typ. 120

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Min. Max. AC CHARACTERISTICS TIMING REQUIREMENTS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted) Limits Symbol Parameter Min. Input rise transition time Input fall transition time Test conditions CMOS input ____ RST pin CMOS input ____ RST pin (1) Input transition time tr(INPUT) tf(INPUT) Unit ns ms ns ms Reference number Limits Symbol Parameter Clock input cycle time External clock input “H” pulse width External clock input “L” pulse width External clock input rising time External clock input falling time Reset input “L” pulse width Wakeup input “L” pulse width (2) Clock, reset and wakeup timing tc(CLKIN) tw(CLKINH) tw(CLKINL) tr(CLKIN) tf(CLKIN) tw(RST) tw(WKUP) Max. 100 Unit ns ns ns ns ns ms ms Reference number 1/4CLKIN 1/4CLKIN Limits Symbol Parameter Min. Data input set-up time before CLKIN Data input hold time after CLKIN DC input “H” set-up time before CLKIN DC input “H” hold time after CLKIN DC input “L” set-up time before CLKIN DC input “L” hold time after CLKIN Test conditions (3) Read and write timing Max. Unit ns ns ns ns ns ns Reference number tsu(D-CLKIN) th(CLKIN-D) tsu(DCH-CLKIN) th(CLKIN-DCH) tsu(DCL-CLKIN) th(CLKIN-DCL) Test conditions

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP (4) Arbitration and external bus master read/write timing Limits Symbol Min.Test conditions Max. Unit ns ns ns ns ns ns ns ns tsu(HREQ-CLKIN) th(CLKIN-HREQ) tsu(CS-CLKIN) th(CLKIN-CS) tsu(A-CLKIN) th(CLKIN-A) tsu(D-CLKINL) th(CLKINL-D) Parameter HREQ input set-up time before CLKIN HREQ input hold time after CLKIN CS input set-up time before CLKIN CS input hold time after CLKIN Address input set-up time before CLKIN Address input hold time after CLKIN Data input set-up time before CLKIN Data input hold time after CLKIN Limits Symbol Parameter Min. ___ INT input pulse width (see note) ___ SBI input pulse width (see note) Test conditions (5) Interrupt control unit timing tw(INT) tw(SBI) Max. Unit ns ns Reference number tc(CLKIN) tc(CLKIN) Note: Both INT and SBI are level-sense inputs. Keep them at an "L" level until the interrupt is accepted. (6) I/O port timing Limits Symbol Parameter Min. Port input “L” pulse width Port input “H” pulse width Test conditions tw(PORTINL) tw(PORTINH) Max. Unit ns ns Reference number Reference number

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP SWITCHING CHARACTERISTICS (VCC = 3.3 ± 0.3 V, CL = 50 pF, TOPR = 0 to 70 °C unless otherwise noted) Limits Symbol Parameter Test conditions (1) Output transition time tr(OUTPUT) tf(OUTPUT) Reference number Min. UnitMax. Typ. Output rising transition time Output falling transition time ns ns (2) Read and write timing Limits Symbol td(CLKIN-BSHX) td(CLKIN-BSL) td(CLKIN-BSLX) td(CLKIN-BSH) td(CLKIN-AV) td(CLKIN-AX) td(CLKIN-BCV) td(CLKIN-BCX) td(CLKIN-SIDV) td(CLKIN-SIDX) td(CLKIN-STV) td(CLKIN-STX) td(CLKIN-RWV) td(CLKIN-RWX) td(CLKIN-BURSTHX) td(CLKIN-BURSTL) td(CLKIN-BURSTLX) td(CLKIN-BURSTH) td(CLKIN-DZX) td(CLKIN-DV) td(CLKIN-DVX) td(CLKIN-DXZ) Reference number Min. UnitMax. BS = “H” effective time after CLKIN BS = “L” delay time after CLKIN BS = “L” effective time after CLKIN BS = “H” delay time after CLKIN Address delay time after CLKIN Address effective time after CLKIN BCH, BCL delay time after CLKIN BCH, BCL effective time after CLKIN SID delay time after CLKIN SID effective time after CLKIN ST delay time after CLKIN ST effective time after CLKIN R/W delay time after CLKIN R/W effective time after CLKIN BURST = “H” effective time after CLKIN BURST = “L” delay time after CLKIN BURST = “L” effective time after CLKIN BURST = “H” delay time after CLKIN Data output enable time after CLKIN Data output delay time after CLKIN Data output effective time after CLKIN Data output disable time after CLKIN Parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tc(CLKIN)/4+8 Test conditions tc(CLKIN)/4

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP (3) Arbitration and external bus master read/write timing Limits Symbol Test conditions td(CLKIN-HACKHX) td(CLKIN-HACKL) td(CLKIN-HACKLX) td(CLKIN-HACKH) td(CLKIN-AZ) td(CLKIN-AZX) td(CLKIN-DZX) td(CLKIN-DV) td(CLKIN-DXZ) td(CLKIN-DVX) td(CS-DCZX) td(CLKIN-DCHX) td(CLKIN-DCL) td(CLKIN-DCXZ) td(CLKIN-DCLX) Max. HACK = “H” effective time after CLKIN HACK = “L” delay time after CLKIN HACK = “L” effective time after CLKIN HACK = “H” delay time after CLKIN Address output disable time after CLKIN Address output enable time after CLKIN Data output enable time after CLKIN Data output delay time after CLKIN Data output disable time after CLKIN Data output effective time after CLKIN __ __ DC output enable time after CS DC = “H” effective time after CLKIN DC = “L” delay time after CLKIN DC output disable time after CLKIN DC = “L” effective time after CLKIN Parameter Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Reference number (4) Standby timing Limits Symbol Test conditions td(CLKIN-STBYHX) td(CLKIN-STBYL) td(CLKIN-STBYLX) td(CLKIN-STBYH) Reference number Min. UnitMax.Parameter ns ns ns ns tc(CLKIN)n/4+15 tc(CLKIN)n/4+15 STBY = “H” effective time after CLKIN STBY = “L” delay time after CLKIN (see note) STBY = “L” effective time after CLKIN STBY = “H” delay time after CLKIN (see note) Note: The STBY signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) degree phase of CLKIN. Limits Symbol Parameter Min. Port output “L” pulse width (see note) Port output “H” pulse width (see note) Test conditions (5) I/O port timing tw(PORTOUTL) tw(PORTOUTH) Max. Unit ns ns Reference number Note: The minimum pulse width value is that where the output is changed within 1 clock of the internal clock. Software processing time to write to the port data register is not included.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Fig. 34 Output switching characteristic measurement circuit C L = 50 pF CMOS output CMOS output (during floating delay time measurement) measured pin C L = 50 pF measured pin 0.5VCC 1.0 kW Fig. 35 Input waveform and timing reference point during characteristic measurement Fig. 36 Output timing measurement point during characteristic measurement timing reference point 0.8VCC 0.2VCC CMOS output (when not specified) 0.9VCCCMOS output (during floating delay time measurement) 0.1VCC 0.6VCC 0.4VCC "H" fi "Z" "L" fi "Z" "Z" fi "H" "Z" fi "L" timing reference point (when not specified) "H" input level "L" input level VCC 0.0 V 0.9VCC 0.1VCC 0.8VCC 0.9VCC 0.1VCC 0.2VCC CMOS input schmitt trigger input "H" input level "L" input level VCC 0.0 V CLKIN input "H" input level "L" input level

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP CMOS input (except for schmitt trigger input and CLKIN input) schmitt trigger input (RST) 0.8VCC 0.9VCC 0.1VCC 0.2VCC tr(INPUT) tf(INPUT) tr(INPUT) tf(INPUT) output pin 0.8VCC 0.2VCC tr(OUTPUT) tf(OUTPUT)3 4 Fig. 37 Input transition time Fig. 38 Output transition time Fig. 39 Clock reset and wakeup timing tw(RST) RST 0.5VCC 0.8VCC 0.2VCC tw(CLKINH) tw(CLKINL) tr(CLKIN) tf(CLKIN) CLKIN (input) (input) tc(CLKIN)5 6 7 8 9 tw(WKUP) WKUP (input) *1 The WKUP and RST signals can be input asynchronously. When returning from standby mode, the same timing applies.

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP CLKIN (input) (output) (output)

0.5 VCC

(input) (output) D0 to D15 D0 to D15 (input) td(CLKIN-DV) td(CLKIN-DZX) td(CLKIN-DVX) td(CLKIN-DXZ) tsu(DCL-CLKIN) th(CLKIN-DCL) tsu(D-CLKIN) th(CLKIN-D) BS BCH, BCL DC 13 15 30 31 38 39 (output)A8 to A30 td(CLKIN-AV)16 (output) td(CLKIN-STV) SID, ST (output) td(CLKIN-RWV) R/W (output)BURST td(CLKIN-BSH) td(CLKIN-BURSTL)27 td(CLKIN-BURSTH)29 td(CLKIN-BSL) td(CLKIN-BCV)18 td(CLKIN-SIDV)20 12 td(CLKIN-BSHX) 14 td(CLKIN-BSLX) td(CLKIN-AX)17 td(CLKIN-BCX)19 td(CLKIN-STX)23 td(CLKIN-SIDX)21 td(CLKIN-RWX)25 td(CLKIN-BURSTHX)26 td(CLKIN-BURSTLX)28 tsu(DCH-CLKIN) th(CLKIN-DCH)36 37 *1 The set up/hold of DC = "H" may vary depending on the wait cycle insertion or when an idle cycle occurs. *1 *1 *2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary.

• minimum value of td(CLKIN-BSLX) = (value in table) – (correction value) = 15 – (60 x 5/100) = 12 [ns]
• maximum value of td(CLKIN-BSH) = (value in table) + (correction value) = (60/4 + 8) + (60 x 5/100) = 26 [ns] [example] BS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (– 5%) to CLKIN:

Fig. 40 Read/write timing

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Fig. 41 Bus arbitration timing CLKIN HREQ HACK A8 to A30, SID, ST, BS, BCH, BCL, R/W, BURST (output) (input) (input) (output) *1 The HREQ signal can be input asynchronously. *2 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary.

• minimum value of td(CLKIN-HACKHX) = (value in table) – (correction value) = 0 – (60 x 5/100) = –3 [ns]
• maximum value of td(CLKIN-HACKL) = (value in table) + (correction value) = 12 + (60 x 5/100) = 15 [ns] [example] HACK signal transition ("H" –> "L") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (– 5%) to CLKIN: 0.5VCC 0.5VCC td(CLKIN-HACKL) td(CLKIN-HACKHX) td(CLKIN-HACKH) td(CLKIN-HACKLX) td(CLKIN-AZX)td(CLKIN-AZ) tsu(HREQ-CLKIN) 41 46 47 *1 *1 th(CLKIN-HREQ)40

SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP Fig. 42 External bus master read/write timing CLKIN (input) (input) (input) (output) D0 to D15 D0 to D15 (input) th(CLKINL-D) HREQ R/W 52 53 (output) tsu(HREQ-CLKIN) HACK 43 td(CLKIN-HACKL) 45 (input) CS 48 tsu(CS-CLKIN) 49 th(CLKIN-CS) td(CLKIN-DV) td(CLKIN-DZX) 50 tsu(A-CLKIN) 51 th(CLKIN-A) (output) DC 60 td(CLKIN-DCL) 59 td(CLKIN-DCHX) 42 td(CLKIN-HACKHX) 44 58 td(CS-DCZX) td(CLKIN-HACKH) td(CLKIN-HACKLX) th(CLKIN-HREQ) 50 51 (input) A8 to A30 BCH, BCL 50 51 50 51 48 49 tsu(D-CLKINL) 48 49 td(CLKIN-DXZ) td(CLKIN-DVX) td(CLKIN-DCLX) td(CLKIN-DCXZ) *1 All switching characteristics and timing requirements based on the falling edge of CLKIN are calculated according to the internal CLKIN (duty ratio is 50%) . When designing external peripheral circuits, the correction for the duty cycle of the actual CLKIN is necessary.

• minimum value of tsu(CS-CLKIN) = (value in table) + (correction value) = 10 + (60 x 5/100) = 13 [ns]
• minimum value of th(CLKIN-CS) = (value in table) + (correction value) = 2 + (60 x 5/100) = 5 [ns] *1 *1 *1 *1 *1 *1 *1 *1 [example] CS signal transition ("L" –> "H") when inputting 16.65 MHz clock whose duty ratio is 45 - 55% (– 5%) to CLKIN:

SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP *2 The STBY goes to an "L" level when switched to the standby mode. *3 When returning from standby mode, the STBY signal goes to an "H" level 1 CLKIN after sampling that WKUP has returned from "L" to "H", or 3 CLKINs after sampling that RST = "L". td(CLKIN-STBYL) STBY (output) CLKIN (input) td(CLKIN-STBYH)68*1 *2 *1 *3 degree phase of CLKIN. td(CLKIN-STBYHX)65 td(CLKIN-STBYLX)67 internal clock (66.6 MHz) *1 The STBY signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270 Fig. 43 Interrupt input timing Fig. 44 Standby timing PX tw(PORTINL) tw(PORTINH)69 70[for input] PX tw(PORTOUTL) tw(PORTOUTH)71 72 [for output] Fig. 45 I/O port timing INT SBI (input) (input) tw(INT) tw(SBI)*1 *1 The INT and SBI signals can be input asynchronously. When returning from CPU sleep mode, the same timing applies. This timing value is "a value necessary for sampling the input to pins", however, not "a value that guarantees the interrupt acceptance". The interrupt request is a level-sensed input , and should be kept "L" until it is accepted.

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• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Keep safety first in your circuit designs!
• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. © 1998 MITSUBISHI ELECTRIC CORP. Revised edition, effective May. 1998. Specifications subject to change without notice. SINGLE-CHIP 32-BIT CMOS MICR OCOMPUTER MITSUBISHI MICROCOMPUTERS M32000D3FP

Rev. Rev. No. date

1.0 First Edition 970507

2.0

• DC signal explanation revised (page 19). 970901
• Figures 17 to 25 revised (page 21 to page 25).
• 2 to 7 CLKIN clock periods are ~ → 3 to 7 CLKIN clock periods are ~ (left column in page 24)
• 2 to 7 CLKIN clock periods are ~ → 3 to 7 CLKIN clock periods are ~ (left column in page 25)
• DC CHARACTERISTICS, AC CHARACTERISTICS, and SWITCHING CHA RACTERISTICS revised (page 33 to 37).
• Figures 40 to 43 revised (page 40 to 43). 2.1
• "After DC outputs an ~ CLKIN falling edge." revised (line 14, page 24). 980501
• Notes in Figure 23 revised (page 24). __ __
• "After DC outputs an ~ CLKIN falling edge." revised (line 15, page 25).
• Notes in Figure 24 revised (page 25).
• Table 2 revised (page 28).
• (3) Arbitration and external bus master read/write timing Symbol Parameter ~~ ~ td(CS-DCZX) DC output enable time after CS corrected (page 37).
• " 58 td(CS-DCZX) *1 " in Fig. 42 corrected (page 42).
• Notes in Figure 44 revised (page 43). REVISION DESCRIPTION LIST M32000D3FP DATA SHEET (1/1) Revision Description