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Technical content

Features

142.9ns (f(XIN)=7MH Z, VCC =2.2V to 3.6V with software one-wait) 2.4V to 2.7V (f(XIN)=7MH Z, without software wait) 2.2V to 2.4V (f(XIN)=7MH Z with software one-wait) interrupt sources; 7 levels (including key input interrupt) (3 for UART or clock synchronous, 2 for clock synchronous) 1 line (P85 shared with NMI pin) (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Audio, cameras, office equipment, communications equipment, portable equipment

Description

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration PIN CONFIGURATION (top view) Package: 100P6S-A Figure 1.1.1. Pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 52 62 72 82 93 0 515253545556575859606162636465666768697071727374757677787980 100 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 0/D 1/D 2/D 3/D 4/D VREF AV SS V CCX IN X OUTV SS RESETCNVssP8 7/X CIN 6/X COUTBYTE 0/A 0(/D 0/-) 1/A 1(/D 1/D 2/A 2(/D 2/D 3/A 3(/D 3/D 4/A 4(/D 4/D 5/A 5(/D 5/D 6/A 6(/D 6/D 7/A 7(/D 7/D 0/A 8(/-/D 1/A 2/A 3/A 4/A 5/A 6/A 7/A 0/A 1/A 2/A 3/A 4/TA2 OUT 6/TA3 OUT P56/ALE 7/TA3 IN P55/HOLD P54/HLDA P53/BCLK P52/RD VccVss P57/RDY/CLK OUT P45/CS1 P46/CS2 P47/CS3 AVcc P63/TXD 0 P65/CLK1 P66/RxD1 P67/TXD 1 P61/CLK0 P62/RxD0 P100/AN0 P101/AN1 P102/AN2 P103/AN3 3/DA 0/TB3 IN 4/DA 1/TB4 IN 5/ANEX0/CLK4 6/ANEX1/S OUT 1/TB1 IN IN 2/TB2 IN OUT 0/TA4 OUT P60/CTS0/RTS0 P64/CTS1/RTS1/CLKS1 2/CLK 2/TA1 OUT 2/INT 1/RxD 2/SCL/TA0 IN /TB5 IN 3/INT 5/NMI P97/ADTRG /SIN4 P44/CS0 P50/WRL/WR P51/WRH/BHE 0/TB0 IN /CLK3 0/T XD 2/SDA/TA0 OUT 4/INT 1/TA4 IN 5/TA2 IN 5/D /INT3 6/D /INT4 7/D /INT5 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 M16C/62 Group 3/CTS 2/RTS 2/TA1 IN

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.1.2. Pin configuration (top view) Package: 100P6Q-A PIN CONFIGURATION (top view) 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 0 21 22 23 24 25 51525354555657585960616263646566676869707172737475 100 P00/D0 P01/D1 P02/D2 P03/D3 P04/D4 P05/D5 P06/D6 P07/D7 P10/D8 P11/D9 P12/D10 3/D 4/D VREF AV SS V CCX IN X OUTV SS RESETCNVssP8 7/X CIN 6/X COUTBYTE 0/A 0(/D 0/-) 1/A 1(/D 1/D 2/A 2(/D 2/D 3/A 3(/D 3/D 4/A 4(/D 4/D 5/A 5(/D 5/D 6/A 6(/D 6/D 7/A 7(/D 7/D 0/A 8(/-/D 1/A 2/A 3/A 4/A 5/A 6/A 7/A 0/A 1/A P42/A18 P43/A19 4/TA2 OUT 6/TA3 OUT P56/ALE 7/TA3 IN P55/HOLD P54/HLDA P53/BCLK P52/RD VccVss P57/RDY/CLK OUT P45/CS1 P46/CS2 P47/CS3 AVcc P63/TXD 0 P65/CLK1 P66/RxD1 P67/TXD 1 P61/CLK0 P62/RxD0 P100/AN0 P101/AN1 P102/AN2 P103/AN3 3/DA 0/TB3 IN 4/DA 1/TB4 IN P95/ANEX0/CLK4 P96/ANEX1/SOUT 4 1/TB1 IN IN 2/TB2 IN OUT 1/TA4 IN 0/TA4 OUT P60/CTS0/RTS0 P64/CTS1/RTS1/CLKS1 2/INT 3/INT 5/NMI P97/ADTRG /SIN4 P44/CS0 P50/WRL/WR P51/WRH/BHE 0/TB0 IN /CLK3 4/INT P72/CLK2/TA1OUT /V P71/RxD2/SCL/TA0IN/TB5IN P70/TXD 2/SDA/TA0OUT 5/TA2 IN 3/CTS 2/RTS 2/TA1 IN 5/D /INT 6/D /INT 7/D /INT P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 M16C/62 Group

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns(f(X IN)=10MH Z, VCC =2.7V to 3.6V) 142.9ns (f(XIN)=7MH Z, VCC =2.2V to 3.6V with software one-wait) Memory ROM (See the figure 1.1.4. ROM Expansion) capacity RAM 10K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P8 5 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 (Clock synchronous) x 2 A-D converter 10 bits x (8 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 24 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt 25 internal and 8 external sources, 4 software sources, 7 levels Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 2.7V to 3.6V (f(X IN)=10MH Z, without software wait) 2.4V to 2.7V (f(XIN)=7MH Z, without software wait) 2.2V to 2.4V (f(XIN)=7MH Z with software one-wait) Power consumption 28.5mW (f(X IN) =10MHZ, VCC =3V without software wait) I/O I/O withstand voltage 3V characteristicsOutput current 1mA Memory expansion Available (to a maximum of 1M bytes) Device configuration CMOS high performance silicon gate Package 100-pin plastic mold QFP Table 1.1.1. Performance outline of M16C/62M group Performance Outline Table 1.1.1 is a performance outline of M16C/62M group.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/62M group: (1) Support for mask ROM version and Flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM and flash memory versions) 100P6Q-A : Plastic molded QFP (mask ROM and flash memory versions) The M16C/62M group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62M group ROM Size (Byte) External ROM 128K 96K 64K 32K M30624MGM-XXXFP/GP Mask ROM version Flash memory version M30620FCMFP/GP 256K M30620MCM-XXXFP/GP M30624FGMFP/GP 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A M30620MCM-XXXGP M30620MCM-XXXFP 100P6Q-A M30624MGM-XXXFP M30624MGM-XXXGP M30620FCMFP M30620FCMGP M30624FGMFP M30624FGMGP RAM capacityROM capacity Package type RemarksType No June, 2000 128K byte 20K byte256K byte 128K byte 256K byte 10K byte 20K byte 10K byte mask ROM version Flash memory 3V version Figure 1.1.4. ROM expansion

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.1.5. Type No., memory size, and package M16C/62 Group M16C Family Package type: FP : Package 100P6S-A GP : 100P6Q-A ROM No. Omitted for blank flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version F : Flash memory version Type No. M 3 0 6 2 0 M C M – X X X F P Shows RAM capacity, pin count, etc (The value itself has no specific meaning)

Electrical characteristics

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.1. Absolute maximum ratings VREF , XIN XOUT - 0.3 to Vcc + 0.3 - 0.3 to Vcc + 0.3 - 0.3 to 4.6 - 65 to 150 300 - 20 to 85 / -40 to 85 (Note) P30 to P37,P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P00 to P07, P10 to P17, P20 to P27, RESET, P90 to P97, P100 to P107, P86, P87, P90 to P97, P100 to P107, P70, P71 P70, P71 - 0.3 to 4.6 CNV SS , BYTE, VCC =AV CC VCC =AV CC - 0.3 to 4.6 - 0.3 to 4.6 VO Pd Ta=25 VI AVcc Vcc Tstg Topr C Symbol Parameter Condition Rated value Unit Supply voltage Analog supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature V V V V V V mW C C Note : Specify a product of -40°C to 85°C to use it.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2 3.6Vcc 3.0 VccAVcc V VIH IOH (avg) mA mA Vss AVss 0.8Vcc V V V V V V V 0.8Vcc 0.5Vcc Vcc Vcc Vcc 0.2Vcc 0.2Vcc 0 0.16Vcc IOH (peak) P72 to P77, P80 to P87, P90 to P97, P100 to P107, - 5.0 - 10.0 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P31 to P37, P40 to P47, P50 to P57, P60 to P67, 10.0 5.0 mA f (XIN) IOL (peak) mAIOL (avg) V XIN, RESET, CNVSS , BYTE P70 to P77, P80 to P87, P90 to P97, P100 to P107, P31 to P37, P40 to P47, P50 to P57, P60 to P67, XIN, RESET, CNVSS , BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P70, 0.8Vcc 4.6 VP71 VIL

10 X Vcc

  • 17 Vcc=2.7V to 3.6V Vcc=2.4V to 2.7V MHz MHz 0 MHz17.5 X Vcc - 35 f (XcIN) kHz5032.768

6 X Vcc

  • 6.2 Vcc=2.7V to 3.6V Vcc=2.2V to 2.7V MHz MHz Vcc=2.2V to 2.4V Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage LOW input voltage HIGH peak output current HIGH average output current LOW peak output current LOW average output current Main clock input oscillation frequency Subclock oscillation frequency with wait No wait Symbol Parameter UnitStandard Min. Typ. Max. (data input function during memory expansion and microprocessor modes) (data input function during memory expansion and microprocessor modes) Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of -40°C to 85°C to use it. Note 4: Relationship between main clock oscillation frequency and supply voltage. Note 5: Execute case without wait, program / erase of flash memory by VCC =2.7V to 3.6V and f(BCLK) £ 6.25 MHz. Execute case with wait, program / erase of flash memory by VCC =2.7V to 3.6V and f(BCLK) £ 10.0 MHz. to 85oC / – 40°C to 85oC(Note3) unless otherwise specified) Main clock input oscillation frequency (With wait) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 2.2 2.7 3.6 Operating maximum frequency [MHZ] Supply voltage[V] (BCLK: no division) 6 X VCC –6.2MHZ Main clock input oscillation frequency (No wait) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 10.0 3.5 0.0Operating maximum frequency [MHZ] Supply voltage[V] (BCLK: no division)

10 X VCC –17MH Z

2.4 7.0 2.2 2.7 3.62.4 10.0 0.0 7.0

17.5 X VCC

–35MH Z Flash program voltage Flash read operation voltage VCC =2.7V to 3.6V V CC =2.4V to 3.6V VCC =2.7V to 3.4V V CC =2.2V to 2.4V Flash memory version program voltage and read operation voltage characteristics

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 85oC / – 40oC to 85oC (Note1), f(XIN) = 10MHZ without wait unless otherwise specified) V VXO U T 2 . 5 2 . 5 V0 . 5 VXO U T 0 . 5 0 . 5 2 . 5IO H = – 1 m A IO H = – 0 . 1 m A IO H = – 5 0 m A IO L= 1 m A IO L= 0 . 1 m A IO L= 5 0 m A P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 37, P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 37, P 40 t o P 47, P 50 t o P 57, P 60 t o P 67, P 72 t o P 77, P 40 t o P 47, P 50 t o P 57, P 60 t o P 67, P 70 t o P 77, P 80 t o P 84, P 86, P 87, P 90 t o P 97, P 1 00 t o P 1 07 H I G H P O W E R L O W P O W E R H I G H P O W E R L O W P O W E R P 80 t o P 84, P 86, P 87, P 90 t o P 97, P 1 00 t o P 1 07 H I G H P O W E R L O W P O W E R XC O U T 3 . 0 1 . 6 V . 20 . 8V 0 . 21 . 8V P 0 0 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 37, P t o P 47, P t o P 57, P t o P 67, P t o P 77, P t o P 87, P t o P 97, P t o P 07, 4 . 0 m A m A W h e n c l o c k i s s t o p p e d2 . 0V R E S E T XI N , R E S E T , C N V s s , B Y T E VI= 3 V VI= 0 V– 4 . 0 P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 37, P t o P 47, P t o P 57, P t o P 67, P t o P 77, P t o P 87, P t o P 97, P t o P 07, XI N , R E S E T , C N V s s , B Y T E XI N XC I N 1 0 . 0 3 . 0 M W M W S q u a r e w a v e , n o d i v i s i o n f ( XI N ) = 1 0 M H z m A9 . 52 1 . 2 5M a s k R O M v e r s i o n 7 5 kW P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 37, P t o P 47, P t o P 57, P t o P 67, P t o P 77, P t o P 84, P 86, P 87, P t o P 97, P t o P VXC O U T H I G H P O W E R L O W P O W E R VI= 0 V 2 03 3 0 W h e n c l o c k i s s t o p p e d T a = 2 5°C 1 . 0 m A T a = 8 5°C 2 0 . 0 W h e n c l o c k i s s t o p p e d f ( XC I N ) = 3 2 k H z W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d O s c i l l a t i o n c a p a c i t y H i g h N o t e 2 . 8 m A 0 . 9 m A f ( XC I N ) = 3 2 k H z W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d O s c i l l a t i o n c a p a c i t y L o w N o t e S q u a r e w a v e , n o d i v i s i o n f ( XI N ) = 1 0 M H z m A1 2 . 02 1 . 2 5 F l a s h m e m o r y V v e r s i o n S q u a r e w a v e f ( XC I N ) = 3 2 k H z 4 5 . 0 m A M a s k R O M v e r s i o n, f l a s h m e m o r y V v e r s i o n S D A , C L K0 t o C L K4, T A 2O U T t o T A 4O U H O L D , R D Y , T A 0I N t o T A 4I N , T B 0I N t o T B 5I N , I N T0 t o I N T5, N M I , A D T R G , C T S0 t o C T S2, S C L , K I0 t o K I3, R x D 0 t o R x D 2, SI N 3, SI N M a s k R O M v e r s i o n, f l a s h m e m o r y V v e r s i o n F l a s h m e m o r y V v e r s i o n p r o g r a m Fl a s h m e m o r y V v e r s i o n e r a s e S q u a r e w a v e , d i v i s i o n b y f ( XI N ) = 1 0 M H z S q u a r e w a v e , d i v i s i o n b y f ( XI N ) = 1 0 M H z 1 4 . 0 1 7 . 0 m A m A S y m b o l VO H H I G H o u t p u t v o l t a g e VO H VO L L O W o u t p u t v o l t a g e L O W o u t p u t v o l t a g e VO L H I G H o u t p u t v o l t a g e S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n M i nM a x .P a r a m e t e r H I G H o u t p u t v o l t a g e W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d H y s t e r e s i s H y s t e r e s i s H I G H i n p u t c u r r e n tII H L O W i n p u t c u r r e n tII L VR A M R A M r e t e n t i o n v o l t a g e IC C P o w e r s u p p l y c u r r e n t VT+ – VT– VT+ – VT– R fX I N R fX C I N F e e d b a c k r e s i s t a n c e F e e d b a c k r e s i s t a n c e R PU L L U P L O W o u t p u t v o l t a g e W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d I n s i n g l e - c h i p m o d e , t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e VS S P u l l - u p r e s i s t a n c e Note 1: Specify a product of -40°C to 85°C to use it. Note 2: With one timer operated using fC32 .

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER R L A D D E R R e f e r e n c e v o l t a g e A n a l o g i n p u t v o l t a g e k W V VI A VR E F 2 . 4 1 0 VC C VR E F 4 0 tC O N V VR E F = VC C B i t s L S B VR E F = VC C – 2 1 0 VR E F = VC C = 3 V , fA D = fA D / 2 9 . 8 m s L a d d e r r e s i s t a n c e C o n v e r s i o n t i m b i t A b s o l u t e a c c u r a c y S a m p l e & h o l d f u n c t i o n n o t a v a i l a b l e ( 8 b i t ) S t a n d a r d M i n y p a xS y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t – %1 . 0 – B i t s8 R O k W2 01 04 m AIV R E F 1 . 0 ts u 3 m s R e s o l u t i o n A b s o l u t e a c c u r a c y S e t u p t i m e O u t p u t r e s i s t a n c e R e f e r e n c e p o w e r s u p p l y i n p u t c u r r e n t( N o t e 1 ) S t a n d a r d M i n y p a xS y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t P a g e p r o g r a m t i m e B l o c k e r a s e t i m e E r a s e a l l u n l o c k e d b l o c k s t i m e L o c k b i t p r o g r a m t i m e 5 0 5 0 X n ( N o t e ) 1 2 0 6 0 0 6 0 0 X n ( N o t e ) 1 2 0 m s m s m s m s P a r a m e t e r S t a n d a r d M i n y p a x U n i t R e s o l u t i o n at Ta = – 20oC to 85oC / – 40oC to 85oC (Note2), f(XIN)=10MH Z unless otherwise specified) Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when DA register contents are not “00”, the current IVREF always flows even though Vref may have been set to be “unconnected” by the A-D control register. Note 2: Specify a product of –40°C to 85°C to use it. Note 1: Connect AVCC pin to VCC pin and apply the same electric potential. Note 2: Specify a product of –40°C to 85°C to use it. = 0V, at Ta = – 20oC to 85oC / – 40oC to 85oC (Note2), f(XIN)=10MH Z unless otherwise specified) Table 1.26.6. Flash memory version electrical characteristics (referenced to VCC = 2.7V to 3.6V, at Ta =0oC to 60oC unless otherwise specified) Note : n denotes the number of block erases. Table 1.26.7. Flash memory version program voltage and read operation voltage characteristics (Ta =0oC to 60oC) Flash program voltage Flash read operation voltage VCC =2.7V to 3.6V V CC =2.4V to 3.6V VCC =2.7V to 3.4V V CC =2.2V to 2.4V

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3V, VSS = 0V, at Ta = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.26.8. External clock input Table 1.26.9. Memory expansion and microprocessor modes 100 100 910 (Note) Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) =f(BCLK) X 2 – 90 [ns] tac2(RD – DB) =f(BCLK) X 2 – 903 X 10 [ns] tac3(RD – DB) =f(BCLK) X 2 – 903 X 109 [ns] Max. External clock rise time nstr Min. External clock input cycle time nstc External clock input HIGH pulse width nstw(H) External clock input LOW pulse width nstw(L) External clock fall time nstf ParameterSymbol Unit Standard Min. Data input setup time nstsu(DB-RD) tsu(RDY-BCLK ) ParameterSymbol UnitMax. Standard RDY input setup time ns Data input hold time nsth(RD-DB) th(BCLK -RDY) nsRDY input hold time HOLD input setup time nstsu(HOLD-BCLK ) HOLD input hold time nsth(BCLK-HOLD ) Data input access time (no wait) nstac1(RD-DB) ns ns tac2(RD-DB) tac3(RD-DB) Data input access time (with wait) Data input access time (when accessing multiplex bus area) HLDA output delay time nstd(BCLK-HLDA) (Note) (Note)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.11. Timer A input (gating input in timer mode) Table 1.26.12. Timer A input (external trigger input in one-shot timer mode) Table 1.26.13. Timer A input (external trigger input in pulse width modulation mode) Table 1.26.14. Timer A input (up/down input in event counter mode) Table 1.26.10. Timer A input (counter input in event counter mode) Timing requirements (referenced to VCC = 3V, VSS = 0V, at Ta = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Standard Max.Min. UnitParameterSymbol nstw(TAL) TAiIN input LOW pulse width 60 nstc(TA) TAiIN input cycle time 150 nstw(TAH) TAiIN input HIGH pulse width 60 Standard Max.Min. UnitParameterSymbol nstc(TA) TAiIN input cycle time 600 nstw(TAH) TAiIN input HIGH pulse width 300 nstw(TAL) TAiIN input LOW pulse width 300 Standard Max.Min. UnitParameterSymbol nstc(TA) TAiIN input cycle time 300 nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameterSymbol nstw(TAH) TAiIN input HIGH pulse width 150 nstw(TAL) TAiIN input LOW pulse width 150 Standard Max.Min. UnitParameterSymbol nstc(UP) TAiOUT input cycle time 3000 nstw(UPH) TAiOUT input HIGH pulse width 1500 nstw(UPL) TAiOUT input LOW pulse width 1500 nstsu(UP-TIN) TAiOUT input setup time 600 nsth(TIN-UP) TAiOUT input hold time 600

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.26.15. Timer B input (counter input in event counter mode) Table 1.26.16. Timer B input (pulse period measurement mode) Table 1.26.17. Timer B input (pulse width measurement mode) Table 1.26.18. A-D trigger input Table 1.26.19. Serial I/O Table 1.26.20. External interrupt INTi inputs Timing requirements (referenced to VCC = 3V, VSS = 0V, at Ta = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Standard Max.Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time (counted on one edge) 150 nstw(TBH) TBiIN input HIGH pulse width (counted on one edge) 60 nstw(TBL) TBiIN input LOW pulse width (counted on one edge) 60 tw(TBH) nsTBiIN input HIGH pulse width (counted on both edges) 160 tw(TBL) nsTBiIN input LOW pulse width (counted on both edges) 160 tc(TB) nsTBiIN input cycle time (counted on both edges) 300 Standard Max.Min. ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min.ParameterSymbol Unit nstc(TB) TBiIN input cycle time 600 nstw(TBH) TBiIN input HIGH pulse width 300 tw(TBL) nsTBiIN input LOW pulse width 300 Standard Max.Min.ParameterSymbol Unit nstc(AD) AD TRG input cycle time (trigger able minimum) 1500 nstw(ADL) AD TRG input LOW pulse width 200 Standard Max.Min.ParameterSymbol Unit nstw(INH) INTi input HIGH pulse width 380 nstw(INL) INTi input LOW pulse width 380 Standard Max.Min. ParameterSymbol Unit nstc(CK) CLKi input cycle time 300 nstw(CKH) CLKi input HIGH pulse width 150 nstw(CKL) CLKi input LOW pulse width 150 th(C-Q) nsTxDi hold time 0 tsu(D-C) nsRxDi input setup time 50 th(C-D) nsRxDi input hold time 90 td(C-Q) nsTxDi output delay time 160

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.26.22. Memory expansion and microprocessor modes (when accessing external memory area with wait) Note 3: Specify a product of –40°C to 85°C to use it. td(BCLK-AD) Address output delay time 60 ns td(BCLK-CS) Chip select output delay time 60 ns th(BCLK-AD) Address output hold time (BCLK standard) 4 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 4 ns td(BCLK-ALE) ALE signal output delay time 60 ns th(BCLK-ALE) ALE signal output hold time – 4 ns td(BCLK-RD) RD signal output delay time 60 ns th(BCLK-RD) RD signal output hold time 0 ns th(RD-AD) Address output hold time (RD standard) 0 ns td(BCLK-WR) WR signal output delay time 60 ns th(BCLK-WR) WR signal output hold time 0 ns th(WR-AD) Address output hold time (WR standard) 0 ns td(BCLK-DB) Data output delay time (BCLK standard) 80 ns th(BCLK-DB) Data output hold time (BCLK standard) 4 ns td(DB-WR) Data output delay time (WR standard) (Note1) ns th(WR-DB) Data output hold time (WR standard)(Note2) 0 ns Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = f(BCLK) – 80 [ns] Symbol StandardMeasuring condition Max.Min.Parameter Unit Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – V OL / VCC ) by a circuit of the right figure. For example, when VOL = 0.2VCC , C = 30pF, R = 1kW , hold time of output “L” level is t = – 30pF X 1kW X ln (1 – 0.2VCC / VCC ) = 6.7ns. DBi R C Figure 1.26.1

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3V, VSS = 0V at Ta = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15 = “1” unless otherwise specified) Table 1.26.23. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Note 2: Specify a product of –40°C to 85°C to use it. Symbol Standard Measuring condition Max.Min.Parameter Unit td(BCLK-AD) Address output delay time 60 ns th(BCLK-AD) Address output hold time (BCLK standard) 4n s td(BCLK-CS) Chip select output delay time 60 ns th(BCLK-CS) Chip select output hold time (BCLK standard) 4n s nsth(RD-AD) Address output hold time (RD standard) (Note 1) td(BCLK-RD) RD signal output delay time 60 ns th(BCLK-RD) RD signal output hold time 0 ns nsth(WR-AD) Address output hold time (WR standard) (Note 1) td(BCLK-WR) WR signal output delay time 60 ns td(BCLK-DB) Data output delay time (BCLK standard) 80 ns th(BCLK-DB) Data output hold time (BCLK standard) 4 ns td(DB-WR) Data output delay time (WR standard) (Note 1) ns th(BCLK-ALE) ALE signal output hold time (BCLK standard) – 4 ns td(AD-ALE) ALE signal output delay time (Address standard) (Note 1) ns th(ALE-AD) ALE signal output hold time(Address standard) 40 ns th(BCLK-WR) WR signal output hold time 0n s nsth(RD-CS) Chip select output hold time (RD standard) (Note 1) th(WR-CS) Chip select output hold time (WR standard) (Note 1) ns td(AD-RD) Post-address RD signal output delay time ns 0 td(AD-WR) Post-address WR signal output delay time ns0 tdZ(RD-AD) Address output floating start time ns8 td(BCLK-ALE) ALE signal output delay time (BCLK standard) ns60 Note 1: Calculated according to the BCLK frequency as follows: th(RD – AD) = f(BCLK) X 2 10 9 [ns] th(WR – AD) = f(BCLK) X 2 [ns] th(RD – CS) = f(BCLK) X 2 10 9 [ns] th(WR – CS) = f(BCLK) X 2 [ns] td(DB – WR) = f(BCLK) X 2 10 9 – 80 [ns] X 3 td(AD – ALE) = f(BCLK) X 2 – 45 [ns] th(WR – DB) = f(BCLK) X 2 [ns] th(WR-DB) Data output hold time (WR standard) ns (Note 1) Figure 1.26.1

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing VCC = 3V tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input Figure 1.26.2. VCC =3V timing diagram (1)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing VCC = 3V Measuring conditions :

  • VCC =3V
  • Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
  • Output timing voltage : Determined with VOL =1.5V, VOH =1.5V Memory Expansion Mode and Microprocessor Mode BCLK HOLD input HLDA output P0, P1, P2, P3, P4, 0 to P52 (Valid with or without wait) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P4 0 to P43. th(BCLK–HOLD)tsu(HOLD–BCLK) (Valid only with wait) td(BCLK–HLDA)td(BCLK–HLDA) Hi–Z tsu(RDY–BCLK) th(BCLK–RDY) BCLK RDY input RD (Multiplexed bus) (Multiplexed bus) WR, WRL, WRH WR, WRL, WRH (Separate bus) RD (Separate bus) Figure 1.26.3. VCC =3V timing diagram (2)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Read timing Write timing BCLK CSi ALE RD 60ns.max 4ns.min 4ns.min Hi–ZDB 0ns.min ADi BHE tcyc 80ns.min BCLK CSi ALE –4ns.min 60ns.max 0ns.min 4ns.min Hi–Z DB 4ns.min ADi BHE tcyc th(BCLK–ALE) th(BCLK–DB) td(BCLK–ALE) td(BCLK–WR) 0ns.min th(WR–AD) Memory Expansion Mode and Microprocessor Mode (With no wait) WR,WRL, WRH td(BCLK–CS) 60ns.max th(BCLK–CS) th(RD–CS) td(BCLK–AD) 60ns.max th(BCLK–AD) 60ns.max td(BCLK–ALE) –4ns.min th(RD–AD) 0ns.min td(BCLK–RD) th(BCLK–RD) tac1(RD–DB) th(RD–DB) 0ns.mintSU(DB–RD) td(BCLK–CS) th(BCLK–CS) 4ns.min60ns.max 0ns.min th(WR–CS) td(BCLK–AD) 60ns.max th(BCLK–AD) 60ns.max th(BCLK–ALE) th(BCLK–WR) td(BCLK–DB) th(WR–DB) td(DB–WR) (tcyc/2–80)ns.min 0ns.min 80ns.max 0ns.min VCC = 3V Figure 1.26.4. VCC =3V timing diagram (3)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Read timing Write timing BCLK CSi ALE RD 4ns.min 4ns.min Hi–Z DB 80ns.min 0ns.min ADi BHE td(BCLK–WR) 60ns.max th(BCLK–WR) 0ns.min BCLK CSi td(BCLK–CS) 60ns.max td(BCLK–AD) ALE th(BCLK–ALE) th(BCLK–CS) 4ns.min tcyc 0ns.min th(WR–CS) 0ns.min th(WR–AD) ADi BHE td(BCLK–DB) 4ns.min th(BCLK–DB) td(DB–WR) (tcyc–80)ns.min 0ns.min th(WR–DB) DBi th(RD–AD) 0ns.min td(BCLK–ALE) 60ns.max tSU(DB–RD) Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Measuring conditions :

  • VCC =3V
  • Input timing voltage : Determined with VIL=0.48V, VIH=1.5V
  • Output timing voltage : Determined with VOL =1.5V, VOH =1.5V WR,WRL, WRH td(BCLK–CS) 60ns.max th(RD–CS)tcyc td(BCLK–AD) 60ns.max th(BCLK–AD) –4ns.min th(BCLK–ALE) 60ns.max td(BCLK–RD) th(BCLK–RD) 0ns.min tac2(RD–DB) th(RD–DB) 0ns.min th(BCLK–AD)60ns.max td(BCLK–ALE) 60ns.max –4ns.min 80ns.max th(BCLK–CS) 4ns.min VCC = 3V Figure 1.26.5. VCC =3V timing diagram (4)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Measuring conditions :

  • VCC =3V
  • Input timing voltage : Determined with VIL=0.48V,VIH=1.5V
  • Output timing voltage : Determined with VOL =1.5V,VOH =1.5V Read timing Write timing 0ns.min 60ns.max –4ns.min th(BCLK–CS) 4ns.min tcyc 80ns.max th(BCLK–DB) 4ns.min td(DB–WR) (tcyc*3/2–80)ns.min Address Data output (tcyc/2)ns.min Address (tcyc/2–60)ns.min td(BCLK–ALE) td(BCLK–WR) 4ns.min td(BCLK–CS) 60ns.max 4ns.min th(BCLK–CS) 4ns.min tcyc th(RD–DB) 0ns.min Address (tcyc/2)ns.min Data inputAddress tac3(RD–DB) tdz(RD–AD) 8ns.max td(AD–RD) 0ns.min td(AD–WR) BCLK CSi ALE ADi BHE ADi /DBi BCLK CSi ALE RD ADi BHE ADi /DBi WR,WRL, WRH th(RD–CS) td(AD–ALE) (tcyc/2–45)ns.min tSU(DB–RD) 80ns.min th(ALE–AD) 40ns.min td(BCLK–AD) 60ns.max 60ns.max td(BCLK–ALE) th(BCLK–ALE) –4ns.min (tcyc/2)ns.min th(RD–AD) th(BCLK–AD) th(BCLK–RD) 0ns.mintd(BCLK–RD) 60ns.max td(BCLK–CS) 60ns.max th(WR–CS) (tcyc/2)ns.min td(BCLK–DB) td(AD–ALE) td(BCLK–AD) 60ns.max th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) th(WR–AD) th(BCLK–WR) th(BCLK–ALE) 0ns.min 60ns.max VCC = 3V Figure 1.26.6. VCC =3V timing diagram (5)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (timer mode) Usage Precaution Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (1) Setting the count start flag to “0” while a count is in progress causes as follows:

  • The counter stops counting and a content of reload register is reloaded.
  • The TAi OUT pin outputs “L” level.
  • The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
  • Selecting one-shot timer mode after reset.
  • Changing operation mode from timer mode to one-shot timer mode.
  • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. Timer A (one-shot timer mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
  • Selecting PWM mode after reset.
  • Changing operation mode from timer mode to PWM mode.
  • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. Timer A (pulse width modulation mode) Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Stop Mode and Wait Mode A-D Converter (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer B (pulse period/pulse width measurement mode) Interrupts (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 ms or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A- D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. (1) Reading address 00000

  • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
  • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. (3) The NMI interrupt
  • The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused.
  • Do not get either into stop mode with the NMI pin set to “L”. (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) External interrupt

  • When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register
  • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
  • When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below in- structions to change the register. Instructions : AND, OR, BCLR, BSET Noise (1) Insert bypass capacitor between VCC and VSS pin for noise and latch up countermeasure.
  • Insert bypass capacitor (about 0.1 mF) and connect short and wide line between VCC and VSS lines.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Notes on the microprocessor mode and transition after shifting from the micropro- cessor mode to the memory expansion mode

  • Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. For that reason, the internal ROM area cannot be accessed.
  • Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNV SS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCM-XXXFP/GP MASK ROM CONFIRMATION FORM GZZ-SH13-95B<02A0> Date : TEL ( ) Receipt Section head signature Supervisor signature Customer Company name Date issued Date : Note : Please complete all items marked h . h Issuance signature Submitted by Supervisor h 1. Check sheet Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. h 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30620MCM-XXXFP, submit the 100P6S mark specification sheet. For the M30620MCM-XXXGP, submit the 100P6Q mark specification sheet. h 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do not use? f(X IN) = MH Z Microcomputer type No. : M30620MCM-XXXFP M30620MCM-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-95B<02A0> MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCM-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do not use? f(X CIN) = kH Z (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. h 4. Special item (Indicate none if there is not specified item) (V)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGM-XXXFP/GP MASK ROM CONFIRMATION FORM GZZ-SH13-48B<98A1> Date : TEL ( ) Receipt Section head signature Supervisor signature Customer Company name Date issued Date : Note : Please complete all items marked h . h Issuance signature Submitted by Supervisor h 1. Check sheet Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. h 2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30624MGM-XXXFP, submit the 100P6S mark specification sheet. For the M30624MGM- XXXGP, submit the 100P6Q mark specification sheet. h 3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do not use? f(X IN) = MH Z Microcomputer type No. : M30624MGM-XXXFP M30624MGM-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-48B<98A1> MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGM-XXXFP/GP MASK ROM CONFIRMATION FORM Mask ROM number (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator Quartz-crystal oscillator External clock input Other ( ) What frequency do not use? f(X CIN) = kH Z (3) Which operation mode do you use? Single-chip mode Memory expansion mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. h 4. Special item (Indicate none if there is not specified item) (V)

(Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/62M (Low voltage version) and M30624FGLFP/GP Item M16C/62M (Low voltage version) M30624FGLFP/GP Serial I/O Memory version Flash memory version only IIC bus mode Memory area Memory expansion

1.2 Mbytes mode

4 Mbytes mode

1 Mbyte fixed

No CTS/RTS separate function CTS/RTS separate function Analog or digital delay is selected as SDA delay Only analog delay is selected as SDA delay Mask ROM version Flash memory version Standard serial I/O mode (Flash memory version) Clock synchronized only Clock synchronized Clock asynchronized

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M16C/62M Group (Low voltage version) Specifications REV.B Jun. First Edition 2000 Edition by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2000 MITSUBISHI ELECTRIC CORPORATION