M30220

M30220 MITSUBISHI | Alldatasheet

Document overview

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Technical content

Features

2.7V to 5.5V (f(XIN)=7MHz with software one-wait) (including key input interrupt) 1 line (P77, shared with NMI pin) 2, 3 and 4 time sharing 4 common outputs 48 segment outputs built-in set-up condencer circuit (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Camera, Home appliances, Portable equipment, Audio, office equipment, etc. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

Description

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns (f(X IN)=10MHz Memory ROM 96 Kbytes capacity RAM 6 Kbytes I/O port P0 to P13 (except P77) 8 bits x 11, 3 bits x 1, 6 bits x 1, 7 bits x 1 Input port P7 7 1 bit x 1 Multifunction TA0 to TA7 16 bits x 8 timer TB0 to TB5 16 bits x 6 Real time port outputs 8 bits x 4 lines Serial I/O UART0 to UART2 (UART or clock synchronous) x 3 A-D converter 10 bits x 8 channels D-A converter 8 bits x 3 channels DMAC 2 channel(trigger:24 sources) LCD COM0 to COM3 4 lines SEG0 to SEG47 48 lines (32 lines are shared with I/O ports) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 25 internal and 8 external sources, 4 software sources Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 4.5V to 5.5V (f(X IN)=10MHz) 2.7V to 5.5V (f(XIN)=7MHz with software one-wait) Power consumption 95mW I/O withstand voltage (P0 to P13) 5 V Output current P1 to P9,P13 5 mA P0, P10 to P12 0.1mA("H" output), 2.5mA("L" output) Device configuration CMOS silicon gate Package 144-pin plastic mold QFP Table 1.1.1. Performance outline of M30220 group Performance Outline Table 1.1.1 is performance outline of M30220 group. I/O char- acteristics

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description VCC , VSS CNV SS XCIN XCOUT AV CC AV SS VREF P00 to P07 P10 to P17 P30 to P35 P40 to P47 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P3 I/O port P4 Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. This pin is a power supply input for the A-D converter. Connect it to VCC . This pin is a power supply input for the A-D converter. Connect it to VSS . This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. Pins in this port also use as LCD segment output and real time port output. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. This is a 6-bit I/O port equivalent to P0. P3 0 to P33 also function as input pins for the key input interrupt function. Pin name I/O Analog power supply input RESET I/O port P5 I/O port P6 P50 to P57 P60 to P67 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. 0 to P27 I/O port P2 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. I I I O I I/O I/O I/O I/O I/O I/O I/O This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer B0 to B5 and INT 3 input pins, CKOUT output pin as selected by software. This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer A0 to A3 I/O pins, INT 4 input pin as selected by software. These pins are provided for the sub clock generating circuit. Connect a ceramic resonator or crystal between the X CIN and the XCOUT pins. To use an externally derived clock, input it to the XCIN pin and leave the XCOUT pin open. XIN XOUT Clock input Clock output I O These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Signal name FunctionPin name I/O I/O I/O I/O I/O I/O port P7 I/O port P8 I/O port P9 I/O port P10 P70 to P76 P80 to P87 P90 to P97 P100 to P107 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as A-D converter analog input pins as selected by software. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD as selected by software. 7 I This is an 3-bit I/O port equivalent to P0. Pins in this port also function as D-A converter analog output pins or start trigger for A-D input pins. I/OI/O port P11P11 0 to P117 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD as selected by software. I/OI/O port P13P130 to P132 OSegment output SEG 0 to SEG 15 Pins in this port function as SEG output for LCD drive circuit. OCommon output COM 0 to COM 3 Power supply input for LCD drive circuit.Power supply input for LCD VL1 to VL3 Pins in this port function as common output for LCD drive circuit. Step-up condenser connect port C 1, C2 Pins in this port function as external pin for LCD step-up condenser. Connect a condenser between C1 and C2. I/OI/O port P12P120 to P127 This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD and real time port output. This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer A4 to A7 I/O pins, INT 5 input pin as selected by software. P70 to P76 are I/O ports equivalent to P0 (P70 and P71 are N channel open-drain output). Pins in this port also function as UART2 I/O pin, INT 0 to INT2 input pins as selected by software. 7 is an input-only port that also functions for NMI.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines CDZSBOIUIPL Figure 1.5.1. Central processing unit register

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Figure 1.5.2. Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Flag register (FLG) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CDZSBOIUIPL b0b15

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Figure 1.6.3. Device's internal status after a reset is cleared The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. 0100 1 000 000 0 0001 0016 0016 0000 0016 0016 0000 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 0 0? 000 000? 000? 0 0 ? 00000 0 0 ? 00000 0000 00 0 000? 000? 000? 000? 000? 000? 000? 00 000? 00 000? 00 000? ?000 ?000 ?000 0000 0 000 0016 0016 0016 ?00000 ?00000 0 000 0 00 0 000 0 00 0 00 00 0 0 00 0 0 ? 00000 0 ? 00000 0 ? 00000 0 0 0000 0016 0016 (26)UART0 receive interrupt control register (005216)••• (1)Processor mode register 0 (0004 16)••• (2)Processor mode register 1 (0005 16)••• (3)System clock control register 0 (0006 16)••• (4)System clock control register 1 (0007 16)••• (5)Address match interrupt enable register (000916)••• (6)Protect register (000A 16)••• (7)Watchdog timer control register (000F 16)••• (8)Address match interrupt register 0 (001016)••• (001116)••• (001216)••• (9)Address match interrupt register 1 (001416)••• (001516)••• (001616)••• (10)DMA0 control register (002C 16)••• (11)DMA1 control register (003C 16)••• (12)INT3 interrupt control register (0044 16)••• (13)Timer B5 interrupt control register (004516)••• (14)Timer B4 interrupt control register (004616)••• (15)Timer B3 interrupt control register (004716)••• (16)Timer A7 interrupt control register (004816)••• (17)Timer A6 interrupt control register (004916)••• (18)Timer A5 interrupt control register (004A16)••• (19)DMA0 interrupt control register (004B 16)••• (20)DMA1 interrupt control register (004C 16)••• (21)Key input interrupt control register (004D16)••• (22)A-D conversion interrupt control register (004E16)••• (23)UART2 transmit interrupt control register (004F16)••• (24)UART2 receive interrupt control register (005016)••• (25)UART0 transmit interrupt control register (005116)••• (58)UART2 transmit/receive mode register (037816)••• (27)UART1 transmit interrupt control register (005316)••• (28)UART1 receive interrupt control register (005416)••• (29)Timer A0 interrupt control register (005516)••• (30)Timer A1 interrupt control register (005616)••• (31)Timer A2 interrupt control register (005716)••• (32)Timer A3 interrupt control register (005816)••• (33)Timer A4 interrupt control register (005916)••• (34)Timer B0 interrupt control register (005A16)••• (35)Timer B1 interrupt control register (005B16)••• (36)Timer B2 interrupt control register (005C16)••• (37)INT0 interrupt control register (005D 16)••• (38)INT1 interrupt control register (005E 16)••• (39)INT2 interrupt control register (005F 16)••• (40)LCD mode register (0120 16)••• (41)Segment output enable register (0122 16)••• (42)Key input mode register (0126 16)••• (43)Count start flag 1 (0340 16)••• (44)One-shot start flag 1 (0342 16)••• (45)Trigger select flag 1 (0343 16)••• (46)Up-down flag 1 (0344 16)••• (47)Timer A5 mode register (0356 16)••• (48)Timer A6 mode register (0357 16)••• (49)Timer A7 mode register (0358 16)••• (50)Timer B3 mode register (035B 16)••• (51)Timer B4 mode register (035C 16)••• (52)Timer B5 mode register (035D 16)••• (53)Interrupt cause select register 0 (035E16)••• (54)Interrupt cause select register 1 (035F16)••• (57)UART2 special mode register (0377 16)••• 0 11 00 00 0 (55)Clock division counter control register (036016)••• 0 0016(56)UART2 special mode register 2 (0376 16)••• x : Nothing is mapped to this bit ? : Undefined 0016

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.6.4. Device's internal status after a reset is cleared 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0000000 000 ? ?? 000000 0016 (85)A-D control register 0 (86)A-D control register 1 (87)D-A control register (88)Port P0 direction register (89)Port P1 direction register (90)Port P2 direction register (91)Port P3 direction register (92)Port P4 direction register (93)Port P5 direction register (94)Port P6 direction register (95)Port P7 direction register (96)Port P8 direction register (97)Port P9 direction register (98)Port P10 direction register (99)Port P11 direction register 000016 000016 000016 0000016 000016 000016 000016 000016 0016 000 0016 (113)Flag register (FLG) (100)Port P12 direction register (101)Port P13 direction register (102)Pull-up control register 0 (103)Pull-up control register 1 (104)Pull-up control register 2 (105)Real time port control register (106)Data registers (R0/R1/R2/R3) (107)Address registers (A0/A1) (108)Frame base register (FB) (109)Interrupt table register (INTB) (110)User stack pointer (USP) (111)Interrupt stack pointer (ISP) (112)Static base register (SB) 0016 11000 0 00 00011 1 10 (03D616)· · · (03D716)· · · (03DC16)· · · (03E216)· · · (03E316)· · · (03E616)· · · (03E716)· · · (03EA16)· · · (03EB16)· · · (03EE16)· · · (03EF16)· · · (03F216)· · · (03F316)· · · (03F616)· · · (03F716)· · · (03FA16)· · · (03FB16)· · · (03FC16)· · · (03FD16)· · · (03FE16)· · · (03FF16)· · ·

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• · · (59) UART2 transmit/receive control register 0 (60)UART2 transmit/receive control register 1 (61)Count start flag 0 (62) Clock prescaler reset flag (63)One-shot start flag 0 (64)Trigger select flag 0 (65)Up-down flag 0 (66)Timer A0 mode register (67)Timer A1 mode register (68)Timer A2 mode register (84) A-D control register 2 (69)Timer A3 mode register (70)Timer A4 mode register (71)Timer B0 mode register (72)Timer B1 mode register (73)Timer B2 mode register (74)UART0 transmit/receive mode register (75)UART0 transmit/receive control register 0 (76)UART0 transmit/receive control register 1 (77)UART1 transmit/receive mode register (78)UART1 transmit/receive control register 0 (79)UART1 transmit/receive control register 1 (80)UART transmit/receive control register 2 (82)DMA0 cause select register (83)DMA1 cause select register (81)Flash memory control register (Note) (037C16)· · · (037D16)· · · (038016)· · · (038116)· · · (038216)· · · (038316)· · · (038416)· · · (039616)· · · (039716)· · · (039816)· · · (039916)· · · (039A16)· · · (039B16)· · · (039C16)· · · (039D16)· · · (03A016)· · · (03A416)· · · (03A516)· · · (03A816)· · · (03AC16)· · · (03AD16)· · · (03B016)· · · (03B416)· · · (03B816)· · · (03BA16)· · · (03D416)· · · 0016 00000 0 01 01000 0 00 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 x : Nothing is mapped to this bit ? : Undefined 0 00 0 0 0 0 0 ?00 0 0 0 0 ?00 0 0 0 0 ?00 0 0 0 00 010000 00 000100 00 010000 00 000100 00 0 0 0 00 0 000 000 The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note : This register is only exist in flash memory version.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR Figure 1.7.1. Location of peripheral unit control registers (1) 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C 16 010D 16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 012016 012116 012216 012316 012416 012516 012616 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer A1 interrupt control register (TA1IC) Timer A3 interrupt control register (TA3IC) UART0 transmit interrupt control register (S0TIC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer A2 interrupt control register (TA2IC) Timer A4 interrupt control register (TA4IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) INT3 interrupt control register (INT3IC) INT4 interrupt control register (INT4IC) INT5 interrupt control register (INT5IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) Timer A7 interrupt control register (TA7IC) Timer A6 interrupt control register (TA6IC) Timer A5 interrupt control register (TA5IC) DMA0 source pointer (SAR0) DMA0 destination pointer (DAR0) DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) DMA1 source pointer (SAR1) DMA1 destination pointer (DAR1) DMA1 transfer counter (TCR1) DMA1 control register (DM1CON) LCD RAM0(LRAM0) LCD RAM1(LRAM1) LCD RAM2(LRAM2) LCD RAM3(LRAM3) LCD RAM4(LRAM4) LCD RAM5(LRAM5) LCD RAM6(LRAM6) LCD RAM7(LRAM7) LCD RAM8(LRAM8) LCD RAM9(LRAM9) LCD RAM10(LRAM10) LCD RAM11(LRAM11) LCD RAM12(LRAM12) LCD RAM13(LRAM13) LCD RAM14(LRAM14) LCD RAM15(LRAM15) LCD RAM16(LRAM16) LCD RAM17(LRAM17) LCD RAM18(LRAM18) LCD RAM19(LRAM19) LCD RAM20(LRAM20) LCD RAM21(LRAM21) LCD RAM22(LRAM22) LCD RAM23(LRAM23) DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) LCD mode register (LCDM) Segment output enable register (SEG) Key input mode register (KUPM) LCD frame frequency counter (LCDTIM) Bus collision detection interrupt control register (BCNIC)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.2. Location of peripheral unit control registers (2) 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C 16 034D 16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C 16 035D 16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C 16 036D 16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C 16 037D 16 037E16 037F16 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Count start flag 0 (TABSR0) One-shot start flag 0 (ONSF0) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Up-down flag 0 (UDF0) Timer A3 (TA3) Timer A4 (TA4) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Trigger select register 0 (TRGSR0) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART transmit/receive control register 2 (UCON) Clock prescaler reset flag (CPSRF) Count start flag 1 (TABSR1) Timer B3 (TB3) Timer B4 (TB4) Timer B5 (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register(TB5MR) Timer A5 (TA5) Timer A6 (TA6) Timer A7 (TA7) One-shot start flag 1 (ONSF1) Trigger select register 1 (TRGSR1) Up-down flag 1(UDF1) Timer A5 mode register (TA5MR) Timer A6 mode register (TA6MR) Timer A7 mode register (TA7MR) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) Interrupt cause select register 1 (IFSR1) DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) Clock division counter (CDC) Interrupt cause select register 0 (IFSR0) Clock division counter control register (CDCC) UART2 special mode register 2(U2SMR2) Flash memory control register (FMCR)(Note) Note : This register is only exist in flash memory version.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SFR Figure 1.7.3. Location of peripheral unit control registers (3) 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) Port P2 direction register (PD2) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Port P8 (P8) Port P8 direction register (PD8) Port P9 (P9) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) A-D register 7 (AD7) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) A-D control register 2 (ADCON2) D-A register 2 (DA2) Port P11 (P11) Port P11 direction register (PD11) Port P12 (P12) Port P12 direction register (PD12) Real time port control register (RTP) Port P13 (P13) Port P13 direction register (PD13)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516). (Note) A software wait is inserted in the internal ROM/RAM area. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit. Table 1.8.1 shows the software waits and bus cycles. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to “1”. Table 1.8.1. Software waits and bus cycles Area Wait bit Bus cycle 1 2 BCLK cycles SFR Internal ROM/RAM 0 1 BCLK cycle Invalid 2 BCLK cycles

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high- speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock (f1, f8, f32, fAD ) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC132 This clock is derived by dividing the sub-clock by 1 or 32. The clock is selected by fC132 clock select bit (bit4 at address 000716). It is used for the timer A and timer B counts, intermittent pull up operation of key input. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Stop Mode, Wait Mode Table 1.9.3. Port status during wait mode Pin Status Port Retains status before wait mode CK OUT When fC1 selected Does not stop When f1, clock devided counter output selected Retains status before stop mode Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is main-tained. Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.9.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Pin Status Port Retains status before stop mode CK OUT When fC1 selected “H” When f1, clock devided counter output selected Retains status before stop mode Table 1.9.2. Port status during stop mode Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re- mains above 2V. Because the oscillation , BCLK, f 1 to f32, fC , fC132 , fC1 , fC32 and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK

01000 Invalid Division by 2 mode

10000 Invalid Division by 4 mode

Invalid Invalid 0 1 0 Invalid Division by 8 mode

11000 Invalid Division by 16 mode

00000 Invalid No-division mode

Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Status Transition Of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub- clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper- ates according to its assigned clock.
• Low-speed mode f C becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.9.7 is the state transition diagram of the above modes.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control Figure 1.9.7. State transition diagram of Power control mode Transition of stop mode, wait mode Transition of normal mode Reset Medium-speed mode (divided-by-8 mode)Interrupt CM10 = “1” All oscillators stopped CPU operation stopped Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 Low-speed mode High-speed mode Main clock is oscillating Sub clock is stopped Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode High-speed/medium- speed mode Low-speed/low power dissipation mode Normal mode Stop mode Stop mode Stop mode All oscillators stopped All oscillators stopped Wait mode Wait mode Wait mode CPU operation stopped CPU operation stopped Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction CM10 = “1” Interrupt Interrupt CM10 = “1” BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = “0” CM06 = “1” High-speed mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = “1” BCLK : f(XCIN) CM07 = “1” Main clock is oscillating Sub clock is oscillating CM07 = “0” (Note 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” CM07 = “1” (Note 2) CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM07 = “1” (Note 2) CM05 = “1” CM06 = “0” (Notes 1,3) CM06 = “1” (Notes 1, 3) Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. (Refer to the following for the transition of normal mode.)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection Figure 1.9.8. Protect register Protect register Symbol Address When reset PRCR 000A 16 XXXXXX00 2 Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 000716) WR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.9.8 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 000616), system clock control register 1 (address 000716) can only be changed when the respective bit in the protect register is set to “1”. The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A 16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

• Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter- rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re- quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an “L” is input to the RESET pin.
• NMI interrupt An NMI interrupt occurs if an “L” is input to the NMI pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates.
• Key-input interrupt ___ A key-input interrupt occurs if either a rising edge or a falling edge is input to the KI pin.
• A-D conversion interrupt This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2 transmission interrupt These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2 reception interrupt These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A7 interrupt These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates.
• INT0 interrupt through INT5 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use NMI FFFF8 16 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC 16 to FFFFF16 Note: Interrupts used for debugging purposes only. Figure 1.10.2. Format for specifying interrupt vector addresses /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 LSBMSB Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.10.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked I flag+0 to +3 (Note 1) BRK instructionSoftware interrupt number 0 +44 to +47 (Note 1) Software interrupt number 11 +48 to +51 (Note 1)Software interrupt number 12 +52 to +55 (Note 1)Software interrupt number 13 +56 to +59 (Note 1)Software interrupt number 14 +68 to +71 (Note 1)Software interrupt number 17 +72 to +75 (Note 1)Software interrupt number 18 +76 to +79 (Note 1)Software interrupt number 19 +80 to +83 (Note 1)Software interrupt number 20 +84 to +87 (Note 1)Software interrupt number 21 +88 to +91 (Note 1)Software interrupt number 22 +92 to +95 (Note 1)Software interrupt number 23 +96 to +99 (Note 1)Software interrupt number 24 +100 to +103 (Note 1)Software interrupt number 25 +104 to +107 (Note 1)Software interrupt number 26 +108 to +111 (Note 1)Software interrupt number 27 +112 to +115 (Note 1)Software interrupt number 28 +116 to +119 (Note 1)Software interrupt number 29 +120 to +123 (Note 1)Software interrupt number 30 +124 to +127 (Note 1)Software interrupt number 31 +128 to +131 (Note 1)Software interrupt number 32 +252 to +255 (Note 1)Software interrupt number 63 to Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause select bit (bit 4 in address 035E16 ). Note 3: It is selected by interrupt request cause select bit (bit 6, 7 in address 035F16 ). Cannot be masked I flag +40 to +43 (Note 1)Software interrupt number 10 +60 to +63 (Note 1)Software interrupt number 15 +64 to +67 (Note 1)Software interrupt number 16 +20 to +23 (Note 1)Software interrupt number 5 +24 to +27 (Note 1)Software interrupt number 6 +28 to +31 (Note 1)Software interrupt number 7 +32 to +35 (Note 1)Software interrupt number 8 +16 to +19 (Note 1) INT3Software interrupt number 4 +36 to +39 (Note 1) Timer A6 Software interrupt number 9 Timer A7 Timer B3 Timer B4 Timer B5 to DMA0 DMA1 Key input interrupt A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3/INT4 Timer A4/INT5 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt Timer A5/Bus collision detection UART2 transmit UART2 receive (Note 2) (Note 3) (Note 3)

• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.10.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.10.4. Interrupt levels enabled according to the contents of the IPL Table 1.10.3. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16. After this, the corresponding interrupt request bit becomes “0”. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.10.4 shows the interrupt response time. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.10.4. Interrupt response time

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt sources without priority levels Value set in the IPL Watchdog timer, NMI Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.10.6 is set in the IPL. Table 1.10.6. Relationship between interrupts without interrupt priority levels and IPL Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Table 1.10.5. Time required for executing the interrupt sequence Reset Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

contents

0000 Indeterminate SP-2 SP-4 vec vec+2 PC

Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.10.5. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 1.10.5. Time required for executing the interrupt sequence

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.10.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM ) Figure 1.10.6. State of stack before and after acceptance of interrupt request

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.10.7. Operation of saving registers (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH ) The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.10.7 shows the operation of the saving registers. Note: Stack pointer indicated by U flag.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.10.9. Maskable interrupts priorities (peripheral I/O interrupts) Timer B2 Timer B0 Timer A3/INT4 Timer A1 Timer B1 Timer A4/INT5 Timer A2 UART1 reception UART0 reception UART2 reception A-D conversion DMA1 Timer A5/Bus collision detection Timer A0 UART1 transmission UART0 transmission UART2 transmission Key input interrupt DMA0 Processor interrupt priority level (IPL) Interrupt enable flag (I flag) INT1 INT2 INT0 Watchdog timer Reset DBC NMI Interrupt request accepted Level 0 (initial value)Priority level of each interrupt High Low Priority of peripheral I/O interrupts (if priority levels are same) Timer B4 INT3 Timer B3 Timer B5 Timer A7 Timer A6 Address match Interrupt request level judgment output

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts Precautions for Interrupts (1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited. (3) The NMI interrupt
• The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused.
• The NMI pin also serves as P77, which is exclusively input. Reading the contents of the P7 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time when the NMI interrupt is input.
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down.
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt.
• Signals input to the NMI pin require an “L” level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 through INT5 regardless of the CPU operation clock.
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.10.17 shows the procedure for changing the INT interrupt generate factor.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts Figure 1.10.17. Switching condition of INT interrupt request Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E

16 Indeterminate

The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.11.2. Watchdog timer control and start registers

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram used by the DMAC. Figure 1.12.1. Block diagram of DMAC /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Data bus low-order bits DMA latch high-order bitsDMA latch low-order bits DMA0 source pointer SAR0(20) DMA0 destination pointer DAR0 (20) DMA0 forward address pointer (20) (Note) Data bus high-order bits /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Address bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA1 destination pointer DAR1 (20) DMA1 source pointer SAR1 (20) DMA1 forward address pointer (20) (Note)/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA0 transfer counter reload register TCR0 (16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 transfer counter TCR1 (16) /LiteDiagLines /LiteDiagLines (addresses 002916, 002816) (addresses 003916, 003816) (addresses 002216 to 002016) (addresses 002616 to 002416) (addresses 003216 to 003016) (addresses 003616 to 003416) Note: Pointer is incremented by a DMA request. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0 or INT1 or both edge Timer A0 to timer A7 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive
• Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timingWhen an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer, and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Table 1.12.1. DMAC specifications Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. Forward address pointer and reload timing for transfer counter

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA0 request cause select register Symbol Address When reset DM0SL 03B8 16 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DMA request cause select bitDSEL0 RW DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Bit name 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) /Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) /Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit DMA request cause expansion bitDMS 0 : Normal 1 : Expanded cause /LiteDiagLines/LiteDiagLines/LiteDiagLines Figure 1.12.2. DMAC register (1)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMAi control register Symbol Address When reset DMiCON(i=0,1) 002C 16, 003C16 00000X002 Bit name FunctionBit symbol Transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bitsDMBIT RW DMASL DMAS DMAE Repeat transfer mode select bit 0 : Single transfer 1 : Repeat transfer DMA request bit (Note 1)0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward DMA enable bit Source address direction select bit (Note 3) Destination address direction select bit (Note 3) 0 : Fixed 1 : Forward DSD DAD Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. (Note 2) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DMA1 request cause select register Symbol Address When reset DM1SL 03BA 16 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 DMA request cause select bitDSEL0 RW DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DSR b3 b2 b1 b0 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2(DMS=0) /timer A5(DMS=1) 0 1 0 1 : Timer A3(DMS=0) /timer A6 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /timer A7 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit name DMA request cause expansion bitDMS 0 : Normal 1 : Expanded cause /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Figure 1.12.3. DMAC register (2)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC b7 b0 b7 b0 (b8)(b15) Function RW

• Transfer counter Set a value one less than the transfer count Symbol Address When reset TCR0 0029 16, 002816 Indeterminate TCR1 0039 16, 003816 Indeterminate DMAi transfer counter (i = 0, 1) Transfer count specification 000016 to FFFF16 (b23) b3 b0 b7 b0 b7 b0 Function RW
• Source pointer Stores the source address Symbol Address When reset SAR0 0022 16 to 002016 Indeterminate SAR1 0032 16 to 003016 Indeterminate DMAi source pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Symbol Address When reset DAR0 0026 16 to 002416 Indeterminate DAR1 0036 16 to 003416 Indeterminate b3 b0 b7 b0 b7 b0 Function RW
• Destination pointer Stores the destination address DMAi destination pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 (b23) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.12.4. DMAC register (3)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC (1) Transfer cycle The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.12.5 shows the example of the transfer cycles for a source read. For convenience, the destina- tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC BCLK (Internal signal) Address bus (Internal signal) RD signal (Internal signal) WR signal (Internal signal) Data bus (Internal signal) CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. BCLK (Internal signal) Address bus (Internal signal) RD signal (Internal signal) WR signal (Internal signal) Data bus (Internal signal) CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle (3) One wait is inserted into the source read under the conditions in (1) BCLK (Internal signal) Address bus (Internal signal) RD signal (Internal signal) WR signal (Internal signal) Data bus (Internal signal) CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle Source + 1 Source + 1 (2) 16-bit transfers and the source address is odd BCLK (Internal signal) Address bus (Internal signal) RD signal (Internal signal) WR signal (Internal signal) Data bus (Internal signal) CPU use CPU use CPU use CPU useSource Source Destination Destination Dummy cycle Dummy cycle Source + 1 Source + 1 (4) One wait is inserted into the source read under the conditions in (2) Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.12.5. Example of the transfer cycles for a source read

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC Transfer unit Access address No. of read cycles No. of read cycles 8-bit transfers Even 1 1 (DMBIT= “1”) Odd 1 1 16-bit transfers Even 1 1 (DMBIT= “0”) Odd 2 2 Table 1.12.2. No. of DMAC transfer cycles Internal memory Internal ROM/RAM Internal ROM/RAM SFR area No wait With wait 12 2 Coefficient j, k (2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC DMA enable bit Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer There are fourteen 16-bit timers. These timers can be classified by function into timers A (eight) and timers timers. Figure 1.13.1. Timer A block diagram

• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode TA0 IN TA1 IN TA2 IN TA3 IN (Note 1) TA4 IN (Note 2) Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 f1 f8 f32 fC132 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter f32 XIN Timer B2 overflow Note 1: The TA3IN pin (P47) is shared with INT4 pin, so be careful. Note 2: The TA4IN pin (P81) is shared with INT5 pin, so be careful.
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode TA5 IN TA6 IN TA7 IN Timer A5 Timer A6 Timer A7 Noise filter Noise filter Noise filter 1/32 fC32XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler fC1 fC132 fc132 clock select bit (bit 4 at address 000716) Port P0 real time output trigger Port P1 real time output trigger Port P12 real time output trigger Timer A5 interrupt Timer A6 interrupt Timer A7 interrupt Port P2 real time output trigger Timer B5 overflow

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.2. Timer B block diagram

• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TB0 IN TB1 IN TB2 IN Timer B0 Timer B1 Timer B2 f1 f8 f32 fC132 Timer B0 interrupt Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler Timer A0 to timer A4
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TB3 IN TB4 IN TB5 IN Timer B3 Timer B4 Timer B5 Timer B3 interrupt Noise filter Noise filter Noise filter Timer B1 interrupt Timer B2 interrupt Timer B4 interrupt Timer B5 interrupt fC1 fC132 Timer A5 to timer A7 fc132 clock select bit (bit 4 at address 000716)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.5. Timer A-related registers (2) Symbol Address When reset TABSR0 0380 16 0016 Count start flag 0 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset TA0 0387 16,038616 Indeterminate TA1 0389 16,038816 Indeterminate TA2 038B 16,038A16 Indeterminate TA3 038D 16,038C16 Indeterminate TA4 038F 16,038E16 Indeterminate TA5 0347 16,034616 Indeterminate TA6 0349 16,034816 Indeterminate TA7 034B 16,034A16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Ai register (Note) WR

• Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
• Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
• One-shot timer mode 0000 16 to FFFF16 Counts a one shot width
• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FE16 (Both high-order and low-order addresses) 000016 to FFFE16 Note: Read and write data in 16-bit units. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset TABSR1 0340 16 000XX000 2 Count start flag 1 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B5 count start flag Timer B4 count start flag Timer B3 count start flag Timer A7 count start flag Timer A6 count start flag Timer A5 count start flag0 : Stops counting 1 : Starts counting TB5S TB4S TB3S TA7S TA6S TA5S /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 : Stops counting 1 : Starts counting Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.6. Timer A-related registers (3) Timer A7 up/down flag Timer A6 up/down flag Timer A5 up/down flag Timer A7 two-phase pulse signal processing select bit Symbol Address When reset UDF1 0344 16 XX0XX000 2 TA7P Up/down flag 1 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 TA7UD TA6UD TA5UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Timer A4 up/down flag Timer A3 up/down flag Timer A2 up/down flag Timer A1 up/down flag Timer A0 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Symbol Address When reset UDF0 0384 16 0016 TA4P TA3P TA2P Up/down flag 0 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 TA4UD TA3UD TA2UD TA1UD TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines TA1OS TA2OS TA0OS One-shot start flag 0 Symbol Address When reset ONSF0 0382 16 00X000002 Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag TA3OS TA4OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Timer A0 event/trigger select bit b7 b6 Note: Set the corresponding port direction register to “0”. WR 1 : Timer start When read, the value is “0”/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.7. Timer A-related registers (4) TA1TGL Symbol Address When reset TRGSR0 0383 16 0016 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected Trigger select register 0 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Timer A2 event/trigger select bit Timer A3 event/trigger select bit Timer A4 event/trigger select bit WR TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines TA6TGL Symbol Address When reset TRGSR1 0343 16 XXXX0000 2 Timer A6 event/trigger select bit 0 0 : Input on TA6IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA5 overflow is selected 1 1 : TA7 overflow is selected Trigger select register 1 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA7IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA5 overflow is selected 1 1 : TA6 overflow is selected Timer A7 event/trigger select bit WR TA6TGH TA7TGL TA7TGH b1 b0 b3 b2 Note: Set the corresponding port direction register to “0”. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA6OS TA7OS TA5OS One-shot start flag 1 Symbol Address When reset ONSF1 0342 16 00XXX000 2 Timer A5 one-shot start flag Timer A6 one-shot start flag Timer A7 one-shot start flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 TA5TGL TA5TGH 0 0 : Input on TA5IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA6 overflow is selected 1 1 : TA7 overflow is selected Timer A5 event/trigger select bit b7 b6 Note: Set the corresponding port direction register to “0”. WR 1 : Timer start When read, the value is “0”/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.8. Timer A-related registers (5) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR WR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. /LiteDiagLines/LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Count source f 1, f8, f32, fC132 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed (1) Timer mode shows the timer Ai mode register in timer mode. Table 1.13.1. Specifications of timer mode Figure 1.13.9. Timer Ai mode register in timer mode Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 TAiMR(i=5 to 7) 035616 to 035816 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA iOUT pin is a pulse output pin) Gate function select bit0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be fixed to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software)

• TB2 overflow, TB5 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0, A1, A5 and A6 can count a single-phase external signal. Timers A2, A3, A4 and A7 can count a single-phase and a two- phase external signal. Table 1.13.2 lists timer specifications when counting a single-phase external signal. Figure 1.13.10 shows the timer Ai mode register in event counter mode. the timer Ai mode register in event counter mode. Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Figure 1.13.10. Timer Ai mode register in event counter mode Timer Ai mode register Note 1: In event counter mode, the count source is selected by the event / trigger select bit . Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAi OUT pin, the downcount is activated. When “H”, the upcount is activated. Set the corresponding port direction register to “0”. Symbol Address When reset TAiMR(i = 0, 1) 039616, 039716 0016 TAiMR(i = 5, 6) 035616, 035716 0016 WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 1 : Event counter mode (Note 1) b1 b0 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) Count polarity select bit (Note 3) MR2 MR1 MR3 0 (Must always be fixed to “0” in event counter mode) TCK0 Count operation type select bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge Up/down switching cause select bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 Invalid in event counter mode Can be “0” or “1” TMOD1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Count source • Two-phase pulse signals input to TAi IN or TAiOUT pin Count operation • Up count or down count can be selected by two-phase pulse signal

• When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TAiIN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A2, A3, A4 or A7 register Write to timer • When counting stopped When a value is written to timer A2, A3, A4 or A7 register, it is written to both reload register and counter
• When counting in progress When a value is written to timer A2, A3, A4 or A7 register, it is written to only reload register. (Transferred to counter at next reload time.) Select function • Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H”
• Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. Note: This does not apply when the free-run function is selected. Table 1.13.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, A4 and A7) TAiOUT Up count Up count Up count Down count Down count Down count TAiIN (i=2, 3, 7) TAiOUT TAiIN (i=3, 4) Count up all edges Count up all edges Count down all edges Count down all edges

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.13.11. Timer Ai mode register in event counter mode Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0”. Note 4: This bit is valid for the timer A3 mode register. For timer A2, A4 and A7 mode registers, this bit can be “0 ”or “1”. Note 5: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (addresses 0384 16 and 034416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038316 and 034316) to “00”. Timer Ai mode register (When not using two-phase pulse signal processing) Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 TA7MR 0358 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) Count polarity select bit (Note 2) MR2 MR1 MR3 0 : (Must always be “0” in event counter mode) TCK1 TCK0 010 0 : Counts external signal's falling edges 1 : Counts external signal's rising edges Up/down switching cause select bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) Bit symbol Bit name Function WR Count operation type select bit Two-phase pulse signal processing operation select bit (Note 4)(Note 5) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation Note 1 : This bit is valid for timer A3 mode register. For timer A2, A4, and A7 mode registers, this bit can be “0” or “1”. Note 2 : When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (addresses 0384 16 and 034416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038316 and 034316) to “00”. Timer Ai mode register (When using two-phase pulse signal processing) Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 TA7MR 0358 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) MR2 MR1 MR3 0 (Must always be “0” when using two-phase pulse signal processing) TCK1 TCK0 010 1 (Must always be “1” when using two-phase pulse signal processing) Bit symbol Bit name Function WR Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation 001 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Count source f 1, f8, f32, fC132 Count operation • The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Table 1.13.4. Timer specifications in one-shot timer mode Figure 1.13.12. Timer Ai mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.13.12 shows the timer Ai mode register in one-shot timer mode. Bit name Timer Ai mode register Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 TAiMR(i = 5 to 7) 035616 to 035816 0016 Function Bit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAi OUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select register Trigger select bit External trigger select bit (Note 2) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216, 034316, 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0” . Note 3: Set the corresponding port direction register to “0” (input mode). WR /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure example of how a 16-bit pulse width modulator operates. Figure 1.13.15 shows the example of how an 8- bit pulse width modulator operates. Figure 1.13.13. Timer Ai mode register in pulse width modulation mode Table 1.13.5. Timer specifications in pulse width modulation mode Item Specification Count source f 1, f8, f32, fC132 Count operation • T he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting 16-bit PWM • High level width n / fi n : Set value
• Cycle time (216-1) / fi fixed 8-bit PWM • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (2 8-1) (m+1) / fim : values set to timer Ai register’s low-order address Count start condition • External trigger is input
• The timer overflows
• The count start flag is set (= 1) Count stop condition • The count start flag is reset (= 0) Interrupt request generation timingPWM pulse goes “L” TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Bit name Timer Ai mode register Symbol Address When reset TAiMR(i=0 to 4) 039616 to 039A16 0016 TAiMR(i=5 to 7) 035616 to 035816 0016 FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132 b7 b6 TCK1 TCK0 Count source select bit WR 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit External trigger select bit (Note 1) 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select register Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216, 034316, 038216 and 038316 ). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0” (input mode). /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Symbol Address When reset TABSR 0 0380 16 0016 Count start flag 0 Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Function /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminate TB2 0395 16, 039416 Indeterminate TB3 0351 16, 035016 Indeterminate TB4 0353 16, 035216 Indeterminate TB5 0355 16, 035416 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) WR

• Pulse period / pulse width measurement mode Measures a pulse period or width
• Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
• Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Symbol Address When reset TABSR1 0340 16 000XX000 2 Count start flag 1 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Timer B5 count start flag Timer B4 count start flag Timer B3 count start flag Timer A7 count start flag Timer A6 count start flag Timer A5 count start flag0 : Stops counting 1 : Starts counting TB5S TB4S TB3S TA7S TA6S TA5S /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Figure 1.13.18. Timer B-related registers (2)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Count source f 1, f8, f32, fC132 Count operation • Counts down

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode shows the timer Bi mode register in timer mode. Table 1.13.6. Timer specifications in timer mode Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Timer Bi mode register Symbol Address When reset TBiMR(i=0 to 2) 039B 16 to 039D16 00XX0000 2 TBiMR(i=3 to 5) 035B16 to 035D16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1” MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132 TCK1 TCK0 Count source select bit Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. 0 (Fixed to “0” in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 1) (Note 2) b7 b6 /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.13.19. Timer Bi mode register in timer mode

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Real time Port When real time port output is selected, the real time port data written to the port Pm register is latched into the real time port latch each time the corresponding timer Ai underflows, with the data output from each corresponding port. The real time port data is written to the corresponding port Pm register. When the real time port mode select bit changes state from “0” to “1”, the value of the real time port latch becomes “0”, which is output from the corresponding pin. It is when timer Ai underflows first that the real time port data is output. If the real time port data is modified when the real time port function is enabled, the modified value is output when timer Ai underflows next time. The port functions as an ordinary port when the real time port function is disabled. Make sure timer Ai for real time port output is set for timer mode, and is set to have “no gate function” using the gate function select bit. Also, before setting the real time port mode select bit to “1”, temporarily turn off the timer Ai used and write its set value to the timer Ai register. Figure 1.14.1 shows the block diagram for real time port output. Figure 1.14.2 shows the real time control register. Figure 1.14.1. Block diagram for real time port output

• Timer mode TAiIN Timer Ai f1 f8 f32 fC132 Timer Ai interrupt Noise filter Timer Bj overflow Port latch T D Port latch T D Data bus Data bus Q Q Pm7 Pm0 Timer Ai+1 overflow Timer Ak overflow j=2, k=4, 0, m=0, 1 when i=0, 1 j=5, k=7, 5, m=2, 12 when i=5, 6 Pm4 to Pm7 real time port mode select bit Port latch T DData bus Q Pm3 Pm 0 to Pm3 real time port mode select bit Port latch T DData bus Q Pm4 Timer Ai mode register's set value used in real time port 00 00 b0b7 b6 b5 b4 b3 b2 b1 Timer Ai mode register (Addresses 035616, 035716, 039616 and 039716) Real time port latch Pm 4 to Pm7 real time port mode select bit Pm 0 to Pm3 real time port mode select bit

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Real time Port Figure 1.14.3. Timing in real time port output operation Figure 1.14.2. Real time port control register Counter content (hex) Time Start count Underflow Underflow Count start flag “1” “0” Timer Ai interrupt request bit (i=0, 1, 5, 6) “1” “0” Real time port output Writing to port Pm register (m=0, 1, 2, 12) Value to port Pm (example) 5516 AA 16

5516 AA 16

Note : After a reset, the value of the real time port latch is “00”. The value of the real time port latch changes irrespective of the real time port mode select bit as the value of the port Pm register is updated by an underflow of the corresponding timer Ai. Real time port control register (Note) Symbol Address When reset RTP 03FF 16 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 RTP2 P1 0 to P13 real time port mode select bit RTP3 P1 4 to P17 real time port mode select bit RTP4 P2 0 to P23 real time port mode select bit RTP5 P2 4 to P27 real time port mode select bit The corresponding ports of output is controlled 0 : Ordinary port output 1 : Real time port output RTP1 P0 4 to P07 real time port mode select bit RTP0 P0 0 to P03 real time port mode select bit RTP6 P12 0 to P123 real time port mode select bit RTP7 P12 4 and P125 real time port mode select bit Note : The corresponding port direction register is invalidated.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Serial I/O is configured as three channels: UART0, UART1, UART2. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A0 16, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. show the registers related to UARTi. Note: SIM : Subscriber Identity Module Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. UART0 UART1 UART2Function CLK polarity selection Continuous receive mode selection LSB first / MSB first selection ImpossibleTransfer clock output from multiple pins selection Impossible ImpossibleSerial data logic switch Impossible Sleep mode selection Impossible ImpossibleTxD, RxD I/O polarity switch Impossible Possible CMOS outputTxD, RxD port output format CMOS output N-channel open-drain output ImpossibleParity error signal output Impossible ImpossibleBus collision detection Impossible Possible Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 3) Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 1) Possible (Note 3) Possible (Note 1) Possible (Note 2) Possible (Note 1) Possible (Note 4) Possible (Note 4) Table 1.15.1. Comparison of functions of UART0 through UART2

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.1. Block diagram of UARTi (i = 0 to 2) n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2) RxD 2 Reception control circuit Transmission control circuit 1 / (n2+1) Bit rate generator (address 037916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 2 CTS 2 / RTS2 f32 Vcc RTS 2 CTS 2 TxD 2 (UART2) RxD polarity reversing circuit TxD polarity reversing circuit RxD 0 1 / (n0+1) Bit rate generator (address 03A116) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 0 Clock source selection CTS 0 / RTS0 f32 Reception control circuit Transmission control circuit Internal External Vcc RTS 0 CTS 0 TxD 0 Transmit/ receive unit RxD 1 1 / (n1+1) Bit rate generator (address 03A916) Clock synchronous type (when internal clock is selected) UART reception Clock synchronous type UART transmission Clock synchronous type Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Receive clock Transmit clock CLK 1 Clock source selection f32 Reception control circuit Transmission control circuit Internal External RTS 1 CTS 1 TxD 1 (UART1) (UART0) CLK polarity reversing circuit CLK polarity reversing circuit CTS/RTS disabled Clock output pin select switch CTS 1 / RTS1/ CLKS 1 CTS/RTS disabled CTS/RTS selected CTS/RTS disabled VCC CTS/RTS disabled CTS/RTS selected CTS/RTS disabled CTS/RTS disabled CTS/RTS selected CLK polarity reversing circuit Internal External Clock source selection Transmit/ receive unit Transmit/ receive unit

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 Data bus low-order bits MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Data bus high-order bits

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type Data bus low-order bits TxD2 UART2 transmit registerPAR disabled PAR enabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 UART2 transmit buffer register UART (8 bits) UART (9 bits) Clock synchronous type UART2 receive buffer register UART2 receive register 2SP 1SP UART (7 bits) UART (8 bits) UART(7 bits) UART (9 bits) Clock synchronous type Clock synchronous type RxD2 UART (8 bits) UART (9 bits) Address 037E Address 037F16 Address 037A16 Address 037B16 Data bus high-order bits D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Reverse No reverse Error signal output circuit RxD data reverse circuit Error signal output enable Error signal output disable Reverse No reverse Logic reverse circuit + MSB/LSB conversion circuit Logic reverse circuit + MSB/LSB conversion circuit PAR enabled PAR disabled UART Clock synchronous type TxD data reverse circuit SP: Stop bit PAR: Parity bit Figure 1.15.3. Block diagram of UART2 transmit/receive unit

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.4. Serial I/O-related registers (1) UARTi bit rate generator b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate U2BRG 0379 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set WR /LiteDiagLines/LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate U2TB 037B 16, 037A16 Indeterminate WR /LiteDiagLines/LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate U2RB 037F 16, 037E16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value of this bit is “0”. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note 1) Framing error flag (Note 1) Parity error flag (Note 1) Error sum flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Receive data WR Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines ABT Arbitration lost detecting flag (Note 2) Invalid0 : Not detected 1 : Detected /LiteDiagLines/LiteDiagLines/LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WR Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit SMD2 Internal/external clock select bit STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock 1 : External clock (Note) Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock 1 : External clock (Note) Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) UART2 transmit/receive mode register Symbol Address When reset U2MR 0378 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WR Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit SMD2 Internal/external clock select bit STPS PRY PRYE IOPOL Parity enable bit 0 : Internal clock 1 : External clock (Note 2) Stop bit length select bit Odd/even parity select bit TxD, RxD I/O polarity reverse bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid 0 : No reverse 1 : Reverse Usually set to “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. Must always be fixed to “0” Note : Set the corresponding port direction register to “0”. Figure 1.15.5. Serial I/O-related registers (2)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) WR Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit CTS/RTS function select bit CTS/RTS disable bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P6 0 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines UART2 transmit/receive control register 0 Symbol Address When reset U2C0 037C 16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) WR Function (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 CRS CRD CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit CTS/RTS function select bit CTS/RTS disable bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P7 3 functions programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit (Note 3) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. 0 : LSB first 1 : MSB first /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.15.6. Serial I/O-related registers (3)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.7. Serial I/O-related registers (4) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.UART2 transmit/receive control register 1 Symbol Address When reset U2C1 037D 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register U2IRS UART2 transmit interrupt cause select bit 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) U2RRM UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Invalid Data logic select bit 0 : No reverse 1 : Reverse 0 : No reverse 1 : Reverse U2LCH U2ERE Error signal output enable bit Must be fixed to “0” 0 : Output disabled 1 : Output enabled /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Note: When using multiple pins to output the transfer clock, the following requirements must be met:

• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM Invalid Invalid Invalid CLK/CLKS select bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines UART2 special mode register Symbol Address When reset U2SMR 0377 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) ABSCS ACSE SSS IIC mode selection bit Bus busy flag 0 : STOP condition detected 1 : START condition detected SCLL sync output enable bit Bus collision detect sampling clock select bit Arbitration lost detecting flag control bit 0 : Normal mode 1 : IIC mode 0 : Update per bit 1 : Update per byte IICM ABC BBS LSYN 0 : Ordinary 1 : Falling edge of RxD2 0 : Disabled 1 : Enabled Transmit start condition select bit Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 Auto clear function select bit of transmit enable bit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines 0 : No auto clear function 1 : Auto clear at occurrence of bus collision Must always be “0” Must always be “0” Must always be “0” Must always be “0” Must always be “0” Must always be “0” Note: Nothing but "0" may be written. (Note) /LiteDiagLines Reserved bit Always set to “0” Reserved bit Always set to “0” Figure 1.15.8. Serial I/O-related registers (5)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.15.2 UARTi transmit/receive mode register. Table 1.15.2. Specifications of clock synchronous serial I/O mode (1) Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32

• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin Transmission/reception control
• CTS function/RTS function/CTS , RTS function chosen to be invalid Transmission start condition• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _ When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L”
• When transmitting _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Interrupt request generation timing Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”.

Clock synchronous serial I/O mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Item Specification Select function • CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected

• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set
• Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. Table 1.15.3. Specifications of clock synchronous serial I/O mode (2)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Figure 1.15.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit/receive mode registers Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock (Note) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Must always be “0” in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode Symbol Address When reset U2MR 0378 16 0016 CKDIR UART2 transmit/receive mode register Internal/external clock select bit STPS PRY PRYE IOPOL 0 : Internal clock 1 : External clock (Note2) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 010 SMD0 SMD1 SMD2 Serial I/O mode select bit0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note1) 0 : No reverse 1 : Reverse Note1 : Usually set to “0”. Note2 : Set the corresponding port direction register to “0”. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note : Set the corresponding port direction register to “0”.

Clock synchronous serial I/O mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.15.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.15.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected) Pin name Function Method of selection TxDi (P63, P67, P70) Serial data output Serial data input Transfer clock output Transfer clock input Programmable I/O port (Outputs dummy data when performing reception only) RxDi (P62, P66, P71) CLKi (P6 1, P65, P72) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTS input RTS output CTSi/RTSi (P6 0, P64, P73)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode 100 Figure 1.15.10. Typical transmit/receive timings in clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected) 1 / fEXT Dummy data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi “H” “L” “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UARTi transmit buffer register to UARTi transmit register Read out from UARTi receive buffer register The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”. fEXT : frequency of external clock Transferred from UARTi receive register to UARTi receive buffer register Receive interrupt request bit (IR)“0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Meet the following conditions are met when the CLK input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of receive timing (when external clock is selected) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Tc TCLK Stopped pulsing because transfer enable bit = “0” Data is set in UARTi transmit buffer register Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) “H” “L” “0” “1” “0” “1” “0” “1” CTSi The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR) “0” “1” Stopped pulsing because CTS = “H” Transferred from UARTi transmit buffer register to UARTi transmit register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software

Clock asynchronous serial I/O (UART) mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 103 Item Specification Transfer data format • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected Transfer clock • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT /16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) Transmission/reception control
• CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A5 16, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” - When CTS function selected, CTS input level = “L” Reception start condition • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
• Framing error This error occurs when the number of stop bits set is not detected
• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer the UARTi transmit/receive mode register. Table 1.15.5. Specifications of UART Mode (1) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode 104 Table 1.15.6. Specifications of UART Mode (2) Item Specification Select function • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave micro- computers

• Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. XD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed.

Clock asynchronous serial I/O (UART) mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 105 Figure 1.15.15. UARTi transmit/receive mode register in UART mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit / receive mode registers Internal / external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock (Note) Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bit b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit Symbol Address When reset U2MR 0378 16 0016 CKDIR UART2 transmit / receive mode register Internal / external clock select bit STPS PRY PRYE IOPOL Must always be fixed to “0” Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bit b2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note : Usually set to “0”. Note : Set the corresponding port direction register to “0”.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode 106 Table 1.15.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N- channel open-drain is selected, this pin is in floating state.) Table 1.15.7. Input/output pin functions in UART mode Pin name Function Method of selection TxDi (P63, P67, P70) Serial data output Serial data input Programmable I/O port Transfer clock input Programmable I/O port RxDi (P62, P66, P71) CLKi (P6 1, P65, P72) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0” (Do not set external clock for UART2) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTS input RTS output CTSi/RTSi (P6 0, P64, P73)

Clock asynchronous serial I/O (UART) mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 107 Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi CTSi The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”. “1” “0” “1” “L” “H” “0” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt cause select bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR) “0” “1” Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SP ST P SP D 0 D 1ST Stopped pulsing because transmit enable bit = “0”Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Data is set in UARTi transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SPD 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register.“0” SP Cleared to “0” when interrupt request is accepted, or cleared by software
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 1.15.16. Typical transmit timings in UART mode(UART0,UART1)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode 108 Figure 1.15.17. Typical transmit timings in UART mode(UART2) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Start bit Parity bit Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Tc SP Stop bit Data is set in UART2 transmit buffer register Transferred from UART2 transmit buffer register to UARTi transmit register SP Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” Transmit interrupt request bit (IR) “0” “1” Transfer clock TxD 2 The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f 1, f8, f32) n : value set to BRG2 Shown in ( ) are bit symbols. Note Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

Clock asynchronous serial I/O (UART) mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 109

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Figure 1.15.18. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0 16, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. D 0Start bit Sampled “L” Receive data taken in BRGi count source Receive enable bit RxDi Transfer clock Receive complete flag RTSi Stop bit “1” “0” “0” “1” “H” “L” The above timing applies to the following settings :
• Parity is disabled.
• One stop bit.
• RTS function is selected. Receive interrupt request bit “0” “1” Transferred from UARTi receive register to UARTi receive buffer register Reception triggered when transfer clock is generated by falling edge of start bit D 7D 1 Cleared to “0” when interrupt request is accepted, or cleared by software

Clock asynchronous serial I/O (UART) mode Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 111 Item Specification Transfer data format • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)

• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) Transfer clock • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock) Transmission / reception control
• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode select function is not available for UART2
• Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition• To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” R eception start condition• To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit
• When transmitting When data transmission from the UART2 transfer register is completed (bit 4 of address 037D 16 = “1”)
• When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD 2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD 2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O) (3) Clock-asynchronous serial I/O mode (compliant with the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.15.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Interrupt request generation timing Note 1: ‘n’ denotes the value 00 16 to FF16 that is set to the UARTi bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. Table 1.15.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode 112 Figure 1.15.21. Typical transmit/receive timing in UART mode (compliant with the SIM interface) Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Start bit Parity bit The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”. “0” “1” “0” “1” “0” “1” Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Transmit interrupt request bit (IR) “0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Shown in ( ) are bit symbols. Tc Transfer clock SP Stop bit Data is set in UART2 transmit buffer register SP A “L” level returns from TxD2 due to the occurrence of a parity error. The level is detected by the interrupt routine. The level is detected by the interrupt routine. Receive enable bit (RE) Receive complete flag (RI) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Start bit Parity bit RxD 2 The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”. “0” “1” “0” “1” Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Receive interrupt request bit (IR) “0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP Shown in ( ) are bit symbols. Tc Transfer clock SP Stop bit A “L” level returns from TxD2 due to the occurrence of a parity error. TxD 2 Read to receive buffer Read to receive buffer D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST PSignal conductor level (Note 2) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SPSP TxD 2 RxD 2 Signal conductor level (Note 2) Note 1 : The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Note 2 : Equal in waveform because TxD2 and RxD2 are connected. Transferred from UART2 transmit buffer register to UART2 transmit register Cleared to “0” when interrupt request is accepted, or cleared by software Cleared to “0” when interrupt request is accepted, or cleared by software Note 1

UART2 Special Mode Register Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 117 The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (0377 16) is used as the arbitration loss detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception buffer register (037F 16), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet- ing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to “1” goes the P7 1 data register to “0” in synchronization with the SCL terminal level going to “L”.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 118 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK Timer A0 1: Timer A0 overflow 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) CLK TxD Enabling transmission CLK TxD RxD With "1: falling edge of RxD2" selected 0: In normal state TxD/RxD Figure 1.15.27. Some other functions added Some other functions added are explained here. Figure 1.15.27 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD 2 level and TxD2 level do not match, but the nonconfor- mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.

UART2 Special Mode Register 2 Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 119 UART2 Special Mode Register 2 UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.15.28 shows the UART2 special mode register 2. UART2 special mode register 2 Symbol Address When reset U2SMR2 0376 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction STAC SWC2 SDHI I C mode selection bit 2 SCL wait output bit 0 : Disabled 1 : Enabled SDA output stop bit UART2 initialization bit Clock-synchronous bit Refer to Table 1.15.10 0 : Disabled 1 : Enabled IICM2 CSC SWC ASL 0 : Disabled 1 : Enabled SDA output disable bit SCL wait output bit 2 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines 0: Enabled 1: Disabled (high impedance) 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output SHTC Start/stop condition control bit Set this bit to "1" in I2C mode (refer to Table 1.15.11) /LiteDiagLines/LiteDiagLines /LiteDiagLines Figure 1.15.28. UART2 special mode register 2

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 120 Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode selection bit 2. Table 1.15.10 shows the types of control to be changed by I2C mode selection bit 2 when the I2C mode selection bit is set to "1". Table 1.15.11 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I 2C mode. Function IICM2 = 1IICM2 = 0 Factor of interrupt number 15 No acknowledgment detection (NACK)UART2 transmission (the rising edge of the final bit of the clock) Factor of interrupt number 16 Acknowledgment detection (ACK) UART2 reception (the falling edge of the final bit of the clock) DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Acknowledgment detection (ACK) UART2 reception (the falling edge of the final bit of the clock) Timing for transferring data from the UART2 reception shift register to the reception buffer. The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The falling edge of the final bit of the reception clock 3 to 6 cycles < duration for setting-up (Note2) 3 to 6 cycles < duration for holding (Note2) Note 1 : When the start/stop condition count bit is "1" . Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up Duration for holding SCL SDA (Start condition) SDA (Stop condition) Table 1.15.10. Functions changed by I2C mode selection bit 2 Table 1.15.11. Timing characteristics of detecting the start condition and the stop condition(Note1)

UART2 Special Mode Register 2 Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 121 IICM=1 and IICM2=0 IICM=1 and IICM2=0 IICM=0 or IICM2=1 IICM=0 or IICM2=1 To DMA0, DMA1 To DMA0 I/0 Noize Filter P71/RXD 2/SCL Reception register CLK control UART2 Noize Filter UART2 P72/CLK2 D T Q D T Q UART2 UART2 R IICM=1 IICM=0 IICM=0 IICM=1 IICM=1 IICM=0 S R Q R S SWC Falling of 9th pulse SWC2 Start condition detection Stop condition detection Falling edge detection L-synchronous output enabling bit Data register Selector Internal clock External clock Selector I/0 Timer Port reading Bus busy UART2 transmission/ NACK interrupt request UART2 reception/ACK interrupt request DMA1 request NACK ACK IICM=1 IICM=0 * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register. Bus collision detection 9th pulse Bus collision/start, stop condition detection interrupt request I/0 delay Noize Filter UART2 P70/TXD2/SDA D T Q UART2 IICM=1 IICM=0 ALSSDHI Selector Timer Arbitration Transmission register Functions available in I2C mode are shown in Figure 1.15.29 — a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the instant when the arbitration loss detection flag is set to "1". Bit 1 of the UART2 special mode register 2 (address 0376 16) is used as the clock synchronization bit. With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (0376 16) is used as the SCL wait output bit. Setting this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to "0" frees the output fixed to "L". Figure 1.15.29. Functional block diagram for I 2C mode

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 Special Mode Register 2 122 Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (0376 16) is used as the SCL pin wait output bit 2. Setting this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (0376 16) is used as the SDA output disable bit. Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detection flag is turned on.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 123 Table 1.16.1. Maximum number of display pixels at each duty ratio LCD Drive Control Circuit The M30220 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Voltage multiplier
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 48 segment output pins and 4 common output pins can be used. Up to 192 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. When using the LCDRAM output function, all segment output pins that have been selected for segment output by the segment output enable register output the content of the corresponding LCDRAM bit 0 or bit 4 when the LCDRAM output enable bit is set to “1” while the time division select bits = “00” and the LCD output enable bit = “0”. diagram of LCD controller / driver. Set the duty ratio select bits to “00 2” when writing the data to the LCDRAM. Duty ratio Maximum number of display pixel 96 dots or 8 segment LCD 12 digits 144 dots or 8 segment LCD 18 digits 192 dots or 8 segment LCD 24 digits

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 124 Figure 1.16.1. Block diagram of LCD controller/driver Data bus low-order bits Timing controller COM 0 COM 1 COM 2 COM 3VSS VL1 VL2 VL3SEG 3SEG 2SEG 1SEG 0 Address 010016 Address 010116 LCDCK LCDCK count source select bit Bias control bit LCD enable bit Duty ratio selection bits Selector Selector Selector Selector SelectorSelector LCD display RAM Address 011716 P06/SEG 46 P07/SEG 47 Level shift Level shift Level shift Level shift Level shift Level shift Common driver Common driver Common driver Common driver C 1 C 2 Voltage multiplier control bit Level Shift Level Shift Level Shift Level Shift Segment driver Segment driver Segment driver Segment driver Segment driver Segment driver Bias control Data bus high-order bits VCC LCD output enable bit 1/2LCD frame frequency control counter (8) “0” “1” f32 fC1 Reload register (8)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 125 Figure 1.16.2. LCD-related registers LCD frame frequency counter (Note) Symbol Address When reset LCDTIM 0124 16 XX 16 Function WR b7 b0 8 bits timer 0016 to FF16 Values that can be set Segment output enable register Symbol Address When reset SEG 0122 16 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SEGO0 Segment output enable bit 0 0 : I/O ports P110 to P114 1 : Segment output SEG24 to SEG28 SEGO1 Segment output enable bit 1 0 : I/O ports P115, P116 1 : Segment output SEG29, SEG 30 SEGO2 Segment output enable bit 2 0 : I/O ports P117 1 : Segment output SEG31 SEGO3 Segment output enable bit 3 0 : I/O ports P120 to P125 1 : Segment output SEG32 to SEG37 SEGO4 Segment output enable bit 4 0 : I/O ports P126 to P127 1 : Segment output SEG38 to SEG39 SEGO5 Segment output enable bit 5 0 : I/O ports P100 to P107 1 : Segment output SEG16 to SEG23 SEGO6 Segment output enable bit 6 0 : I/O ports P00 to P07 1 : Segment output SEG40 to SEG47 SEGO7 0 : disable 1 : enable LCD output enable bit Note : LCDCK is a clock for a LCD timing controller. LCD mode register Symbol Address When reset LCDM 0120 16 0X0000002 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Not used 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0–COM2) 1 1 : 4 duty (use COM0–COM3) b1 b0 PUMP LCDEN LCDT1 BIAS LCDT0 Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Voltage multiplier control bit 0 : Voltage multiplier disable 1 : Voltage multiplier enableLCDCK count source select bit (Note) 0 : f 1 : fC1 LSRC LRAMOUT LCDRAM output bit 0 : LCD waveform output 1 : LCDRAM data output Duty ratio select bit Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: Set this register when LCD output enable bit is “0” (disable).

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 126 Voltage Multiplier The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and apply voltage by external resistor division.) To activate the voltage multiplier, choose the segment/port and duty rate, select bias control, and set up the LCD frame frequency counter and LCDCK count source using the segment enable register and LCD mode register, then enable the LCD output enable bit (bit 7 at address 0122 16) and set the voltage multiplier control bit (bit 4 at address 012016) to “1” (= voltage multiplier enabled). When voltage is input to the VL1 pin during operating the voltage multiplier, voltage that is twice as large as VL1 occurs at the VL2 pin, and voltage that is three times as large as VL1 occurs at the VL3 pin. The voltage multiplier control bit (bit 4 of the address 012016) controls the voltage multiplier. When using the voltage multiplier, apply a voltage equal to or greater than 1.3 V but not exceeding 2.1 V to the V L1 pin before enabling the voltage multiplier control bit. When not using the voltage multiplier, enable the LCD output enable bit and apply an appropriate voltage to the LCD power supply input pins (V L1 to VL3). When the LCD output enable bit is disabled, the VL3 pin is connected to VCC internally. Table 1.16.2. Bias control and applied voltage to VL1 to VL3 Bias value Voltage value VL3 = VLCD 1/3 bias V L2 = 2/3 VLCD VL1 = 1/3 VLCD 1/2 bias V L3 = VLCD VL2 = VL1 = 1/2 VLCD Note : VLCD is the maximum value of supplied voltage for the LCD panel. Figure 1.16.3. Example of circuit at each bias VL3 VL2 C 2 C 1 VL1 1/3 bias when using the voltage multiplier VL3 VL2 C 2 C 1 VL1 1/3 bias when not using the voltage multiplier Open Open R1=R2=R3 Contrast control VL3 VL2 C 2 C 1 VL1 1/2 bias Open Open R4=R5 Contrast control When selecting LCDRAM data output (not using LCD panel) VL1 VL3 VL2 C 1 C 2 Open Open Bias Control and Applied Voltage to LCD Power Input Pins To the LCD power input pins (VL1 to VL3), apply the voltage shown in Table 1.16.2 according to the bias value. Select a bias value by the bias control bit (bit 2 of the address 012016).

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 127 Common Pin and Duty Ratio Control The common pins (COM0 to COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio select bits (bits 0 and 1 of address 012016). LCD Display RAM Address 010016 to 011716 is the designated RAM for the LCD display. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. Figure 1.16.4 shows the LCD display RAM map. Table 1.16.3. Duty ratio control and common pins used Duty Duty ratio select bit Common pins used ratio Bit 1 Bit 0 2 0 1 COM 0, COM1 (Note 1) 3 1 0 COM 0 to COM2 (Note 2) 4 1 1 COM 0 to COM3 LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation. The LCDCK count source frequency is fC1 (same frequency as XCIN) or f32 (divide-by-32 of XIN frequency). Figure 1.16.4. LCD display RAM map Note 1 : COM2 and COM3 are open. Note 2 : COM3 is open. 010616 010716 010816 010916 010A16 010B16 010C 16 010D 16 010E16 010F16 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 SEG 24 SEG 26 SEG 28 SEG 30 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 25 SEG 27 SEG 29 SEG 31 Bit Address 010016 010116 010216 010316 010416 010516 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 11 76543 210 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10 011016 011116 011216 011316 SEG 33 SEG 35 SEG 37 SEG 39 SEG 32 SEG 34 SEG 36 SEG 38 011416 011516 011616 011716 SEG 41 SEG 43 SEG 45 SEG 47 SEG 40 SEG 42 SEG 44 SEG 46 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 RW

16 X (LCD frame frequency count value + 1)

f(LCDCK)= f(LCDCK) duty ratioFrame frequency= (frequency of count source for LCDCK)

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER LCD Drive Control Circuit 129 Figure 1.16.6. LCD drive waveform (1/3 bias) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 OFFON OFFON OFFON OFFON VL3 VL2 VSS VL1 VL3 VL2 VSS VL1 VL3 VSS VL3 VL2 VSS VL1 VL3 VSS COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 130 Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1)0V to AVCC (VCC ) Operating clock fAD (Note 2)VCC = 5V f AD /divide-by-2 of fAD /divide-by-4 of fAD , fAD =f(XIN) VCC = 3V divide-by-2 of fAD /divide-by-4 of fAD , fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V • Without sample and hold function –3LSB

• With sample and hold function (8-bit resolution) –2LSB
• With sample and hold function (10-bit resolution) –3LSB VCC = 3V • Without sample and hold function (8-bit resolution) –2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN 0 to AN7) A-D conversion start condition• Software trigger A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the AD TRG /P130 input changes from “H” to “L” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles
• With sample and hold function 8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P90 to P97 also function as the analog signal input pins. The direction registers of these pins for A- D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF , reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the fAD frequency to 250kHZ min. With the sample and hold function, set the fAD frequency to 1MHZ min. Table 1.17.1. Performance of A-D converter

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 131 Figure 1.17.1. Block diagram of A-D converter /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines fAD fAD A-D conversion rate selection (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) CKS1=1 CKS0=0 A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) Resistor ladder Successive conversion register P90/AN0 P91/AN1 P92/AN2 P93/AN3 P95/AN5 P96/AN6 P97/AN7 A-D control register 0 (address 03D616) A-D control register 1 (address 03D716) Vref VIN Data bus high-order Data bus low-order V REF P94/AN4 ADGSEL0 = 0 VCUT=0 AV SS VCUT=1 CKS0=1 CKS1=0 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 Decoder Comparator Addresses /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 132 Figure 1.17.2. A-D converter-related registers (1) A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 (Note 2) MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected WR b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Always set to “0”.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 133 Figure 1.17.3. A-D converter-related registers (2) A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 0000XXX0 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Bit symbol Bit name Function R W Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. A-D register i Symbol Address When reset ADi(i=0 to 7) 03C0 16 to 03CF16 Indeterminate Eight low-order bits of A-D conversion result Function R W (b15) b7b7 b0 b0 (b8)

• During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
• During 8-bit mode When read, the content is indeterminate /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SMP Reserved bit Always set to “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 000

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 134 (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- ter in one-shot mode. Table 1.17.2. One-shot mode specifications Figure 1.17.4. A-D conversion register in one-shot mode A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 00: fAD /4 is selected 1: fAD /2 is selected CKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Vref connected WR Invalid in one-shot mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 0 : One-shot mode (Note 2) b4 b3 CH0 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Frequency select bit10 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Always set to “0”. Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 135 (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. repeat mode. A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG triggerTRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit A-D operation mode select bit 1 1 : Vref connected WR Invalid in repeat mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) b2 b1 b0 0 1 : Repeat mode (Note 2) b4 b3 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 0 : Any mode other than repeat sweep mode 1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 Always set to “0”. Figure 1.17.5. A-D conversion register in repeat mode Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Star condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin Table 1.17.3. Repeat mode specifications

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 136 (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D control register in single sweep mode. Table 1.17.4. Single sweep mode specifications Figure 1.17.6. A-D conversion register in single sweep mode A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 0 : Single sweep modeMD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected CKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 0 : Any mode other than repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected WR 1 0 Invalid in single sweep mode Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Always set to “0”. Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected)

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 137 (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D control register in repeat sweep mode 0. Figure 1.17.7. A-D conversion register in repeat sweep mode 0 A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 0MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 0 : Any mode other than repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected WR 1 1 Invalid in repeat sweep mode 0 Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesAlways set to “0”. Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) Table 1.17.5. Repeat sweep mode 0 specifications

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 138 Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure 1.17.8 shows the A-D control register in repeat sweep mode 1. A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 1MD0 MD1 Trigger select bit 0 : Software trigger 1 : ADTRG trigger TRG ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 00 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit 1 : Repeat sweep mode 1A-D operation mode select bit 1 1 : Vref connected WR 1 1 Invalid in repeat sweep mode 1 Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. b4 b3 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 10 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Always set to “0”. Figure 1.17.8. A-D conversion register in repeat sweep mode 1 Table 1.17.6. Repeat sweep mode 1 specifications

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter 139 Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A Converter 140 D-A Converter This is an 8-bit, R-2R type D-A converter. The microcomputer contains three independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 to 2 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = V REF X n/ 256 (n = 0 to 255) VREF : reference voltage circuit. Item Performance Conversion method R-2R method Resolution 8 bits Analog output pin 3 channels Table 1.18.1. Performance of D-A converter Data bus low-order bits /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines P130/DA0 D-A register0 (8) R-2R resistor ladder D-A0 output enable bit (Address 03D816) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines P131/DA1 D-A register1 (8) R-2R resistor ladder D-A1 output enable bit (Address 03DA16) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines P132/DA2 D-A register2 (8) R-2R resistor ladder D-A2 output enable bit (Address 03DE16) Figure 1.18.1. Block diagram of D-A converter

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 143 Figure 1.19.1. Programmable I/O ports (1) P10 to P17, P20 to P27 P00 to P07, P120 to P127 Data bus Direction register Port latch Pull-up selected P30 to P33, P41, P43, P45, P47, P50 to P56, P62, P66, P74 to P76, P81, P83, P85, P87 Data bus Direction register Port latch Pull-up selection P34, P35 Port ON/OFF LCD drive timing Port/segment VL1/VSS VL3/VCC Data bus Direction register Port latch Timer A overflow “1” “1” Segment output D CK Q VL3/VCC VL2/VCC Data bus Direction register Port latch Pull-up selection Timer A overflow Intermittent pull-up control “1” D CK Q D CK Q Interface logic level shift circuit Intermittent pull-up control

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 144 Figure 1.19.2. Programmable I/O ports (2) P40, P42, P44, P46, P60, P61, P64, P65, P72, P73, P80, P82, P84, P86 P57, P63, P67 Data bus Direction register Port latch Pull-up selection Output Data bus Direction register Port latch Pull-up selection Output P70, P71 Data bus Direction register Port latch Output Input respective peripheral functions P77 Data bus NMI interrupt input “1” “1” Input respective peripheral functions “1”

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 145 Figure 1.19.3. Programmable I/O ports (3) P90 to P97 Data bus Direction register Port latch Pull-up selection Analog input P100 to P107, P110 to P117 Port ON/OFF LCD drive timing Port/segment Interface logic level shift circuit Data bus Direction register Port latch “1” Segment output VL1/VSS VL3/VCCVL3/VCC VL2/VCC P130 Data bus Direction register Analog output Pull-up selection Input respective peripheral functions Port latch

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 147 Figure 1.19.6. Direction register Port P3 direction register Symbol Address When reset PD3 03E716 XX000000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD3_0 Port P3 0 direction register PD3_1 Port P3 1 direction register PD3_2 Port P3 2 direction register PD3_3 Port P3 3 direction register PD3_4 Port P3 4 direction register 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. PD3_5 Port P3 5 direction register Port Pi direction register (Note) Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 12 except 3 and 7) Symbol Address When reset PDi ( i = 0 to 12 except 3 and 7)03E216, 03E316, 03E616, 03EA16, 00 16 03EB 16, 03EE16, 03F216, 03F316, 03F616, 03F716, 03FA16 Note : Do not access the Port P12 direction register in words. Port P7 direction register Symbol Address When reset PD7 03EF 16 X00000002 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD7_0 Port P7 0 direction register PD7_1 Port P7 1 direction register PD7_2 Port P7 2 direction register PD7_3 Port P7 3 direction register PD7_4 Port P7 4 direction register 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD7_5 Port P7 5 direction register PD7_6 Port P7 6 direction register Port P13 direction register (Note) Symbol Address When reset PD13 03FB 16 XXXXX000 2 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PD13_0 Port P13 0 direction register PD13_1 Port P13 1 direction register PD13_2 Port P13 2 direction register 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note : Do not access this register in words.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 148 Figure 1.19.7. Port register Port Pi register (Note) Symbol Address When reset Pi ( = 0 to 12 except 3 and 7) 03E016, 03E116, 03E416, 03E816, Indeterminate 03E916, 03EC 16, 03F016, 03F116, 03F416, 03F516, 03F816 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Port P3 register Symbol Address When reset P3 03E5 16 Indeterminate Bit mame FunctionBit symbol WR Port P7 register Symbol Address When reset P7 03ED 16 Indeterminate WR Port P13 register (Note) Symbol Address When reset P13 03F9 16 Indeterminate WR b7 b6 b5 b4 b3 b2 b1 b0 Note : Do not access this Register in words. Note : Do not access the Port P12 register in words. Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input an âtput to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 12 except 3 and 7) Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data P3_0 Port P3 0 register P3_1 Port P3 1 register P3_2 Port P3 2 register P3_3 Port P3 3 register P3_4 Port P3 4 register P3_5 Port P3 5 register P7_0 Port P7 0 register P7_1 Port P7 1 register P7_2 Port P7 2 register P7_3 Port P7 3 register P7_4 Port P7 4 register P7_5 Port P7 5 register P7_6 Port P7 6 register P7_7 Port P7 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P7 0 : “L” level data 1 : “H” level data P13_0 Port P13 0 register P13_1 Port P13 1 register P13_2 Port P13 2 register Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Bit mame FunctionBit symbol Bit mame FunctionBit symbol Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 149 Figure 1.19.8. Pull-up control register Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 000000112 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU04 P2 0 to P23 pull-up PU05 P2 4 to P27 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P37 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Pull-up control register 1 Symbol Address When reset PUR1 03FD 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 to P57 pull-up PU14 P6 0 to P63 pull-up PU15 P6 4 to P67 pull-up PU16 P7 0 to P73 pull-up PU17 P7 4 to P77 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high Pull-up control register 2 Symbol Address When reset PUR2 03FE 16 111100002 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PU20 P8 0 to P83 pull-up PU21 P8 4 to P87 pull-up PU22 P9 0 to P93 pull-up PU23 P9 4 to P97 pull-up PU24 P10 0 to P103 pull-up PU25 P10 4 to P107 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high PU26 P11 0 to P113 pull-up PU25 P10 4 to P107 pull-up PU27 P11 4 to P117 pull-up

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 151 Table 1.19.1. Example connection of unused pins in single-chip mode Figure 1.19.11. Example connection of unused pins Pin name Connection Ports P0 to P13 (excluding P77) XOUT (Note) AV SS , VREF AV CC After setting for output mode, leave these pins open; or after setting for input mode, connect every pin to VSS or VCC via a resistor. Open Connect to VCC Connect to VSS Note: With external clock input to XIN pin. NMI Connect via resistor to VCC (pull-up) C1, C2 VL1 VL2, VL3 Open Connect to VCC Connect to VSS CNV SS Connect to VSS Port P0 to P13 (except for P77) (Input mode)··

• (Input mode) (Output mode)NMI AV CC AV SS VREF Microcomputer VCC VSS Open
• ·· VL3 VL2 VL1 CNV SS

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 152 Timer A (timer mode) Usage Precaution Timer A (event counter mode) (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. (1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (1) Setting the count start flag to “0” while a count is in progress causes as follows:

• The counter stops counting and a content of reload register is reloaded.
• The TAi OUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. Timer A (one-shot timer mode) (1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. Timer A (pulse width modulation mode) Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 153 Stop Mode and Wait Mode A-D Converter (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer B (pulse period/pulse width measurement mode) (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 ms or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A- D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”. (1) Make sure timer Ai for real time port output is set for timer mode, and is set to have “no gate function” using the gate function select bit. (2) Before setting the real time port mode select bit to “1”, temporarily turn off the timer Ai used and write its set value to the timer Ai register. Real time port Interrupts (1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited.

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 154 Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below in- structions to change the register. Instructions : AND, OR, BCLR, BSET (3) The NMI interrupt
• The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused.
• Do not get either into stop mode with the NMI pin set to “L”. (4) External interrupt
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:

Electrical characteristics

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 155 Table 1.21.1. Absolute maximum ratings Operating ambient temperature Parameter Unit Input voltage RESET, Analog supply voltage Supply voltage Output voltage VO – 0.3 to Vcc+0.3 – 0.3 to Vcc+0.3 Pd Power dissipation Storage temperature – 0.3 to 6.5 Rated value – 0.3 to 6.5 V V V Condition VI AVcc Vcc Tstg Topr Symbol mW V – 40 to 150 300 – 20 to 85 P30 to P35, P40 to P47, P50 to P57, P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P57, P60 to P67, P10 to P17, P20 to P27, P30 to P35, Vcc=AVcc Vcc=AVcc P60 to P67, P72 to P77, P80 to P87, VREF , XIN P90 to P97, P100 to P107, VL1 P130 to P132 – 0.3 to VL2 VL2 VL1 to VL3 VL3 VL2 to 6.5 P70, P71, C1, C2 – 0.3 to 6.5 P72 to P76, P80 to P87, P90 to P97, P130 to P132, XOUT P00 to P07, P100 to P107, P110 to P117, P120 to P127, – 0.3 to VccWhen output port When segment output – 0.3 to VL3 P70, P71 – 0.3 to 6.5 (Mask ROM version CNVss) (flash memory version CNVss) P110 to P117, P120 to P127, Ta = 25°C

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 156 Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P70 to P76 and P122 to P127 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P72 to P76 and P122 to P127 must be 80mA max. The total IOL (peak) for ports P8, P9, P10, P11, P120, P121 and P130 to P132 must be 80mA max. The total IOH (peak) for ports P8, P9, P10, P11, P12 0,P121 and P130 to P132 must be 80mA max. Note 3: Relationship between main clock oscillation frequency and supply voltage. unless otherwise specified) Typ. Max. UnitParameter Vcc Supply voltage Symbol Min Standard f (XcIN) Subclock oscillation frequency kHz5032.768 V Analog supply voltage VccAVcc V 0Analog supply voltage Analog supply voltageVss AVss 0.8Vcc V V V Vcc 0.2Vcc0 LOW input voltage HIGH input voltage –0.5 LOW peak output current 10.0 f (XIN) Main clock input oscillation frequency MHz IOL (peak) 10VCC =4.0V to 5.5V With wait

5 X VCC

IOH (avg) HIGH average output current IOH (peak) HIGH peak output current IOL (avg) LOW average output current mA mA mA 2.5 0 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P00 to P07, P100 to P107, P110 to P117, P120 to P127 5.0 0VCC =2.7V to 4.0V –10.000 MHz10VCC =4.0V to 5.5V

2.31 X VCC MHz

0VCC =2.7V to 4.0V +0.760 No wait 2.7 5.55.0 P70, P71 0.8Vcc 6.5 P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P10 to P17, P20 to P27, P30 to P35, P40 to P47, –10.0 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27, P30 to P35, P40 to P47, –0.1 mA –5.0 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27,P30 to P35, P40 to P47, 5.0 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27, P30 to P35, P40 to P47, (Note 1) (Note 1) (Note 3) P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, 130 to P132, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, 130 to P132, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P130 to P132 P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P130 to P132 XIN, RESET, CNVSS XIN, RESET, CNVSS /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 5.54.02.7 0.0 3.5 10.0 Main clock input oscillation frequency (No wait) Supply voltage [V] (BCLK: no division) Operating maximum frequency [MH 5 X Vcc–10.000MHz /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 5.54.02.7 0.0 10.0 Main clock input oscillation frequency (With wait) Supply voltage [V] (BCLK: no division) 7.0 2.31 X VCC +0.760MHz Operating maximum frequency [MH

Electrical characteristics (Vcc = 5V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 157 Table 1.21.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MH Z unless otherwise specified) VCC = 5V S y m b o l VO H VO H H I G H o u t p u t v o l t a g e H I G H o u t p u t v o l t a g e S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n V 4 . 7 M i nM a x . 3 . 0 P a r a m e t e r IO H = – 0 . 1 m A IO H = – 5 m A P 00 t o P 07, P 1 00 t o P 1 07, P 1 10 t o P 1 17, P 1 20 t o P 1 27 P 10 t o P 17, P 20 t o P 27, P 30 t o P 35, P 40 t o P 47, P 50 t o P 57, P 60 t o P 67, V VO H XO U TH I G H o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V3 . 0 3 . 0 IO H = – 1 m A IO H = – 0 . 5 m A VO L L O W o u t p u t v o l t a g e V2 . 0IO L= 5 m A VO L XO U TL O W o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V2 . 0 2 . 0 IO H = 1 m A IO H = 0 . 5 m A H y s t e r e s i s H y s t e r e s i s H I G H i n p u t c u r r e n t II H VT -VT VT -VT 0 . 20 . 8V 0 . 2 1 . 8 V 5 . 0 m A m A R E S E T T A 0I N t o T A 7I N , T B 0I N t o T B 5I N , VI= 5 V – 5 . 0 L O W i n p u t c u r r e n t II L VR A M R A M r e t e n t i o n v o l t a g e W h e n c l o c k i s s t o p p e d 2 . 0 V VI= 0 V VO L XC O U TL O W o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d VO H XC O U TH I G H o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V 1 . 6 W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d 3 . 0 k W1 6 7 . 0 P u l l - u p r e s i s t a n c e R P U L L U P VI= 0 V 3 0 . 0 5 0 . 0 R f X C I N F e e d b a c k r e s i s t a n c e XC I N 6 . 0M W R f X I N F e e d b a c k r e s i s t a n c e XI N 1 . 0M W P 72 t o P 76, P 80 t o P 87, P 90 t o P 97, P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 35, P 40 t o P 47, P 50 t o P 57, P 1 30 t o P 1 32 P 60 t o P 67, P 70 t o P 76, P 80 t o P 87, P 90 t o P 97, P 1 00 t o P 1 07, P 1 10 t o P 1 17, P 1 20 t o P 1 27, P 1 30 t o P 1 32 IO H = – 2 0 0 m A IO L= 2 0 0 m A 0 . 4 5 3 . 0 I N T0 t o I N T5, A D T R G , C T S0, C T S1, C L K0, C L K1, N M I , P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, P 60 t o P 67, P 70 t o P 77, P 80 t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P 32, XI N , R E S E T C N VS S P 60 t o P 67, P 72 t o P 76, P 80 t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, K I0 t o K I1 ( N o t e ) , K I1 6 t o K I1 N o t e : H a s n o e f f e c t d u r i n g i n t e r m i t t e n t p u l l u p o p e r a t i o n . T A 2O U T t o T A 4O U T, T A 7O U P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, P 60 t o P 67, P 70 t o P 77, P 80 t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P 32, XI N , R E S E T C N VS S

Electrical characteristics (Vcc = 5V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 158 Table 1.21.5. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) VCC = 5V S y m b o l S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n M i n .M a x .P a r a m e t e r I c c P o w e r s u p p l y c u r r e n t S q u a r e w a v e , n o d i v i s i o n W h e n c l o c k i s s t o p p e d T a = 2 5 º C 1 . 0 m A m A T a = 8 5 º C 2 0 . 0 W h e n c l o c k i s s t o p p e d 1 9 . 03 8 . 0f ( XI N ) = 1 0 M H z f ( XC I N ) = 3 2 k H z W h e n a W A I T i n s t r u c t i o n i s e x e c u t e d 4 . 0 m A I / o p i n i s n o l o a d a p p l i e d f ( XC I N ) = 3 2 k H z S q u a r e w a v e 9 0 . 0 m A VL 1 S u p p l y v o l t a g e ( V L 1 ) W h e n v o l t a g e m u l t i p l i e r u s e d V1 . 32 . 11 . 7 IL 1 P o w e r s u p p l y c u r r e n t ( V L 1 ) V L 1 = 1 . 7 VT B D m A3 . 0 f ( XC I N ) = 3 2 k H z S q u a r e w a v e M a s k R O M v e r s i o n F l a s h m e m o r y v e r s i o n 1 6 0 . 0 m A S t a n d a r d M i n y p a x R e s o l u t i o n A b s o l u t e a c c u r a c y B i t s L S B VR E F = VC C ± 3 1 0 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t VR E F = VC C = 5 V R L A D D E R tC O N V L a d d e r r e s i s t a n c e C o n v e r s i o n t i m b i t R e f e r e n c e v o l t a g e A n a l o g i n p u t v o l t a g e k W m s V VI A VR E F 1 0 VC C VR E F 4 0 3 . 3 C o n v e r s i o n t i m b i t ) m s2 . 8tC O N V tS A M P S a m p l i n g t i m e 0 . 3 m s VR E F = VC C S a m p l e & h o l d f u n c t i o n n o t a v a i l a b l e S a m p l e & h o l d f u n c t i o n a v a i l a b l e ( 1 0 b i t ) VR E F = VC C = 5 V L S B± 3 S a m p l e & h o l d f u n c t i o n a v a i l a b l e ( 8 b i t ) VR E F = VC C = 5 V ± 2 L S B M i n .T y p .M a x . ts u R O R e s o l u t i o n A b s o l u t e a c c u r a c y S e t u p t i m e O u t p u t r e s i s t a n c e R e f e r e n c e p o w e r s u p p l y i n p u t c u r r e n t B i t s k W m AIV R E F 1 . 0 1 . 5 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t 2 01 04 m s o t S t a n d a r d Table 1.21.4. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MH Z unless otherwise specified) Table 1.21.6. D-A conversion characteristics (referenced to VCC = AVCC =VREF =5V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified) Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.

Electrical characteristics (Vcc = 5V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 159 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.7. External clock input Table 1.21.9. Timer A input (gating input in timer mode) Table 1.21.10. Timer A input (external trigger input in one-shot timer mode) Table 1.21.11. Timer A input (external trigger input in pulse width modulation mode) Table 1.21.12. Timer A input (up/down input in event counter mode) VCC = 5V Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 100 Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit TAiIN input HIGH pulse widthtw(TAH) ParameterSymbol tc(TA) TAiIN input cycle time 100 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 400 200 200 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 200 100 100 Standard Max.Min. ns ns Unit tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width 100 100 Standard Max.Min. ns ns ns Unit ns ns Symbol Parameter TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 2000 1000 1000 400 400 Table 1.21.8. Timer A input (counter input in event counter mode)

Electrical characteristics (Vcc = 5V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 160 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.13. Timer B input (counter input in event counter mode) Table 1.21.14. Timer B input (pulse period measurement mode) Table 1.21.15. Timer B input (pulse width measurement mode) Table 1.21.16. A-D trigger input Table 1.21.17. Serial I/O Table 1.21.18. External interrupt INTi inputs VCC = 5V Standard Max.Min. TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) ParameterSymbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tc(AD) tw(ADL) Symbol Parameter Unit AD TRG input cycle time (trigger able minimum) AD TRG input LOW pulse width 100 200 400 200 200 400 200 200 1000 125 ns ns ns ns ns ns ns Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max.Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) ParameterSymbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 250 250 200 100 100

Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.21.1. Port P0 to P13 measurement circuit P10 30pF P11 P12 P13

Timing (VCC = 5V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 162 tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN)TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input VCC = 5V

Electrical characteristics (Vcc = 3V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 163 VCC = 3V Table 1.21.19. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait) S y m b o l VO H VO H H I G H o u t p u t v o l t a g e H I G H o u t p u t v o l t a g e S t a n d a r d T y p . U n i tM e a s u r i n g c o n d i t i o n V M i nM a x 2 . 0 P a r a m e t e r IO H = – 2 0 m A IO H = – 1 m A P 00 t o P 07, P 1 00 t o P 1 07, P 1 10 t o P 1 17, P 1 20 t o P 1 27 P 10 t o P 17, P 20 t o P 27, P 30 t o P 35, P 40 t o P 47, P 50 t o P 57, P 60 t o P 67, V VO H XO U TH I G H o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V 2 . 5 2 . 5 IO H = – 0 . 1 m A IO H = – 5 0 m A VO L L O W o u t p u t v o l t a g e V0 . 5IO L= 1 m A VO L XO U TL O W o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V 0 . 5 0 . 5 IO H = 0 . 1 m A IO H = 5 0 m A H y s t e r e s i s H y s t e r e s i s H I G H i n p u t c u r r e n t II H VT -VT VT -VT 0 . 2 0 . 8 V 0 . 2 1 . 8 V 4 . 0 m A m A R E S E T T A 0I N t o T A 7I N , T B 0I N t o T B 5I N , VI= 3 V – 4 . 0 L O W i n p u t c u r r e n t II L VR A M R A M r e t e n t i o n v o l t a g e W h e n c l o c k i s s t o p p e d2 . 0V VI= 0 V VO L XC O U TL O W o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d VO H XC O U TH I G H o u t p u t v o l t a g e H I G H P O W E R L O W P O W E R V 1 . 6 W i t h n o l o a d a p p l i e d W i t h n o l o a d a p p l i e d 3 . 0 k WT B D P u l l - u p r e s i s t a n c e R P U L L U P VI= 0 V T B D 1 2 0 . 0 R f X C I N F e e d b a c k r e s i s t a n c e XC I N 1 0 . 0 M W R f X I N F e e d b a c k r e s i s t a n c e XI N 3 . 0 M W P 72 t o P 76, P 80 t o P 87, P 90 t o P 97, P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P 30 t o P 35, P 40 t o P 47, P 50 t o P 57, P 1 30 t o P 1 32 P 60 t o P 67, P 70 t o P 76, P 80 t o P 87, P 90 t o P 97, P 1 00 t o P 1 07, P 1 10 t o P 1 17, P 1 20 t o P 1 27, P 1 30 t o P 1 32 2 . 5 I N T0 t o I N T5, A D T R G , C T S0, C T S1, C L K0, C L K1, N M I , P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, P 60 t o P 67, P 70 t o P 77, P 80 t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P 32, XI N , R E S E T C N VS S P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, P 60 t o P 67, P 70 t o P 77, P 80 t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P 32, XI N , R E S E T C N VS S P 00 t o P 07, P 10 t o P 17, P 20 t o P 27, P t o P 35, P t o P 47, P t o P 57, P t o P 67, P t o P 76, P t o P 87, P t o P 97, P t o P 07, P t o P 17, P t o P 27, P t o P T A 2O U T t o T A 4O U T, T A 7O U K t o K N o t e K t o K N o t e : H a s n o e f f e c t d u r i n g i n t e r m i t t e n t p u l l u p o p e r a t i o n .

Electrical characteristics (Vcc = 3V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 164 VCC = 3V Table 1.21.22. D-A conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V, at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified) Note : This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent. Table 1.21.21. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait unless otherwise specified) Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Icc Power supply current Square wave, no division When clock is stopped Ta=25 ºC 1.0 µA mA Ta=85 ºC 20.0 When clock is stopped 6.0 15.0f(XIN)=7MHz f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity High (Note) 2.8 µA I/o pin is no load applied f(XCIN)=32kHz Square wave 40.0 µA VL1 Supply voltage (VL1) When voltage multiplier used V1.3 2.11.7 IL1 Power supply current (VL1) VL1=1.7V TBD µA3.0 f(XCIN)=32kHz Square wave Mask ROM version Flash memory version 110.0 µA f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity Low (Note) 0.9 µA Note: With one timer operated using fC32 . S t a n d a r d R e s o l u t i o n A b s o l u t e a c c u r a c y B i t s L S B VR E F = VC C ± 2 1 0 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o n VR E F = VC C = 3 V , øA D = fA D / 2 R L A D D E R L a d d e r r e s i s t a n c e R e f e r e n c e v o l t a g e A n a l o g i n p u t v o l t a g e k W V VI A VR E F 2 . 7 1 0 VC C VR E F 4 0 C o n v e r s i o n t i m e( b i t ) m s1 4 . 0tC O N V VR E F = VC C S a m p l e h o l d f u n c t i o n n o t a v a i l a b l e( 8 b i t ) M i n .T y p .M a x . U n i t M i n .T y p .M a x . ts u R O R e s o l u t i o n A b s o l u t e a c c u r a c y S e t u p t i m e O u t p u t r e s i s t a n c e R e f e r e n c e p o w e r s u p p l y i n p u t c u r r e n t B i t s k W m AIV R E F 1 . 0 1 . 0 S y m b o lP a r a m e t e rM e a s u r i n g c o n d i t i o nU n i t 2 01 04 m s o t S t a n d a r d Table 1.21.20. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait)

Electrical characteristics (Vcc = 3V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 165 Table 1.21.25. Timer A input (gating input in timer mode) Table 1.21.26. Timer A input (external trigger input in one-shot timer mode) Table 1.21.27. Timer A input (external trigger input in pulse width modulation mode) Table 1.21.28. Timer A input (up/down input in event counter mode) Table 1.21.24. Timer A input (counter input in event counter mode) Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) VCC = 3V Table 1.21.23. External clock input Max. External clock rise time nstr Min. External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock fall time ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol UnitStandard 143 Standard Max. nsTAiIN input LOW pulse widthtw(TAL) Min. ns ns Unit TAiIN input HIGH pulse widthtw(TAH) ParameterSymbol tc(TA) TAiIN input cycle time 150 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 600 300 300 Standard Max.Min. ns ns ns Unit TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width tc(TA) tw(TAH) tw(TAL) Symbol Parameter 300 150 150 Standard Max.Min. ns ns Unit tw(TAH) tw(TAL) Symbol Parameter TAiIN input HIGH pulse width TAiIN input LOW pulse width 150 150 Standard Max.Min. ns ns ns Unit ns ns Symbol Parameter TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 3000 1500 1500 600 600

Electrical characteristics (Vcc = 3V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 166 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) VCC = 3V Table 1.21.29. Timer B input (counter input in event counter mode) Table 1.21.30. Timer B input (pulse period measurement mode) Table 1.21.31. Timer B input (pulse width measurement mode) Table 1.21.32. A-D trigger input Table 1.21.33. Serial I/O Table 1.21.34. External interrupt INTi inputs Standard Max.Min. TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) ns ns ns tc(TB) tw(TBH) tw(TBL) ParameterSymbol Unit tc(TB) tw(TBL) tw(TBH) ns ns ns TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) Standard Max.Min. ns ns tc(TB) tw(TBH) Symbol Parameter Unit tw(TBL) ns TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width Standard Max.Min. ns ns tc(TB) Symbol Parameter Unit tw(TBL) ns tw(TBH) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Standard Max.Min. ns ns tc(AD) tw(ADL) Symbol Parameter Unit AD TRG input cycle time (trigger able minimum) AD TRG input LOW pulse width 150 160 160 300 600 300 300 600 300 300 1500 200 ns ns ns ns ns ns ns Standard Max.Min. ns ns tw(INH) tw(INL) Symbol Parameter Unit INTi input LOW pulse width INTi input HIGH pulse width Standard Max.Min. CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width tc(CK) tw(CKH) tw(CKL) ParameterSymbol Unit td(C-Q) tsu(D-C) th(C-Q) TxDi hold time RxDi input setup time TxDi output delay time th(C-D) RxDi input hold time 380 380 300 150 150 160

Timing (Vcc = 3V) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 167 VCC = 3V tsu(D–C) TAiIN input TAiOUT input During event counter mode TBiIN input CLKi TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(AD) tw(ADL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) INTi input AD TRG input

Description (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 168 Table 1.22.1. Outline performance of the M30220 (flash memory version) Outline Performance Table 1.22.1 shows the outline performance of the M30220 (flash memory version). Item Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect Performance Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.22.1 No division (8 K bytes) (Note) In units of words Collective erase/block erase Program/erase control by software command 6 commands 100 times Parallel I/O and standard serial modes are supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area Power supply voltage 2.7V to 5.5 V (f(XIN)=10MHz, without wait, 4.0V to 5.5V, f(X IN)=7MHz, with one wait, 2.7V to 5.5V) Program/erase voltage 4.5V to 5.5 V (f(XIN)=10.0MHz, with one wait, f(X IN)=5.0MHz, without wait)

Description (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 169 Flash Memory The M30220 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 5 V, and 2 power sources when VCC is 3.3 V. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program- mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 1.22.1, so that memory can be erased one block at a time. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure 1.22.1. Block diagram of flash memory version 0E000016 0F000016 Block 2 : 32K byte 0F800016 Block 1 : 32K byte User ROM area 8K byte0DE000 16 0FFFFF 16 0DFFFF 16 Boot ROM area Note 1: The boot ROM area can be rewritten in only parallel input/ output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. Flash memory size Flash memory start address 128K byte 0E000016 Block 4 : 32K byte Block 3 : 32K byte0E800016 Parallel I/O mode 0E000016 0F000016 Block 2 : 32K byte 0F800016 Block 1 : 32K byte User ROM area 8K byte 0DE000 16 0FFFFF 16 0DFFFF 16 Boot ROM area Block 4 : 32K byte Block 3 : 32K byte0E800016 CPU rewrite mode, standard serial I/O mode

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 170 CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 1.22.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.22.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P7 4 pin high, the CNVSS pin high, the CPU starts operat- ing using the control program in the boot ROM area (program start address is DE00016 fixation). This mode is called the “boot” mode. Block Address Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 171 Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it can be excuted. The CPU rewrite mode is accessed by applying 5V – 10% to the CNV SS pin and writing “1” for the CPU rewrite mode select bit (bit 1 in address 03B416). Software commands are accepted once the mode is accessed. In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad- dress (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 1.23.1 shows the flash memory control register. Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”. Bit 1 is the CPU rewrite mode select bit. When this bit is set to “1” and 5V – 10% are applied to the CNV SS pin, the M30220 accesses the CPU rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in RAM for write to bit 1. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing a “0” . Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Figure 1.23.2 shows a flowchart for setting/releasing the CPU rewrite mode.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 172 Flash memory control register Symbol Address When reset FMCR 03B4 16 XXXX0001 2 WR b7 b6 b5 b4 b3 b2 b1 b0 FMCR0 Bit symbol Bit name Function RW 0: Busy (being written or erased) 1: Ready CPU rewrite mode select bit (Note 1) 0: Normal mode (Software commands invalid) 1: CPU rewrite mode FMCR1 CPU rewrite mode entry flag Flash memory reset bit (Note 2) 0: Normal operation 1: Reset Nothing is assigned. When write, set "0". When read, values are indeterminate. FMCR2 FMCR3 Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the control program in the RAM for write to this bit. Note 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting it to 1 (reset). /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines RY/BY status flag 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) Figure 1.23.1. Flash memory control registers

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 173 End Start Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 4) Single-chip mode, or boot mode (Note 1) Set processor mode register (Note 2) Using software command execute erase, program, or other operation Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Transfer CPU rewrite mode control program to internal RAM Note 1: Apply 5V ± 10 % to CNV SS pin by confirmation of CPU rewrite mode entry flag when started operation with single-chip mode. Note 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):

5.0 MHz or less when wait bit (bit 7 at address 000516) = “0” (without internal access wait state)

10.0 MHz or less when wait bit (bit 7 at address 000516) = “1” (with internal access wait state)

Note 3: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Write “0” to CPU rewrite mode select bit Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession)(Note 3) Check the CPU rewrite mode entry flag Program in ROM Program in RAM Figure 1.23.2. CPU rewrite mode set/reset flowchart

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 174 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 0006 16 and bits 6 and 7 at address 000716):

5.0 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)

10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)

(2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the vari- able vector table, they can be used by transferring the vector into the RAM area. (4) Reset If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Set a 5 ms wait to release the reset operation. Also, when the reset has been released, the program execute start address is automatically set to 0DE000 16, therefore program so that the execute start address of the boot ROM is 0DE00016.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 175 Command Program Clear status register Read array Read status register X X X X(Note 3) First bus cycle Second bus cycle FF16 7016 5016 4016 Write Write Write Write XS R DRead Write Erase all block X 2016Write X 2016Write (Note 2) WA (Note 3) WD (Note 3) Block erase X 2016Write D0 16Write BA (Note 4) Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) (Note 5) Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: X denotes a given address in the user ROM area (that is an even address). Cycle number Software Commands Table 1.23.1 lists the software commands available with the M30220 (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D 8 to D15) is ignored. The content of each software command is explained below. Table 1.23.1. List of software commands (CPU rewrite mode) Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D 15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D 7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4 to SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “50 16” in the first bus cycle.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 176 Start Write 4016 Status register read Program completed NO YES Write address Write data SR4=0? Program error NO YES SR7=1? or RY/BY=1? Write Figure 1.23.3. Program flowchart Program Command (40 16) Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by reading the status register or the RY/ BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF 16) is written. ____ The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Erase All Blocks Command (20 16/2016) By writing the command code “2016” in the first bus cycle and the confirmation command code “2016” in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be confirmed by reading the status register ____ or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of the erase operation. In this case, the read status register mode remains active until the Read Array command (FF 16) is written.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 177 Write 2016 2016/D016 Block address Erase completed NO YES Start Write SR5=0? Erase error YES NO 2016:Erase all blocks D0 16:Block erase SR7=1? or RY/BY=1? Status register read Figure 1.23.4. Erase flowchart Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed by reading the status register or ____ the RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. In this case, the read status register mode remains active until the Read Array command (FF 16). ____ The RY/BY status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed. ____ The RY/BY status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 178 Status Register The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input Table 1.23.2 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (50 16) After a reset, the status register is set to “8016”. Each bit in this register is explained below. Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared. Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. If “1” is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase com- mands are not accepted. Before executing these commands, execute the clear status register com- mand (50 16) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to 1.

CPU Rewrite Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 179 Read status register SR4=1 and SR5 =1 ? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program errorNO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (50 16) before executing these commands. Should a program error occur, the block in error cannot be used. Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.23.5 shows a full status check flowchart and the action to be taken when each error occurs. Figure 1.23.5. Full status check flowchart and remedial procedure for errors Each bit of SRD SR4 (bit4) SR5 (bit5) SR7 (bit7) SR6 (bit6) Status name Definition SR1 (bit1) SR2 (bit2) SR3 (bit3) SR0 (bit0) "1" "0" Program status Erase status Sequencer status Reserved Reserved Reserved Reserved Ready Busy Terminated in error Terminated in error Terminated normally Terminated normally --Reserved Table 1.23.2. Definition of each bit in status register

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 180 Symbol Address When reset ROMCP 0FFFFF 16 FF16 ROM code protect level 2 set bit (Note 1, 2) 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled ROM code protect control address Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled ROM code protect reset bit (Note 3) ROM code protect level 1 set bit (Note 1) ROMCP2 ROMCR ROMCP1 b3 b2 b5 b4 b7 b6 Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. Reserved bit Always set this bit to 1. Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. ROM code protect function The ROM code protect function reading out or modifying the contents of the flash memory version by using the ROM code protect control address (0FFFFF 16) during parallel I/O mode. Figure 1.23.6 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is imple- mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. Figure 1.23.6. ROM code protect control address

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 181 ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF 16, 0FFFE316, 0FFFEB 16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Figure 1.23.7. ID code store addresses Reset vector Watchdog timer vector Single step vector Address match vector BRK instruction vector Overflow vector Undefined instruction vector ID7 ID6 ID5 ID4 ID3 ID2 ID1 DBC vector NMI vector 0FFFFC 16 to 0FFFFF16 0FFFF8 16 to 0FFFFB16 0FFFF4 16 to 0FFFF716 0FFFF0 16 to 0FFFF316 0FFFEC 16 to 0FFFEF16 0FFFE8 16 to 0FFFEB16 0FFFE4 16 to 0FFFE716 0FFFE0 16 to 0FFFE316 0FFFDC 16 to 0FFFDF16 4 bytes Address

Appendix Parallel I/O Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 182 Parallel I/O Mode The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M30220 (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.22.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.22.1. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0DE000 16 through 0DFFFF 16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.

Appendix Standard Serial I/O Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 183 Pin Description VCC ,VSS Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. CNV SS Connect to VCC when VCC = 4.5V to 5.5 V. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT AV CC , AVSS VREF Connect AVSS to VSS and AVCC to VCC , respectively. Enter the reference voltage for AD from this pin. P00 to P07 Input "H" or "L" level signal or open. P10 to P17 Input "H" or "L" level signal or open. P20 to P27 Input "H" or "L" level signal or open. P30 to P35 Input "H" or "L" level signal or open. P40 to P47 Input "H" or "L" level signal or open. P70 to P73, P75, P76 Input "H" or "L" level signal or open. P74 Input "H" level signal. P77 P64 to P67 Input "H" or "L" level signal or open. P60 Standard serial mode 1: BUSY signal output pin Standard serial mode 2: Monitors the program operation check P61 P62 Serial data input pin P63 Serial data output pin P80 to P87 Input "H" or "L" level signal or open. P90 to P97 Input "H" or "L" level signal or open. P100 to P107 Input "H" or "L" level signal or open. Name Power input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P7 CE input NMI input Input port P6 BUSY output SCLK input RxD input TxD output Input port P8 Input port P9 Input port P10 I/O I I I O I I I I I I I I I I O I I O I I I Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input "L". XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT Clock input Clock output I O XCIN Connect a crystal oscillator between XCIN and XCOUT pins. To input an externally generated clock, input it to XCIN pin and open XCOUT pin.XCOUT Sub-clock input Sub-clock output I O P50 to P57 Input "H" or "L" level signal or open.Input port P5 I Connect this pin to Vcc. P110 to P117 Input "H" or "L" level signal or open.Input port P11 I P120 to P127 Input "H" or "L" level signal or open.Input port P12 I P130 to P132 Input "H" or "L" level signal or open.Input port P13 I SEG 0 to SEG15 Open when not used LCD control circuit.Segment output O COM 0 to COM3 Open when not used LCD control circuit.Common output O VL3 to VL1 Input LCD power source. Connect VL1 to VSS , VL2 to VCC , VL3 to VCC when not used LCD control circuit. Power supply input for LCD C 1 to C2 Step-up condenser connect port Pins in this port function as external pin for LCD step-up condenser. Connect a condenser between C1 and C2 when used LCD voltage multiplier. Open when not used LCD voltage multiplier. Pin functions (Flash memory standard serial I/O mode)

Appendix Standard Serial I/O Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 184 Figure 1.25.1. Pin connections for serial I/O mode (1) 1/R XD 2/SCLXOUTVSSXIN VCC RESET P7 7/NMI 6/INT 5/INT 4/INT P46/TA3OUT /INT4 P45/TA2IN P43/TA1IN P44/TA2OUT SEG /P12 SEG /P1 22SEG /P12 SEG /P12 SEG /P11 SEG /P11 SEG /P11 SEG /P11 SEG /P11 SEG /P11 SEG /P11 SEG /P10 VCCVSS SEG /P10 SEG /P10 SEG /P10 SEG /P10 SEG 0 VL3 VL2 VL1 AV SS VREF AV CC Vss SEG 1 XCOUTXCIN CNV SS COM 3 COM 2 COM 1 COM 0 0/TA4 OUT /INT 3/TA5 IN 4/TA6 OUT 2/TA5 OUT 110 113 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 109 111 112 144 108107106105104103102 10099 98 97 96 95 94 93 92 91 90 89101 7988 87 86 85 84 83 82 81 80 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SEG 10 1/TA4 IN /INT 0/T XD 2/SDA 2/CLK P41/TA0IN P42/TA1OUT P40/TA0OUT P62/RxD0 P35 P34 5/CLK 7/TxD 6/RxD 3/TxD SEG /P12 SEG /P12 SEG /P12 SEG /P12 SEG /P11 SEG 9 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG8 3/AN 2/AN 1/AN 4/AN 5/AN 6/AN P97/AN7 0/AN 7/TA7 IN 6/TA7 OUT 5/TA6 IN SEG /P0 SEG /P0 SEG /P0 SEG /P0 SEG /P0 SEG /P0 SEG /P0 SEG /P0 SEG 18/P102 SEG 17/P101 SEG 16/P100 SEG 15 SEG 14 SEG 12 SEG 11 SEG 13 P61/CLK0 P53/TB3IN P50/TB0IN P51/TB1IN P52/TB2IN P55/TB5IN P54/TB4IN P56/INT3 P57/CKOUT P47/TA3IN/INT4 P132/DA2 P130/ADTRG /DA0 P131/DA1 0/KI 1/KI 2/KI 3/KI 4/KI P15/KI5 P16/KI6 P17/KI7 P20/KI8 P21/KI9 P22/KI10 P23/KI11 P24/KI12 P25/KI13 P26/KI14 P27/KI15 P30/KI16 P31/KI17 P32/KI18 P33/KI19 3/CTS 2/RTS P60/CTS0/RTS0 4/CTS 1/RTS 1/CTS 0/CLKS M30220 flash memory version (144P6Q-A, 144PFB-A) BUSY RxD SCLK TxDRESET VCC VSS Note1V PPNote2 Mode setup method Signal CNVss RESET CE Value 4.5V to 5.5V Vss Vcc Vcc CE Note 1: Connect oscillator circuit. Note 2: Connect to VCC when VCC = 4.5V to 5.5 V.

Appendix Standard Serial I/O Mode (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 185 Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O mode is started by connecting “H” to the P74 (CE) pin and “H” to the CNVSS pin (when VCC = 4.5 V to 5.5 V, connect to VCC ; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord- ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 1.25.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK 0 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK0 pin to "H" level and release the reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and RTS0 (BUSY). The CLK0 pin is the transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS output. The RTS 0 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK0 pin to "L" level and release the reset. The operation uses the two UART0 pins RxD0 and TxD0. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.22.1 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com- mands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 186 Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART0). Standard serial I/O mode 1 is engaged by releasing the reset with the P6 1 (CLK0) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK 0 pin, and are then input to the MCU via the RxD0 pin. In transmis- sion, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD 0 pin. The TxD0 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS0 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS0 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 187 Software Commands Table 1.25.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Software commands are explained here below. Table 1.25.1. Software commands (Standard serial I/O mode 1) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Block erase

4 Erase all blocks

5 Read status register

6 Clear status register

7 Code processing function

8 Download function

9 Version data output function

10 Boot ROM area output

11 Read check data

(middle) Address (middle) Address (middle) D0 16 SRD output Address (low) Size (low) Version data output Address (middle) Check data (low) Address (high) Address (high) Address (high) SRD1 output Address (middle) Size (high) Version data output Address (high) Check data (high) Data output Data input D0 16 Address (high) Check- sum Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input ID1 To required number of times Version data output Data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte Data output to 259th byte FF 16 4116 2016 A7 16 7016 5016 F516 FA 16 FB 16 FC 16 FD 16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Not acceptable 1st byte transfer Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 190 Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “20 16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A 8 to A23. When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.A8 to A15 A16 to A232016 D0 16 CLK0 RxD0 TxD0 RTS0(BUSY) (M16C reception data) (M16C transmit data) Figure 1.25.6. Timing for block erasing

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 194 Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD 16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. Check data adds write data in 1 byte units and obtains the two’s-compliment of the insignificant 2 bytes of the accumulated data. Figure 1.25.13. Timing for the read check data Check data (low) CLK0 RxD0 TxD0 RTS0(BUSY) FD 16 (M16C reception data) (M16C transmit data) Check data (high)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 195 Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table 1.25.2 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Table 1.25.2. Status register (SRD) Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition "1" "0" Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 196 Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.25.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 1.25.3. Status register 1 (SRD1) Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the down- load function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data receive time out Reserved Definition "1" "0" Update completed Match Not update Mismatch Normal operation Not verified Verification mismatch Reserved Verified Time out

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 197 Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 1.25.14 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register SR4=1 and SR5 =1 ? NO Command sequence error YES SR5=0? YES Block erase errorNO SR4=0? YES Program errorNO End (block erase, program) Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (50 16) before executing these commands. Should a program error occur, the block in error cannot be used. Figure 1.25.14. Full status check flowchart and remedial procedure for errors

Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 198 Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. Figure 1.25.15. Example circuit application for the standard serial I/O mode 1 RTS 0(BUSY) CLK 0 R XD 0 TXD 0 CNVss Clock input BUSY output Data input Data output M30220 flash (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.5V to 5.5 V. VPP power source input NMI P74(CE)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 199 Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0). Standard serial I/O mode 2 is engaged by releasing the reset with the P6 1 (CLK0) pin "L" level. The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Fig- ure 1.25.16) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.25.16). (1) Transmit "B0 16" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Figure 1.25.16. Peripheral unit and initial communication MCU with internal flash memory Peripheral unit (1) Transfer "B016" If the oscillation frequency input by the main clock is 10 MHz, the MCU outputs "B0 16". If other than

10 MHz, the MCU does not

output anything. (2) Transfer "00 16" 16 times At least 15ms transfer interval 1st 2nd 15 th 16th (3) Transfer check code "B016" "B016" "0016" "0016" "0016" "B016" "B016" "0016" Reset The bit rate generator setting completes (9600bps)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 200 How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.25.4 gives the operation fre- quency and the baud rate that can be attained for. Table 1.25.4 Operation frequency and the baud rate Operation frequency (MH Z) Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps 10MH Z 8MH Z 7.3728MH Z 6MH Z 5MH Z 4.5MH Z 4.194304MH Z 4MH Z 3.58MH Z 3MH Z 2MH Z : Communications possible – : Communications not possible Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö Ö

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 201 Software Commands Table 1.25.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com- mands of standard serial I/O mode 1. Software commands are explained here below. Table 1.25.5. Software commands (Standard serial I/O mode 2) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

4 Erase all unlocked blocks

12 Baud rate 9600

13 Baud rate 19200

14 Baud rate 38400

15 Baud rate 57600

(middle) Address (middle) Address (middle) D0 16 SRD output Address (low) Size (low) Version data output Address (middle) Check data (low) B0 16 B1 16 B2 16 B3 16 Address (high) Address (high) Address (high) SRD1 output Address (middle) Size (high) Version data output Address (high) Check data (high) Data output Data input D0 16 Address (high) Check- sum Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input ID1 To required number of times Version data output Data output Data output to 259th byte Data input to 259th byte To ID7 Version data output to 9th byte Data output to 259th byte FF 16 4116 2016 A7 16 7016 5016 F516 FA 16 FB 16 FC 16 FD 16 B0 16 B1 16 B2 16 B3 16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Not acceptable Acceptable Acceptable Acceptable Acceptable 1st byte transfer Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans- ferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 205 Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA 16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. FA 16 Program data Program data Data size (high) Data size (low) Check sum RxD0 TxD0 (M16C reception data) (M16C transmit data) Figure 1.25.23. Timing for download

Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Under development Preliminary Specifications REV.E Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30220 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 210 Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. Figure 1.25.23. Example circuit application for the standard serial I/O mode 2 BUSY CLK 0 R XD 0 TXD 0 CNVss Monitor output Data input Data output M30220 flash (1) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.5V to 5.5 V. VPP power source input NMI P74(CE)

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M30220 Group Specification REV.E Oct. First Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1999 MITSUBISHI ELECTRIC CORPORATION