M30218

M30218 MITSUBISHI | Alldatasheet

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Mitsubishi single-chip microcomputer Mitsubishi Electric Corporation Kitaitami Works Mitsubishi Electric Semiconductor System Corporation REV.A1 M30218 Group User’s manual (tentative) Specifications written in this user's manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance im- provements. Please make sure your manual is the latest edition.

Keep safety first in your circuit designs! Notes regarding these materials l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). l When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein.

This user's manual describes the function and features of the Mitsubishi M30218 Group CMOS 16-bit microcomputer. The software features are explained to help designers take full advantage of the M16C functions. For details about the software, please refer to the “M16C/60, M16C/20 series software manual”, and for the development support tools, please refer to the related instruction manual.

This user's manual is written for the M30218 group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual is for the use of the models below.

• M30217MA-XXXXFP
• M30218MC-XXXXFP
• M30218FCFP These products have similar features except for the memories, which differ from one product to another. This manual gives descriptions of M30218MC-XXXXFP. Memories built-in are as shown below. Be careful when writing a program, as the memories have different capacities. The figure of each register configuration describes its functions, contents at reset, and attributes as follows :
• Bit attribute Bit attribute RAM size (Byte) 12K 512 M30218MC-XXXXFP M30218FCFP 128K ROM size (Byte) M30217MA-XXXXFP5K 96K T A 1 O S T A 2 O S T A 0 O S O n e - s h o t s t a r t f l a g S y m b o lA d d r e s sW h e n r e s e t O N S 6 0 X T i m e r A 0 o n e - s h o t s t a r t f l a g T i m e r A 1 o n e - s h o t s t a r t f l a g T i m e r A 2 o n e - s h o t s t a r t f l a g T i m e r A 3 o n e - s h o t s t a r t f l a g T i m e r A 4 o n e - s h o t s t a r t f l a g T A 3 O S T A 4 O S B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 T A 0 T G L T A 0 T G H 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T i m e r A 0 e v e n t / t r i g g e r s e l e c t b i t b b N o t e : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . W h e n T A iI N i s s e l e c t e d T A iO U T a s s i g n e d o n s a m e p i n c a n n o t b e u s e d i t o WR 1 : T i m e r s t a r t W h e n r e a d t h e v a l u e i s N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e “ 0 ” . T h e v a l u e , i f r e a d t u r n s o u t t o b e @i n d e t e r m i n a t e

This manual comprises of five chapters. Use the suggested chapters as a reference for the following topics: * To understand the basic way of using peripheral * To observe applications of This manual includes a quick reference immediately following the Table of Contents, indicate the page of the topic to be pursued. * To find a page describing a specific register

M16C Family-related document list Usages (Microcomputer development flow) Outline design of system Selection of microcomputer Detail design of system Hard- ware devel- opment System evaluation Soft- ware devel- opment

Contents

Hardware specifications (pin assignment, memory map, specifications of peripheral func- tions, electrical characteristics, timing charts) Detailed description about hardware specifica- tions, operation, and application examples (connection with peripherals, relationship with software) Method for creating programs using assembly and C languages Detailed description about operation of each instruction (assembly language) Hardware Type of document Data sheet and data book User’s manual Software M16C Family M16C/80 Series M16C/80 Group M16C/60 Series M16C/60 Group M16C/61 Group M16C/62 Group M16C/20 Series M16C/20 Group M16C/21 Group M16C Family Line-up Programming manual Software manual

2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode se-

2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode

2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock

2.6.6 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode, using

Chapter 3 Examples of Peripheral functions Applications ________

This page kept blank for layout purposes.

Quick Reference to Pages Classified by Address 0 0 4 01 C 1 D 1 C 1 D 1 C 1 D 1 C 1 D 1 0 0 0 01 C 1 D 1 C 1 D 1 I N T 1 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 1 I C ) T i m e r B 0 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 0 I C ) T i m e r B 2 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 2 I C ) T i m e r A 1 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 1 I C ) T i m e r A 3 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 3 I C ) U A R T t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S T I C I N T 2 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 2 I C ) I N T 0 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 0 I C ) T i m e r B 1 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 1 I C ) T i m e r A 0 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 0 I C ) T i m e r A 2 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 2 I C ) T i m e r A 4 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 4 I C ) U A R T r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S R I C U A R T t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r S T I C U A R T r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r S R I C D M A 1 i n t e r r u p t c o n t r o l r e g i s t e r ( D M 1 I C ) D M A 0 i n t e r r u p t c o n t r o l r e g i s t e r ( D M 0 I C ) A - D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r ( A D I C ) D M A 0 c o n t r o l r e g i s t e r ( D M 0 C O N ) D M A 0 s o u r c e p o i n t e r ( S A R 0 ) D M A 0 t r a n s f e r c o u n t e r ( T C R 0 ) D M A 0 d e s t i n a t i o n p o i n t e r ( D A R 0 ) D M A 1 c o n t r o l r e g i s t e r ( D M 1 C O N ) D M A 1 s o u r c e p o i n t e r ( S A R 1 ) D M A 1 t r a n s f e r c o u n t e r ( T C R 1 ) D M A 1 d e s t i n a t i o n p o i n t e r ( D A R 1 ) W a t c h d o g t i m e r s t a r t r e g i s t e r ( W D T S ) W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D C ) P r o c e s s o r m o d e r e g i s t e r 0 ( P M 0 ) A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( R M A D 0 ) A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 ( R M A D 1 ) S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( C M 0 ) S y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( C M 1 ) A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r ( A I E R ) P r o t e c t r e g i s t e r ( P R C R ) P r o c e s s o r m o d e r e g i s t e r 1 ( P M 1 ) 0 0 2 01 C 1 D 1 C 1 D 1 4 3 5 0 5 1 5 1 5 1 5 0 5 1 5 1 5 1 4 7 1 8 2 2 4 3 2 7 4 3 3 4 5 7 5 8 5 9 A d d r e s sR e g i s t e rP a g eA d d r e s sR e g i s t e rP a g e I N T 3 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 3 I C ) I N T 4 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 4 I C ) I N T 5 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 5 I C ) 3 4 3 4 S I / O 2 a u t o m a t i c t r a n s f e r i n t e r r u p t c o n t r o l r e g i s t e r ( A S I O I C ) F L D i n t e r r u p t c o n t r o l r e g i s t e r ( F L D I C ) P 3 F L D / p o r t s w i t c h r e g i s t e r ( P 3 F P R ) P 5 d i g i t o u t p u t s e t r e g i s t e r ( P 5 D O R ) T o f f 2 t i m e s e t r e g i s t e r ( T O F F 2 ) F L D d a t a p o i n t e r ( F L D D P ) F L D o u t p u t c o n t r o l r e g i s t e r ( F L D C O N ) P 6 d i g i t o u t p u t s e t r e g i s t e r ( P 6 D O R ) P 4 F L D / p o r t s w i t c h r e g i s t e r ( P 4 F P R ) P 2 F L D / p o r t s w i t c h r e g i s t e r ( P 2 F P R ) T d i s p t i m e s e t r e g i s t e r ( T D I S P ) T o f f 1 t i m e s e t r e g i s t e r ( T O F F 1 ) F L D m o d e r e g i s t e r ( F L D M ) S e r i a l I O a u t o m a t i c t r a n s f e r d a t a p o i n t e r S I O D P S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 ( S I O 2 C O N 1 ) S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 ( S I O 2 C O N 2 ) S e r i a l I / O 2 r e g i s t e r / t r a n s f e r c o u n t e r ( S I O 2 ) S e r i a l I / O 2 c o n t r o l r e g i s t e r 3 ( S I O 2 C O N 3 ) 5 7 5 7 5 6 1 0 5 1 0 5 1 0 4 1 0 4 1 0 5

Quick Reference to Pages Classified by Address A d d r e s sR e g i s t e rP a g eA d d r e s sR e g i s t e rP a g e 0 3 8 01 C 1 D 1 C 1 D 1 0 3 A 01 A A A A A A A A A A A A C 1 A D 1 A A B B B B B B B B B B B B B C 1 B D 1 B B D M A 1 r e q u e s t c a u s e s e l e c t r e g i s t e r ( D M 1 S L ) D M A 0 r e q u e s t c a u s e s e l e c t r e g i s t e r ( D M 0 S L ) U A R T 0 t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( U 0 M R ) U A R T 0 t r a n s m i t b u f f e r r e g i s t e r ( U 0 T B ) U A R T 0 r e c e i v e b u f f e r r e g i s t e r ( U 0 R B ) U A R T 1 t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( U 1 M R ) U A R T 1 t r a n s m i t b u f f e r r e g i s t e r ( U 1 T B ) U A R T 1 r e c e i v e b u f f e r r e g i s t e r ( U 1 R B ) T i m e r A 0 ( T A 0 ) T i m e r A 1 ( T A 1 ) T i m e r A 2 ( T A 2 ) T i m e r B 0 ( T B 0 ) T i m e r B 1 ( T B 1 ) T i m e r B 2 ( T B 2 ) C o u n t s t a r t f l a g ( T A B S R ) O n e - s h o t s t a r t f l a g ( O N S F ) T i m e r A 0 m o d e r e g i s t e r ( T A 0 M R ) T i m e r A 1 m o d e r e g i s t e r ( T A 1 M R ) T i m e r A 2 m o d e r e g i s t e r ( T A 2 M R ) T i m e r B 0 m o d e r e g i s t e r ( T B 0 M R ) T i m e r B 1 m o d e r e g i s t e r ( T B 1 M R ) T i m e r B 2 m o d e r e g i s t e r ( T B 2 M R ) U p - d o w n f l a g ( U D F ) T i m e r A 3 ( T A 3 ) T i m e r A 4 ( T A 4 ) T i m e r A 3 m o d e r e g i s t e r ( T A 3 M R ) T i m e r A 4 m o d e r e g i s t e r ( T A 4 M R ) T r i g g e r s e l e c t r e g i s t e r ( T R G S R ) U A R T 0 b i t r a t e g e n e r a t o r ( U 0 B R G ) U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( U 0 C 0 ) U A R T 0 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( U 0 C 1 ) U A R T 1 b i t r a t e g e n e r a t o r ( U 1 B R G ) U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( U 1 C 0 ) U A R T 1 t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 1 ( U 1 C 1 ) U A R T t r a n s m i t r e c e i v e c o n t r o l r e g i s t e r U C O N C R C d a t a r e g i s t e r ( C R C D ) C R C i n p u t r e g i s t e r ( C R C I N ) C l o c k p r e s c a l e r r e s e t f l a g ( C P S R F ) 7 3 7 4 7 3 7 3 8 3 7 2 8 2 9 1 9 0 9 1 9 2 9 0 9 1 9 0 9 1 9 2 9 0 9 2 5 0 5 0 1 2 7 0 3 E 01 E E E E E E E E E E E E C 1 E D 1 E E F F F F F F F F F F F F F C 1 F D 1 F F 0 3 C 01 C C C C C C C C C C C C C 1 C D 1 C C D D D D D D D D D D D D D C 1 D D 1 D D P o r t P 0 ( P 0 ) P o r t P 1 ( P 1 ) P o r t P 2 ( P 2 ) P o r t P 3 ( P 3 ) P o r t P 3 d i r e c t i o n r e g i s t e r ( P D 3 ) P o r t P 4 ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P D 4 ) P o r t P 5 ( P 5 ) P o r t P 6 ( P 6 ) P o r t P 7 ( P 7 ) P o r t P 7 d i r e c t i o n r e g i s t e r ( P D 7 ) P o r t P 8 ( P 8 ) P o r t P 8 d i r e c t i o n r e g i s t e r ( P D 8 ) P o r t P 9 ( P 9 ) P o r t P 9 d i r e c t i o n r e g i s t e r ( P D 9 ) P o r t P 1 0 ( P 1 0 ) P o r t P 1 0 d i r e c t i o n r e g i s t e r ( P D 1 0 ) P u l l - u p c o n t r o l r e g i s t e r 0 ( P U R 0 ) P u l l - u p c o n t r o l r e g i s t e r 1 ( P U R 1 ) A - D r e g i s t e r 7 ( A D 7 ) A - D r e g i s t e r 0 ( A D 0 ) A - D r e g i s t e r 1 ( A D 1 ) A - D r e g i s t e r 2 ( A D 2 ) A - D r e g i s t e r 3 ( A D 3 ) A - D r e g i s t e r 4 ( A D 4 ) A - D r e g i s t e r 5 ( A D 5 ) A - D r e g i s t e r 6 ( A D 6 ) A - D c o n t r o l r e g i s t e r 0 ( A D C O N 0 ) A - D c o n t r o l r e g i s t e r 1 ( A D C O N 1 ) D - A r e g i s t e r 0 ( D A 0 ) D - A r e g i s t e r 1 ( D A 1 ) D - A c o n t r o l r e g i s t e r ( D A C O N ) A - D c o n t r o l r e g i s t e r 2 ( A D C O N 2 ) 1 1 8 1 1 8 1 1 7 1 2 6 1 2 6 1 2 6 1 3 2 1 3 2 1 3 2 1 3 2 1 3 3 F l a s h m e m o r y c o n t r o l r e g i s t e r F C O N N o t e F l a s h m e m o r y c o n t r o l r e g i s t e r F C O N N o t e F l a s h c o m m a n d r e g i s t e r ( F C M D ) ( N o t e ) N o t e : T h i s r e g i s t e r i s o n l y e x i s t i n f l a s h m e m o r y v e r s i o n . 1 5 5 1 3 2 1 3 2

Description

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R The M30218 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling musical instruments, house- hold appliances and other high-speed processing applications. The M30218 group includes a wide range of products with different internal memory types and sizes and various package types.

Features

• Shortest instruction execution time .100ns (f(X IN)=10MHz) 2.7V to 5.5V (f(XIN)=3.5MHz)(Note) (high-breakdown-voltage P-channel open-drain output : 52pins) 1 channels for clock synchronous (max.256 bytes automatic transfer function) (built-in feedback resistor, and external ceramic or quartz oscillator) Note: Only mask ROM version.

Applications

Household appliances, office equipment, Audio etc. Specifications written in this manual are believed to be accurate, but are not guaranteed to be en- tirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R ROM RAM P3, P4, P7 to P10 P0 to P2, P5, P6 TA0, TA1, TA2, TA3, TA4 TB0, TB1, TB2 UART0, UART1 SI/O2 Table 1. Performance outline of M30218 group Table 1 shows a performance outline of M30218 group. Note: Only mask ROM version.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Pin Description VCC , VSS CNV SS XIN XOUT AV CC AV SS VEE P00/FLD16 to P07/FLD23 P10/FLD24 to P17/FLD31 P20/FLD32 to P27/FLD39 P30/FLD40 to P37/FLD47 P40/FLD48 to P47/FLD56 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input pull-down power source Output port P0 Output port P1 Output port P2 I/O port P3 I/O port P4 Supply 2.7V(Note1) to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Connect a bypass capacitor across the VCC pin and VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A-D converter. Connect this pin to VCC . This pin is a power supply input for the A-D converter. Connect this pin to VSS . This is an 8-bit CMOS output port and high-breakdown-voltage P- channel open-drain output structure. A pull-down resistor is built in between port P0 and V EE pin. At reset, this port is set to VEE level. P0 function as FLD controller output pins as selected by software. This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit output port equivalent to P0. A pull-down resistor is not built in between P2 and VEE pin (Note2). Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit I/O port. A pull-down resistor is not built in between P3 and VEE pin (Note2). It has an input/output port direction register that allows the user to set each pin for input or output. This is low-voltage input level, and high-breakdown-voltage P-channel open-drain output structure. Pins in this port also function as FLD controller output pins as selected by software. This is an 8-bit I/O port equivalent to P3. This is low-voltage input level. 0 to P43 is high-breakdown-voltage P-channel open-drain output structure, P44 to P47 is CMOS output. A pull-down resistor is not built in between P4(P40 to P43) and VEE pin (Note2). Pins in this port also function as FLD controller output pins as selected by software. P44 to P47 also function as UART0 I/O pins as selected by software. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. Pin name Input Input Input Output Output Output Output I/O type Analog power supply input Input/output Input/output RESET VREF This pin is a reference voltage input for the A-D converter.InputReference voltage input Apply voltage supplied to pull-down resistors of ports P0 to P1,P5,P6. P50/FLD8 to P57/FLD15 Output port P5 This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. Output P60/FLD0 to P67/FLD7 Output port P6 This is an 8-bit output port equivalent to P0. Pins in this port also function as FLD controller output pins as selected by software. Output

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Pin Description Signal name FunctionPin name I/O type Input/output Input/output I/O port P9 I/O port P10 P90 to P97 P100 to P107 This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P9 7 function as D-A converter output pins, clock output pins (same frequency of XIN/8, XIN/32 or XCIN) and DIM signal output pin of FLD controller as selected by software. P96 function as D- A converter output pins and clock I/O pin of serial I/O with automatic transfer as selected by software. P9 0 to P95 function as I/O pin of serial I/O with automatic transfer as selected by software. This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. Pins in this port also function as A-D converter input pins as selected by software. P70 to P77 I/O port P7 This is an 8-bit I/O port equivalent to P3. This is CMOS input/output. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P7 0 to P72 function as TimerB0 to B2 input pins as selected by software. P73 function as TimerA0 I/O pin as selected by software. P74 to P77 function as TimerA1 to A4 I/O pins, and UART1 I/O pins as selected by software. Input/output P80 to P87 I/O port P8 This is an 8-bit I/O port equivalent to P7. When set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. P8 0 to P85 function as external interrupt input pins as selected by software. P86,P87 function as sub-clock input pin as selected by software. In this case, connect a quarts oscillator between 6(XOUT pin) and P87(XCIN pin) Input/output Note 1: Supply 4.0V to 5.5V to the VCC pin in flash memory version. Note 2: Port P20 to P27, P30 to P37, and P40 to P43 can be selected whether pull-down resistors are built-in or not by the mask option specification. Flash memory version does not have this option.

Figure 6. Location of peripheral unit control registers (1)

Figure 7. Location of peripheral unit control registers (2) Note: This register is only exist in flash memory version.

and FB) come in two sets; therefore, these have two register banks. arithmetic/logic operations. use as 32-bit data registers (R2R0, R3R1). In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Figure 8. Central processing unit register Note: These registers consist of two register banks.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure CA-2 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

Figure 9. Flag register (FLG)

• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. C a r r y f l a g D e b u g f l a g Z e r o f l a g S i g n f l a g R e g i s t e r b a n k s e l e c t f l a g O v e r f l o w f l a g I n t e r r u p t e n a b l e f l a g S t a c k p o i n t e r s e l e c t f l a g R e s e r v e d a r e a P r o c e s s o r i n t e r r u p t p r i o r i t y l e v e l R e s e r v e d a r e a F l a g r e g i s t e r ( F L G )CDZSBOIUI P L b 0b 1 5

Figure 12. Device's internal status after a reset is cleared The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Figure 13. Device's internal status after a reset is cleared The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note: This register is only exist in flash memory version.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004 16) in the memory expan- sion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high- speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, fAD , f1SIO2, f8SIO2) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

(bit 2 at address 000616) is set to “1”, the output of f8 and f32 stop by executing of WAIT instruction. that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. to stop mode, the value before stop mode is retained. Table 3. Port status during stop mode allowing power dissipation to be reduced. Table 4 shows the status of the ports in wait mode. WAIT instruction was executed. Table 4. Port status during wait mode to entering wait mode is maintained. Note: Attention that reducing the power dissipation is impossible.

Table 5. Operating modes dictated by settings of system clock control registers 0 and 1 shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. The main clock is divided by 2 to obtain the BCLK. The main clock is divided by 4 to obtain the BCLK. mode, make sure the sub-clock is oscillating stably. The main clock is divided by 16 to obtain the BCLK. The main clock is divided by 1 to obtain the BCLK. after powering up and after stop mode is cancelled. fC is the BCLK and the main clock is stopped. the oscillation to stabilize before switching over the clock.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Power Control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper- ates according to its assigned clock.
• Low-speed mode f C becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 19 shows the state transition diagram of the above modes.

Figure 19. State transition diagram of Power control mode Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow.

the respective bit in the protect register is set to “1”. been written to an address. The program must therefore be written to return these bits to “0”. Figure 20. Protect register N o t h i n g i s a s s i g n e d .

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

• Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter- rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re- quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates.
• A-D conversion interrupt This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt This is an interrupt that the SI/O automatic transfer generates.
• Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates
• Timer B0 interrupt through timer B2 interrupt These are interrupts that timer B generates.
• INT0 interrupt through INT5 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

Note: Interrupts used for debugging purposes only. Figure 22. Format for specifying interrupt vector addresses variable vector table in which addresses can be varied by the setting.

• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 6 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.

Table 6. Interrupts assigned to the fixed vector tables and addresses of vector tables

Table 7. Interrupts assigned to the variable vector tables and addresses of vector tables Note : Address relative to address in interrupt table register (INTB).

• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 7 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec- tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 23 shows the memory map of the interrupt control registers.

Figure 23. Interrupt control registers

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Table 9. Interrupt levels enabled according to the contents of the IPLTable 8. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 8 shows the settings of interrupt priority levels and Table 9 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

instant the interrupt routine is executed — is described here. in the temporary register (Note) within the CPU. (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. address of the interrupt routine. Note: This register cannot be utilized by the user. time required for executing the interrupt sequence (b). Figure 24 shows the interrupt response time. (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 24. Interrupt response time

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 11 shows set in the IPL. Table 11. Relationship between interrupts without interrupt priority levels and IPL Table 10. Time required for executing the interrupt sequence The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs.

0000 Indeterminate SP-2 SP-4 vec vec+2 PC

W R Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction. Time (b) is as shown in Table 10. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 25. Time required for executing the interrupt sequence

(PC) are saved in the stack area. request, and the state the stack after the acceptance of the interrupt request. PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 26. State of stack before and after acceptance of interrupt request

Figure 27. Operation of saving registers Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. a time. Figure 27 shows the operation of the saving registers. Note: Stack pointer indicated by U flag.

Figure 29. Maskable interrupts priorities

Figure 31. Switching condition of INT interrupt request

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. (3) External interrupt
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 through INT5 regardless of the CPU operation clock.
• When the polarity of the INT0 through INT5 pins is changed, the interrupt request bit is sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 31 shows the procedure for changing the INT interrupt generate factor. Precautions for Interrupts

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E RPrecautions for Interrupts Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET

Figure 33. Watchdog timer control and start registers

16 Indeterminate

regardless of whatever value is written.

Figure 34. Block diagram of DMAC interrupt priority level. The DMA transfer doesn't affect any interrupts either. number of transfers. For details, see the description of the DMA request bit. Note: Pointer is incremented by a DMA request.

• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) Maximum No. of bytes transferred128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) DMA request factors (Note) Falling edge of INT0 or INT1 (INT0 can be selected by DMA0, INT1 by DMA1) Timer A0 to timer A4 interrupt requests Timer B0 to timer B2 interrupt requests UART0 transmission and reception interrupt requests UART1 transmission and reception interrupt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward or fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive
• Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timingWhen an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive.
• After the transfer counter underflows in single transfer mode At the time of starting data transfer immediately after turning the DMAC active, re the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer.

Table 12. DMAC specifications flag (I flag) nor by the interrupt priority level.

Figure 35. DMAC-related registers (1) Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. cannot be set to “1” simultaneously. Note: Address 03B816 is for INT0; address 03BA16 is for INT1. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

Figure 36. DMAC-related registers (2)

• Transfer counter Set a value one less than the transfer count Symbol Address When reset TCR0 0029 16, 002816 Indeterminate TCR1 0039 16, 003816 Indeterminate DMAi transfer counter (i = 0, 1) Transfer count specification 000016 to FFFF16 (b23) b3 b0 b7 b0 b7 b0 Function RW
• Source pointer Stores the source address Symbol Address When reset SAR0 0022 16 to 002016 Indeterminate SAR1 0032 16 to 003016 Indeterminate DMAi source pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Symbol Address When reset DAR0 0026 16 to 002416 Indeterminate DAR1 0036 16 to 003416 Indeterminate b3 b0 b7 b0 b7 b0 Function RW
• Destination pointer Stores the destination address DMAi destination pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 (b23) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

ber of DMAC transfer cycles. Table 13. No. of DMAC transfer cycles

The M30218 group has fluorescent display (FLD) drive and control circuits. Table 14 shows the FLD controller specifications.

• 52 pins ( 20 pins can switch general purpose port)
• 4 pins ( 4 pins can switch general purpose port) (A driver must be installed externally)
• Used FLD output 28 segment X 28 digit (segment number + digit number ≤ 56)
• Used digit output 40 segment X 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501 56 segment X (connect number of M35501) digit (segment number ≤ 56, digit number ≤ number of M35501 X 16)
• Used P4 4 to P47 expansion 52 segment X 16 digit (segment number ≤ 52, digit number ≤ 16)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• 3.2 µs to 819.2 µs (count source XIN/32,10MHz)
• 12.8 µs to 3276.8 µs (count source XIN/128,10MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan used digit
• Key-scan used segment
• Digit pulse output function This function automatically outputs digit pulse.
• M35501 connect function The number of digits can be increased easily by using the output of DIM OUT (P97) as CLK for the M35501.
• Toff section generate / not generate function This function does not generate Toff1 section when the connected outputs are the same.
• Gradation display function This function allows each segment to be set for dark or bright display.
• P4 4 to P47 expansion function This function provides 16 lines of digit outputs from four ports by attaching a 4 16 decoder. Item FLD controller port High-breakdown-volt- age output port CMOS port Display pixel number Period Dimmer time Interrupt Key-scan Expand function

Table 14. FLD controller specifications

Figure 38. Block Diagram for FLD Control Circuit

Figure 39. FLDC-related Register(1) Note : When a gradation display mode is selected, a number of timing is max. 16 timing. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. counter count source select bit.

Figure 40. FLDC-related Register(2) Note: Reading the FLD data pointer takes out the count at that moment.

Figure 41. FLDC-related Register(3)

Figure 42. FLDC-related Register(4)

Figure 43. Segment/Digit Setting Example Table 15. Pins in FLD Automatic Display Mode 035D 16) can set each pin either FLD port (“0”) or digit port (“1”). the value of FLD automatic display RAM. the port as a display pin, a driver must be installed externally. Shown below is a register setup example where only FLD output is used. generated, there is no need to set the display pattern in the FLD automatic display RAM. DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. general-purpose port ( used program). DIG output : This output is connected to digit of the FLD. SEG output : This output is connected to segment of the FLD. Port output : This output is general-purpose port ( used program).

on the number of timings and the use/not use of gradation display. automatic display RAM, they can be the ordinary RAM. to 056F16 are used as a gradation display control data store area. This mode is used when the display timing is 16 or greater. This mode can be used for up to 32-timing. 16 to 05DF16 are used as an FLD display data store area. the FLD data pointer is read. Figure 44. FLD Automatic Display RAM Assignment

The area of addresses 057016 to 05DF16 are used as a FLD automatic display RAM. assign in sequence from the last data respectively. Set the FLD data pointer reload register to the value given by the number of digits – 1. and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1” . The area of addresses 050016 to 05DF16 are used as a FLD automatic display RAM. assign in sequence from the last data respectively. Set the FLD data pointer reload register to the value given by the number of digits - 1. Figure 45. Example of Using the FLD Automatic Display RAM in 16-timing•Ordinary Mode

057016 The last timing

Figure 46. Example of Using the FLD Automatic Display RAM in 16-timing•Gradation Display Mode

050016 The last timing

055016 The last timing

056016 The last timing

Figure 47. Example of Using the FLD Automatic Display RAM in 32-timing Mode

Figure 48. FLDC Timing

• Grayscale display mode is not selected (Address 035016 bit 5 = “0”)
• Grayscale display mode is selected and set for bright display (Address 035016 bit 5 = “1” and the corresponding grayscale display control data = “0”) Low output period for blurring prevention Display output period Display output period Low output period for blurring prevention
• Grayscale display mode is selected and set for dark display (Address 0350 16 bit 5 = “1” and the corresponding grayscale display control data = “1”) Low output period for dark display Timing setting Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
• Tdisp time setting The Tdisp time represents the length of display timing. In non-gradation display mode, it consists of a FLD display output period and a Toff1 time. In gradation display mode, it consists of the display output period and Toff1 time plus a low signal output period for dark display. Set the Tdisp time by the Tdisp counter count source select bit of the FLDC mode register and the Tdisp time set register. Supposing that the value of the Tdisp time set register is n, the Tdisp time is represented as Tdisp = (n+1) x t (t: count source). When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Tdisp time set register is 200 (C8 16), the Tdisp time is: Tdisp = (200+1) x 3.2 (at XIN= 10 MHz) = 643 µs. When reading the Tdisp time set register, the value in the counter is read out.
• Toff1 time setting The Toff1 time represents a non-output (low signal output) time to prevent blurring of FLD, and to dim the display. Use the Toff1 time set register to set this Toff1 time. Make sure the value set to Toff1 is smaller than Tdisp and Toff2. Supposing that the value of the Toff1 time set register is n1, the Toff1 time is represented as Toff1 = n1 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Toff1 time set register is 30 (1E 16), Toff1 = 30 x 3.2 (at XIN = 10 MHz) = 96 µs.
• Toff2 time setting The Toff2 time is provided for dark display. For bright display, the FLD display output remains effective until the counter that is counting Tdisp reaches the terminal count. For dark display, however, “L” (or “off”) signal is output when the counter that is counting Toff2 reaches the terminal count. This Toff2 time setting is valid only for FLD ports which are in the gradation display mode and whose gradation display control RAM value is “1” . Set the Toff2 time by the Toff2 time set register. Make sure the value set to Toff2 is smaller than Tdisp but larger than Toff1. Supposing that the value of the Toff2 time set register is n2, the Toff2 time is repre- sented as Toff2 = n2 x t. When the Tdisp counter count source select bit of the FLDC mode register is “0” and the value of the Toff2 time set register is 180 (B4 16), Toff2 = 180 x 3.2 (at XIN = 10 MHz) = 576 µs.

Figure 49. Timing using digit interrupt register, Tdisp time set register, Toff1 time set register, Toff2 time set register, and FLD data pointer. FLD automatic display can be interrupted by writing “0” to bit 1. FLD digit interrupts for key scanning, follow the procedure described below. (1) Read the port value each time the interrupt occurs. (2) The key is fixed on the last digit interrupt.

Figure 50. Timing using FLD blanking interrupt this time, key scanning that makes use of FLD segments can be achieved.

1. Write “0” to bit 0 of the FLDC mode register (address 035016).
2. Set the port corresponding to the segment for key-scan to the output port.

After the key-scan is performed, write “1” to bit 0 of FLDC mode register (address 035016).

• Note: When performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. Do not set “0” in bit 1 of the FLDC mode register (address 035016). 2. Do not set “1” in the ports corresponding to digits.

This function disables the Toff1 time and Toff2 time and outputs display data for the duration of Tdisp. Unlike the Toff section generate/not generate function, this function disables all display data. 7 dimmer output control bit (bit 4 of address 035116) to “1”. adjusting the polarity when using an externally installed driver. Figure 51. P4 to P47 FLD Output pulses

• Grayscale display mode is not selected
• Grayscale display mode is selected and set for bright display (grayscale display control data = “0”)
• Grayscale display mode is selected and set for dark display (grayscale display control data = “1”)
• Grayscale display mode is selected and Toff2 SET/RESET bit is “1” (grayscale display control data = “1”) Output selecting P4 4 to P47 Toff invalid

(RESET) when the Tdisp time expires. breakdown-voltage ports: section of Toff generate / not generate bit” to “1”. ports: section of Toff generate / not generate bit” to “1”. Figure 52. Toff Section Generated/not generated Function Section of Toff1 is not generated because of output is same. Section of Toff1 is not generated because of output is same.

Figure 53. Digit Pulses Output Function in the FLD automatic display RAM.

(three). All these timers function independently. Figure 54 shows the block diagram of timers. Figure 54. Timer block diagram

• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Timer mode
• One-shot mode
• PWM mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Event counter mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode
• Timer mode
• Pulse width measuring mode TA0 IN/ TA3 OUT TA1 IN/ TA4 OUT TA2 IN/ TA0 OUT TA3 IN/ TA1 OUT TA4 IN/ TA2 OUT TB0 IN TB1 IN TB2 IN Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 f1 f8 f32 fc32 Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Timer B0 interrupt Timer B1 interrupt Timer B2 interrupt Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter 1/32 fC32 f32 XIN XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler

Figure 57. Timer A-related registers (2)

• T i m e r m o d e0 0 0 01 6 t o F F F F C o u n t s a n i n t e r n a l c o u n t s o u r c e F u n c t i o n V a l u e s t h a t c a n b e s e t
• E v e n t c o u n t e r m o d e C o u n t s p u l s e s f r o m a n e x t e r n a l s o u r c e o r t i m e r o v e r f l o t o F F F
• O n e - s h o t t i m e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s a o n e s h o t w i d t h
• P u l s e w i d t h m o d u l a t i o n m o d e ( 1 6 - b i t P W M ) F u n c t i o n s a s a b i t p u l s e w i d t h m o d u l a t o r 0 01 6 t o F E1 B o t h h i g h o r d e r a n d l o w o r d e r a d d r e s s e s 0 0 0 01 6 t o F F F E1 N o t e : R e a d a n d w r i t e d a t a i s i n 1 6 - b i t u n i t s .
• P u l s e w i d t h m o d u l a t i o n m o d e ( 8 - b i t P W M ) T i m e r l o w o r d e r a d d r e s s f u n c t i o n s a s a n b i t p r e s c a l e r a n d h i g h o r d e r a d d r e s s f u n c t i o n s a s a n b i t p u l s e w i d t h m o d u l a t o r

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 58 Timer A-related registers (3) S y m b o lA d d r e s sW h e n r e s e t C P S R 6 0 X X X X X X C l o c k p r e s c a l e r r e s e t f l a g B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 C l o c k p r e s c a l e r r e s e t f l a g 0 : N o e f f e c t P r e s c a l e r i s r e s e t W h e n r e a d t h e v a l u e i s C P S R WR N o t h i n g i s a s s i g n e d . T h e s e b i t s c a n n e i t h e r b e s e t n o r r e s e t W h e n r e a d t h e i r c o n t e n t s a r e i n d e t e r m i n a t e T A 1 T G L S y m b o lA d d r e s sW h e n r e s e t T R G S 6 0 T i m e r A 1 e v e n t / t r i g g e r s e l e c t b i t 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T r i g g e r s e l e c t r e g i s t e r B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T i m e r A 2 e v e n t / t r i g g e r s e l e c t b i t T i m e r A 3 e v e n t / t r i g g e r s e l e c t b i t T i m e r A 4 e v e n t / t r i g g e r s e l e c t b i t WR T A 1 T G H T A 2 T G L T A 2 T G H T A 3 T G L T A 3 T G H T A 4 T G L T A 4 T G H b b b b b b b b N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o W h e n T A iI N i s s e l e c t e d T A iO U T a s s i g n e d o n s a m e p i n c a n n o t b e u s e d i t o T A 1 O S T A 2 O S T A 0 O S O n e - s h o t s t a r t f l a g S y m b o lA d d r e s sW h e n r e s e t O N S 6 0 X T i m e r A 0 o n e - s h o t s t a r t f l a g T i m e r A 1 o n e - s h o t s t a r t f l a g T i m e r A 2 o n e - s h o t s t a r t f l a g T i m e r A 3 o n e - s h o t s t a r t f l a g T i m e r A 4 o n e - s h o t s t a r t f l a g T A 3 O S T A 4 O S B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 N o t h i n g i s a s s i g n e d . T h i s b i t c a n n e i t h e r b e s e t n o r r e s e t W h e n r e a d t h e c o n t e n t i s i n d e t e r m i n a t e T A 0 T G L T A 0 T G H 0 0 : I n p u t o n T A N i s s e l e c t e d N o t e T B o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T A o v e r f l o w i s s e l e c t e d T i m e r A 0 e v e n t / t r i g g e r s e l e c t b i t b b N o t e : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . W h e n T A iI N i s s e l e c t e d T A iO U T a s s i g n e d o n s a m e p i n c a n n o t b e u s e d i t o WR 1 : T i m e r s t a r t W h e n r e a d t h e v a l u e i s

• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TAiIN pin function Programmable I/O port or gate input TAiOUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table16.) Figure 59 shows the timer Ai mode register in timer mode.

Table 16. Specifications of timer mode Figure 59. Timer Ai mode register in timer mode

60 shows the timer Ai mode register in event counter mode. Ai mode register in event counter mode. Table 17. Timer specifications in event counter mode (when not processing two-phase pulse signal)

• TB2 overflow, TAj overflow Count operation •Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, the reload register's content is reloaded and the timer starts over again.(Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function •Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. B i t n a m eF u n c t i o n T i m e r A i m o d e r e g i s t e r N o t e I n e v e n t c o u n t e r m o d e t h e c o u n t s o u r c e i s s e l e c t e d b y t h e e v e n t t r i g g e r s e l e c t b i t a d d r e s s e s a n d N o t e T h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d N o t e V a l i d o n l y w h e n c o u n t i n g a n e x t e r n a l s i g n a l N o t e W h e n a n L s i g n a l i s i n p u t t o t h e T A iO U T p i n t h e d o w n c o u n t i s a c t i v a t e d W h e n H t h e u p c o u n t i s a c t i v a t e d S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o S y m b o lA d d r e s sW h e n r e s e t T A i M R i 6 0 WR b 7b 6b 5b 4b 3b 2b 1b 0 O p e r a t i o n m o d e s e l e c t b i t E v e n t c o u n t e r m o d e ( N o t e b b T M O D 0 M R 0 P u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : P u l s e i s n o t o u t p u t T Ai O U T p i n i s a n o r m a l p o r t p i n P u l s e i s o u t p u t N o t e T Ai O U T p i n i s a p u l s e o u t p u t p i n C o u n t p o l a r i t y s e l e c t b i t N o t e M R 2 M R 1 M R 3 0 ( M u s t a l w a y s b e f i x e d t o “ 0 ” i n e v e n t c o u n t e r m o d e ) T C K 0 C o u n t o p e r a t i o n t y p e s e l e c t b i t 010 0 : C o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e C o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e U p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : U p / d o w n f l a g ' s c o n t e n t T Ai O U T p i n s i n p u t s i g n a l N o t e 0 : R e l o a d t y p e F r e e r u n t y p e B i t s y m b o l T C K 1 I n v a l i d i n e v e n t c o u n t e r m o d e C a n b e o r T M O D 1

Figure 60. Timer Ai mode register in event counter mode

• When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TAiIN pin function Two-phase pulse input TAiOUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A2, A3, or A4 register Write to timer •When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter
• When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) Select function •Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H”
• Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. Note: This does not apply when the free-run function is selected.

Table 18. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2,A3 and A4

N o t e 1 : T h i s b i t i s v a l i d f o r t i m e r A 3 m o d e r e g i s t e r . Figure 61. Timer Ai mode register in event counter m

• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Programmable I/O port or pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) (3) One-shot timer mode In this mode, the timer operates only once. (See Table 19.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 62 shows the timer Ai mode register in one-shot timer mode.

Table 19. Timer specifications in one-shot timer mode Figure 62. Timer Ai mode register in one-shot timer mode

modulator operates. Figure 65 shows the example of how an 8-bit pulse width modulator operates. Table 20. Timer specifications in pulse width modulation mode Figure 63. Timer Ai mode register in pulse width modulation mode

• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting 16-bit PWM •High level width n / fi n : Set value
• Cycle time (2 16-1) / fi fixed 8-bit PWM •High level width n X (m+1) / fi n : values set to timer Ai register’s high-order address
• Cycle time (28-1) X (m+1) / fi m : values set to timer Ai register’s low-order address Count start condition •External trigger is input
• The timer overflows
• The count start flag is set (= 1) Count stop condition •The count start flag is reset (= 0) Interrupt request generation timingPWM pulse goes “L” TAiIN pin function Programmable I/O port or trigger input TAiOUT pin function Pulse output Read from timer When timer Ai register is read, it indicates an indeterminate value Write to timer •When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) T i m e r A i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T A i M R i t o t o 6 0 B i t n a m eF u n c t i o nB i t s y m b o l b 7 b 3 b O p e r a t i o n m o d e s e l e c t b i t 1 1 : P W M m o d e b 1 b 0 T M O D 1 T M O D 0 M R 0 M R 2 M R 1 M R 3 0 0 : f1 fC b 7 b 6 T C K 1 T C K 0 C o u n t s o u r c e s e l e c t b i t WR 111 1 ( M u s t a l w a y s b e f i x e d t o “ 1 ” i n P W M m o d e ) 1 6 / 8 - b i t P W M m o d e s e l e c t b i t 0 : F u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r F u n c t i o n s a s a n b i t p u l s e w i d t h m o d u l a t o r T r i g g e r s e l e c t b i t E x t e r n a l t r i g g e r s e l e c t b i t N o t e 0 : F a l l i n g e d g e o f T A iI N p i n ' s i n p u t s i g n a l ( N o t e 2 ) R i s i n g e d g e o f T A iI N p i n s i n p u t s i g n a l N o t e 0 : C o u n t s t a r t f l a g i s v a l i d S e l e c t e d b y e v e n t t r i g g e r s e l e c t r e g i s t e r N o t e 1 : V a l i d o n l y w h e n t h e T Ai I N p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t a d d r e s s e s a n d I f t i m e r o v e r f l o w i s s e l e c t e d t h i s b i t c a n b e o r N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o

Figure 68. Timer B-related registers (2)

• P u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e M e a s u r e s a p u l s e p e r i o d o r w i d t h
• T i m e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s t h e t i m e r s p e r i o d F u n c t i o n V a l u e s t h a t c a n b e s e t
• E v e n t c o u n t e r m o d e0 0 0 01 6 t o F F F F1 C o u n t s e x t e r n a l p u l s e s i n p u t o r a t i m e r o v e r f l o w N o t e R e a d a n d w r i t e d a t a i n b i t u n i t s N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e

• When the timer underflows, the reload register's content is reloaded and the timer starts over again. Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 21.) Figure 69 shows the timer Bi mode register in timer mode.

Table 21. Timer specifications in timer mode Figure 69. Timer Bi mode register in timer mode I n v a l i d i n t i m e r m o d e .

Figure 70. Timer Bi mode register in event counter mode shows the timer Bi mode register in event counter mode. Table 22. Timer specifications in event counter mode

• Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation •Counts down
• When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer •When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) T i m e r B i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T B i M R i t o t o D 1 6 0 X X B i t n a m eF u n c t i o nB i t s y m b o l WR b O p e r a t i o n m o d e s e l e c t b i t 0 1 : E v e n t c o u n t e r m o d e b b T M O D 1 T M O D 0 M R 0C o u n t p o l a r i t y s e l e c t b i t N o t e M R 2 M R 1 M R 3 I n v a l i d i n e v e n t c o u n t e r m o d e . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d i n e v e n t c o u n t e r m o d e t u r n s o u t t o b e i n d e t e r m i n a t e T C K 1 T C K 0 0 0 : C o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s C o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e s C o u n t s e x t e r n a l s i g n a l s f a l l i n g a n d r i s i n g e d g e s I n h i b i t e d b b N o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e N o t e 1 : V a l i d o n l y w h e n i n p u t f r o m t h e T B iI N p i n i s s e l e c t e d a s t h e e v e n t c l o c k . I f t i m e r s o v e r f l o w i s s e l e c t e d t h i s b i t c a n b e o r N o t e T i m e r B N o t e T i m e r B t i m e r B N o t e S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o I n v a l i d i n e v e n t c o u n t e r m o d e . C a n b e o r E v e n t c l o c k s e l e c t 0 : I n p u t f r o m T B iI N p i n ( N o t e 4 ) T B j o v e r f l o w j i h o w e v e r j w h e n i 0 ( F i x e d t o “ 0 ” i n e v e n t c o u n t e r m o d e ; i = 0 ) ( N o t e 2 ) ( N o t e 3 )

Figure 75. Block diagram of transmit/receive unit

Figure 76. Serial I/O-related registers (1) 03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

Figure 77. Serial I/O-related registers (2)

Figure 78. Serial I/O-related registers (3)

• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM Invalid Invalid Invalid CLK/CLKS select bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Reserved bit Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.

Table 24. Specifications of clock synchronous serial I/O mode

• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016, 03A816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at address 03A016, 03A816 =“1”) : Input from CLKi pin (Note 2)
• CTS function/ RTS function/ CTS,RTS function chosen to be invalid
• To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”_______ _______ _ When CTS function is selected, CTS input level = "L"
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 03A516, 03AD16) = “1” _ Transmit enable bit (bit 0 at address 03A516, 03AD16) = “1” _ Transmit buffer empty flag (bit 1 at address 03A516, 03AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at address 03A416, 03AC16) = “1”: CLKi input level = “L”
• When transmitting _ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0,1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
• Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi re- ceive buffer register are read out
• CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected
• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection UART1 transfer clock can be set 2 pins, and can be selected to output from which pin. Note 1: “n” denotes the value 00 16 to FF16 that is set to the UART bit rate generator. Note 2: Maximum 5 Mbps. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. Item Transfer data format Transfer clock Transmission/reception control Transmission start condi- tion Reception start condition Interrupt request generation timing Error detection Select function

Figure 79. UARTi transmit/receive mode register in clock synchronous serial I/O mode (i=0,1) Table 25. Input/output pin functions in clock synchronous serial I/O mode (i=0,1)

Figure 80. Typical transmit/receive timings in clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 T c TC L K S t o p p e d p u l s i n g b e c a u s e t r a n s f e r e n a b l e b i t = “ 0 ” D a t a i s s e t i n U A R T i t r a n s m i t b u f f e r r e g i s t e r T c = TC L K = 2 ( n + 1 ) / f i f i f r e q u e n c y o f B R G i s c o u n t s o u r c e f1, f8, n v a l u e s e t t o B R G i T r a n s f e r c l o c k T r a n s m i t e n a b l e b i t T E T r a n s m i t b u f f e r e m p t y f l a g T l C L K i T x D i T r a n s m i t r e g i s t e r e m p t y f l a g T X E P T “ H ” “ L ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” C T S i S h o w n i n ( ) a r e b i t s y m b o l s . T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s I n t e r n a l c l o c k i s s e l e c t e d C T S f u n c t i o n i s s e l e c t e d C L K p o l a r i t y s e l e c t b i t T r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t T r a n s m i t i n t e r r u p t r e q u e s t b i t I R ) “ 0 ” “ 1 ” C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . S t o p p e d p u l s i n g b e c a u s e C T S = “ H ” 1 / fE X T D u m m y d a t a i s s e t i n U A R T i t r a n s m i t b u f f e r r e g i s t e r T r a n s m i t e n a b l e b i t T E T r a n s m i t b u f f e r e m p t y f l a g T l C L K i R x D i R e c e i v e c o m p l e t e f l a g R l R T S i “ H ” “ L ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” “ 0 ” “ 1 ” R e c e i v e e n a b l e b i t R E ) “ 0 ” “ 1 ” R e c e i v e d a t a i s t a k e n i n T r a n s f e r r e d f r o m U A R T i t r a n s m i t b u f f e r r e g i s t e r t o U A R T i t r a n s m i t r e g i s t e r R e a d o u t f r o m U A R T i r e c e i v e b u f f e r r e g i s t e r S h o w n i n ( ) a r e b i t s y m b o l s . T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s E x t e r n a l c l o c k i s s e l e c t e d R T S f u n c t i o n i s s e l e c t e d C L K p o l a r i t y s e l e c t b i t fE X T: f r e q u e n c y o f e x t e r n a l c l o c k T r a n s f e r r e d f r o m U A R T i r e c e i v e r e g i s t e r t o U A R T i r e c e i v e b u f f e r r e g i s t e r R e c e i v e i n t e r r u p t r e q u e s t b i t I R ) “ 0 ” “ 1 ” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 T r a n s f e r r e d f r o m U A R T i t r a n s m i t b u f f e r r e g i s t e r t o U A R T i t r a n s m i t r e g i s t e r C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . M e e t t h e f o l l o w i n g c o n d i t i o n s w h e n t h e C L K i n p u t b e f o r e d a t a r e c e p t i o n H T r a n s m i t e n a b l e b i R e c e i v e e n a b l e b i D u m m y d a t a w r i t e t o U A R T i t r a n s m i t b u f f e r r e g i s t e r

function is selected, CTS/RTS function of UART1 cannot be used. Figure 83. The transfer clock output from the multiple pins function usage performed only in clock synchronous serial I/O mode.

Table 26. Specifications of clock synchronous serial I/O mode

• Start bit: 1 bit
• Parity bit: Odd, even or nothing as selected
• Stop bit: 1 bit or 2 bits as selected Transfer clock •When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT /16(n+1) (Note 1) (Note 2) Transmission/reception control
• CTS function/RTS function/CTS, RTS function chosen to be invalid Transmission start condition•To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A5 16, 03AD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”_______ _______ - When CTS function is selected, CTS input level = “L” Reception start condition •To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1” - Start bit detection Interrupt request •When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B0 16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B0 16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
• When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection •Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
• Framing error This error occurs when the number of stop bits set is not detected
• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function •Sleep mode selection This mode is used to transfer data to and from one of multiple slave microcomputers Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”.

Table 27. Input/output pin functions in UART mode (i=0,1) Figure 84. UARTi transmit/receive mode register in UART mode

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 85. Typical transmit timings in UART mode C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . T h e t r a n s f e r c l o c k s t o p s m o m e n t a r i l y a s C T S i s “ H ” w h e n t h e s t o p b i t i s c h e c k e d . C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d .

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 86. Typical receive timing in UART mode C l e a r e d t o “ 0 ” b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.

active or “L” active for active logic.

• 8-bit serial I/O mode (non-automatic transfer)
• Automatic transfer serial I/O mode
• Transfer data length: 8 bits
• Full duplex mode / transmit-only mode selected by bit 5 at address 034216
• When internal clock is selected (bit 2 at address 034216 = “0”) : selected by bits 5 to 7 at address 034816
• When external clock is selected (bit 2 at address 034216 = “1”) : Input from SCLK21 pin, SCLK22 pin(Note 2)
• When internal clock is selected : f(XIN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32, f(XIN)/64, f(XIN)/128, f(XIN)/256
• When external clock is selected : input cycle 0.95 µs or less
• SSTB2 output / SBUSY2 input or output / SRDY2 input or output chosen
• To start transmission / reception, the following requirements must be met: _ Serial I/O initialization bit (bit 4 at address 034216) = “1” _ When SBUSY2 input, or SRDY2 input is selected : selected input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met: _ Input level of SCLK21 or SCLK22 = “H”
• To stop transmission and reception, set serial I/O initialization bit (bit 4 at address 034216) to “0” regardless internal clock and external clock.
• 8-bit serial I/O mode : Interrupts requested when 8-bit data transfer is com- pleted
• Automatic transfer serial I/O mode :Interrupts requested when last receive data transfer to Automatic transfer RAM
• SOUT2 P-channel output disable function CMOS output or N-channel open-drain output can be selected
• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Serial I/O2 clock pin select bit Serial clock input/output can be selected; S CLK21 or SCLK22
• SBUSY output, SSTB2 output select function (only automatic transfer serial mode) SBUSY output, SSTB2 output can be selected; 1-byte data transfer unit or all data transfer unit
• SOUT2 pin control bit Either output active or high-impedance can be selected as a SOUT2 pin state at serial non-transfer . Note 1: It is necessary to set the serial I/O clock pin select bit ( bit 7 at address 034216) Item Serial mode Transfer data format Transfer clock Transfer rate Transmission/reception control Transmission / reception start condition Transmission and reception stop condition Interrupt request generation timing Select function

Table 28. Specifications of clock synchronous serial I/O2

Figure 87. Block Diagram of Serial I/O2

Figure 88. Serial I/O2 Control Registers 1, 2

2 P - c h a n n e l o u t p u t

Figure 89. Serial I/O2 automatic transfer data pointer

• Automatic transfer data pointer set Specify the low-order 8 bits of the first data store address on the serial I/O automatic transfer RAM. Data is written into the latch and read from the decrement counter. Serial I/O2 register/transfer counter Symbol Address When reset SIO2 0346 16 0016 Function R W b7 b6 b5 b4 b3 b2 b1 b0
• Number of automatic transfer data set Set the number of automatic transfer data. Set a value one less than number of transfer data. Data is written into the latch and read from the decrement counter.

Table 29. Functions of the serial I/O2 input/output pins SOUT2 pin control bit (bit 6 of address 034416). pin into a high-impedance state. automatically reset to “0” and put into an output active state.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Serial I/O2 Mode There are two types of serial I/O2 modes: 8-bit serial I/O mode where automatic transfer RAM is not used, and an automatic transfer serial I/O mode. (1) 8-bit Serial I/O Mode Address 034616 is assigned to the serial I/O2 register. When the internal synchronous clock is selected, a serial transfer of the 8-bit serial I/O is started by a write signal to the serial I/O2 register (address 0346 16). The serial transfer status flag (bit 5 of address 034416) is set to “1” by writing into the serial I/O2 register and reset to “0” after completion of 8-bit transfer. At the same time, a serial I/O2 interrupt request occurs. If the transfer is completed, the receive data is read out from serial I/O2 register. When the external synchronous clock is selected, the contents of the serial I/O2 register are con- tinuously shifted while transfer clocks are input to S CLK21 or SCLK22 . Therefore, the clock needs to be controlled externally. (2) Automatic Transfer Serial I/O Mode Address 034616 is assigned to the transfer counter (1-byte units). The serial I/O2 automatic trans- fer controller controls the write and read operations of the serial I/O2 register. The serial I/O auto- matic transfer RAM is mapped to addresses 00400 16 to 004FF16. Before starting transfer, make sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is set to the automatic transfer data pointer (address 0340 16). When the internal synchronous clock is selected, the transfer interval is inserted between one data and another in the following cases: 1. When using no handshake signal 2. When using the S RDY2 output, SBUSY2 output, and SSTB2 output of the handshake signal inde pendently 3. When using a combination of S RDY2 output and SSTB2 output or a combination of SBUSY2 output and SSTB2 output of the handshake signal The transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval set bit (bits 0–4 of address 0348 16 ). Also, when using SBUSY2 output as a signal for each occurrence of the all transfer data, a transfer interval is inserted before the system starts sending or receiving the first data and after the system finished sending or receiving the last data, not just between one data and another. Furthermore, when using S STB2 output, the transfer interval between each 1-byte data is extended by 2 cycles from the set value no matter how the SBUSY2 output. SSTB2 output function select bit (bit 4 of address 034416) is set. When using SBUSY2 output and SSTB2 output in combination as a signal for each occurrence of the all transfer data, the transfer interval after the system finished sending or receiving the last data is extended by 2 cycles from the set value. When an external synchronous clock is selected, the automatic transfer interval is disabled.

Figure 90. Automatic Transfer Serial I/O Operation system clock before the transfer clock is input after writing to the transfer counter. a rise of clock at the last bit of one-byte data. written into the automatic transfer RAM. At the same time, a serial I/O2 interrupt request occurs. interval set bits (bit 0 to bit 4 of address 034816) are held in the latch.

There are five types of handshake signal : SSTB2 output, SBUSY2 input/output, and SRDY2 input/output. (bits 2, 3 of address 034216=11), or the SSTB2 output goes to “H” (bits 2, 3 of address 034216=10). output from SOUT2 , SSTB2 output is “H” (or SSTB2 output is “L”) in the period of 1 cycle of the transfer clock. Furthermore, after 1 cycle, the serial transfer status flag (bit 5 of address 034416) is reset to “0”. select bit (bit 4 of address 034416). Figure 91. SSTB2 Output Operation

• Serial operation used SSTB2 output Operation mode : 8-bit serial I/O mode Transfer clock : Internal synchronous clock SSTB2 output timing : Each 1-byte data Internal clock Serial transfer status flag (bit 5 at address 034416) SCLK2i (i=1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816
• Serial operation used SSTB2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock SSTB2 output timing : Each transfer of all data Internal clock Serial transfer status flag (bit 5 at address 034416) SCLK2i (i=1, 2)(output) SSTB2 (output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816

Figure 96. SBUSY2 Output Operation (3)

• Serial operation used SBUSY2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock SBUSY2 output timing : Each 1-byte data Serial transfer status flag (bit 5 at address 034416) SCLK2i (i = 1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 SBUSY2 (output) Internal clock "1" "0" "H" "L" D 0 Tc D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 Automatic transfer interval Automatic transfer RAM Serial I/O2 register Serial I/O2 register Automatic transfer RAM
• Serial operation used SBUSY2 output Operation mode : Automatic transfer serial I/O mode Transfer clock : Internal synchronous clock SBUSY2 output timing : Each transfer of all data Serial transfer status flag (bit 5 at address 034416) SCLK2i (i = 1, 2)(output) SOUT2 Tc : Internal synchronous clock is selected by bits 5 to 7 of address 034816 SBUSY2 (output)

• With sample and hold function (8-bit resolution) ±2LSB
• Without sample and hold function (10-bit resolution) ±3LSB VCC = 3V • Without sample and hold function (8-bit resolution)(Note 3) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN 0 to AN7) A-D conversion start condition•Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” Conversion speed per pin •Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the φAD frequency to 250kHz min. With the sample and hold function, set the φAD frequency to 1MHz min. Note 3: Only mask ROM version. A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P10 0 to P107 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from V REF , reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 30 shows the performance of the A-D converter. Figure 101 shows the block diagram of the A-D converter, and Figures 102 and 103 show the A-D converter-related registers.

Table 30. Performance of A-D converter

Figure 101. Block diagram of A-D converter

Figure 102. A-D converter-related registers (1)

Figure 103. A-D converter-related registers (2)

0 Without sample and hold

1 With sample and hold

• During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
• During 8-bit mode When read, the content is indeterminate Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

31 shows the specifications of one-shot mode. Figure 104 shows the A-D control register in one-shot mode. Table 31. One-shot mode specifications

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected Reading of result of A-D converterRead A-D register corresponding to selected pin

Figure 104. A-D conversion register in one-shot mode

32 shows the specifications of repeat mode. Figure 105 shows the A-D control register in repeat mode. Table 32. Repeat mode specifications Figure 105. A-D conversion register in repeat mode

register in single sweep mode. Table 33. Single sweep mode specifications

• Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converterRead A-D register corresponding to selected pin

Figure 106. A-D conversion register in single sweep mode

control register in repeat sweep mode 0. Table 34. Repeat sweep mode 0 specifications Figure 107. A-D conversion register in repeat sweep mode 0

108 shows the A-D control register in repeat sweep mode 1. Table 35. Repeat sweep mode 1 specifications Figure 108. A-D conversion register in repeat sweep mode 1

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (a) Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, 28 φ AD cycles are achieved with 8-bit resolution and 33 φ AD cycles with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. Table 36. Performance of D-A converter Figure 109. Block diagram of D-A converter

puter uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. pleted in two machine cycles. Figure 112 shows the block diagram of the CRC circuit. Figure 113 shows the CRC-related registers. Figure 113. CRC-related registers Figure 112. Block diagram of CRC circuit

Figure 114. Calculation example using the CRC calculation circuit conformity with the modulo-2 operation. operation. Also switch between the MSB and LSB of the result as stored in CRC data.

Figure 115. Programmable I/O ports (1)

Figure 116. Programmable I/O ports (2)

Figure 119. Pull-up control register read, turns out to be indeterminate. read, turns out to be indeterminate.

Table 37. Example connection of unused pins Figure 120. Example connection of unused pins Note 1: With external clock input to XIN pin. Note 2: In case of pull-down option is specified, leave the specified ports open. Note 3: Connect a bypass capacitor. Note 1: In case of pull-down option is specified, leave the specified ports (port P3, P4) open. Note 2: Connect a bypass capacitor.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456789012 3 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567890123 MASK OPTION OF PULL-DOWN RESISTOR (object product: mask ROM version) Whether built-in pull-down resistors are connected or not to high-breakdown voltage ports P20 to P27, P30 to P37,and P40 to P43 can be specified in ordering mask ROM. The option type can be specified from among 7 types; A to G. A B C D E F G

0 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42

Note 1: The electrical characteristics of high-breakdown voltage ports P20 to P27, P30 to P37, and P40 to P43’s built-in pull-down resistors are the same as that of high-breakdown voltage ports P00 to P07. Note 2: The absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. After calculating the power dissipation, specify the option type. Note 3: The option types B to G cannot be specified because these types are currently under development. Power Dissipation Calculating Method (Fixed number depending on microcomputer’s standard)

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value = 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW (Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a X c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA) (1) Digit pin power dissipation {h X b X (1–Toff / Tdisp) X voltage} / a (2) Segment pin power dissipation {i X d X (1–Toff / Tdisp) X voltage} / a (3) Pull-down resistor power dissipation (digit) {power dissipation per 1 digit X (b X f / b) X (1–Toff / Tdisp) } / a (4) Pull-down resistor power dissipation (segment) {power dissipation per 1 segment X (d X g / c) X (1–Toff / Tdisp) } / a (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190 mW

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 X 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 X 16 X (1–1/16) X 2} / 17 = 31.77 mW (2) Segment pin power dissipation {3 X 31 X (1–1/16) X 2} / 17 = 10.26 mW (3) Pull-down resistor power dissipation (digit) (50 – 2) 2 /68 X (16 X 16/16) X (1 – 1/16) / 17 = 29.90 mW (4) Pull-down resistor power dissipation (segment) (50 – 2)2 /68 X (31 X 20/20) X (1 – 1/16) / 17 = 57.93 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW DIG0 DIG1 DIG2 DIG3 DIG13 DIG14 DIG15 Timing number 12 3 1 6 1 7 1514 Tscan Repeat cycle

Figure 121. Digit timing waveform (1)

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation {18 X 12 X (1–1 / 16) X 2} / 11 = 36.82 mW (2) Segment pin power dissipation {3 X 114 X (1–1 / 16) X 2} / 11 = 58.30 mW (3) Pull-down resistor power dissipation (digit) (50– 2) 2 / 68 X (12 X 10 / 12) X (1 – 1 / 16) / 11 = 28.88 mW (4) Pull-down resistor power dissipation (segment) (50 – 2)2 / 68 X (114 X 22 / 24) X (1 – 1 / 16) / 11 = 301.77 mW (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW (1) + (2)+ (3) + (4) + (5) = 615.77 mW (There is a limit of use temperature) DIG0 DIG1 DIG2 DIG3 DIG7 DIG8 DIG9 Timing number 12 3 4 567 8 91 0 1 1 DIG4 DIG5 DIG6 Tscan Repeat cycle

Figure 122. Digit timing waveform (2)

• VOH output fall voltage of high-breakdown port 2 V (max.); | Current value | = at 18 mA
• Resistor value 68 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V X 38 mA = 190 mW Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 50 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114 ( for Toff invalid waveform;50)
• All segment number during repeat cycle: 264 (= 11 X 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA) (1) Digit pin power dissipation [{18 X 10 X (1–1/16) X 2} + {18 X 2 X 2}] / 11 = 37.23 mW (2) Segment pin power dissipation [{3 X 64 X (1–1/16) X 2} + {3 X 50 X 2}] / 11 = 60.00 mW (3) Pull-down resistor power dissipation (digit) [{(50– 2) (4) Pull-down resistor power dissipation (segment) (5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 190.00 mW (1) + (2)+ (3) + (4) + (5) = 627.02 mW (There is a limit of use temperature)

Figure 123. Digit timing waveform (3)

Electrical characteristics

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Table 38. Absolute maximum ratings Note 1: When writing to flash ,only CNVss is –0.3 to 13 (V) . Note: VCC = 4.0V to 5.5V in flash memory version. Table 39. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Table 40. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = – 20 to average value measured over 100ms. The total peak current is the peak of all the currents. Note 2: The peak output current is the peak current flowing in each port. Note 3: The average output current in an average value measured over 100ms. Note 4: When the oscillating frequency has a duty cycle of 50 %. Note 6: VCC =4.0V to 5.5V in flash memory version. Note 7: Relationship between main clock oscillation frequency and supply voltage.

Table 41. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, Note 1: Except when reading ports P3, P40 to P43. Note 2: Fixed XCIN-XCOUT drive capacity select bit to “HIGH” and XIN pin to “H” level. Note 3: This contains an electric current to flow into AVCC pin.

Table 42. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V Table 43. D-A conversion characteristics (referenced to VCC = 5V, VSS = AVSS = 0V, VREF = 5V The A-D converter's ladder resistance is not included.

Table 44. External clock input Table 45. High-breakdown voltage p-channel open-drain output port Symbol StandardMeasuring condition Max.Typ.Parameter Unit Min. Note 1: When bit 7 of the FLDC mode register (address 035016) is at “0”. Note 2: When bit 7 of the FLDC mode register (address 035016) is at “1”. Note: Ports P2, P3, and P40 to P43 need external resistors in mask ROM version. 0 to P43 need external resistors in flash memory version. Figure 124. Circuit for measuring output switching characteristics

Table 46. Timer A input (counter input in event counter mode) Table 47. Timer A input (gating input in timer mode) Table 48. Timer A input (external trigger input in one-shot timer mode) Table 49. Timer A input (external trigger input in pulse width modulation mode) Table 50. Timer A input (up/down input in event counter mode)

Table 52. Timer B input (pulse period measurement mode) Table 51. Timer B input (counter input in event counter mode) Table 53. Timer B input (pulse width measurement mode) Table 54. Serial I/O Table 55. External interrupt INTi inputs Table 56. Automatic transfer serial I/O

Timing (VCC =5V) VCC =5V M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R tsu(D-C) TAiIN input TAiOUT input During event counter mode TBiIN input CLK i TxD i RxD i tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) SOUT SIN SCLK 0.2VCC td(SCLK-SOUT) 0.2VCC 0.8VCC 0.8VCC tSU(SiN-SCLK) th(SCLK-SiN) tV(SCLK-SOUT) tWL(SCLK) tWH(SCLK)tf(SCLK) tC(SCLK) tr

Table 57. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, Note 1: Except when reading ports P3, P40 to P43. Note 2: With one timer operated using fC32 . Note 3: This contains an electric current to flow into AVCC pin.

Table 58. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, Vss = AVSS = 0V Table 59. D-A conversion characteristics (referenced to VCC = 3V, VSS = AVSS = 0V, VREF = 3V Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.

Table 60. External clock input

Table 61. Timer A input (counter input in event counter mode) Table 62. Timer A input (gating input in timer mode) Table 63. Timer A input (external trigger input in one-shot timer mode) Table 64. Timer A input (external trigger input in pulse width modulation mode) Table 65. Timer A input (up/down input in event counter mode)

Table 67. Timer B input (pulse period measurement mode) Table 66. Timer B input (counter input in event counter mode) Table 68. Timer B input (pulse width measurement mode) Table 69. Serial I/O Table 70. External interrupt INTi inputs Table 71. Automatic transfer serial I/O

Timing(VCC =3V, only mask ROM version) VCC =3V M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R tsu(D-C) TAiIN input TAiOUT input During event counter mode TBiIN input CLK i TxD i RxD i tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) INTi input td(C-Q) th(C-D) th(C-Q) th(TIN-UP) tsu(UP-TIN) TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) TAiOUT input (Up/down input) SOUT SIN SCLK 0.2VCC td(SCLK-SOUT) 0.2VCC 0.8VCC 0.8VCC tSU(SiN-SCLK) th(SCLK-SiN) tV(SCLK-SOUT) tWL(SCLK) tWH(SCLK)tf(SCLK) tC(SCLK) tr

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect Performance 4.0V to 5.5 V (f(XIN)=10MHz) VPP =12V ± 5% (f(XIN)=10MHz) Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.AA.3. One division (3.5 K bytes) (Note) In units of byte Collective erase / block erase Program/erase control by software command 6 commands 100 times Standard serial I/O mode is supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area VCC =5V ± 10% (f(XIN)=10MHz) Table 72. Outline Performance of the M30218 group (flash memory version) Table 72 shows the outline performance of the M30218 group (flash memory version).

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Flash Memory The M30218 group (flash memory version) contains the NOR type of flash memory that requires a high- voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device operation. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Pro- cessing Unit (CPU). Each mode is detailed in the pages to follow. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure 125. Block diagram of flash memory version Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. when this address input is low.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 125 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low (VSS ). In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P52 pin high (VCC ), the CNVSS pin high(VPPH ), the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. CPU rewrite mode operation procedure The internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the CPU to the flash memory control register (addresses 03B4 16, 03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom- plished, a CPU write control program must be written into the boot ROM area in parallel input/output mode. The following shows a CPU rewrite mode operation procedure. <Start procedure (Note 1)> (1) Apply VPP H to the CNVSS /VPP pin and VCC to the port P46 pin for reset release. Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program. In this case, set the CPU write mode select bit of the flash memory control register to “1” before applying V PP H to the CNVSS /VPP pin. (2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump to this control program in RAM. (The operations described below are controlled by this program.) (3) Set the CPU rewrite mode select bit to “1”. (4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled. (5) Execute operation on the flash memory by writing software commands to the flash command regis- ter. Note 1: In addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and writing to the watchdog timer. <Clearing procedure> (1) Apply VSS to the CNVSS /VPP pin. (2) Set the CPU rewrite mode select bit to “0”.

5 MHz or less when wait bit (bit 7 at address 0005

10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)(Note 1)

• CPU, ROM, RAM, timer, UART, SI/O2(non-automatic transfer), port In case of setting internal access wait state, refer to the following explain (software wait). Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16) (Note 2). A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit. Table 73 shows the software wait and bus cycles. Figure 128 shows example bus timing when using software waits. Note 2: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to “1”. Area Wait bit Bus cycle 1 2 BCLK cycles SFR Internal ROM/RAM 0 1 BCLK cycle Invalid 2 BCLK cycles

Table 73. Software waits and bus cycles

Figure 128. Typical bus timings using software wait

Table 74 lists the software commands available with the M30218 group (flash memory version). the operation to erase or program. The content of each software command is explained below. Table 74. List of Software Commands (CPU Rewrite Mode) The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. passes. See Figure 129 for an example of a programming flowchart.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” to the flash command register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. The CPU compares this read data with the data that it previously wrote to the address using the program command. If the compared data do not match, the user need to execute the program and program-verify operations one more time. Erase command (20 16 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. During erase operation, the watchdog timer remains idle, with the value “7FFF16 set in it. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure 129 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” to the flash command register in the first bus cycle. When the user execute an instruction to read byte data from the address to be verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out. The CPU must sequentially erase-verify memory contents one address at a time, over the entire area erased. If any address is encountered whose content is not “FF 16” (not erased), the CPU must stop erase-verify at that point and execute erase and erase-verify operations one more time. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

Figure 129. Program and erase execution flowchart in the CPU rewrite mode command is disabled, with the flash memory placed in read mode.

Appendix Standard Serial I/O Mode M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Pin Description VCC ,VSS Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin. CNV SS Apply 12V ± 5 % to this pin. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT AV CC , AVSS VREF Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. P00 to P07 Output exclusive use pin. P10 to P17 Output exclusive use pin. P20 to P27 Output exclusive use pin. P30 to P37 Input "H" or "L" level signal or open. P40 to P43 Input "H" or "L" level signal or open. P44 Serial data output pin. P45 P46 Serial clock input pin. P47 P50 to P57 Output exclusive use pin. Name Power input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input Output port P0 Output port P1 Output port P2 Input port P3 Input port P4 TxD output SCLK input BUSY output Output port P5 I/O I I I O I O O O I I I I O O RxD input Serial data input pin. O BUSY signal output pin. P60 to P67 Output exclusive use pin. P70 to P77 Input "H" or "L" level signal or open. Output port P6 Input port P7 O I P80 to P87 Input "H" or "L" level signal or open.Input port P8 I P90 to P97 Input "H" or "L" level signal or open.Input port P9 I P100 to P107 Input "H" or "L" level signal or open.Input port P10 I Pin functions (Flash memory standard serial I/O mode)

Figure 130. Pin connections for serial I/O mode (1)

Appendix Standard Serial I/O Mode M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Standard Serial I/O Mode The standard serial I/O mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific serial programmer. The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard serial I/O mode is started by clearing the reset with V PPH at the CNVss pin. (For the normal microprocessor mode, set CNVss to “L”.) This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used. Figure 130 shows the pin connections for the standard serial I/O mode. Serial data I/O uses three UART0 pins: CLK 0, RxD0, TxD0, and RTS0 (BUSY). The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs the CMOS signal. The RTS0 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level when the reception operation starts. Transmission and reception data is transferred serially in 8-byte blocks. In the standard serial I/O mode, only the user ROM area shown in Figure 125 can be rewritten, the boot ROM area cannot. The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code does not match the content of the flash memory, the command sent from the programmer is not accepted. Function Overview (Standard Serial I/O Mode) In the standard serial I/O mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O (UART0) . In reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the CLK 0 pin and input into the flash memory via the RxD0 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the TxD 0 pin. The TxD0 pin is CMOS output. Transmission is in 8-bit blocks and LSB first. When busy, either during transmission or reception, or while executing an erase operation or program, the RTS 0 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the RTS0 (BUSY) pin is “L” level. Also, data in memory and the status register can be read after inputting a software command. It is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. Software commands and the status register are explained here following.

Table 75. Software commands (Standard serial I/O mode)

1 Page read

2 Page program

3 Bclock ease

4 Erase all unlocked blocks

5 Read status register

6 Clear status register

7 Read lockbit status

8 ID check function

9 Download function

10 Version data output function

11 Boot area output function

transferred from the serial programmer to the flash memory microcomputer. Note2: SRD refers to status register data. SRD1 refers to status register 1 data. Note3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Send the “20 16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) Send the verify command code “D016” in the 4th byte of the transmission. With the verify com- mand code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A 16 to A23. When block erasing ends, the RTS0 (BUSY) signal changes from the “H” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. Figure 135.Timing for block erasing A8 to A15 A16 to A232016 D0 16 CLK0 RxD0 TxD0 RTS0(BUSY)

16” command code in the 1st byte of the transmission. (2) Send the program size in the 2nd and 3rd bytes of the transmission. (4) The program to execute is sent in the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. Figure 138. Timing for download

16). Also, the status register is cleared by writing the clear status register command (5016). Table 76. Status register (SRD) “1” when the operation ends. to “1”. When the erase status is cleared, it is set to “0”. to “1”. When the program status is cleared, it is set to “0”.

check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). the flag status is maintained even after the reset. Table 77. Status register 1 (SRD1) tion using the download function.

cording to programmer, therefore see the programmer manual for more information. more information, see the programmer manual. Figure 143. Example circuit application for the standard serial I/O mode

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R QFP100-P-1420-0.65 1.58 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 100P6S-A Plastic 100pin 145 20mm body QFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.35 ––I2 1.3 ––M D 14.6 ––M E 20.6 10°0° 0.1 1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F 100 x – – 0.13 b x M

Peripheral Functions Usage

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.1.2 Protect Operation

The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write-enabled state. (2) The contents of system clock control register 0 and that of system clock control register 1 are changed. (3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write-inhibited state. (4) To change the contents of processor mode register 0 and that of processor mode register 1, follow the same steps as in dealing with system clock control registers. Operation

2.1.1 Overview

'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by the protect function The registers affected by the protect function are: (a) System clock control registers 0, 1 (addresses 000616 and 000716) (b) Processor mode registers 0, 1 (addresses 000416 and 000516) The values in registers (1) through (2) cannot be changed in write-protect state. To change values in the registers, put the individual registers in write-enabled state. (2) Protect register Figure 2.1.1 shows protect register.

2.1 Protect

Figure 2.1.1. Protect register P r o t e c t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P R C 6 X X X X X B i t n a m eB i t s y m b o l b 0 : W r i t e - i n h i b i t e d W r i t e e n a b l e d P R C 1 P R C 0 E n a b l e s w r i t i n g t o p r o c e s s o r m o d e r e g i s t e r s a n d a d d r e s s e s a n d F u n c t i o n 0 : W r i t e - i n h i b i t e d W r i t e e n a b l e d E n a b l e s w r i t i n g t o s y s t e m c l o c k c o n t r o l r e g i s t e r s a n d a d d r e s s e s a n d WR N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.1.2. Set-up procedure for protect function (1) Clearing the protect (set to write-enabled state) Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled b7 b0 (3) Setting the protect (set to write-inhibited state) Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited b7 b0 Setting system clock control register i (i = 0, 1)(2)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.2.1 Overview

The following is an overview for timer A, a 16-bit timer. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. (b) Event counter mode This mode counts the pulses from the outside and the number of underflows in other timers. The free-run type, in which nothing is reloaded from the reload register, can be selected when an under- flow occurs. The pulse output function can also be selected. Please refer to the timer mode expla- nation for details, as the operation is identical. Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count or down count in the event counter mode, depending on the phase of the two input signals. (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. Please refer to the one-shot timer mode explanation for details, as the operation is identical.

2.2 Timer A

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (2) Count source The internal count source can be selected from f1, f8, f32, and fC32 . Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32. (3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [FFFF 16 - the set value + 1] becomes the frequency division ratio when an up count is performed. In one-shot timer mode, the value set in the timer register be- comes the frequency division ratio. The counter overflows (or underflows) when a count source equal to a frequency division ratio is input, and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the port register does not vary). (4) Reading the timer Either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation mode is indeterminate. (5) Writing to the timer To write to the timer register when a count is in progress, the value is written only to the reload register. When writing to the timer register when a count is stopped, the value is written both to the reload register and to the counter. Write a value in 16-bit units. (6) Relation between the input/output to/from the timer and the direction register With the output function of the timer, pulses are output regardless of the direction register of the relevant port. To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer A (a) TA0 IN, TA1IN, TA2IN, TA3IN, TA4IN Input pins to timer A. (b) TA0 OUT , TA1OUT , TA2OUT , TA3OUT , TA4OUT Output pins from timer A. They become input pins to timer A when event counter mode is active. (8) Registers related to timer A timer A-related registers.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.3. Timer A-related registers (2) Symbol Address When reset TABSR 0380 16 0016 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate TA1 0389 16,038816 Indeterminate TA2 038B 16,038A16 Indeterminate TA3 038D 16,038C16 Indeterminate TA4 038F 16,038E16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Ai register (Note) WR

• Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
• Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
• One-shot timer mode 0000 16 to FFFF16 Counts a one shot width
• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
• Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FE16 (Both high-order and low-order addresses) 000016 to FFFE16 Note: Read and write data in 16-bit units.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.4. Timer A-related registers (3) Timer A4 up/down flag Timer A3 up/down flag Timer A2 up/down flag Timer A1 up/down flag Timer A0 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384 16 0016 TA4P TA3P TA2P Up/down flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 TA4UD TA3UD TA2UD TA1UD TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” TA1OS TA2OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 00X00000 2 Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag TA3OS TA4OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Timer A0 event/trigger select bit b7 b6 Note: Set the corresponding port direction register to “0”. When selecting the TAiIN (i = 0–4) pin, TAiOUT (i = 0–4) pin which is assigned to the same pin cannot be used. WR 1 : Timer start When read, the value is “0”

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.5. Timer A-related registers (4) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR WR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TA1TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected Trigger select register Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Timer A2 event/trigger select bit Timer A3 event/trigger select bit Timer A4 event/trigger select bit WR TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”. When selecting the TAiIN (i = 0–4) pin, TAiOUT (i = 0–4) pin which is assigned to the same pin cannot be used.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.

2.2.2 Operation of Timer A (timer mode)

Table 2.2.1. Choosed functions Figure 2.2.6. Operation timing of timer mode FFFF 16 n 000016 Time Start count again Count start flag Timer Ai interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow (3) Stop count Item Count source Pulse output function Gate function Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TAiIN pin is at “L” level Performs count only for the period in which the TAiIN pin is at “H” level

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.7. Set-up procedure of timer mode Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (TAiIN pin is a normal port pin)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.2.3 Operation of Timer A (timer mode, gate function selected)

Figure 2.2.8. Operation timing of timer mode, gate function selected In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are Table 2.2.2. Choosed functions (1) When the count start flag is set to “1” and the TAiIN pin inputs at “H” level, the counter per- forms a down count on the count source. (2) When the TAiIN pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop.

• Make the pulse width of the signal input to the TAiIN pin not less than two cycles of the count source. Operation Note FFFF 16 n 000016 Time Count start flag Timer Ai interrupt request bit “1” “1” Counter content (hex) n = reload register content TAiIN pin input signal (2) Stop count “0” “0” Set to “1” by software “H” “L” (4) Stop count (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (3) Underflow Set to “1” by software Cleared to “0” by software Start count again. Item Count source Pulse output function Gate function Set-up O O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TAiIN pin is at “L” level Performs count only for the period in which the TAiIN pin is at “H” level

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.9. Set-up procedure of timer mode, gate function selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Pulse output function select bit 0 : Pulse is not output (TA iOUT pin is a normal port pin) Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Gate function select bit 1 1 : Timer counts only when TAiIN pin is held “H” (Note) b4 b3 Selection of timer mode b7 b0 0000 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note: Set the corresponding port direction register to “0”. Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Start count

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.10. Operation timing of timer mode, pulse output function selected

2.2.4 Operation of Timer A (timer mode, pulse output function selected)

In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are dure. Table 2.2.3. Choosed functions (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. Also, the output polarity of the TAi OUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT pin outputs an “L” level. Operation FFFF 16 n 000016 Time Count start flag Timer Ai interrupt request bit “1” “1” Counter content (hex) n = reload register content Pulse output from TAiOUT pin “H” “0” “L” “0” Set to “1” by software Set to “1” by software Cleared to “0” by software (3) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow Start count again Item Count source Pulse output function Gate function Set-up O O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TAiIN pin is at “L” level Performs count only for the period in which the TAiIN pin is at “H” level

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Pulse output function select bit 1 : Pulse is output (Note) (TAiOUT pin is a pulse output pin) Selecting timer mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of timer mode b7 b0 0001 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Note: The settings of the corresponding port register and port direction register are invalid. Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f32 fC32 Gate function select bit 0 0 : 0 1 : b4 b3 Gate function not available (TAiIN pin is a normal port pin)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.12. Operation timing of event counter mode, reload type selected

2.2.5 Operation of Timer A (event counter mode, reload type selected)

In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items procedure. Note: j = i – 1, but j = 4 when i = 0. (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. (5) If an overflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. Operation Table 2.2.4. Choosed functions FFFF 16 n 000016 Time Counter content (hex) n = reload register content (1) Start count Count start flag“1” Set to “1” by software “0” Timer Ai interrupt request bit “1” “0” Up/down flag “1” “0” Set to “1” by software Set to “1” by software (5) Overflow Cleared to “0” when interrupt request is accepted, or cleared by software Start count again /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (2) Underflow /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Switch count Cleared to “0” by software (4) Stop count Item ItemSet-up Set-up Count source Input signal to TAiIN (counting falling edges) Input signal to TAiIN (counting rising edges) Timer overflow (TB2/TAj overflow) Count operation type Reload type Free-run type Factor for switching between up and down Content of up/down flag Input signal to TAiOUT Pulse output function No pulses output Pulses output O O O O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.13. Set-up procedure of event counter mode, reload type selected Selecting event counter mode and functions b7 b0 Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Up/down switching cause select bit 0 : Up/down flag's content Selection of event counter mode Invalid in event counter mode (i = 0, 1) Invalid when not using two-phase pulse signal processing(i = 2 to 4) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Count polarity select bit 0 : Counts external signal's falling edge 0100 000 b7 b0

000 Up/down flag [Address 038416]

0 : Down count Timer A1 up/down flag 0 : Down count Timer A2 up/down flag 0 : Down count Timer A3 up/down flag 0 : Down count Timer A4 up/down flag 0 : Down count When not using the 2-phase pulse signal processing function, set the select bit to “0”. Setting one-shot start flag and trigger select register Trigger select register [Address 038316] TRGSR One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b7 b6 b7 b0 b7 b0 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) b1 b0 Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note) b3 b2 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) b5 b4 Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) b7 b6 Note: Set the corresponding port direction register to “0”. Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Setting up/down flag

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.14. Operation timing of event counter mode, free run type selected

2.2.6 Operation of Timer A (event counter mode, free run type selected)

In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items procedure. Note: j = i – 1, but j = 4 when i = 0 (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. Table 2.2.5. Choosed functions Operation FFFF 16 n 000016 Time Counter content (hex) n = reload register content (1) Start count Count start flag“1” “0” Timer Ai interrupt request bit “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Up/down flag “1” “0” Set to “1” by software (2) Underflow (3) Switch count (4) Overflow Set to “1” by software Item ItemSet-up Set-up Count source Input signal to TAiIN (counting falling edges) Input signal to TAiIN (counting rising edges) Timer overflow (TB2/TAj overflow) Count operation type Reload type Free-run type Factor for switching between up and down Content of up/down flag Input signal to TAiOUT Pulse output function No pulses output Pulses output O O O O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.15. Set-up procedure of event counter mode, free run type selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Selecting event counter mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Up/down switching cause select bit 0 : Up/down flag's content Selection of event counter mode Invalid in event counter mode (i = 0, 1) Invalid when not using two-phase pulse signal processing(i = 2 to 4) Count operation type select bit 1 : Free-run type 0 (Must always be “0” in event counter mode) Count polarity select bit 0 : Counts external signal's falling edge b7 b0 0100 001 b7 b0 000 Setting up/down flag Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A1 up/down flag 0 : Down count Timer A2 up/down flag 0 : Down count Timer A3 up/down flag 0 : Down count Timer A4 up/down flag 0 : Down count When not using the 2-phase pulse signal processing function, be sure to set the select bit to “0”. Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Setting one-shot start flag and trigger select register b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b7 b6 b7 b0 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) b1 b0 Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note) b3 b2 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) b5 b4 Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) b7 b6Note: Set the corresponding port direction register to “0”.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected

2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode,

normal mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table Figure 2.2.17 shows the set-up procedure. Table 2.2.6. Choosed functions Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4 multiplication processes. (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”.

• The up count or down count conditions are as follows: If a rising edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”, an up count is performed. If a falling edge is present at the TAi IN pin when the input signal level to the TAiOUT pin is “H”, a down count is performed. Operation Note 000016 Count start flag Timer Ai interrupt request bit “1” “0” “1” “0” FFFF 16 Counter content (hex) Input pulse TAiOUT “H” “L” “H” “L” TAiIN Set to “1” by software Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Underflow (3) Overflow Time Item Count operation type 2-phase pulses process (Note) Set-up O O Reload type Free run type Normal processing 4-multiplication processing

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Start count Selecting event counter mode and functions 0 (Must always be “0” when using two-phase pulse signal processing) Timer Ai mode register (i= 2, 3) [Address 039816, 039916] TAiMR (i= 2, 3) 1 (Must always be “1” when using two-phase pulse signal processing) Selection of event counter mode Two-phase pulse signal processing operation select bit 0 : Normal processing operation Count operation type select bit 1 : Free-run type 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) b7 b0 0100 1001 Two-phase pulse signal processing select bit b7 b0 Up/down flag [Address 038416] UDF Timer A2 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled Setting count start flag Count start flag [Address 038016] TABSR Timer A2 count start flag Timer A3 count start flag b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected

2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,

multiply-by-4 mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table Figure 2.2.19 shows the set-up procedure. Table 2.2.7. Choosed functions Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4- multiplication processes. (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the interrupt request bit goes to “1”.

• The up count or down count conditions are as follows: Operation Note Table 2.2.8. The up count or down count conditions TimeSet to “1” by software 000016 Count start flag Timer Ai interrupt request bit “1” “0” “1” “0” FFFF 16 Counter content (hex) Input pulse TAiOUT “H” “L” “H” “L”TAiIN (1) Start count (2) Underflow (3) Overflow Cleared to “0” when interrupt request is accepted, or cleared by software Item ItemSet-up Set-up Count operation type Reload type Free run typeO Processing 2 phase pulses (Note) O Normal processing 4-multiplication processing Up count Input signal to the TAiOUT pin Input signal to the TAiIN pin Down count Input signal to the TAiOUT pin Input signal to the TAiIN pin “H” level “L” level Rising Falling Rising Falling “L” level “H” level “H” level “L” level Rising Falling Falling Rising “H” level “L” level

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.19. Set-up procedure of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Selecting event counter mode and functions 0 (Must always be “0” when using two-phase pulse signal processing) Timer Ai mode register (i= 3, 4) [Address 039916, 039A16] TAiMR (i= 3, 4) 1 (Must always be “1” when using two-phase pulse signal processing) Selection of event counter mode Two-phase pulse signal processing operation select bit 1 : Multiply-by-4 processing operation Count operation type select bit 1 : Free-run type 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) b7 b0 0100 1011 Two-phase pulse signal processing select bit b7 b0 Up/down flag [address 038416] UDF Timer A3 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled Timer A4 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled Setting count start flag Count start flag [Address 038016] TABSR Timer A3 count start flag Timer A4 count start flag b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.2.9 Operation of Timer A (one-shot timer mode)

Figure 2.2.20. Operation timing of one-shot mode In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items procedure. Operation Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TAiOUT pin outputs an “H” level. (2) The instant the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Ai interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TAi OUT pin outputs an “L” level. At this time, the timer Ai interrupt request bit goes to “1”. Table 2.2.9. Choosed functions Item Count source Pulse output function Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Writing “1” to the one-shot start flag FFFF 16 n 000116 Timer Ai interrupt request bit Counter content (hex) n = reload register content Reload One-shot pulse output from TAiOUT pin “H” 1 / fi X (n) “L” Time Reload 1 / fi X (n+1) Write signal to one-shot start flag “1” “0” Count start flag “1” “0” (1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software (2) Stop count (3) Start count (4) Stop countStart count Reload Set to “1” by software Cleared to “0” by software

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.21. Set-up procedure of one-shot mode Pulse output function select bit 1 : Pulse is output Selecting one-shot timer mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) External trigger select bit When internal is selected, this bit can be “1” or “0” Selection of one-shot timer mode b7 b0 1001 0 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Trigger select bit 0 : When the one-shot start flag is set “1” Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f f32 fC32 Setting one-shot timer's time Can be set to 000116 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Setting one-shot start flag One-shot start flag [Address 038216] ONSF Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag b7 b0 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing timer Ai interrupt request bit Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one-shot timer mode)'

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled procedure.

2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected)

Figure 2.2.22. Operation timing of one-shot mode, external trigger selected Operation Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. At this time, the TAiOUT pin output level goes to “H” level. (2) If the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Ai interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TAi OUT pin outputs an “L” level. At this time, the timer Ai interrupt request bit goes to “1”. Table 2.2.10. Choosed functions Item Count source Pulse output function Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Writing “1” to the one-shot start flag FFFF 16 n 000116 Timer Ai interrupt request bit Counter content (hex) n = reload register content ReloadReload (4) Stop count One-shot pulse output from TAiOUT pin “H” 1 / fi X (n) “L” 1 / fi X (n+1) TAiIN pin input signal “H” “L” “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Count start flag “1” “0” (2) Stop count (1) Start count (3) Start count Time Reload Start count Set to “1” by software Trigger during count Cleared to “0” by software

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected Setting one-shot timer's time Can be set to 000116 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Pulse output function select bit 1 : Pulse is output Selecting one-shot timer mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) External trigger select bit 1 : Rising edge of TAiIN pin's input signal Selection of one-shot timer mode b7 b0 10111 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Trigger select bit 1 : Selected by event/trigger select bit Setting event/trigger select bit Trigger select register [Address 038316] TRGSR One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b7 b6 b7 b0 b7 b0 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note) b1 b0 Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note) b3 b2 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) b5 b4 Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) b7 b6Note: Set the corresponding port direction register to “0”. Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Clearing timer Ai interrupt request bit Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one-shot timer mode)'

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the set-up procedure.

2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)

Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. Table 2.2.11. Choosed functions (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level. (2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Ai interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT outputs an “L” level.

• The period of PWM pulses becomes (216 – 1)/fi, and the “H” level pulse width becomes n/fi. If the timer Ai register is set to “000016”, the pulse width modulator does not work, and the TAiOUT pin output level remains at “L”. (fi : frequency of the count source f1, f8, f32, fC32 ; n : value of the timer) Operation Note Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Count source TA iIN pin input signal PWM pulse output from TAiOUT pin Timer Ai interrupt request bit Count start flag 1 / fi X (2 –1) Conditions: Reload register = 000316, external trigger (rising edge of TAiIN pin input signal) is selected Trigger is not generated by this signal “H” “H” “L” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software 1 / fi X n “1” “0” Set to “1” by software (1) Start count (2) Output level “H” to “L” Note: n = 000016 to FFFE16 (3) One period is complete (4) Stop count Cleared to “0” by software

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected Setting PWM pulse's “H” level width Can be set to 000016 to FFFE16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Setting event/trigger select bit One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note 2) b7 b6 b7 b0 b7 b0 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note 2) b1 b0 Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note 2) b3 b2 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note 2) b5 b4 Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note 2) b7 b6 Note 2: Set the corresponding port direction register to “0”. Trigger select register [Address 038316] TRGSR 1 (Must always be “1” in PWM mode) Selecting PWM mode and functions Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) External trigger select bit 1 : Rising edge of TAiIN pin's input signal (Note 1) Selection of PWM mode b7 b0 11111 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Note 1: Set the corresponding port direction register to “0”. Clearing timer Ai interrupt request bit Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit b7 b0 Refer to 'Precaution for Timer A (pulse width modulation mode)'

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)

Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the set-up procedure. Table 2.2.12. Choosed functions Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. (1) If the TAiIN pin input level changes from “H” to “L” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level. (2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Ai interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT pin outputs an “L” level.

• The period of PWM pulses becomes (m + 1) X (28 – 1) / fi, and the “H” level pulse width becomes n X (m + 1) / fi. If “0016” is set in the eight higher-order bits of the timer Ai register, the pulse width modulator does not work, and the TAiOUT pin output level remains at “L”. (fi : frequency of the count source f1, f8, f32, fc32; n : value of the timer)
• When a trigger is generated, the TAiOUT pin outputs “L” level of same amplitude as “H” level of the set PWM pulse, after which it starts PWM pulse output. Operation Note Item Count source PWM mode Count start condition Set-up O O O Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Count source (Note 1) Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected TA iIN pin input Underflow signal of 8-bit prescaler (Note 2) PWM pulse output from TA iOUT pin “H” “H” “L” “L” Timer Ai interrupt request bit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines “H” “L” “1” “0” Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 00 16 to FE16; n = 0016 to FE16. 1 / fi X (m + 1) X n Count start flag “1” “0” (1) Start count (2) Output level “H” to “L” Cleared to “0” when interrupt request is accepted, or cleared by software (3) (4) Stop count 1 / fi X (m+1) Conditions: One period is complete

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected Start count Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag b7 b0 Setting PWM pulse's period and “H” level width Can be set to 0016 to FE16 b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Can be set to 0016 to FE16 1 (Must always be “1” in PWM mode) Selecting PWM mode and function Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) External trigger select bit 0 : Falling edge of TAiIN pin's input signal (Note1) Selection of PWM mode b7 b0 11011 16/8-bit PWM mode select bit 1: Functions as an 8-bit pulse width modulator b7 b6 Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Trigger select bit 1 : Selected by event/trigger select register Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Setting event/trigger select bit One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note 2) b7 b6 b7 b0 Trigger select register [Address 038316] TRGSR b7 b0 Timer A1 event/trigger select bit 0 0 : Input on TA1IN is selected (Note 2) b1 b0 Timer A2 event/trigger select bit 0 0 : Input on TA2IN is selected (Note 2) b3 b2 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note 2) b5 b4 Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note 2) b7 b6Note 2: Set the corresponding port direction register to “0”. Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Note 1: Set the corresponding port direction register to “0”. Clearing timer Ai interrupt request bit Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit b Refer to 'Precaution for Timer A (pulse width modulation mode)'

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.2.13 Precautions for Timer A (timer mode)

Figure 2.2.28. Reading timer Ai register (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.28 gets “FFFF 16”. Reading the timer Ai register after setting a value in the timer Ai regis- ter with a count halted but before the counter starts counting gets a proper value. 2 1 0 n n – 1Counter value (Hex.) 2 1 0 FFFF n – 1Read value (Hex.) Reload Time n = reload register content

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.29 gets “FFFF 16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts count- ing gets a proper value. (3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse signals input signals to the TAi IN pin and TAiOUT pin (i = 2, 3, 4), as shown in Figure 2.2.30. (4) When free run type is selected, if count is stopped, set a value in the timer Ai register again.

2.2.14 Precautions for Timer A (event counter mode)

Figure 2.2.30. Standard of 2-phase pulses Figure 2.2.29. Reading timer Ai register 210 n n – 1Counter value (Hex.)

210 FFFFRead value

(Hex.) Reload Time n = reload register content (1) Down count FFFD FFFE FFFF n n + 1Counter value (Hex.) FFFD FFFE FFFF 0000 n + 1Read value (Hex.) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Reload Time n = reload register content (2) Up count n – 1 T2 T3 TA2 OUT TA3 OUT TA4 OUT TA2 IN TA3 IN TA4 IN (Min.) T2, T3 (Min.) Vcc = 5V, f(XIN) = 10MHz 800ns 200ns (Min.) T2, T3 (Min.) Vcc = 3V, f(XIN) = 7MHz, one-wait 2µs 500ns

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows:

• The counter stops counting and a content of reload register is reloaded.
• The TAi OUT pin outputs “L” level.
• The interrupt request is generated and the timer Ai interrupt request bit goes to “1”. (3) The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of the maximum count source occurs between the trigger input to the TAi IN pin and the one-shot timer output. (4) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (5) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.

2.2.15 Precautions for Timer A (one-shot timer mode)

Figure 2.2.31. One-shot timer delay Note: The above applies when an external trigger (falling edge of TAiIN pin input signal) is selected. TAiIN pin input signal“H” “L” Count source Trigger input Start one-shot pulse output One-shot pulse output from TAiOUT pin

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compli- ance with any of the following procedures:

• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAi OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”.

2.2.16 Precautions for Timer A (pulse width modulation mode)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.3 Timer B

2.3.1 Overview

The following is an overview for timer B, a 16-bit timer. (1) Mode Timer B operates in one of three modes: (a) Timer mode The internal count source is counted. (b) Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted. (c) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured. (2) Count source An internal count source can be selected from f 1, f8, f32, and fC32 . f1, f8, and f32 are clocks obtained by dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the CPU secondary clock by 32. (3) Frequency division ratio The frequency division ratio equals [the value set in the timer register + 1]. The counter underflows when a count source equal to a frequency division ratio is input, and an interrupt request occurs. (4) Reading the timer In timer mode or event counter mode, the count value at the time of reading the timer register will be read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) Writing to the timer When writing to the timer register while a count is in progress, the value is written only to the reload register. When writing to the timer register while a count has stopped, the value is written both to the reload register and the count. Write the value in 16-bit increments. The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.2. Timer B-related registers (1) T i m e r B i m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T B i M R i t o t o D 1 6 0 X X B i t s y m b o l B i t n a m e F u n c t i o n WR b 0 0 : T i m e r m o d e E v e n t c o u n t e r m o d e P u l s e p e r i o d p u l s e w i d t h m e a s u r e m e n t m o d e I n h i b i t e d b b T C K 1 M R 3 M R 2 M R 1 T M O D 1 M R 0 T M O D 0 T C K 0 F u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e C o u n t s o u r c e s e l e c t b i t F u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e O p e r a t i o n m o d e s e l e c t b i t N o t e N o t e N o t e 1 : T i m e r B 0 . N o t e T i m e r B t i m e r B

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.3. Timer B-related registers (2) Symbol Address When reset TABSR 0380 16 0016 Count start flag Bit nameBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Timer B2 count start flag Timer B1 count start flag Timer B0 count start flag Timer A4 count start flag Timer A3 count start flag Timer A2 count start flag Timer A1 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting TB2S TB1S TB0S TA4S TA3S TA2S TA1S TA0S Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminate TB2 0395 16, 039416 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) WR

• Pulse period / pulse width measurement mode Measures a pulse period or width
• Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
• Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note: Read and write data in 16-bit units. Function

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are

2.3.2 Operation of Timer B (timer mode)

Table 2.3.1. Choosed functions (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the counter contin- ues counting. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Figure 2.3.4. Operation timing of timer mode Item Count source Set-up O Internal count source (f1 / f8 / f32 / fc32) FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software (2) Underflow (3) Stop count(1) Start count Cleared to “0” when interrupt request is accepted, or cleared by software Start count again

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.5. Set-up procedure of timer mode Setting divide ratio Can be set to 000016 to FFFF16 b7 b0 (b15) (b8) b7 b0 Timer B0 register [Address 039116, 039016] TB0 Timer B1 register [Address 039316, 039216] TB1 Timer B2 register [Address 039516, 039416] TB2 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0 Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Selecting timer mode and functions Invalid in timer mode Can be “0” or “1” Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) Fixed to “0” in timer mode ( i = 0) This bit can neither be set nor reset (i = 1, 2) Selection of timer mode b7 b0 Invalid in timer mode Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are

2.3.3 Operation of Timer B (event counter mode)

Table 2.3.2. Choosed functions Note: j = i – 1, but j = 2 when i = 0 Figure 2.3.6. Operation timing of event counter mode (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Item Set-up Count source Input signal to the TBiIN pin (counting falling edges) Timer overflow(TBj overflow) O Input signal to the TBiIN pin (counting rising edges) Input signal to the TBiIN pin (counting rising edges and falling edges) FFFF 16 n 000016 Time Count start flag Timer Bi interrupt request bit “1” “1” Counter content (hex) n = reload register content Set to “1” by software “0” “0” Set to “1” by softwareCleared to “0” by software (1) Start count (2) Underflow (3) Stop count Cleared to “0” when interrupt request is accepted, or cleared by software Start count again

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.7. Set-up procedure of event counter mode Setting divide ratio Can be set to 000016 to FFFF16 (n) b7 b0 (b15) (b8) b7 b0 Timer B0 register [Address 039116, 039016] TB0 Timer B1 register [Address 039316, 039216] TB1 Timer B2 register [Address 039516, 039416] TB2 Start count Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Selecting event counter mode and functions Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) Fixed to “0” in event counter mode ( i = 0) This bit can neither be set nor reset (i = 1, 2) Selection of event counter mode b7 b0 Invalid in event counter mode Event clock select 0 : Input from TBiIN pin (Note) 000 Count polarity select bit 0 0 : Counts external signal falling edges b3 b2 Note: Set the corresponding port direction register to “0”.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Op- erations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure 2.3.9 shows the set-up procedure.

2.3.4 Operation of Timer B (pulse period measurement mode)

Figure 2.3.8. Operation timing of pulse period measurement mode Table 2.3.3. Choosed functions Operation Note (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request is not generated. (3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “0000 16”, and the measurement is started again.

• The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) OMeasurement mode Count source Measurement pulse Count start flag Timer Bi interrupt request bit Timing at which counter reaches “000016” “1” “H” “1” Transfer (indeterminate value)Reload register ← counter transfer timing “L” “0” “0” Timer Bi overflow flag“1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Measurement of pulse time interval from falling edge to falling edge Transfer (measured value)Cleared to “0” when interrupt request is accepted, or cleared by software (1) Start count (2) Start measurement(3) Start measurement again (Note 1) (Note 1) (Note 2)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.9. Set-up procedure of pulse period measurement mode Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Selecting pulse period / pulse width measurement mode and functions Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) Fixed to “0” in pulse period/pulse width measurement mode (i = 0) This bit can neither be set nor reset (i = 1,2) Selection of pulse period / pulse width measurement mode b7 b0 Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Measurement mode select bit 0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) b3 b2 Clearing overflow flag Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) b7 b0 Timer Bi overflow flag 0 : Timer did not overflow Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Start count Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Op- erations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure 2.3.11 shows the set-up procedure.

2.3.5 Operation of Timer B (pulse width measurement mode)

Figure 2.3.10. Operation timing of pulse width measurement mode Operation Note Table 2.3.4. Choosed functions (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request is not generated. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “0000 16”, and measurement is started again.

• The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Bi overflows. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine.
• The value of the counter at the beginning of a count is indeterminate. Thus there can be in- stances in which the timer Bi overflow flag goes to “1” immediately after a count is performed.
• The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Item Set-up Count source Internal count source (f1 / f8 / f32 / fc32) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Measurement mode Measurement pulse “H” Count source Reload register ← counter transfer timing Count start flag Timer Bi interrupt request bit Timing at which counter reaches “000016” “1” “1” “L” “0” “0” Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. (Note 1)(Note 1)(Note 1) (Note 2) (1) Start count (2) Start measurement (3) Start measurement again Cleared to “0” when interrupt request is accepted, or cleared by software Transfer (indeterminate value) Transfer(measured value) (Note 1)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.3.11. Set-up procedure of pulse width measurement mode Start count Setting count start flag Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Selecting pulse period / pulse width measurement mode and functions Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) Fixed to “0” in pulse period/pulse width measurement mode (i = 0) This bit can neither be set nor reset (i = 1, 2) Selection of pulse period / pulse width measurement mode b7 b0 Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 Measurement mode select bit 1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) b3 b2 Clearing overflow flag Timer Bi mode register (i=0 to 2) [Address 039B16 to 039D16] TBiMR (i=0 to 2) b7 b0 Timer Bi overflow flag 0 : Timer did not overflow Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the flag to “1”. (2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing shown in Figure 2.3.12 gets “FFFF 16”. Reading the timer Bi register after setting a value in the timer Bi regis- ter with a count halted but before the counter starts counting gets a proper value.

2.3.6 Precautions for Timer B (timer mode, event counter mode)

Figure 2.3.12. Reading timer Bi register 21 0 n n – 1Counter value (Hex.) 21 0 FFFF n – 1Read value (Hex.) Reload Time n = reload register content

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Bi overflow flag goes to “1”. This flag cannot be set to “0” by writing to the timer Bi mode register when the count start flag is “1”. (4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is trans- ferred to the reload register. At this time, timer Bi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi overflow flag may go to “1” immediately after a count is started. (7) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (8) If the input signal to the TBi IN pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H” level width or an “L” level width.

2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.4.1 Overview

Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. The bit rate generator count source can be se- lected from the following: f 1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK pin becomes the transfer rate. (3) Error detection Only overrun error can be detected. Overrun error is an error that occurs when the next data is made ready before the reception buffer register is read. (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer register, then receive the data again. To initialize the UARTi receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the serial I/O mode select bit to “000 2” (invalid serial I/O). 3. Set the serial I/O mode select bit. 4. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side, set the UARTi transmit buffer register again, then transmit the data again. To set the UARTi transmit buffer register again 1. Set the serial I/O mode select bits to “000 2” (invalidate serial I/O). 2. Set the serial I/O mode select bits again. 3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi transmit buffer register. (5) Function selection For clock-synchronous serial I/O, the following functions can be selected: (a) CTS/RTS function In the CTS function, an external IC can start transmission/reception by inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the level is set to “H” during transmission/reception, it will stop from the next data. The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS goes to “H” at the falling edge of the transfer clock. The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from:

• CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port.
• CTS function only enabled CTS/RTS pin performs the CTS function.
• RTS function only enabled CTS/RTS pin performs the RTS function.

2.4 Clock-Synchronous Serial I/O

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (b) Function for choosing polarity This function switches the polarity of the transfer clock. The following operations are available:

• Data is input at the falling edge of the transfer clock, and is output at the rising edge.
• Data is input at the rising edge of the transfer clock, and is output at the falling edge. (c) Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the following:
• LSB first Data is transmitted from bit 0.
• MSB first Data is transmitted from bit 7. (d) Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the recep- tion-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer register so as to make the reception-enabled status ready. But at the time of starting reception, read the receive buffer register into a dummy manner.
• Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready.
• Successive reception mode Reading the reception buffer register makes the reception-enabled status ready. (e) Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock. This function is effective only when selecting the internal clock. Switching among pins for outputting the transfer clock allows data trans- mission to two external ICs in a time-sharing manner. (f) Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. When transmis- sion buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register. Therefore, data can be transmitted in succession. When transmission register empty timing is selected, an interrupt occurs when data transmission is complete. Following are some examples in which various functions (a) through (f) are selected:
• Transmission Operation WITH: CTS function, transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple
• Transmission Operation WITH: CTS/RTS function disabled, transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to mul-
• Reception WITH: RTS function, reception at falling edge of transfer clock, LSB First, successive

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.2. Serial I/O-related registers (1) b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmission data Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate UARTi bit rate generator b7 b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by (n + 1) 0016 to FF16 Values that can be set Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b15) (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16 and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Reception data WR WR WR Reception data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.3. Serial I/O-related registers (2) WR U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t U i M R i A A 6 0 b B i t n a m eB i t s y m b o l M u s t b e f i x e d t o 0 0 1 S e r i a l I O i n v a l i d I n h i b i t e d I n h i b i t e d I n h i b i t e d b 2 b 1 b 0 C K D I R S M D 1 S M D 0 S e r i a l I / O m o d e s e l e c t b i t S M D 2 I n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t S T P S P R Y P R Y E S L E P P a r i t y e n a b l e b i t 0 : I n t e r n a l c l o c k E x t e r n a l c l o c k S t o p b i t l e n g t h s e l e c t b i t O d d / e v e n p a r i t y s e l e c t b i t S l e e p s e l e c t b i t 0 : O n e s t o p b i t T w o s t o p b i t s 0 : P a r i t y d i s a b l e d P a r i t y e n a b l e d 0 : S l e e p m o d e d e s e l e c t e d S l e e p m o d e s e l e c t e d 1 0 0 : T r a n s f e r d a t a 7 b i t s l o n g T r a n s f e r d a t a b i t s l o n g T r a n s f e r d a t a b i t s l o n g S e r i a l I O i n v a l i d I n h i b i t e d I n h i b i t e d I n h i b i t e d b 2 b 1 b 0 0 : I n t e r n a l c l o c k E x t e r n a l c l o c k I n v a l i d V a l i d w h e n b i t 6 = “ 1 ” O d d p a r i t y E v e n p a r i t y I n v a l i d I n v a l i d M u s t a l w a y s b e “ 0 ” F u n c t i o n D u r i n g U A R T m o d e F u n c t i o n D u r i n g c l o c k s y n c h r o n o u s s e r i a l I O m o d e U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 S y m b o lA d d r e s sW h e n r e s e t U i C i A A C 1 6 0 b F u n c t i o n D u r i n g U A R T m o d e F u n c t i o n D u r i n g c l o c k s y n c h r o n o u s s e r i a l I O m o d e T X E P T C L K 1 C L K 0 C R S C R D N C H C K P O L B R G c o u n t s o u r c e s e l e c t b i t T r a n s m i t r e g i s t e r e m p t y f l a g 0 : T r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e T r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e C L K p o l a r i t y s e l e c t b i t C T S / R T S f u n c t i o n s e l e c t b i t C T S / R T S d i s a b l e b i t D a t a o u t p u t s e l e c t b i t 0 0 : f1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b b 0 : L S B f i r s t M S B f i r s t 0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r d u r i n g t r a n s m i s s i o n N o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r t r a n s m i s s i o n c o m p l e t e d 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t U F O R MT r a n s f e r f o r m a t s e l e c t b i t 0 0 : f1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b b V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e 0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r d u r i n g t r a n s m i s s i o n N o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r t r a n s m i s s i o n c o m p l e t e d 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t M u s t a l w a y s b e “ 0 ” B i t n a m eB i t s y m b o l M u s t a l w a y s b e “ 0 ” N o t e 1 : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . N o t e T h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t WR

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.4. Serial I/O-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16, 03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Note: When using multiple pins to output the transfer clock, the following requirement must be met:

• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM Invalid Invalid Invalid CLK/CLKS select bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Reserved bit Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table

2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)

Note: This can be selected only when UART1 is used in combination with the internal clock. When this function is selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”. (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register makes data transmissible status ready. (2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be controlled on the reception side). (3) In synchronization with the first falling edge of the transfer clock, transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges. (4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that transmission is completed. The transfer clock stops at “H” level. (5) If the next transmission data is set in the UARTi transmit buffer register while transmission is in progress (before the eighth bit has been transmitted), the data is transmitted in succession. Operation Table 2.4.1. Choosed functions Item ItemSet-up Set-up Transfer clock source CLK polarity Internal clock (f1 / f8 / f32) External clock (CLKi pin) CTS function CTS function enabled CTS function disabled Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock O O O Transmission interrupt factor Transmission buffer empty Transmission complete Output transfer clock to multiple pins (Note) Not selected Selected O O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example of wiring Figure 2.4.5. Operation timing of transmission in clock-synchronous serial I/O mode Example of operation CLKi TXDi CTSi CLK R XD Port Microcomputer Receiver side IC D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TCLK Stopped pulsing because transfer enable bit = “0” Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi TxDi Transmit register empty flag (TXEPT) “H” “L” “0” “1” “0” “1” “0” “1” CTSi Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (1) Transmission enabled /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (2) Confirming CTS /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (3) Start transmissionTc /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (4) Transmission is complete /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines (5) Transmit next data Data is set to UARTi transmit buffer register Stopped pulsing because CTSi = “H” Shown in ( ) are bit symbols. The above timing applies to the following settings:

• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”. Transferred from UARTi transmit buffer register to UARTi transmit register

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1) Continued to the next page Internal/external clock select bit 0 : Internal clock Setting UARTi transmit/receive mode register (i=0, 1) UART0 transmit/receive mode register U0MR [Address 03A0 16] UART1 transmit/receive mode register U1MR [Address 03A8 16] Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 0 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UARTi transmit/receive control register 0 (i=0, 1) UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 0000 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected (Note) CTS/RTS disable bit 0 : CTS/RTS function enabled Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “0” . Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output UART transmit/receive control register 2 UCON [Address 03B0 16] UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) CLK/CLKS select bit 1 0 : Normal mode (CLK output is CLK1 only) UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Valid when bit 5 = “1” Fix “0” to this bit. b7 b0 Setting UART transmit/receive control register 2

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2) Start transmission When CTSi input level = “L” Setting UARTi bit rate generator (i = 0, 1) UARTi bit rate generator (i = 0, 1) [Address 03A116, 03A916] UiBRG (i = 0, 1) Can be set to 0016 to FF16 (Note) b7 b0 Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmission is complete Continued from the previous page UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD 16] Transmit enable bit 1 : Transmission enabled b7 b0 Transmission enabled Writing transmit data UART0 receive buffer register [Address 03A316, 03A216] U0TB UART1 receive buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8) UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Checking the status of UARTi transmit /receive control register (i = 0, 1) Writing next transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8)

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O

mode, transfer clock output from multiple pins function selected) Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”. (1) Setting the transmit enable bit to “1” makes data transmissible status ready. (2) When transmission data is written to the UART1 transmit buffer register, transmission data held in the UART1 transmit buffer register is transmitted to the UART1 transmit register in synchronization with the first falling edge of the transfer clock. At this time, the first bit of the transmission data is transmitted from the TxD1 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that the transmission is completed. The transfer clock stops at “H” level. At this time, the UART1 transmit interrupt request bit goes to “1”. (4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the CLKS1 pin to go to the transfer clock output pin. Change the transfer clock output pin when transmission is halted. Operation In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table Table 2.4.2. Choosed functions Item ItemSet-up Set-up Transfer clock source CLK polarity Internal clock (f1 / f8 / f32) External clock (CLKi pin) CTS function CTS function enabled CTS function disabled Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock O O O Transmission interrupt factor Transmission buffer empty Transmission complete Output transfer clock to multiple pins (Note 1) Not selected Selected O O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example of wiring Example of operation Figure 2.4.8. Operation timing of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected Microcomputer TXD 1 (P67) CLKS 1 (P64) CLK 1 (P65)I N CLK IN CLK Note: This applies when performing only transmission with an internal clock selected in the clock synchronous serial I/O mode. Transmit interrupt request bit “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit buffer empty flag CLK 1 TxD 1 “0” “1” Transmit enable bit “0” “1” Transfer clock CLKS 1 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 CLK, CLKS select bit 1 “0” “1” “0” “1”CLK, CLKS select bit 0 (1) Transmission enabled (2) Start transmission (3) Transmission is complete (4) Clock switched

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.9. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (1) Internal/external clock select bit 0 : Internal clock Setting UART1 transmit/receive mode register UART1 transmit/receive mode register [Address 03A816] U1MR Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 0 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UART1 transmit/receive control register 0 UART1 transmit/receive control register 0 [Address 03AC16] U1C0 CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 100 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 Valid when bit 4 = “0” Data output select bit 0 : TXDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CTS/RTS disable bit 1 : CTS/RTS function disabled Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Continued to the next page Setting UART transmit/receive control register 2 UART transmit/receive control register 2 [Address 03B016] UCON CLK/CLKS select bit 1 1 : Transfer clock output from multiple pins function selected UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) CLK/CLKS select bit 0 0 : Clock output to CLK1 1 : Clock output to CLKS1 Fix “0” to this bit. b7 b0 1 10

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.10. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (2) Setting UART1 bit rate generator UART1 bit rate generator [Address 03A916] U1BRG Can be set to 0016 to FF16 (Note) b7 b0 Writing transmit data UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8) Transmission enabled UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit enable bit 1 : Transmission enabled b7 b0 Checking the status of UART1 transmit buffer register UART1 transmit/receive control register 1 [Address 03AD16] U1C1 b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Start transmission Writing next transmit data UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8) Transmission is complete Continued from the previous page Note: Write to UARTi bit rate generator when transmission/reception is halted.

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3. Operations of the circled items are described below. Figure 2.4.11 shows the operation timing, and Fig-

2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)

Table 2.4.3. Choosed functions Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is selected, UART1 CTS/RTS function cannot be utilized. Set the UART1 CTS/RTS disable bit to “1”. (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”, and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the output from the RTSi pin goes to “L” level, which informs the transmission side that the data receivable status is ready (output the transfer clock from the IC on the transmission side after checking that the RTS output has gone to “L” level). (2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting right the content of the UARTi reception data in synchronization with the rising edges of the transfer clock. (3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H” level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer register is read. Operation Item ItemSet-up Set-up Transfer clock source CLK polarity Internal clock (f1 / f8 / f32) External clock (CLKi pin) RTS function RTS function enabled RTS function disabled Input reception data at the rising edge of the transfer clock Input reception data at the falling edge of the transfer clock O O O Continuous receive mode Disabled Enabled O Output transfer clock to multiple pins (Note 1) Not selected Selected O Transfer clock LSB first MSB first O

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example of wiring Figure 2.4.11. Operation timing of reception in clock-synchronous serial I/O mode Example of operation CLKi R XDi RTSi CLK TXD Port Microcomputer Transmitter side IC 1 / fEXT Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLKi RxDi Receive complete flag (Rl) RTSi “H” “L” “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” The above timing applies to the following settings:

• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”. fEXT : frequency of external clock Make sure that the following conditions are met when the CLKi pin input =“H” before data reception
• Transmit enable bit → “1”
• Receive enable bit → “1”
• Dummy data write to UARTi transmit buffer register Receive interrupt request bit (IR)“0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Reception data is taken in Transferred from UARTi receive register to UARTi receive buffer register (1) Reception enabled (2) Start reception (3) Reception is complete Read out from UARTi receive buffer register Transferred from UARTi transmit buffer register to UARTi transmit register (4) Read of reception data Dummy data is set in UARTi transmit buffer register

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.12. Set-up procedure of reception in clock-synchronous serial I/O mode (1) Continued to the next page Internal/external clock select bit 1 : External clock Setting UARTi transmit/receive mode register (i=0, 1) UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A816] Invalid in clock synchronous I/O mode Must be fixed to “001” b7 b0 0100 1 Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode Setting UARTi transmit/receive control register 0 (i=0, 1) UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge b7 b0 0100 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected CTS/RTS disable bit 0 : CTS/RTS function enabled Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Transfer format select bit 0 : LSB first Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output UART transmit/receive control register 2 UCON [Address 03B016] UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled CLK/CLKS select bit 1 0 : Normal mode (CLK output is CLK1 only) UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled Valid when bit 5 = “1” Fix “0” to this bit. b7 b0 Setting UART transmit/receive control register 2

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.4.13. Set-up procedure of reception in clock-synchronous serial I/O mode (2) Writing dummy data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting dummy data b7 b0 b7 b0 (b15) (b8) Checking completion of reception b7 b0 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Start reception Processing after reading out reception data Continued from the previous page Checking error UART0 receive buffer register [Address 03A716, 03A616]U0RB UART1 receive buffer register [Address 03AF16, 03AE16]U1RB Overrun error flag 0 : No overrun error 1 : Overrun error found b7 b0 b7 b0 (b15) (b8) Receive data Reception enabled UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit enable bit 1 : Transmission enabled b7 b0 Receive enable bit 1 : Reception enabled UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O)

(1) With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmis- sion side that the reception has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with consistent timing. With the internal clock, the RTS function has no effect. Figure 2.4.14 shows an example of wiring. Figure 2.4.14. Example of wiring TxD i RxD i CLK i CTS i TxD i RxD i CLK i RTS i Transmitter side IC Receiver side IC

Clock-Synchronous Serial I/O M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Transmission Reception (1) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1. Set the transmit enable bit (to “1”) 2. Write transmission data to the UARTi transmit buffer register 3. “L” level input to the CTSi pin (when the CTS function is selected) (1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxDi pin (transmission pin) when receiving data. (2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled status) and setting dummy data in the UARTi transmission buffer register generates a shift clock. With the external clock selected, a shift clock is generated when the transmit enable bit is set to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input to the CLKi pin. (3) In receiving data in succession, an overrun error occurs when the next reception data is made ready in the UARTi receive register with the receive complete flag set to “1” (before the content of the UARTi receive buffer register is read), and overrun error flag is set to “1”. In this instance, the next data is written to the UARTi receive buffer register, so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again. If an overrun error occurs, the UARTi receive interrupt request bit does not go to “1”. (4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit buffer register every time reception is made. (5) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1. Set receive enable bit (to “1”) 2. Set transmit enable bit (to “1”) 3. Write dummy data to the UARTi transmit buffer register (6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This is not related to the content of the transmit buffer empty flag or the content of the transmit enable bit. Output from the RTS pin goes to “H” level when reception starts, and goes to “L” level when reception is completed. This is not related to the content of the transmit buffer empty flag or the content of the receive complete flag.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.5 Clock-Asynchronous Serial I/O (UART)

2.5.1 Overview

UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O. (1) Transmission/reception format Figure 2.5.1 shows the transmission/reception format, and Table 2.5.1 shows the names and func- tions of transmission data. Figure 2.5.1. Transmission/reception format Table 2.5.1. Transmission data names and functions Transfer data length : 7 bits 1ST – 7DATA 1SP 1ST – 7DATA 2SP 1ST – 7DATA – 1PAR – 1SP 1ST – 7DATA – 1PAR – 2SP Transfer data length : 8 bits 1ST – 8DATA 1SP 1ST – 8DATA 2SP 1ST – 8DATA – 1PAR – 1SP 1ST – 8DATA – 1PAR – 2SP Transfer data length : 9 bits 1ST – 9DATA 1SP 1ST – 9DATA 2SP 1ST – 9DATA – 1PAR – 1SP 1ST – 9DATA – 1PAR – 2SP ST : Start bit DATA : Character bit (Transfer data) PAR : Parity bit SP : Stop bit Name Function ST (start bit) DATA (character bits) SP (stop bit) A 1-bit “L” signal to be added immediately before character bits. This bit signals the start of data transmission. Transmission data set in the UARTi transmit buffer register. A signal to be added immediately after character bits so as to increase data reliability. The level of this signal so varies that the total number of 1's in character bits and this bit always becomes even or odd depending on which parity is chosen, even or odd. PAR (parity bit) Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after the parity bit if parity is checked). This / they signals the end of data transmission.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans- fer rate. The count source for the bit rate generator can be selected from f 1, f8, f32, and the input from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respec- tively. Table 2.5.2. Example of baud rate setting Table 2.5.3. Error detection (3) An error detection In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3. Baud rate (bps) BRG's count source System clock : 10MHz System clock : 7.3728MHz BRG's set value : n Actual time (bps) BRG's set value : n 600 1200 2400 4800 9600 14400 19200 28800 31250 f 129 (8116) 64 (4016) 32 (2016) 129 (8116) 64 (4016) 42 (2A16) 32 (2016) 21 (1516) 19 (1316) 600 1201 2367 4807 9615 14534 18939 28409 31250 95 (5F 16) 47 (2F16) 23 (1716) 95 (5F16) 47 (2F16) 31 (1F16) 23 (1716) 15 (F16) 600 1200 2400 4800 9600 14400 19200 28800 Actual time (bps) Type of error When the flag turns onDescription How to clear the flag

• This error occurs when the next data lines up before the content of the UARTi receive buffer register is read.
• The next data is written to the UARTi receive buffer register.
• The UARTi receive interrupt request bit does not go to “1”.
• This error occurs when the stop bit falls short of the set number of stop bits.
• With parity enabled, this error occurs when the total number of 1's in character bits and the parity bit is different from the specified number.
• This flag turns on when any error (overrun, framing, or parity) is detected. The error is detected when data is transferred from the UARTi receive register to the UARTi receive buffer register.
• Set the serial I/O mode select bits to “000 2”.
• Set the receive enable bit to “0”.
• When all error (overrun, framing, and parity) are removed, the flag is cleared.
• Set the serial I/O mode select bits to ”000 2”.
• Set the receive enable bit to “0”.
• Read the lower-order byte of the UARTi receive buffer register. Overrun error Framing error Parity error Error-sum flag

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer register, then receive the data again. To initialize the UARTi receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side, set the UARTi transmit buffer register again, then transmit the data again. To set the UARTi transmit buffer register again 1. Set the serial I/O mode select bits to “000 2” (invalidate serial I/O). 2. Set the serial I/O mode select bits again. 3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi transmit buffer register. (5) Functions selection In operating UART, the following functions can be used: (a) CTS/RTS function CTS function is a function in which an external IC can start transmission/reception by means of inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception starts, so if the level is gone to“ H” while transmission/reception is in progress, transmission/recep- tion stops at the next data. RTS function is a function to inform an external IC that RTS pin output level has changed to “L” when reception is ready. RTS regoes to “H” at the falling edge of the transfer clock. When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions.

• CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port.
• CTS function only enabled CTS/RTS pin performs the CTS function.
• RTS function only enabled CTS/RTS pin performs the RTS function. (b) Sleep mode Sleep mode is a mode in which data is transferred to a particular microcomputer among those con- nected by use of clock-asynchronous serial I/O devices. (c) Data logic select function This function is to reserve data when writing to transmit buffer register or reading from receive buffer register. The following are examples in which functions (a) to (c) are chosen:

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. (7) Pins related to the serial I/O

• CTS0, CTS1 pins :Input pins for the CTS function
• RTS0, RTS1 pins :Output pins for the RTS function
• CLK0, CLK1 pins :Input pins for the transfer clock
• RxD0, RxD1 pins :Input pins for data
• TxD0, TxD1 pins :Output pins for data/

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.3. UARTi-related registers (1) b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmission data Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate UARTi bit rate generator b7 b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by (n + 1) 0016 to FF16 Values that can be set Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b15) (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016 and 03A816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16 and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Reception data WR WR WR Reception data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.4. UARTi-related registers (2) WR U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t U i M R i A A 6 0 b B i t n a m eB i t s y m b o l M u s t b e f i x e d t o 0 0 1 S e r i a l I O i n v a l i d I n h i b i t e d I n h i b i t e d I n h i b i t e d b 2 b 1 b 0 C K D I R S M D 1 S M D 0 S e r i a l I / O m o d e s e l e c t b i t S M D 2 I n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t S T P S P R Y P R Y E S L E P P a r i t y e n a b l e b i t 0 : I n t e r n a l c l o c k E x t e r n a l c l o c k S t o p b i t l e n g t h s e l e c t b i t O d d / e v e n p a r i t y s e l e c t b i t S l e e p s e l e c t b i t 0 : O n e s t o p b i t T w o s t o p b i t s 0 : P a r i t y d i s a b l e d P a r i t y e n a b l e d 0 : S l e e p m o d e d e s e l e c t e d S l e e p m o d e s e l e c t e d 1 0 0 : T r a n s f e r d a t a 7 b i t s l o n g T r a n s f e r d a t a b i t s l o n g T r a n s f e r d a t a b i t s l o n g S e r i a l I O i n v a l i d I n h i b i t e d I n h i b i t e d I n h i b i t e d b 2 b 1 b 0 0 : I n t e r n a l c l o c k E x t e r n a l c l o c k I n v a l i d V a l i d w h e n b i t 6 = “ 1 ” O d d p a r i t y E v e n p a r i t y I n v a l i d I n v a l i d M u s t a l w a y s b e “ 0 ” F u n c t i o n D u r i n g U A R T m o d e F u n c t i o n D u r i n g c l o c k s y n c h r o n o u s s e r i a l I O m o d e U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 S y m b o lA d d r e s sW h e n r e s e t U i C i A A C 1 6 0 b F u n c t i o n D u r i n g U A R T m o d e F u n c t i o n D u r i n g c l o c k s y n c h r o n o u s s e r i a l I O m o d e T X E P T C L K 1 C L K 0 C R S C R D N C H C K P O L B R G c o u n t s o u r c e s e l e c t b i t T r a n s m i t r e g i s t e r e m p t y f l a g 0 : T r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e T r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e C L K p o l a r i t y s e l e c t b i t C T S / R T S f u n c t i o n s e l e c t b i t C T S / R T S d i s a b l e b i t D a t a o u t p u t s e l e c t b i t 0 0 : f1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b b 0 : L S B f i r s t M S B f i r s t 0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r d u r i n g t r a n s m i s s i o n N o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r t r a n s m i s s i o n c o m p l e t e d 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t U F O R MT r a n s f e r f o r m a t s e l e c t b i t 0 0 : f1 i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d I n h i b i t e d b b V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e V a l i d w h e n b i t 4 = “ 0 ” C T S f u n c t i o n i s s e l e c t e d N o t e R T S f u n c t i o n i s s e l e c t e d N o t e 0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r d u r i n g t r a n s m i s s i o n N o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r t r a n s m i s s i o n c o m p l e t e d 0 : T X D i p i n i s C M O S o u t p u t T X D i p i n i s N c h a n n e l o p e n d r a i n o u t p u t M u s t a l w a y s b e “ 0 ” B i t n a m eB i t s y m b o l M u s t a l w a y s b e “ 0 ” N o t e 1 : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . N o t e T h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d 0 : C T S / R T S f u n c t i o n e n a b l e d C T S R T S f u n c t i o n d i s a b l e d P a n d P f u n c t i o n a s p r o g r a m m a b l e I O p o r t WR

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.5. UARTi-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16, 03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Note: When using multiple pins to output the transfer clock, the following requirement must be met:

• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 X00000002 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WRFunction (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable UART1 continuous receive mode enable bit CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK1 only) 1 : Transfer clock output from multiple pins function selected 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM U1RRM Invalid Invalid Invalid CLK/CLKS select bit 1 (Note) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Reserved bit Must always be “0” Must always be “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the show the set-up procedures.

2.5.2 Operation of Serial I/O (transmission in UART mode)

Table 2.5.4. Choosed functions (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register readies the data transmissible status. (2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be con- trolled on the reception side). (3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit, and stop bit(s). (4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit goes to “1”. The transfer clock stops at “H” level. (5) If the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted. Operation Item Set-up Transfer clock source Internal clock (f1 / f8 / f32) External clock (CLKi pin) CTS function CTS function enabled CTS function disabled O O Transmission interrupt factor Transmission buffer empty Transmission completeO Sleep mode Sleep mode off Sleep mode selected O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example of wiring Example of operation Figure 2.5.6. Operation timing of transmission in UART mode TXDi CTSi R XD Port Microcomputer Receiver side IC Transmit enable bit (TE) Transmit buffer empty flag (Tl) Transmit register empty flag (TXEPT) D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P Start bit Parity bit TxDi CTSi “0” “1” “0” “1” “L” “H” “0” “1” Transmit interrupt request bit (IR) “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P SP D 0 D 1ST Shown in ( ) are bit symbols. SP Stopped pulsing because transfer enable bit = “0”Stop bit Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Tc Transfer clock When confirming stop bit, stopped transfer clock once because CTS = “H” Started transfer clock again to start transmitting immediately after confirming CTS = “L” (1) Transmission enabled (2) Confirme CTS (3) Start transmission (4) Confirme stop bit (5) Start transmission The above timing applies to the following settings :

• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.7. Set-up procedure of transmission in UART mode (1) Continued to the next page Setting UARTi transmit/receive mode register (i=0, 1) Internal/external clock select bit 0 : Internal clock Stop bit length select bit 0 : One stop bit b7 b0 0101 0 Odd/even parity select bit (Valid when bit 6 = “1”) 0 : Odd parity Parity enable bit 1 : Parity enabled Sleep select bit 0 : Invalid Serial I/O mode select bit 1 0 1 : Transfer data 8 bits long b2 b1 b0 010 UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A8 16] Setting UARTi transmit/receive control register 0 (i = 0, 1) UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC 16] Must be “0” in UART mode b7 b0 0000 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CTS/RTS disable bit 0 : CTS/RTS function enabled Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “0” in UART mode Setting UART transmit/receive control register 2 UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must be “0” in UART mode UART1 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Invalid in UART mode Invalid in UART mode Invalid in UART mode Reserved bit Fix “0” to this bit. b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.8. Set-up procedure of transmission in UART mode (2) Start transmission When CTSi input level = “L” Setting UARTi bit rate generator (i = 0, 1) UARTi bit rate generator (i = 0, 1) [Address 03A116, 03A916] UiBRG (i = 0, 1) Can be set to 0016 to FF16 (Note) b7 b0 Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmission is complete Continued from the previous page UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit enable bit 1 : Transmission enabled b7 b0 Transmission enabled Writing transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8) UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 b7 b0 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Checking the status of UARTi transmit/receive control (i = 0, 1) Writing next transmit data UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data b7 b0 b7 b0 (b15) (b8)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In receiving data in UART mode, choose functions from those listed in Table 2.5.5. Operations of the 2.5.11 show the set-up procedures.

2.5.3 Operation of Serial I/O (reception in UART mode)

Table 2.5.5. Choosed functions (1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from the RTSi pin goes to “L” level to inform the transmission side that the receivable status is ready. (2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s). (3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the UARTi receive interrupt request bit goes to “1”, and output from the RTS pin goes to “L” level. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi receive buffer register is read. Operation Item Set-up Transfer clock source Internal clock (f1 / f8 / f32) External clock (CLKi pin) RTS function RTS function enabled RTS function disabled O O Sleep mode Sleep mode off Sleep mode selected O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Example of wiring Example of operation Figure 2.5.9. Operation timing of reception in UART mode R XDi RTSi TXD Port Microcomputer Transmitter side IC CLKi CLK D 0 D 1 D 7Start bit Reception started when transfer clock is generated by falling edge of start bit Sampled “L” Receive data taken in BRGi's count source Receive enable bit RxD i Transfer clock Receive complete flag RTS i Stop bit “1” “0” “0” “1” “H” “L” Timing of transfer data 8 bits long applies to the following settings :

• Transfer data length is 8 bits.
• Parity is disabled.
• One stop bit
• RTS function is selected. Receive interrupt request bit “0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transferred from UARTi receive register to UARTi receive buffer register (1) Reception enabled (2) Start reception (4) Data is read (3) Receiving is completed

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.10. Set-up procedure of reception in UART mode (1) Continued to the next page UART transmit/receive control register 2 [Address 03B016] UCON Invalid in UART mode Must be fixed to “0” in UART mode Invalid in UART mode Invalid in UART mode Reserved bit Fix “0” to this bit. b7 b0 Setting UART transmit/receive control register 2 Setting UARTi transmit/receive mode register (i=0, 1) Internal/external clock select bit 1 : External clock UART0 transmit/receive mode register [Address 03A0 16] U0MR UART1 transmit/receive mode register [Address 03A8 16] U1MR Valid when bit 6 = “1” Parity enable bit 0 : Parity diabled b7 b0 0101 1 Sleep select bit 0 : Sleep mode deselected Serial I/O mode select bit 1 0 1 : Transfer data 8 bits long b2 b1 b0 Stop bit length select bit 0 : One stop bit Setting UARTi transmit/receive control register 0 (i=0, 1) Must be fixed to “0” in UART mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be fixed to “0” in UART mode Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output UART0 transmit/receive control register 0 [Address 03A416] U0C0 UART1 transmit/receive control register 0 [Address 03AC16] U1C0 b7 b0 0100 BRG count source select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Inhibited b1 b0 CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected CTS/RTS disable bit 0 : CTS/RTS function enabled

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.5.11. Set-up procedure of reception in UART mode (2) Start reception Processing after reading out reception data Continued from the previous page Checking error UART0 receive buffer register [Address 03A716, 03A616]U0RB UART1 receive buffer register [Address 03AF16, 03AE16]U1RB Overrun error flag 0 : No overrun error 1 : Overrun error found b7 b0 b7 b0 (b15) (b8) Receive data Framing error flag 0 : No framing error 1 : Framing error found Parity error flag 0 : No parity error 1 : Parity error found Error sum flag 0 : No error 1 : Error found Setting UARTi bit rate generator (i = 0, 1) UARTi bit rate generator (i = 0, 1) [Address 03A116, 03A916] UiBRG (i = 0, 1) Can be set to 0016 to FF16 b7 b0 Reception enabled UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 b7 b0 Receive enable bit 1 : Reception enabled Checking completion of reception UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 b7 b0 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Note: Write to UARTi bit rate generator when transmission/reception is halted.

2.6 Serial I/O2

2.6.1 Overview

Serial I/O2 performs 8-bit data serial communication, synchronized with the clocks. In the automatic transfer serial I/O mode, serial communication of up to 256 bytes can be continuously performed without use of the CPU. The following is the Serial I/O2 overview. (1) Transfer format Transfer format is 8-bit data. (2) Transfer rate When selecting an internal clock as the transfer clock, the transfer rate is the division ratio selected by the internal synchronous clock selection bits. Any one of f(X IN)/4, f(XIN)/8, f(XIN)/16, f(XIN)/32, f(XIN)/64, f(XIN)/128 or f(XIN)/256 can be selected by the internal synchronous clock selection bits. When selecting an external clock as the transfer clock, the transfer rate is the frequency of the clock input to the CLK pin. (3) Automatic transfer serial I/O mode Clock synchronous communication, which does not depend on the CPU, can be continuously per- formed up to 256 bytes. (4) Selection function The following selection functions can be applied to Serial I/O2. (a) S STB2 output (for selecting internal synchronous clock)

• STB function invalid: SSTB2 output pin is used as a programmable I/O pin.
• STB function valid: SSTB2 output pin functions as SSTB2 or SSTB2 output. (b) SBUSY2 input/output
• SBUSY2 input/output function invalid: SBUSY2 pin is used as a programmable I/O pin.
• SBUSY2 input/output function valid: SBUSY2 pin functions as input/output of SBUSY2 or SBUSY2 . (c) SRDY2 input/output
• SRDY2 input/output function invalid: SRDY2 pin is used as a programmable I/O pin.
• SRDY2 input/output function valid: SRDY2 pin functions as input/output of SRDY2 or SRDY2 . (d) SOUT2 P-channel output disable (invalid for P94 as I/O port) The SOUT2 output pin can be switched between C-MOS 3 state and N-channel open-drain when in the 8-bit or the automatic transfer serial I/O mode. The mode is selected by the serial transfer select bits. (e) LSB first/MSB first This function switches the starting bit for the transmission/reception; either bit 0 or bit 7. The following two types can be selected with the transfer direction select bit:
• LSB first: transmission/reception begins with from bit 0.
• MSB first: transmission/reception begins with from bit 7.

(f) Transfer mode Either the full duplex mode or the transmit-only mode can be selected. The SIN2 pin can be used as a programmable input/output port in the transmit-only mode. (g) Plural transfer clock input/output pin This function switches the pins for transfer clock input/output. By switching the transfer clock pins, data can be transmitted/received to two external ICs in a time-sharing manner. (h) S OUT2 pin control This pin selects either output active (value of last transmitted data or undefined value) or high-imped- ance as the S OUT2 pin state for non-transfer periods (i.e. before and after serial transfers). (5) Input to serial I/O2 and direction register When inputting external signals to Serial I/O2, set the corresponding port direction register to input. (6) Serial I/O2-related pins (a) SSTB2 pin: Output pin for STB and STB functions. (b) SBUSY2 pin: Input/output pin for BUSY and BUSY functions. (c) SRDY2 pin: Input/output pin for RDY and RDY functions. (d) SCLK21 , SCLK22 pins: Input/output pins for transfer clocks. Pin is selectable by user. (e) SIN2 pin: Data input pin. (f) SOUT2 pin: Data output pin.

Figure 2.6.2. Serial I/O2 related-registers (1) S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 S y m b o lA d d r e s sW h e n r e s e t S I O C O N 6 0 B i t n a m eF u n c t i o n RB i t s y m b o l W b 4 b SR D Y 2 • SB U S Y 2 p i n c o n t r o l b i t sS C O N 2 0 S C O N 2 1 S C O N 2 2 S C O N 2 3 S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 S y m b o lA d d r e s sW h e n r e s e t S I O C O N 6 0 B i t n a m eF u n c t i o nB i t s y m b o l R W b S e r i a l t r a n s f e r s e l e c t b i t sS C O N 1 0 S C O N 1 1 S C O N 1 2 S C O N 1 3 S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t b i t s SS T B p i n c o n t r o l b i t 0 0 : I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t E x t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n SS T B o u t p u t I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n SS T B o u t p u t 0 : S e r i a l I / O i n i t i a l i z a t i o n S e r i a l I O e n a b l e d S e r i a l I / O i n i t i a l i z a t i o n b i t T r a n s f e r m o d e s e l e c t b i t 0 : F u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e SI N p i n i s a SI N i n p u t T r a n s m i t o n l y m o d e SI N p i n i s a n I O p o r t S C O N 1 4 S C O N 1 5 S e r i a l I / O 2 c l o c k p i n s e l e c t b i t T r a n s f e r d i r e c t i o n s e l e c t b i tS C O N 1 6 S C O N 1 7 0 0 : S e r i a l I / O d i s a b l e d s e r i a l I O p i n s a r e I O p o r t s b i t s s e r i a l I O I n h i b i t A u t o m a t i c t r a n s f e r s e r i a l I O b i t s 0 : L S B f i r s t M S B f i r s t 0 : SC L K 1 ( SC L K p i n i s a n I O p o r t SC L K 2 ( SC L K p i n i s a n I O p o r t 0 : F u n c t i o n s a s e a c h 1 - b y t e s i g n a l F u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a SB U S Y 2 o u t p u t • SS T B 2 o u t p u t f u n c t i o n s e l e c t b i t V a l i d i n a u t o m a t i c t r a n s f e r m o d e S e r i a l t r a n s f e r s t a t u s f l a g 0 : S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g S C O N 2 4 S C O N 2 5 SO U T d i s a b l e b i t SO U T 2 p i n c o n t r o l b i t a t n o t r a n s f e r s e r i a l d a t a )S C O N 2 6 S C O N 2 7 0 : O u t p u t a c t i v e O u t p u t h i g h i m p e d a n c e 0 : C M O S 3 - s t a t e P c h a n n e l o u t p u t i s v a l i d N c h a n n e l o p e n d r a i n P c h a n n e l o u t p u t i s i n v a l i d b b b b SR D Y 2 p i nS B U S Y 2 p i n I O p o r tI O p o r t N o t u s e d SR D Y o u t p u tI O p o r t SR D Y o u t p u tI O p o r t I O p o r tS B U S Y i n p u t I O p o r tS B U S Y i n p u t I O p o r tS B U S Y o u t p u t I O p o r tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y i n p u tS B U S Y o u t p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t SR D Y o u t p u tS B U S Y i n p u t b b b b

Serial I/O2 control register 3 Symbol Address When reset SIO2CON3 0348 16 000000002 Bit name FunctionBit symbol RW b7 b6 b5 b4 b3 b2 b1 b0 Automatic transfer interval set bits TTRAN0 TTRAN1 TTRAN2 TTRAN3 Internal synchronous clock selection bits 000:f(XIN)/4 001:f(XIN)/8 010:f(XIN)/16 011:f(XIN)/32 100:f(XIN)/64 101:f(XIN)/128 110:f(XIN)/256 TTRAN4 TCLK0 TCLK1 TCLK2 00000 :2 cycles of transfer clocks 00001 :3 cycles of transfer clocks 11110 :32 cycles of transfer clocks 11111 :33 cycles of transfer clocks Data is written to a latch and read from a decrement counter. b4b3b2b1b0 b7b6b5 Serial I/O2 automatic transfer data pointer Symbol Address When reset SIO2DP 0340 16 0016 Function R W b7 b6 b5 b4 b3 b2 b1 b0

• Automatic transfer data pointer set Specify the low-order 8 bits of the first data store address on the serial I/O automatic transfer RAM. Data is written into the latch and read from the decrement counter. Serial I/O2 register/transfer counter Symbol Address When reset SIO2 0346 16 0016 Function R W b7 b6 b5 b4 b3 b2 b1 b0
• Number of automatic transfer data set Set the number of automatic transfer data. Set a value one less than number of transfer data. Data is written into the latch and read from the decrement counter. Figure 2.6.3. Serial I/O2 related-registers (2)

2.6.2 Serial I/O2 connection examples

(1) Control of peripheral IC equipped with CS pin Figure 2.6.4 shows connection examples with peripheral ICs which have the CS pin. The automatic transfer function can be used in all examples. SB U S Y SC L K SO U T SI N C S C L K I N O U T SB U S Y SC L K SO U T C S C L K D A T A O n l y t r a n s m i s s i o n U s i n g SI N p i n a s I O p o r t SB U S Y SC L K SO U T SI N C S C L K I N O U T P o r t SC L K SO U T SI N P o r t C S C L K I N O U T C S C L K I N O U T M g r o u p P e r i p h e r a l I C O S D c o n t r o l l e r e t c T r a n s m i s s i o n a n d r e c e p t i o n M g r o u pP e r i p h e r a l I C E E P R O M e t c T r a n s m i s s i o n a n d r e c e p t i o n W h e n c o n n e c t i n g SI N w i t h SO U T W h e n c o n n e c t i n g I N w i t h O U T i n p e r i p h e r a l I C M g r o u p]1 P e r i p h e r a l I C ] 2 E E P R O M e t c C o n n e c t i o n o f p l u r a l I C M g r o u p P e r i p h e r a l I C P e r i p h e r a l I C S e l e c t a n N c h a n n e l o p e n d r a i n o u t p u t f o r SO U T p i n o u t p u t c o n t r o l U s e t h e O U T p i n o f p e r i p h e r a l I C w h i c h i s a n N c h a n n e l o p e n d r a i n o u t p u t a n d b e c o m e s h i g h i m p e d a n c e d u r i n g r e c e i v i n g d a t a N o t e : “ P o r t ” m e a n s a n o u t p u t p o r t c o n t r o l l e d b y s o f t w a r e . Figure 2.6.4. Serial I/O2 onnection examples (1)

2.6.3 Serial I/O2 modes

Figure 2.6.6 shows Serial I/O2 modes. S e r i a l I / O 2 8 - b i t s e r i a l I O A u t o m a t i c t r a n s f e r s e r i a l I O I n t e r n a l c l o c k U s i n g h a n d s h a k e s i g n a l E x t e r n a l c l o c k O u t p u t SR D Y 2 ] s i g n a l F u l l d u p l e x m o d e T r a n s m i t - o n l y m o d e N o t u s i n g h a n d s h a k e s i g n a l U s i n g h a n d s h a k e s i g n a l N o t u s i n g h a n d s h a k e s i g n a l I np u t SR D Y 2 ] s i g n a l o t O u t p u t SB U S Y2 ] s i g n a l I np u t SB U S Y2 ] s i g n a l O u t p u t SS T B2 ] s i g n a l O u t p u t SR D Y 2 ] s i g n a l I np u t SR D Y 2 ] s i g n a l o t O u t p u t SB U S Y2 ] s i g n a l I np u t SB U S Y2 ] s i g n a l N o t e T h i s i s o n l y v a l i d w h e n o u t p u t t i n g t h e SB U S Y s i g n a l A c t i v e l o g i c c a n a p p l y t o e a c h s i g n a l o f SR D Y SB U S Y SS T B Figure 2.6.6. Serial I/O2 modes

2.6.4 Serial I/O2 Operations (transmission in 8-bit serial I/O mode)

The functions listed in Table 2.6.1 can be selected in the 8-bit serial I/O mode for Serial I/O2 transmission/ reception. Operations of the circled items are described below. Figure 2.6.7 shows the operation timing, Operation (1) Serial I/O2 becomes transmission-enabled with the following settings: serial transfer select bits SCON10 to “1” and SCON11 to “0”; transfer mode select bit (SCON15) to “1”; serial I/O initialization bit (SCON14) to “1”. (2) When transmission data is written to the serial I/O2 register, transmission starts and the serial transfer status flag is set to “1”. (3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. (4) When one-byte data transmission is completed, the serial transfer status flag is set to “0” to indicate the transmission completion. The transfer clock stops at “H” level. (5) Continuous transmission can be performed by setting the next transmission data in the serial I/O2 register during transmission, before output of the 8th bit. I t e mS e t - u pS e t - u p O I t e m T r a n s f e r c l o c k s o u r c e I n t e r n a l c l o c k ( f1 / f8 / f3 A u t o m a t i c t r a n s f e r s e r i a l I O S e l e c t e d O OSS T B 2 o u t p u t f u n c t i o n O O T r a n s f e r d i r e c t i o n E xt e r n a l c l o c k ( C L Ki p i n ) N o t s e l e c t e d N o t s e l e c t e d SS T B 2 ( “ H ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d SS T B 2 ( “ L ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d L S B f i r s tO MS B f i r s t SB U S Y2 f u n c t i o n N o t s e l e c t e d SB U S Y 2 i n p u t SB U S Y2 o u t p u t ( “ H ” a t s t o p r e q u i r e d SB U S Y2 o u t p u t ( “ L ” a t s t o p r e q u i r e d SR D Y2 f u n c t i o n N o t s e l e c t e d SR D Y 2 i n p u t SR D Y 2 o u t p u t SR D Y2 o u t p u t ( “ H ” a t r e a d y ) SR D Y2 o u t p u t ( “ L ” a t r e a d y ) Table 2.6.1. Selectable functions

Figure 2.6.7. Operation timing of transmission in 8-bit serial I/O mode, using plural transfer clock output function output SB U S Y SC L K SO U T C S C L K D A T A “1 ” “0 ” “H ” “L ” D 0 TC D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SO U T ( 2 ) T r a n s m i s s i o n s t a r t( 4 ) T r a n s m i s s i o n i s c o m p l e t e d M g r o u pP e r i p h e r a l I C C o n n e c t i o n e x a m p l e O p e r a t i o n e x a m p l e I n t e r n a l c l o c k S e r i a l t r a n s f e r s t a t u s f l a g b i t o f a d d r e s s SB U S Y 2 ( o u t p u t ) SC L K o u t p u t T c : I n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 81 T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : I n t e r n a l c l o c k i s s e l e c t e d b i t s e r i a l I O m o d e SB U S Y o u t p u t t i m i n g E a c h b y t e

Figure 2.6.8. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer clock output function output (1) 0 0 1 0 0 0 0 0 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p C o n t i n u e d t o t h e n e x t p a g e S e r i a l t r a n s f e r s e l e c t b i t s b b S e r i a l I O d i s a b l e d s e r i a l I O p i n s a r e I O p o r t s S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b b I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t S e r i a l I / O i n i t i a l i z a t i o n b i t S e r i a l I O i n i t i a l i z a t i o n T r a n s f e r m o d e s e l e c t b i t T r a n s m i t o n l y m o d e SI N p i n i s a n I O p o r t T r a n s f e r d i r e c t i o n s e l e c t b i t L S B f i r s t S e r i a l I / O 2 c l o c k p i n s e l e c t b i t SC L K SC L K p i n i s a n I O p o r t 0 0 0 1 1 0 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p SR D Y 2 • SB U S Y 2 p i n c o n t r o l b i t s b b b b 0 1 1 0 SR D Y p i n a s I O p o r t SB U S p i n a s SB U S Y o u t p u t SB U S Y 2 o u t p u t • SS T B 2 o u t p u t f u n c t i o n s e l e c t b i t F u n c t i o n s a s e a c h b y t e s i g n a l S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g SO U T 2 p i n c o n t r o l b i t O u t p u t a c t i v e SO U T

2 P - c h a n n e l o u t p u t d i s a b l e b i t

C M O S s t a t e P c h a n n e l o u t p u t i s v a l i d 0 1 1 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p A u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b b b b b 0 0 0 0 c y c l e s o f t r a n s f e r c l o c k s 0 0 0 1 c y c l e s o f t r a n s f e r c l o c k s 1 1 1 0 c y c l e s o f t r a n s f e r c l o c k s 1 1 1 1 c y c l e s o f t r a n s f e r c l o c k s I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b b b 0 1 1 f XI N ) 0 1 S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p S e r i a l t r a n s f e r s e l e c t b i t s b b b i t s e r i a l I O d i s a b l e d

Figure 2.6.9. Set-up procedure for transmission in 8-bit serial I/O mode, using plural transfer clock output function output (2) b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N E n a b l i n g tr a n s m i s s i o n T r a n s m i s s i o n i s c o m p l e t e d S e r i a l I / O i n i t i a l i z a t i o n b i t ( N o t e ) S e r i a l I O e n a b l e d b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N C o n f i r m a t i o n o f c o m p l e t e t r a n s m i s s i o n S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g N o t e A f t e r s e t t i n g t h e s e r i a l t r a n s f e r s e l e c t b i t s p e r f o r m t h i s s e t u p b S e r i a l I O r e g i s t e r A d d r e s s S I O W r i t i n g t r a n s m i s s i o n d a t a S e t t r a n s m i s s i o n d a t a F r o m t h e p r e v i o u s p a g e

2.6.5 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O mode)

The functions listed in Table 2.6.2 can be selected in the automatic transfer serial I/O mode for Serial I/O2 transmission/reception. Operations of the circled items are described below. Figure 2.6.10 shows the Operation(1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2 transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts. (2) The transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. The reception data is received bit by bit from the upper bits, synchronized with each rising edge. (3) When eight-byte data transmission/reception is completed, the serial transfer status flag is set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H” level. Table 2.6.2. Selectable functions I t e mS e t - u pS e t - u p O I t e m T r a n s f e r c l o c k s o u r c e I n t e r n a l c l o c k ( f1 / f8 / f3 A u t o m a t i c t r a n s f e r s e r i a l I O S e l e c t e dO O SS T B 2 o u t p u t f u n c t i o n O O T r a n s f e r d i r e c t i o n E xt e r n a l c l o c k ( C L Ki p i n ) N o t s e l e c t e d N o t s e l e c t e d SS T B 2 ( “ H ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d SS T B 2 ( “ L ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d L S B f i r s tO MS B f i r s t SB U S Y2 f u n c t i o n N o t s e l e c t e d SB U S Y 2 i n p u t SB U S Y2 o u t p u t ( “ H ” a t s t o p r e q u i r e d SB U S Y2 o u t p u t ( “ L ” a t s t o p r e q u i r e d SR D Y2 f u n c t i o n N o t s e l e c t e d SR D Y 2 i n p u t SR D Y 2 o u t p u t SR D Y2 o u t p u t ( “ H ” a t r e a d y ) SR D Y2 o u t p u t ( “ L ” a t r e a d y )

Figure 2.6.10. Operation timing of transmission/reception in automatic transfer serial I/O mode SC L K SO U T SI N C L K SI N SO U T M g r o u pP e r i p h e r a l I C TC SC L K SI N SO U T “ 1 ” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 ( 1 ) T r a n s m i s s i o n / r e c e p t i o n s t a r t ( 3 ) T r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d S e r i a l t r a n s f e r s t a t u s f l a g b i t o f a d d r e s s T c : I n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 81 T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : I n t e r n a l c l o c k i s s e l e c t e d A u t o m a t i c t r a n s f e r s e r i a l I O m o d e T r a n s f e r c l o c k “ 0 ” W r i t i n g t o s e r i a l I / O 2 t r a n s f e r c o u n t e r a d d r e s s “ 1 ” “ 0 ” S e r i a l I / O 2 i n t e r r u p t r e q u e s t T r a n s f e r i n t e r v a lT r a n s f e r i n t e r v a l T r a n s m i s s i o n / r e c e p t i o n o f t h e s e c o n d b y t e T r a n s m i s s i o n / r e c e p t i o n o f t h e e i g h t h b y t e C l e a r e d t o “ 0 ” w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e Connection example Operation example

Figure 2.6.11. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1) 0 0 0 0 0 0 0 0 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p C o n t i n u e d t o t h e n e x t p a g e S e r i a l t r a n s f e r s e l e c t b i t s b b S e r i a l I O d i s a b l e d s e r i a l I O p i n s a r e I O p o r t s S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b b I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t S e r i a l I / O i n i t i a l i z a t i o n b i t S e r i a l I O i n i t i a l i z a t i o n T r a n s f e r m o d e s e l e c t b i t F u l l d u p l e x t r a n s m i t a n d r e c e i v e m o d e SI N p i n i s a SI N i n p u t T r a n s f e r d i r e c t i o n s e l e c t b i t L S B f i r s t S e r i a l I / O 2 c l o c k p i n s e l e c t b i t SC L K SC L K p i n i s a n I O p o r t 0 0 0 0 0 0 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p SR D Y 2 • SB U S Y 2 p i n c o n t r o l b i t s b b b b 0 0 0 0 SR D Y p i n a n d SB U S p i n a s I O p o r t SB U S Y 2 o u t p u t • SS T B 2 o u t p u t f u n c t i o n s e l e c t b i t F u n c t i o n s a s e a c h b y t e s i g n a l F u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g SO U T 2 p i n c o n t r o l b i t O u t p u t a c t i v e SO U T C M O S s t a t e P c h a n n e l o u t p u t i s v a l i d 0 1 1 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p A u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b b b b b 0 0 0 0 c y c l e s o f t r a n s f e r c l o c k s I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b b b 0 1 1 f XI N ) 1 1 S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p S e r i a l t r a n s f e r s e l e c t b i t s b b A u t o m a t i c t r a n s f e r s e r i a l I O b i t 00000

Figure 2.6.12. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2) b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N E n a b l i n g tr a n s m i s s i o n T r a n s m i s s i o n r e c e p t i o n i s c o m p l e t e d S e r i a l I / O i n i t i a l i z a t i o n b i t S e r i a l I O e n a b l e d b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N C o n f i r m a t i o n o f c o m p l e t e a u t o m a t i c t r a n s m i s s i o n S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g b A u t o m a t i c t r a n s f e r R A M A d d r e s s e s t o F W r i t i n g t r a n s m i s s i o n d a t a S e t t r a n s m i s s i o n d a t a f o r t r a n s m i s s i o n b y t e n u m b e r b y t e s t o a d d r e s s e s t o T h e a r e a f r o m a d d r e s s e s t o F w h i c h i s n o t u s e d i n t h i s e x a m p l e c a n b e u s e d a s g e n e r a l p u r p o s e R A M b S e r i a l I O a u t o m a t i c t r a n s f e r d a t a p o i n t e r A d d r e s s S I O D P S e r i a l I O a u t o m a t i c t r a n s f e r d a t a p o i n t e r S e t t h e l o w e r 8 b i t s ( 0 71 6) o f a d d r e s s 0 4 0 71 6 ( N o t e ) N o t e S p e c i f y t h e l o w e r b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l I O a u t o m a t i c t r a n s f e r R A M W h e n s e t t i n g a v a l u e w r i t e a t n o n t r a n s m i s s i o n r e c e p t i o n F r o m t h e p r e v i o u s p a g e 11100000 b S e r i a l I O t r a n s f e r c o u n t e r A d d r e s s S I O A u t o m a t i c t r a n s f e r s t a r t S e t T r a n s f e r b y t e n u m b e r W r i t i n g t o t h i s r e g i s t e r s t a r t s a u t o m a t i c t r a n s f e r O t h e r p r o c e s s e s c a n b e p e r f o r m e d w h i l e a u t o m a t i c t r a n s f e r i s b e i n g p e r f o r m e d b A u t o m a t i c t r a n s f e r R A M A d d r e s s e s t o F T a k i n g i n r e c e p t i o n d a t a T a k e i n r e c e p t i o n d a t a a t a d d r e s s e s t o i n t o t h e R A M f o r p r o c e s s

2.6.6 Serial I/O2 Operations (transmission/reception in automatic transfer serial I/O

mode, using handshake signal) The functions listed in Table 2.6.3 can be selected in the automatic transfer serial I/O mode for Serial I/O2 transmission/reception. Operations of the circled items are described below. Figure 2.6.13 shows the Operation(1) After setting the relevant registers, by writing the transfer byte number to the serial I/O2 transfer counter, the serial transfer status flag is set to “1” and automatic transfer starts. S RDY2 output simultaneously goes to “H” level. (2) When “L” level is input to the SBUSY2 pin, the SRDY2 output goes to “L” level, synchronized with the falling edge of the transfer clock, and the serial transfer starts. (3) The transmission data is transmitted bit by bit from the lower bits, synchronized with each falling edge. The reception data is received bit by bit from the upper bits, synchronized with each rising edge. (4) When sixteen-byte data transmission/reception is completed, the serial transfer status flag is set to “0” to indicate the transmission/reception completion. The transfer clock stops at “H” level. Table 2.6.3. Selectable functions I t e mS e t - u pS e t - u p O I t e m T r a n s f e r c l o c k s o u r c e I n t e r n a l c l o c k ( f1 / f8 / f3 A u t o m a t i c t r a n s f e r s e r i a l I O S e l e c t e dO O SS T B 2 o u t p u t f u n c t i o n O O T r a n s f e r d i r e c t i o n E xt e r n a l c l o c k ( C L Ki p i n ) N o t s e l e c t e d N o t s e l e c t e d SS T B 2 ( “ H ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d SS T B 2 ( “ L ” a t t r a n s m i s s i o n / r e c e p t i o n c o m p l e t e d L S B f i r s tO MS B f i r s t SB U S Y2 f u n c t i o n N o t s e l e c t e d SB U S Y 2 i n p u t SB U S Y2 o u t p u t ( “ H ” a t s t o p r e q u i r e d SB U S Y2 o u t p u t ( “ L ” a t s t o p r e q u i r e d SR D Y2 f u n c t i o n N o t s e l e c t e d SR D Y 2 i n p u t SR D Y 2 o u t p u t SR D Y2 o u t p u t ( “ H ” a t r e a d y ) SR D Y2 o u t p u t ( “ L ” a t r e a d y )

Figure 2.6.13. Operation timing of transmission/reception in automatic transfer serial I/O mode Connection example Operation example C L K2 SO U T SI N C L K I N O U T SR D Y 2 R D Y SB U S Y 2 B U S Y M g r o u pP e r i p h e r a l I C SC L K SI N SO U T SR D Y SB U S Y D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D4 D5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D4 D5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 TC ( 2 ) T r a n s m i s s i o n / r e c e p t i o n s t a r t ( 4 ) T r a n s m i s s i o n / r e c e p t i o n i s c o m p l e t e d S e r i a l t r a n s f e r s t a t u s f l a g b i t o f a d d r e s s T c : I n t e r n a l s y n c h r o n o u s c l o c k w h i c h i s s e l e c t e d w i t h b i t s 5 t o 7 o f a d d r e s s 0 3 4 81 T h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : I n t e r n a l c l o c k i s s e l e c t e d A u t o m a t i c t r a n s f e r s e r i a l I O m o d e T r a n s f e r c l o c k W r i t i n g t o s e r i a l I / O 2 t r a n s f e r c o u n t e r a d d r e s s S e r i a l I / O 2 i n t e r r u p t r e q u e s t T r a n s f e r i n t e r v a lT r a n s f e r i n t e r v a l T r a n s m i s s i o n / r e c e p t i o n o f t h e s e c o n d b y t e T r a n s m i s s i o n / r e c e p t i o n o f t h e s i x t e e n t h b y t e C l e a r e d t o “ 0 ” w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d , o r c l e a r e d b y s o f t w a r e ( 1 ) A u t o m a t i c t r a n s f e r s t a r t “ 1 ” “ 0 ” “ 1 ” “ 0 ”

Figure 2.6.14. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (1) 0 0 0 0 0 0 0 0 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p C o n t i n u e d t o t h e n e x t p a g e S e r i a l t r a n s f e r s e l e c t b i t s b b S e r i a l I O d i s a b l e d s e r i a l I O p i n s a r e I O p o r t s S e r i a l I / O 2 s y n c h r o n o u s c l o c k s e l e c t b i t s b b I n t e r n a l s y n c h r o n o u s c l o c k SS T B p i n i s a n I O p o r t S e r i a l I / O i n i t i a l i z a t i o n b i t S e r i a l I O i n i t i a l i z a t i o n T r a n s f e r m o d e s e l e c t b i t F u l l d u p l e x t r a n s m i t a n d r e c e i v e m o d e SI N p i n i s a SI N i n p u t T r a n s f e r d i r e c t i o n s e l e c t b i t L S B f i r s t S e r i a l I / O 2 c l o c k p i n s e l e c t b i t SC L K SC L K p i n i s a n I O p o r t 0 0 1 1 1 1 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p SR D Y 2 • SB U S Y 2 p i n c o n t r o l b i t s b b b b 1 1 1 1 SR D Y p i n a s SR D Y o u t p u t SB U S p i n a s SB U S Y i n p u t SB U S Y 2 o u t p u t • SS T B 2 o u t p u t f u n c t i o n s e l e c t b i t F u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g SO U T 2 p i n c o n t r o l b i t O u t p u t a c t i v e SO U T C M O S s t a t e P c h a n n e l o u t p u t i s v a l i d 0 1 1 b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p A u t o m a t i c t r a n s f e r i n t e r v a l s e t b i t s b b b b b 0 0 0 0 c y c l e s o f t r a n s f e r c l o c k s I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s b b b 0 1 1 f XI N ) 1 1 S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N S e r i a l I O c o n t r o l r e g i s t e r s e t u p S e r i a l t r a n s f e r s e l e c t b i t s b b A u t o m a t i c t r a n s f e r s e r i a l I O b i t 00000

Figure 2.6.15. Set-up procedure for transmission/reception in automatic transfer serial I/O mode (2) b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N E n a b l i n g tr a n s m i s s i o n T r a n s m i s s i o n r e c e p t i o n i s c o m p l e t e d S e r i a l I / O i n i t i a l i z a t i o n b i t S e r i a l I O e n a b l e d b S e r i a l I O c o n t r o l r e g i s t e r A d d r e s s S I O C O N C o n f i r m a t i o n o f c o m p l e t e a u t o m a t i c t r a n s m i s s i o n S e r i a l t r a n s f e r s t a t u s f l a g S e r i a l t r a n s f e r c o m p l e t i o n S e r i a l t r a n s f e r r i n g b A u t o m a t i c t r a n s f e r R A M A d d r e s s e s t o F W r i t i n g t r a n s m i s s i o n d a t a S e t t r a n s m i s s i o n d a t a f o r t r a n s m i s s i o n b y t e n u m b e r b y t e s t o a d d r e s s e s t o T h e a r e a f r o m a d d r e s s e s t o F w h i c h i s n o t u s e d i n t h i s e x a m p l e c a n b e u s e d a s g e n e r a l p u r p o s e R A M b S e r i a l I O a u t o m a t i c t r a n s f e r d a t a p o i n t e r A d d r e s s S I O D P S e r i a l I O a u t o m a t i c t r a n s f e r d a t a p o i n t e r S e t 0 F1 6 ( N o t e ) N o t e S p e c i f y t h e l o w e r b i t s o f t h e f i r s t d a t a s t o r e a d d r e s s o n t h e s e r i a l I O a u t o m a t i c t r a n s f e r R A M W h e n s e t t i n g a v a l u e w r i t e a t n o n t r a n s m i s s i o n r e c e p t i o n F r o m t h e p r e v i o u s p a g e 11110000 b S e r i a l I O t r a n s f e r c o u n t e r A d d r e s s S I O A u t o m a t i c t r a n s f e r s t a r t S e t T r a n s f e r b y t e n u m b e r W r i t i n g t o t h i s r e g i s t e r s t a r t s a u t o m a t i c t r a n s f e r O t h e r p r o c e s s e s c a n b e p e r f o r m e d w h i l e a u t o m a t i c t r a n s f e r i s b e i n g p e r f o r m e d b A u t o m a t i c t r a n s f e r R A M A d d r e s s e s t o F T a k i n g i n r e c e p t i o n d a t a T a k e i n r e c e p t i o n d a t a a t a d d r e s s e s t o i n t o t h e R A M f o r p r o c e s s

2.6.7 Precautions for Serial I/O2

(1) Clock (a) Using internal clock After setting the synchronous clock to an internal clock, clear the serial I/O interrupt request bit before performing a normal serial I/O transfer or a serial I/O automatic transfer. (b) Using external clock After inputting “H” level to the external clock input pin, clear the serial I/O interrupt request bit before performing a normal serial I/O transfer or a serial I/O automatic transfer. (2) Using Serial I/O2 interrupt Clear bit 3 of the interrupt control register to “0” by software before enabling interrupts. (3) State of S OUT2 pin The SOUT2 pin control bit of the serial I/O2 control register 2 can be used to select the SOUT2 pin state for non-transfer periods. Either output active or high-impedance can be selected. However, when using an external synchronous clock, set the S OUT2 pin control bit to “1” while the serial I/O2 clock input is in “H” level (after transfer completion) in order to put the SOUT2 pin in the high-impedance state. (4) Serial I/O initialization bit

• To terminate a serial transfer while transferring, set “0” to the serial I/O initialization bit of the serial I/O2 control register 1.
• When “1” is written to the serial I/O initialization bit, Serial I/O2 is enabled, however, each register is not initialized. The value of each register needs to be set by software. (5) Handshake signal (a) SBUSY2 input signal Input “H” level to the SBUSY2 input and “L” level to the SBUSY2 input in the initial state. When using the external synchronous clock, switch the input level to the SBUSY2 input and the SBUSY2 input while the serial I/O2 clock input is in “H” level. (b) SRDY2 input/output signal When using the internal synchronous clock, input “L” level to the SRDY2 input and “H” level to the SRDY2 input in the initial state. (6) In 8-bit serial I/O mode When the external synchronous clock is used, the contents of the serial I/O2 register are being shifted continually while the transfer clock is input to the serial I/O2 clock pin. At this time, the clock must be controlled externally.

(7) In automatic transfer serial I/O mode <How to set automatic transfer interval> (a) When using BUSY2 output and,

• SBUSY2 output•SSTB2 output function as signals for each transfer data, which is set by SBUSY2 output•SSTB2 output function select bit of the serial I/O2 control register 2, then the transfer interval is inserted before the first data is transmitted/received and after the last data is transmitted/received. Accordingly, regardless of the contents of the S BUSY2 output•SSTB2 output function select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic transfer interval set bits of the serial I/O2 control register 3. (b) When using S STB2 output, regardless of the contents of the SBUSY2 output•SSTB2 output function select bit, the transfer interval for each 1-byte data becomes 2 cycles longer than the value set by the automatic transfer interval set bits of the serial I/O2 control register 3. (c) When using the combined output of S BUSY2 and SSTB2 as the signal for each transfer data set, the transfer interval after completion of transmission/reception of the last data becomes 2 cycles longer than the value set by the automatic transfer interval set bits.

(d) Set the automatic transfer interval for each 1-byte data transfer as explained below to avoid incorrect transmit/receive of the serial data.

• Not using FLD controller Keep the interval open for 5 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data.
• Using FLD controller a. Gradation display OFF Keep the interval open for 17 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data. b. Gradation Display ON Keep the interval open for 27 cycles or more of the internal system clock from the rising edge of the last bit of 1-byte data. Tables 2.6.4 and 2.6.5 show the serial I/O2 control register 3 (address 0348 16) setting example. (e) When using an external clock, the automatic transfer interval setting becomes invalid. Serial I/O2 control register 3, SIO2CON3 (address 034816) Internal synchronous clock selection bits b7 b6 b5 0 0 0 : f(XIN) / 4 0 0 1 : f(XIN) / 8 0 1 0 : f(XIN) / 16 Automatic transfer interval set bits (b4 to b0) 0 0 0 0 0 : 2 cycles of transfer clocks 0 0 0 0 1 : 3 cycles of transfer clocks 0 0 0 1 0 : 4 cycles of transfer clocks 0 0 0 1 1 : 5 cycles of transfer clocks 0 0 1 0 0 : 6 cycles of transfer clocks 0 0 1 0 1 : 7 cycles of transfer clocks 0 0 0 0 0 : 2 cycles of transfer clocks 0 0 0 0 1 : 3 cycles of transfer clocks 0 0 0 1 0 : 4 cycles of transfer clocks 0 0 0 0 0 : 2 cycles of transfer clocks Not using FLDC Usable Usable Usable Usable Usable Usable Usable Usable Usable Usable Gradation display mode OFF Prohibited Prohibited Prohibited Usable Usable Usable Prohibited Usable Usable Usable Gradation display mode ON Prohibited Prohibited Prohibited Prohibited Prohibited Usable Prohibited Prohibited Usable Usable Note: Do not perform the following in the automatic transfer serial I/O mode:
• Transfer within the RAM area (addresses 0040016 to 005FF16) using the DMAC
• Transfer within the RAM area (addresses 0040016 to 005FF16) using assembler instructions SMOVF and SMOVB. Table 2.6.4 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with internal synchronous clock) Serial I/O2 control register 3, SIO2CON3 (address 0348 16); Automatic transfer interval set bits Not using FLDC Gradation display mode OFF Gradation display mode ON “n” cycles of transfer clocks Transfer clock 5 n cycles ≥ 5 cycles of internal system clock Transfer clock 5 n cycles ≥ 17 cycles of internal system clock Transfer clock 5 n cycles ≥ 27 cycles of internal system clock Table 2.6.5 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with external synchronous clock)

<How to set serial I/O2 transfer counter> (a) Write the value of the number of transfer-data decreased by 1 to the serial I/O2 transfer counter. (b) When using an external clock, after writing a value to the serial I/O2 register/transfer counter, wait for 5 or more cycles of the internal system clock before inputting the transfer clock to the serial I/O2 clock pin. <Serial I/O initialization bit> The serial I/O automatic transfer interrupt request occurs when “0” is written to the serial I/O initializa- tion bit during an operation. Use software to set this interrupt priority level to level 0 (interrupt dis- abled), or any other methods which will disable it. <Interrupt request bit> The occurrence timing of serial I/O automatic transfer interrupt request may be delayed:

• Normally, the maximum delay is 17 cycles. In the FLD gradation display mode ON, the maximum delay increases to 27 cycles.
• If the occurrence timing of the serial I/O2 interrupt request is delayed, the flags and the signals which change simultaneously with the timing of the interrupt request, such as the serial transfer status flag and the handshake signals, will also change in accordance to the delay.

2.7 FLD (VFD) Controller

2.7.1 Overview

The FLD controller drives and controls FLDs (fluorescent display). The following is the FLD controller overview. (1) FLDC port There are a total of 56 ports, consisting of 52 high-breakdown-voltage (HBV) ports and 4 CMOS ports. 20 of the 52 HBV ports can be switched to normal ports, and all of the 4 CMOS ports can be switched to general purpose ports. However, when using CMOS ports as display pins, external drivers must be installed. Ports P0, P1, P5 and P6, totaling 32 ports, have built-in pull-down resistors. Additionally, by selecting the pull-down resistor option in the mask options when ordering the mask ROM version, users can chose to have the built-in pull-down resistors connected to ports P2, P3 and 0 to P43. (2) Display pixel number (a) Using all ports for FLD output 28 segments 5 28 digits (segment number + digit number ≤ 56) (b) Using digit pulse output function 40 segments 5 16 digits (segment number + digit number ≤ 56, however, digit number ≤ 16) (c) Using P44 to P47 expansion function 52 segments 5 16 digits (segment number ≤ 52, digit number ≤ 16) (3) Selection function The following selection functions can be applied to the FLD controller. (a) Tscan control Two types of interrupt sources can be selected, using the Tscan control bits (bits 2, 3 of address 0350 16):

• FLD digit interrupt This is generated when the Toff1 time for each timing ends (at rising edge of digit output). Key scanning, which makes use of FLD digits, can be applied by using each FLD digit interrupt.
• FLD blanking interrupt This is generated when the FLD data pointer (address 0358 16) reaches FF16. The FLD automatic display output is turned off for a duration of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp, depending on post-interrupt settings. Key scanning, which makes use of FLD segments, can be applied during this time.

(b) Timing number The following two types of timing can be selected:

• 16-timing This timing is used when the display timing is 16 sets or less.
• 32-timing This timing is used when the display timing is more than 16 sets. This can be used for up to 32 sets. (c) Gradation display mode The gradation display mode can apply bright/dark display for each segment when the display timing is 16 or less. Selection of gradation mode is as follows:
• Gradation display mode ON Make sure to fix the timing number control bit (bit 4 of address 0350 16) to “0” as the maximum timing is 16. Additionally, set the value to the Toff2 time set register (address 035616) so that Toff2 time can be less than Tdisp time and more than Toff1 time.
• Gradation display mode OFF (d) HBV port drivability Two types of drivability, strong or weak, can be selected for HBV ports. This setting is also valid when using HBV ports as general purpose ports. (e) P4 4 to P47 FLD output reverse Selecting this function enables the polarity reversal of the FLD output from P44 to P47. This function is useful for adjusting the polarity when using an externally installed driver. (f) P44 to P47 Toff invalid Selecting this function disables Toff1 time and Toff2 time and outputs display data for the duration of Tdisp. (g) P9 7 dimmer signal output Selecting this function outputs a signal from DIMOUT (P97) to the decoder which, in turn, sends out the dimmer signal. The decoder controls this signal to enable the dimmer function. (h) Toff section generate/not generate This function can be applied to all of the HBV ports (P0, P1, P2, P3, P40 to P43, P5, P6) and CMOS ports (P44 to P47). Two types can be selected:
• Generate Toff section The Toff section is generated.
• No Toff section This function reduces unwanted noises generated whenever a port switches due to the combined capacity of the FLD ports. When continuous data is output to each FLD port, the Toff1 section of the continuous parts is not generated.

(i) Toff2 SET/RESET change In gradation display mode, this function specifies either output (SET) or “0” (RESET) depending on Toff2 time for FLD output of dark display data (when gradation display control data is “1”). Two types can be selected:

• Toff2SET RAM data is output to the FLD output ports (SET) at the time set by Toff2 and is returned to “0” (RESET) when the Tdisp time ends.
• Toff2RESET RAM data is output to the FLD output ports (SET) at the time set by Toff1 and is returned to “0” (RESET) at the time set by Toff2. (4) Expansion function The FLD controller is equipped with an expansion function. (a) Digit pulses output function Digit pulses can be output automatically from ports P5 and P6. When the same number of “1s” as the timing number are consecutively written from P6 0 to the digit output set registers (addresses 035C16, 035D 16), the contents of the FLD automatic display RAM for the ports that have been selected for digit output are disabled. The digit pulses are then automatically output. If a value exceeding the timing number for any port is set, the output of such port becomes “L” level. (b) P4 4 to P47 expansion function These ports have CMOS output structure. This function provides 16 lines of FLD digit outputs to these four ports by connecting the decoder which converts 4-bit data to 16-bit data. (5) Registers related to FLD controller related-registers.

Figure 2.7.1. Memory map of FLDC related-registers 0 3 5 41 0 3 5 51 0 3 5 61 0 3 5 71 0 3 5 81 0 3 5 C 1 T o f f 1 t i m e s e t r e g i s t e r ( T O F F 1 ) T o f f 2 t i m e s e t r e g i s t e r ( T O F F 2 ) F L D d a t a p o i n t e r ( F L D D P ) P o r t P 5 d i g i t o u t p u t s e t r e g i s t e r ( P 5 D O R ) 0 3 5 31 0 3 5 21 0 3 5 91

6 P o r t P 2 F L D / p o r t s w i t c h r e g i s t e r ( P 2 F P R )

6 P o r t P 3 F L D / p o r t s w i t c h r e g i s t e r ( P 3 F P R )

6 P o r t P 4 F L D / p o r t s w i t c h r e g i s t e r ( P 4 F P R )

F L D i n t e r r u p t c o n t r o l r e g i s t e r ( F L D I C ) F L D C m o d e r e g i s t e r ( F L D M ) T d i s p t i m e s e t r e g i s t e r ( T D I S P ) P o r t P 6 d i g i t o u t p u t s e t r e g i s t e r ( P 6 D O R )0 3 5 D 1 0 3 5 11

6 F L D o u t p u t c o n t r o l r e g i s t e r ( F L D C O N )

Figure 2.7.2. FLDC related-registers (1) F L D C m o d e r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t F L D 6 0 B i t n a m eF u n c t i o nB i t s y m b o l b A u t o m a t i c d i s p l a y c o n t r o l b i t 0 : G e n e r a l - p u r p o s e m o d e A u t o m a t i c d i s p l a y m o d eF L D M 0 F L D M 1 F L D M 2 F L D M 3 D i s p l a y s t a r t b i t0 : S t o p d i s p l a y D i s p l a y s t a r t t o d i s p l a y b y s w i t c h i n g t o T s c a n c o n t r o l b i t s 0 0 : F L D d i g i t i n t e r r u p t a t r i s i n g e d g e o f e a c h d i g i t X T d i s p X T d i s p X T d i s p 0 : 1 6 t i m i n g m o d e t i m i n g m o d e T i m i n g n u m b e r c o n t r o l b i t G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : N o t s e l e c t i n g S e l e c t i n g N o t e F L D M 4 F L D M 5 N o t e : W h e n a g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d , a n u m b e r o f t i m i n g i s m a x . 1 6 t i m i n g . S e t t h e t i m i n g n u m b e r c o n t r o l b i t t o T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( XI N ) / 3 2 f XI N ) 8F L D M 6 H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 0 : D r i v a b i l i t y s t r o n g D r i v a b i l i t y w e a kF L D M 7 F L D o u t p u t c o n t r o l r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t F L D C O 6 0 B i t n a m eF u n c t i o nB i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 F L D C O N 7 F L D C O N 5 F L D C O N 4 F L D C O N 2 F L D C O N0 F L D C O N 6 P 44 t o P 47 F L D o u t p u t r e v e r s e b i t P 44 t o P 47 F L D T o f f i s i n v a l i d b i t 0 : P e r f o r m n o r m a l l y T o f f i s i n v a l i d P 97 d i m m e r o u t p u t c o n t r o l b i t 0 : O u t p u t n o r m a l l y D i m m e r o u t p u t C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e b i t 0 : s e c t i o n o f T o f f d o e s N O T g e n e r a t e s e c t i o n o f T o f f g e n e r a t e s H i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e b i t 0 : s e c t i o n o f T o f f d o e s N O T g e n e r a t e s e c t i o n o f T o f f g e n e r a t e s T o f f 2 S E T R E S E T c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t T o f f 2 s e t a t T o f f g r a d a t i o n d i s p l a y d a t a i s s e t a t T o f f r e s e t a t T o f f WR 0 : O u t p u t n o r m a l l y R e v e r s e o u t p u t N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h i s b i t w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e F L D b l a n k i n g i n t e r r u p t a t f a l l i n g e d g e o f l a s t d i g i t b 3 b 2 WR

Figure 2.7.3. FLDC related-registers (2) T o f f 1 t i m e s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T O F F 6 F WR b F u n c t i o n V a l u e s t h a t c a n b e s e t C o u n t s T o f f t i m e C o u n t s o u r c e i s s e l e c t e d b y T d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t S u p p o s i n g t h a t t h e s e t v a l u e i s n t h e T o f f t i m e i s e x p r e s s e d a s T o f f n c o u n t s o u r c e E x a m p l e T o f f ms ms C o n d i t i o n s f XI N ) M H z F L D C m o d e r e g i s t e r F L D M f XI N ) s e l e c t e d a s T d i s p c o u n t e r c o u n t s o u r c e T o f f t i m e s e t r e g i s t e r t o F T o f f 2 t i m e s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T O F F 6 F WR b C o u n t s T o f f t i m e C o u n t s o u r c e i s s e l e c t e d b y T d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t S u p p o s i n g t h a t t h e s e t v a l u e i s n t h e T o f f t i m e i s e x p r e s s e d a s T o f f n c o u n t s o u r c e T h i s s e t t i n g o f T o f f t i m e a p p l i e s o n l y t o t h e F L D p o r t s a s t h e f o l l o w i n g G r a d a t i o n d i s p l a y m o d e a n d T h e R A M v a l u e o f g r a d a t i o n d i s p l a y c o n t r o l i s d a r k d i s p l a y E x a m p l e T o f f ms ms C o n d i t i o n s f XI N ) M H z F L D C m o d e r e g i s t e r F L D M f XI N ) s e l e c t e d a s T d i s p c o u n t e r c o u n t s o u r c e T o f f t i m e s e t r e g i s t e r B t o F F u n c t i o n V a l u e s t h a t c a n b e s e t T d i s p t i m e s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t T D I S 6 0 WR b F u n c t i o n V a l u e s t h a t c a n b e s e t t o F 6C o u n t s T d i s p t i m e . C o u n t s o u r c e i s s e l e c t e d b y T d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t S u p p o s i n g t h a t t h e s e t v a l u e i s n t h e T d i s p t i m e i s e x p r e s s e d a s T d i s p n c o u n t s o u r c e W h e n r e a d i n g t h i s r e g i s t e r t h e v a l u e i n t h e c o u n t e r o f T d i s p t i m e s e t r e g i s t e r i s r e a d o u t E x a m p l e T d i s p ms ms C o n d i t i o n s f XI N ) M H z F L D C m o d e r e g i s t e r F L D M f XI N ) s e l e c t e d a s T d i s p c o u n t e r c o u n t s o u r c e T d i s p t i m e s e t r e g i s t e r C S y m b o lA d d r e s sW h e n r e s e t T O F F 6 F

F L D d a t a p o i n t e r S y m b o lA d d r e s sW h e n r e s e t F L D D i n d e t e r m i n a t e WR b C o u n t s F L D o u t p u t t i m i n g S e t t h i s r e g i s t e r t o F L D o u t p u t d a t a T h e s e t v a l u e i s w r i t t e n i n t o t h e F L D d a t a p o i n t e r r e l o a d r e g i s t e r W h e n r e a d i n g t h i s r e g i s t e r t h e v a l u e o f t h e F L D d a t a p o i n t e r i s r e a d o u t t o N o t e R e a d i n g t h e F L D d a t a p o i n t e r t a k e s o u t t h e c o u n t a t t h a t m o m e n t F u n c t i o n V a l u e s t h a t c a n b e s e t N o r m a l p o r t F L D o u t p u t p o r t P o r t P 2 F L D / p o r t s w i t c h r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P F P 6 0 WR b P 2 F P R 0 P 2 F P R 2 P 2 F P R 1 P 2 F P R 3 P 2 F P R 4 P 2 F P R 6 P 2 F P R 5 P 2 F P R 7 P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t B i t n a m eF u n c t i o nB i t s y m b o l N o r m a l p o r t F L D o u t p u t p o r t P o r t P 3 F L D / p o r t s w i t c h r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P F P 6 0 WR b P 3 F P R 0 P 3 F P R 2 P 3 F P R 1 P 3 F P R 3 P 3 F P R 4 P 3 F P R 6 P 3 F P R 5 P 3 F P R 7 P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t B i t n a m eF u n c t i o nB i t s y m b o l Figure 2.7.4. FLDC related-registers (3)

N o r m a l p o r t F L D o u t p u t p o r t P o r t P 4 F L D / p o r t s w i t c h r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P F P 6 0 WR b P 4 F P R 0 P 4 F P R 2 P 4 F P R 1 P 4 F P R 3 P 4 F P R 4 P 4 F P R 6 P 4 F P R 5 P 4 F P R 7 P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t N o r m a l p o r t F L D o u t p u t p o r t P o r t P F L D p o r t s w i t c h b i t B i t n a m eF u n c t i o nB i t s y m b o l F L D o u t p u t D i g i t o u t p u t P o r t P 5 d i g i t o u t p u t s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P D O C 1 6 0 WR b P 5 D O R0 P 5 D O R 2 P 5 D O R 1 P 5 D O R 3 P 5 D O R 4 P 5 D O R 6 P 5 D O R 5 P 5 D O R 7 P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 51 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 52 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 53 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 54 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 55 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 56 F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P 57 F L D d i g i t s w i t c h b i t B i t n a m eF u n c t i o nB i t s y m b o l Figure 2.7.5. FLDC related-registers (4)

F L D o u t p u t D i g i t o u t p u t P o r t P 6 d i g i t o u t p u t s e t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t P D O D 1 6 0 WR b P 6D O R0 P 6D O R 2 P 6D O R 1 P 6D O R 3 P 6D O R 4 P 6D O R 6 P 6D O R 5 P 6D O R 7 P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t F L D o u t p u t D i g i t o u t p u t P o r t P F L D d i g i t s w i t c h b i t B i t n a m eF u n c t i o nB i t s y m b o l Figure 2.7.6. FLDC related-registers (5)

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2.7.2 FLD operation (FLD automatic display and key-scan using segments)

The FLD controller can choose functions from those listed in Table 2.7.1. The circled items are described procedures. Table 2.7.1. Selectable functions Note 1: When selecting the FLD blanking interrupt, any one of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp can be selected as Tscan time. Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number. I t e mS e t - u pS e t - u p O I t e m T s c a n c o n t r o l N o t e F L D d i g i t i n t e r r u p t F L D b l a n k i n g i n t e r r u p t H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y S t r o n g W e a kO T i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g O P 97 d i m m e r o u t p u tN o r m a l p o r t D i m m e r o u t p u t O T d i s p c o u n t e r c o u n t s o u r c e f ( XI N ) / 3 2 f ( XI N ) / 1 2 8 O H i g h - b r e a k d o w n - v o l t a g e p o r t s S e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e Se c t i o n o f T o f f d o e s N O T g e n e r a t e Se c t i o n o f T o f f g e n e r a t e sO G r a d a t i o n d i s p l a y m o d e N o t e N o t s e l e c t i n g Se l e c t i n gO T o f f 2 S E T R E S E T R e s e t a t T o f f 2 Se t a t T o f f 2 O Operation(1) The FLD starts an automatic display when both the automatic display control bit and the display start bit are set to “1”. (2) The display data, the contents from the first address through the last address, in the FLD automatic display RAM for each port is output to each port. The last address is the result of decreasing the number indicated in the FLD data pointer from the first address. The grada- tion display control data is arranged at an address which is calculated by subtracting “70 16” from the stored address in the FLD automatic display RAM of the corresponding timing and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”. However, the contents of the FLD automatic display RAM for ports P5 0, P51, and P60 to P67 are disabled by selection of the digit pulse output function, and the digit pulses are automati- cally output. (3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the pointer is reloaded and starts counting over again. (4) The FLD interrupt request bit is set to “1” simultaneously with the falling edge of the last timing. The FLD automatic display output is turned off for a duration of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp, depending on post-interrupt settings. During this time, key scanning, which makes use of FLD segments, can be applied. (5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to the display start bit.

Figure 2.7.7. Operation timing of FLD automatic display F L D 3 2 ( P 20) F L D 3 3 ( P 21) F L D 3 4 ( P 22) F L D 3 9 ( P 27)

• • •
• • • P 50, P 51 P 60–P 67 P 30, P 31 P 20– P 27 P 34– P 37 S e g m e n t D i g i t R E C n L E V E L A M P M C H S U N M O N T U E W E D T H U F R I S A T l L R M G r o u p K e y - m a t r i x P a n e l w i t h f l u o r e s c e n t d i s p l a y F L D l l l S e g m e n t C o n n e c t i o n e x a m p l e T d i s p T s c a n F L D b l a n k i n g i n t e r r u p t r e q u e s t o c c u r F L D 9 ( P 51) F L D 8 ( P 50) F L D 7 ( P 67) F L D 0 ( P 60) F L D 3 2– F L D 4 P 20– P 27, P 30, P 31) K e y - s c a n
• • • T o f f T o f f
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• • • O p e r a t i o n e x a m p l e E n l a r g e d v i e w o f T s c a n S P E P

Figure 2.7.8. Set-up procedure for FLD automatic display (1) 0 0 0 0 b P o r t P d i r e c t i o n r e g i s t e r s e t u p P o r t P d i r e c t i o n r e g i s t e r A d d r e s s E P D S e t P P t o i n p u t p o r t s f o r k e y s c a n i n p u t 1 1 1 1 1 1 1 1 b D i s p l a y p i p o r t s w i t c h o f P P P a n d P s e t u p P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R 0 0 0 0 0 0 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P a n d P t o F L D o u t p u t p o r t s F L D F L D S e t P P t o n o r m a l I O o u t p u t p o r t s 0 0 0 0 0 0 1 1 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s C 1 P D O R S e t P a n d P t o d i g i t o u t p u t p o r t s F L D F L D S e t P P t o F L D o u t p u t p o r t s 1 1 1 1 1 1 1 1 S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 1 1 1 1 1 1 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s D 1 P D O R S e t P P t o d i g i t o u t p u t p o r t s F L D t o F L D 1 0 1 0 1 1 0 1 b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t A u t o m a t i c d i s p l a y m o d e D i s p l a y s t a r t b i t S t o p d i s p l a y T s c a n c o n t r o l b i t s b b X T d i s p F L D b l a n k i n g i n t e r r u p t T i m i n g n u m b e r c o n t r o l b i t t i m i n g m o d e G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t S e l e c t i n g T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t D r i v a b i l i t y w e a k 0 1 0 0 0 0 b F L D o u t p u t c o n t r o l r e g i s t e r A d d r e s s F L D C O N F L D o u t p u t c o n t r o l r e g i s t e r s e t u p P 44 t o P 47 F L D o u t p u t r e v e r s e b i t O u t p u t n o r m a l l y P 44 t o P 47 F L D T o f f i s i n v a l i d b i t P e r f o r m n o r m a l l y P 97 d i m m e r o u t p u t c o n t r o l b i t O u t p u t n o r m a l l y C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f d o e s N O T g e n e r a t e H i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f g e n e r a t e s T o f f 2 S E T / R E S E T c h a n g e b i t g r a d a t i o n d i s p l a y d a t a i s r e s e t a t T o f f s e t a t T o f f C o n t i n u e d t o t h e n e x t p a g e

F L D d a t a p o i n t e r s e t u p 1 1 1 1 1 1 1 1 b T d i s p T o f f a n d T o f f t i m e s e t u p 1 1 0 0 1 0 0 0 b T d i s p t i m e s e t r e g i s t e r A d d r e s s T D I S P b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t a r t D i s p l a y s t a r t b i t D i s p l a y b F L D i n t e r r u p t c o n t r o l r e g i s t e r A d d r e s s F L D I C F L D i n t e r r u p t c o n t r o l r e g i s t e r s e t u p I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b b b L e v e l i n t e r r u p t d i s a b l e d L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l C o n t i n u e d f r o m t h e p r e v i o u s p a g e S e t C T d i s p c o u n t s o u r c e ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 1 1 1 1 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 1 0 1 1 0 1 0 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t B T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 0 1 0 0 1 b F L D d a t a p o i n t e r A d d r e s s F L D D P S e t d i g i t n u m b e r I n t e r r u p t r e q u e s t b i t N o t e I n t e r r u p t n o t r e q u e s t e d N o t h i n g i s a s s i g n e d N o t e O n l y c a n b e w r i t t e n t o t h i s b i t D o n o t w r i t e F L D d i s p l a y s t a r t Figure 2.7.9. Set-up procedure for FLD automatic display (2)

F L D b l a n k i n g i n t e r r u p t r o u t i n e P u s h re g i s t e r s a n d a n y o t h e r s e t u p b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t G e n e r a l p u r p o s e m o d e 1 1 1 1 1 1 1 1 b P P a n d P s e t u p 0 0 0 0 0 0 0 0 b 0 0 0 0 0 0 0 0 b S e t p o r t s f o r k e y s c a n t o n o r m a l p o r t s 0 0 b P o r t P A d d r e s s E P S e t L l e v e l t o p o r t s c o r r e s p o n d i n g t o d i g i t s P o r t P A d d r e s s E C 1 P S e t L l e v e l t o p o r t s c o r r e s p o n d i n g t o d i g i t s P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R 0 0 0 0 0 0 0 0 b P o r t P A d d r e s s E P O u t p u t L l e v e l f r o m p o r t s f o r k e y s c a n K e y s c a n p r o c e s s i n g 0 0 0 0 0 0 0 0 b P o r t P A d d r e s s E P O u t p u t L l e v e l f r o m p o r t s f o r k e y s c a n P s e t u p 1 1 1 1 1 1 1 1 b S e t n o r m a l p o r t s t o F L D o u t p u t p o r t s P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t A u t o m a t i c d i s p l a y m o d e R T I Figure 2.7.10. Set-up procedure for key-scan processing

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M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.7.3 FLD operation (FLD automatic display and key-scan using digits)

The FLD controller can choose functions from those listed in Table 2.7.2. The circled items are described procedures. Table 2.7.2. Selectable functions Note 1: When selecting the FLD blanking interrupt, any one of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp can be selected as Tscan time. Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number. Operation(1) The FLD starts an automatic display when both the automatic display control bit and the display start bit are set to “1”. (2) The display data, the contents from the first address through the last address, in the FLD automatic display RAM for each port is output to each port. The last address is the result of decreasing the number indicated in the FLD data pointer from the first address. The grada- tion display control data is arranged at an address which is calculated by subtracting “70 16” from the stored address in the FLD automatic display RAM of the corresponding timing and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”. However, the contents of the FLD automatic display RAM for ports P5 0, P51, and P60 to P67 are disabled by selection of the digit pulse output function, and the digit pulses are automati- cally output. (3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the pointer is reloaded and starts counting over again. (4) The FLD interrupt request bit is set to “1” simultaneously with the end of Toff1 time (at the rising edge of a digit) for each timing. Key scanning, which makes use of FLD digits, can be applied by using each FLD digit interrupt. (5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to the display start bit. I t e mS e t - u pS e t - u p O I t e m T s c a n c o n t r o l N o t e F L D d i g i t i n t e r r u p t F L D b l a n k i n g i n t e r r u p t H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y S t r o n g W e a kO T i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g O P 97 d i m m e r o u t p u tN o r m a l p o r t D i m m e r o u t p u t O T d i s p c o u n t e r c o u n t s o u r c e f ( XI N ) / 3 2 f ( XI N ) / 1 2 8 O H i g h - b r e a k d o w n - v o l t a g e p o r t s S e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e Se c t i o n o f T o f f d o e s N O T g e n e r a t e Se c t i o n o f T o f f g e n e r a t e sO G r a d a t i o n d i s p l a y m o d e N o t e N o t s e l e c t i n g Se l e c t i n gO T o f f 2 S E T R E S E T R e s e t a t T o f f 2 Se t a t T o f f 2 O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.7.11. Operation timing of FLD automatic display P 20–P 27 P 30, P 31 P 50, P 51 P 60– P 67 P 34– P 37 S e g m e n t D i g i t D i g i t S P E P R E C n L E V E L A M P M C H S U N M O N T U E W E D T H U F R I S A T l L R M 8 Gr o u p K e y - m a t r i x P a n e l w i t h f l u o r e s c e n t d i s p l a y F L D l l l T d i s p T s c a n = 0 ms F L D 9 ( P 51) F L D 8 ( P 50) F L D 7 ( P 67) F L D 0 ( P 60) F L D 3 2– F L D 4 P 20– P 27, P 30, P 31) T o f f 2 T o f f 1 F L D d i g i t i n t e r r u p t r e q u e s t o c c u r F L D d i g i t i n t e r r u p t r e q u e s t o c c u r F L D d i g i t i n t e r r u p t r e q u e s t o c c u r F L D d i g i t i n t e r r u p t r e q u e s t o c c u r C o n n e c t i o n e x a m p l e O p e r a t i o n e x a m p l e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.7.12. Set-up procedure for FLD automatic display (1) 0 0 0 0 b P o r t P d i r e c t i o n r e g i s t e r s e t u p P o r t P d i r e c t i o n r e g i s t e r A d d r e s s E P D S e t P P t o i n p u t p o r t s f o r k e y s c a n i n p u t 1 1 1 1 1 1 1 1 b D i s p l a y p i p o r t s w i t c h o f P P P a n d P s e t u p P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R 0 0 0 0 0 0 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P a n d P t o F L D o u t p u t p o r t s F L D F L D S e t P P t o n o r m a l I O o u t p u t p o r t s 0 0 0 0 0 0 1 1 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s C 1 P D O R S e t P a n d P t o d i g i t o u t p u t p o r t s F L D F L D S e t P P t o F L D o u t p u t p o r t s 1 1 1 1 1 1 1 1 S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 1 1 1 1 1 1 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s D 1 P D O R S e t P P t o d i g i t o u t p u t p o r t s F L D t o F L D 1 0 1 0 0 0 0 1 b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t A u t o m a t i c d i s p l a y m o d e D i s p l a y s t a r t b i t S t o p d i s p l a y T s c a n c o n t r o l b i t s b b F L D d i g i t i n t e r r u p t T i m i n g n u m b e r c o n t r o l b i t t i m i n g m o d e G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t S e l e c t i n g T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t D r i v a b i l i t y w e a k 0 1 0 0 0 0 b F L D o u t p u t c o n t r o l r e g i s t e r A d d r e s s F L D C O N F L D o u t p u t c o n t r o l r e g i s t e r s e t u p P 44 t o P 47 F L D o u t p u t r e v e r s e b i t O u t p u t n o r m a l l y P 44 t o P 47 F L D T o f f i s i n v a l i d b i t P e r f o r m n o r m a l l y P 97 d i m m e r o u t p u t c o n t r o l b i t O u t p u t n o r m a l l y C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f d o e s N O T g e n e r a t e H i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f g e n e r a t e s T o f f 2 S E T / R E S E T c h a n g e b i t G r a d a t i o n d i s p l a y d a t a i s r e s e t a t T o f f s e t a t T o f f C o n t i n u e d t o t h e n e x t p a g e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.7.13. Set-up procedure for FLD automatic display (2) F L D d a t a p o i n t e r s e t u p 1 1 1 1 1 1 1 1 b T d i s p T o f f a n d T o f f t i m e s e t u p 1 1 0 0 1 0 0 0 T d i s p t i m e s e t r e g i s t e r A d d r e s s T D I S P b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t a r t D i s p l a y s t a r t b i t D i s p l a y b F L D i n t e r r u p t c o n t r o l r e g i s t e r A d d r e s s F L D I C F L D i n t e r r u p t c o n t r o l r e g i s t e r s e t u p I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b b b L e v e l i n t e r r u p t d i s a b l e d L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l C o n t i n u e d f r o m t h e p r e v i o u s p a g e S e t C T d i s p c o u n t s o u r c e ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 1 1 1 1 0 T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 1 0 1 1 0 1 0 0 T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t B T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 0 1 0 0 1 b F L D d a t a p o i n t e r A d d r e s s F L D D P S e t d i g i t n u m b e r I n t e r r u p t r e q u e s t b i t N o t e I n t e r r u p t n o t r e q u e s t e d N o t h i n g i s a s s i g n e d N o t e O n l y c a n b e w r i t t e n t o t h i s b i t D o n o t w r i t e F L D d i s p l a y s t a r t

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.7.4 FLD operation (FLD display and key-scan using segment by software)

FLD display and key-scan using the Timer A0 interrupt are explained in detail below. Figure 2.7.14 shows Operation (1) Set both the automatic display control bit and the display start bit to “0”. (2) Output segment data and digit data from each port during the Timer A0 interrupt processing. (3) After finishing display of all digits, perform key-scan within during the Timer A0 interrupt processing.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.7.14. Operation timing of FLD display P 50, P 51 P 60–P 67 P 30, P 31 P 20– P 27 P 34– P 37 S e g m e n t D i g i t S P E P R E C n L E V E L A M P M C H S U N M O N T U E W E D T H U F R I S A T l L R M 3 0 2 1 8 Gr o u p K e y - m a t r i x P a n e l w i t h f l u o r e s c e n t d i s p l a y ( F L D ) l l l S e g m e n t P 51 P 50 P 67 P 60 P 20– P 27, P 30, P K e y - s c a n

• • •
• • •
• • • P 20 P 21 P 22 P 27
• • •
• • • C o n n e c t i o n e x a m p l e O p e r a t i o n e x a m p l e E n l a r g e d v i e w o f k e y - s c a n

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R 0 0 0 0 b P o r t P d i r e c t i o n r e g i s t e r s e t u p P o r t P d i r e c t i o n r e g i s t e r A d d r e s s E P D S e t P a n d P t o o u t p u t p o r t s f o r s e g m e n t o u t p u t b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t G e n e r a l p u r p o s e m o d e D i s p l a y s t a r t b i t S t o p d i s p l a y H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t D r i v a b i l i t y w e a k b C l o c k p r e s c a l e r r e s e t f l a g A d d r e s s C P S R F C o n t i n u e d t o t h e n e x t p a g e S e t P P t o i n p u t p o r t s f o r k e y s c a n i n p u t T i m e r A m o d e r e g i s t e r A d d r e s s T A M R Ti m e r m o d e T i m e r A a n d f u n c t i o n s s e t u p S e l e c t i o n o f t i m e r m o d e P u l s e o u t p u t f u n c t i o n s e l e c t b i t P u l s e i s n o t o u t p u t T A U T p i n i s a n o r m a l p o r t p i n G a t e f u n c t i o n s e l e c t b i t b b G a t e f u n c t i o n n o t a v a i l a b l e ( T A 0I N p i n i s a n o r m a l p o r t p i n ) 0 ( M u s t a l w a y s b e “ 0 ” i n t i m e r m o d e ) C o u n t s o u r c e s e l e c t b i t b b fC C o u n t s o u r c e p e r i o d f ( XI N ) : 1 0 M H Z f ( X cI N ) : 3 2 . 7 6 8 k H Z b 7b 6 C o u n t s o u r c e 1 0 0 n s 8 0 0 n s 3 . 2 ms 9 7 6 . 5 6 ms f fC b 0000 b b b b T i m e r A r e g i s t e r A d d r e s s T A C a n b e s e t t o 0 0 0 01 6 t o F F F F1 Di v i d e r a t i o s e t - u p Cl o c k p r e s c a l e r r e s e t f l a g s e t - u p T h i s f u n c t i o n i s e f f e c t i v e w h e n fC i s s e l e c t e d a s t h e c o u n t s o u r c e R e s e t t h e p r e s c a l e r f o r g e n e r a t i n g fC b y d i v i d i n g t h e XC I N b y C l o c k p r e s c a l e r r e s e t f l a g N o e f f e c t P r e s c a l e r i s r e s e t W h e n r e a d t h e v a l u e i s 1 00 Figure 2.7.15. Set-up procedure for FLD display (1)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R b C o u n t s t a r t f l a g A d d r e s s T A B S R C o u n t s t a r t f l a g s e t u p b T A i n t e r r u p t c o n t r o l r e g i s t e r A d d r e s s T A I C T A i n t e r r u p t c o n t r o l r e g i s t e r s e t u p I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b b b L e v e l i n t e r r u p t d i s a b l e d L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l C o n t i n u e d f r o m t h e p r e v i o u s p a g e I n t e r r u p t r e q u e s t b i t N o t e I n t e r r u p t n o t r e q u e s t e d N o t h i n g i s a s s i g n e d N o t e O n l y c a n b e w r i t t e n t o t h i s b i t D o n o t w r i t e T i m e r A 0 c o u n t s t a r t f l a g S t a r t s c o u n t i n g Figure 2.7.16. Set-up procedure for FLD display (2)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R T A i n t e r r u p t r o u t i n e P u s h re g i s t e r s a n d a n y o t h e r s e t u p 1 1 1 1 1 1 1 1 b P P P a n d P s e t u p 0 0 b 0 0 b P o r t P A d d r e s s E P S e t t o p o r t s c o r r e s p o n d i n g t o s e g m e n t s P o r t P A d d r e s s E P 0 0 0 0 0 0 0 0 b P o r t P A d d r e s s E P S e t s e g m e n t d a t a S e g m e n t d a t a s e t u p 0 0 b P o r t P A d d r e s s E P R T I 000000 S e t t o p o r t s c o r r e s p o n d i n g t o s e g m e n t s 0 0 b P o r t P A d d r e s s E P S e t t o p o r t s c o r r e s p o n d i n g t o d i g i t s 1 1 1 1 1 1 1 1 b 0 0 b P o r t P A d d r e s s E C 1 P S e t t o p o r t s c o r r e s p o n d i n g t o d i g i t s 000000 S e t s e g m e n t d a t a 0 0 b P o r t P A d d r e s s E P S e t d i g i t d a t a D i g i t d a t a s e t u p 0 0 b P o r t P A d d r e s s E C 1 P S e t d i g i t d a t a 000000 Figure 2.7.17. Set-up procedure for key-scan processing

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R This page kept blank for layout purposes.

2.7.5 FLD operation (Display with digit expander M35501FP)

The FLD controller can choose functions from those listed in Table 2.7.3. The circled items are described Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp Table 2.7.3. Selectable functions Note 1: When selecting the FLD blanking interrupt, any one of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp can be selected as Tscan time. Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number. Operation(1) The FLD starts an automatic display when both the automatic display control bit and the display start bit are set to “1”. (2) The display data, the contents from the first address through the last address, in the FLD automatic display RAM for each port is output to each port. The last address is the result of decreasing the number indicated in the FLD data pointer from the first address. The grada- tion display control data is arranged at an address which is calculated by subtracting “70 16” from the stored address in the FLD automatic display RAM of the corresponding timing and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”. (3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the pointer is reloaded and starts counting over again. (4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71, respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97). (5) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to the display start bit. I t e mS e t - u pS e t - u p O I t e m T s c a n c o n t r o l N o t e F L D d i g i t i n t e r r u p t F L D b l a n k i n g i n t e r r u p t H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y S t r o n g W e a kO T i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g O P 97 d i m m e r o u t p u tN o r m a l p o r t D i m m e r o u t p u tO T d i s p c o u n t e r c o u n t s o u r c e f ( XI N ) / 3 2 f ( XI N ) / 1 2 8 O H i g h - b r e a k d o w n - v o l t a g e p o r t s S e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e Se c t i o n o f T o f f d o e s N O T g e n e r a t e Se c t i o n o f T o f f g e n e r a t e sO G r a d a t i o n d i s p l a y m o d e N o t e N o t s e l e c t i n g Se l e c t i n gO T o f f 2 S E T R E S E T R e s e t a t T o f f 2 Se t a t T o f f 2 O

Figure 2.7.18. Connection example of FLD automatic display (1) D i g i t ( 1 6 ) F l u o r e s c e n t d i s p l a y ( F L D ) P 30– P 37 P 10– P 17 P 00– P 07 P 20– P 27 S e g m e n t ( 5 2 ) M 3 0 2 1 8 G r o u p M 3 5 5 0 1 F P C L K S E L R E S E T D I G 0– D I G 1 P 40– P 43 D I M O U T P 70 P 71 O V FI N P 60– P 67 P 50– P 57 O V FO U T C o n n e c t i o n e x a m p l e

N O V FO U T F L D 0– F L D 5 P 00– P 07, P 10– P 17, P 20– P 27, P 30– P 37, P 40– P 43, P 50– P 57, P 60– P 67)

• • • C L K D I G 0 D I G 3 D I G 1 2 D I G 1 D I G 2 D I G 1 3 D I G 1 4 D I G 1 5 M 3 0 2 1 8 G r o u p M 3 5 5 0 1 F P
• • • O p e r a t i o n e x a m p l e E n l a r g e d v i e w
• • • T d i s p T o f f 2 T o f f 1 C L K D I G 0 D I G 1 D I G 2 D I G 1 5 M 3 5 5 0 1 F P
• • • M 3 0 2 1 8 G r o u p F L D 0– F L D 5 P 00– P 07, P 10– P 17, P 20– P 27, P 30– P 37, P 40– P 43, P 50– P 57, P 60– P 67) Figure 2.7.19. Operation timing of FLD automatic display

Figure 2.7.20. Set-up procedure for FLD automatic display (1) 1 1 1 1 1 1 1 1 b D i s p l a y p i n p o r t s w i t c h o f P P P P a n d P s e t u p P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R 1 1 1 1 1 1 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 0 0 0 0 0 0 0 0 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s C 1 P D O R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 1 1 1 1 1 1 S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 0 0 0 0 0 0 0 0 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s D 1 P D O R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 0 1 0 0 0 0 1 b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t A u t o m a t i c d i s p l a y m o d e D i s p l a y s t a r t b i t S t o p d i s p l a y T s c a n c o n t r o l b i t s b b F L D d i g i t i n t e r r u p t T i m i n g n u m b e r c o n t r o l b i t t i m i n g m o d e G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t S e l e c t i n g T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t D r i v a b i l i t y w e a k C o n t i n u e d t o t h e n e x t p a g e 0 0 0 0 1 1 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P P t o n o r m a l I O p o r t s S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 b P o r t P d i r e c t i o n r e g i s t e r A d d r e s s E P D S e t P t o o u t p u t p o r t f o r S E L s i g n a l o f M S e t P t o o u t p u t p o r t f o r R E S E T s i g n a l o f M M i n i t i a l i z a t i o n 0 0 b P o r t P A d d r e s s E D 1 P O u t p u t S E L s i g n a l L o f M O u t p u t R E S E T s i g n a l o f M N o t e N o t T o r e m o v e r e s e t s t a t e a f t e r r e t a i n i n g L l e v e l f o r ms o r m o r e o u t p u t H l e v e l w h e n C L K s i g n a l L

Figure 2.7.21. Set-up procedure for FLD automatic display (2) F L D d a t a p o i n t e r s e t u p 1 1 1 1 1 1 1 1 b T d i s p T o f f a n d T o f f t i m e s e t u p 1 1 0 0 1 0 0 0 b T d i s p t i m e s e t r e g i s t e r A d d r e s s T D I S P b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t a r t D i s p l a y s t a r t b i t D i s p l a y C o n t i n u e d f r o m t h e p r e v i o u s p a g e S e t C T d i s p c o u n t s o u r c e ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 1 1 1 1 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 1 0 1 1 0 1 0 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t B T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 0 1 1 1 1 b F L D d a t a p o i n t e r A d d r e s s F L D D P S e t d i g i t n u m b e r F L D d i s p l a y s t a r t 0 1 0 1 0 0 b F L D o u t p u t c o n t r o l r e g i s t e r A d d r e s s F L D C O N F L D o u t p u t c o n t r o l r e g i s t e r s e t u p P 44 t o P 47 F L D o u t p u t r e v e r s e b i t O u t p u t n o r m a l l y P 44 t o P 47 F L D T o f f i s i n v a l i d b i t P e r f o r m n o r m a l l y P 97 d i m m e r o u t p u t c o n t r o l b i t D i m m e r o u t p u t C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f d o e s N O T g e n e r a t e H i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f g e n e r a t e s T o f f 2 S E T / R E S E T c h a n g e b i t G r a d a t i o n d i s p l a y d a t a i s r e s e t a t T o f f s e t a t T o f f

This page kept blank for layout purposes.

2.7.6 FLD operation (Display with digit expander M35501FP: column discrepancy)

The FLD controller can choose functions from those listed in Table 2.7.4. The circled items are described Remarks: Also refer to the M35501FP data sheet on http://www.infomicom.mesc.co.jp Table 2.7.4. Selectable functions Note 1: When selecting the FLD blanking interrupt, any one of 1 5 Tdisp, 2 5 Tdisp, or 3 5 Tdisp can be selected as Tscan time. Note 2: When selecting the gradation display mode, make sure to use 16-timing as the timing number. Operation(1) The FLD starts an automatic display when both the automatic display control bit and the display start bit are set to “1”. (2) The display data, the contents from the first address through the last address, in the FLD automatic display RAM for each port is output to each port. The last address is the result of decreasing the number indicated in the FLD data pointer from the first address. The grada- tion display control data is arranged at an address which is calculated by subtracting “70 16” from the stored address in the FLD automatic display RAM of the corresponding timing and pin. Bright display is performed by setting “0”, and dark display is performed by setting “1”. (3) The FLD data pointer counts down during Tdisp time. When the count reaches “FF 16”, the pointer is reloaded and starts counting over again. (4) Supply signals to the RESET pin and SEL pin of the M35501FP from ports P70 and P71, respectively. Supply the dimmer signal to the CLK pin from the DIMOUT (P97). (5) Input the OVFOUT output of the M35501FP to TB2IN (P72) and count the input signals as a count source with Timer B2. Generate the Timer A0 interrupt at FLD display intervals and confirm the value of Timer B2. If the value is incorrect, reset the M35501FP. (6) During FLD automatic display, the FLD automatic display can be interrupted by writing “0” to the display start bit. I t e mS e t - u pS e t - u p O I t e m T s c a n c o n t r o l N o t e F L D d i g i t i n t e r r u p t F L D b l a n k i n g i n t e r r u p t H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y S t r o n g W e a kO T i m i n g n u m b e r1 6 - t i m i n g 3 2- t i m i n g O P 97 d i m m e r o u t p u tN o r m a l p o r t D i m m e r o u t p u tO T d i s p c o u n t e r c o u n t s o u r c e f ( XI N ) / 3 2 f ( XI N ) / 1 2 8 O H i g h - b r e a k d o w n - v o l t a g e p o r t s S e c t i o n o f T o f f g e n e r a t e n o t g e n e r a t e Se c t i o n o f T o f f d o e s N O T g e n e r a t e Se c t i o n o f T o f f g e n e r a t e sO G r a d a t i o n d i s p l a y m o d e N o t e N o t s e l e c t i n g Se l e c t i n gO T o f f 2 S E T R E S E T R e s e t a t T o f f 2 Se t a t T o f f 2 O

Figure 2.7.22. Connection example of FLD automatic display D i g i t ( 1 6 ) F l u o r e s c e n t d i s p l a y ( F L D ) P 30– P 37 P 10– P 17 P 00– P 07 P 20– P 27 S e g m e n t ( 5 2 ) M 3 0 2 1 8 G r o u p M 3 5 5 0 1 F P C L K S E L R E S E T D I G 0– D I G 1 P 40– P 43 D I M O U T P 70 P 71 O V FI N P 60– P 67 P 50– P 57 O V FO U T C o n n e c t i o n e x a m p l e T B 2I N

N O V FO U T

• • • C L K D I G 0 D I G 1 D I G 1 4 D I G 1 5 M 3 5 5 0 1 F P
• • • R E S E T S E L O V FI N O V FO U T
• • • C L K D I G 0 D I G 1 D I G 1 4 D I G 1 5 M 3 5 5 0 1 F P C o l u m n d i s c r e p a n c y o c c u r N o i s e
• • • F L D 0– F L D 5 P 00– P 07, P 10– P 17, P 20– P 27, P 30– P 37, P 40– P 43, P 50– P 57, P 60– P 67) M 3 0 2 1 8 G r o u p C o r r e c t op e r a t i o n e x a m p l e I n co r r e c t op e r a t i o n e x a m p l e F L D 0– F L D 5 P 00– P 07, P 10– P 17, P 20– P 27, P 30– P 37, P 40– P 43, P 50– P 57, P 60– P 67) M 3 0 2 1 8 G r o u p Figure 2.7.23. Operation timing of FLD automatic display

Figure 2.7.24. Set-up procedure for FLD automatic display (1) 1 1 1 1 1 1 1 1 b D i s p l a y p i n p o r t s w i t c h o f P P P P a n d P s e t u p P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R 1 1 1 1 1 1 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 0 0 0 0 0 0 0 0 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s C 1 P D O R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 1 1 1 1 1 1 S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 0 0 0 0 0 0 0 0 b P o r t P d i g i t o u t p u t s e t r e g i s t e r A d d r e s s D 1 P D O R S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 0 1 0 0 0 0 1 b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D C m o d e r e g i s t e r s e t u p A u t o m a t i c d i s p l a y c o n t r o l b i t A u t o m a t i c d i s p l a y m o d e D i s p l a y s t a r t b i t S t o p d i s p l a y T s c a n c o n t r o l b i t s b b F L D d i g i t i n t e r r u p t T i m i n g n u m b e r c o n t r o l b i t t i m i n g m o d e G r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t S e l e c t i n g T d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t f XI N ) H i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t D r i v a b i l i t y w e a k C o n t i n u e d t o t h e n e x t p a g e 0 0 0 0 1 1 1 1 b P o r t P F L D p o r t s w i t c h r e g i s t e r A d d r e s s P F P R S e t P P t o n o r m a l I O p o r t s S e t P P t o F L D o u t p u t p o r t s F L D t o F L D 1 1 b P o r t P d i r e c t i o n r e g i s t e r A d d r e s s E P D S e t P t o o u t p u t p o r t f o r S E L s i g n a l o f M S e t P t o o u t p u t p o r t f o r R E S E T s i g n a l o f M M i n i t i a l i z a t i o n 0 0 b P o r t P A d d r e s s E D 1 P O u t p u t S E L s i g n a l L o f M O u t p u t R E S E T s i g n a l o f M N o t e N o t T o r e m o v e r e s e t s t a t e a f t e r r e t a i n i n g L l e v e l f o r ms o r m o r e o u t p u t H l e v e l w h e n C L K s i g n a l L

Figure 2.7.25. Set-up procedure for FLD automatic display (2) F L D d a t a p o i n t e r s e t u p 1 1 1 1 1 1 1 1 b T d i s p T o f f a n d T o f f t i m e s e t u p 1 1 0 0 1 0 0 0 b T d i s p t i m e s e t r e g i s t e r A d d r e s s T D I S P C o n t i n u e d f r o m t h e p r e v i o u s p a g e S e t C T d i s p c o u n t s o u r c e ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 1 1 1 1 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 1 0 1 1 0 1 0 0 b T o f f t i m e s e t r e g i s t e r A d d r e s s T O F F S e t B T o f f c o u n t s o u r c e 6 ms C o n d i t i o n s f XI N ) M H z C o u n t s o u r c e f XI N ) ms 1 1 1 1 1 1 1 1 b 0 0 0 0 1 1 1 1 b F L D d a t a p o i n t e r A d d r e s s F L D D P S e t d i g i t n u m b e r C o n t i n u e d t o t h e n e x t p a g e 0 1 0 1 0 0 b F L D o u t p u t c o n t r o l r e g i s t e r A d d r e s s F L D C O N F L D o u t p u t c o n t r o l r e g i s t e r s e t u p P 44 t o P 47 F L D o u t p u t r e v e r s e b i t O u t p u t n o r m a l l y P 44 t o P 47 F L D T o f f i s i n v a l i d b i t P e r f o r m n o r m a l l y P 97 d i m m e r o u t p u t c o n t r o l b i t D i m m e r o u t p u t C M O S p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f d o e s N O T g e n e r a t e H i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f T o f f g e n e r a t e / n o t g e n e r a t e b i t S e c t i o n o f T o f f g e n e r a t e s T o f f 2 S E T / R E S E T c h a n g e b i t G r a d a t i o n d i s p l a y d a t a i s r e s e t a t T o f f s e t a t T o f f 0 0 1 1 b T i m e r B m o d e r e g i s t e r A d d r e s s D 1 T B M R Ev e n t c o u n t e r m o d e T i m e r B a n d f u n c t i o n s s e t u p 0000 S e l e c t i o n o f e v e n t c o u n t e r m o d e C o u n t p o l a r i t y s e l e c t b i t b b C o u n t s e x t e r n a l s i g n a l s r i s i n g e d g e s I n v a l i d i n e v e n t c o u n t e r m o d e E v e n t c l o c k s e l e c t I n p u t f r o m T B N p i n N o t e N o t e: S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o “ 0 ” . I n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e “ 0 ” .

T i m e r A m o d e r e g i s t e r A d d r e s s T A M R Ti m e r m o d e T i m e r A a n d f u n c t i o n s s e t u p S e l e c t i o n o f t i m e r m o d e P u l s e o u t p u t f u n c t i o n s e l e c t b i t P u l s e i s n o t o u t p u t T A U T p i n i s a n o r m a l p o r t p i n G a t e f u n c t i o n s e l e c t b i t b b G a t e f u n c t i o n n o t a v a i l a b l e ( T A 0I N p i n i s a n o r m a l p o r t p i n ) 0 ( M u s t a l w a y s b e “ 0 ” i n t i m e r m o d e ) C o u n t s o u r c e s e l e c t b i t b b b 0000 b b b b T i m e r A r e g i s t e r A d d r e s s T A Se t 3 2 4 01 Di v i d e r a t i o T i m e r A s e t u p C o n t i n u e d f r o m t h e p r e v i o u s p a g e b b b b T i m e r B r e g i s t e r A d d r e s s T B S e t F F F F1 Di v i d e r a t i o T i m e r B s e t u p b C o u n t s t a r t f l a g A d d r e s s T A B S R C o u n t s t a r t f l a g s e t u p b T A i n t e r r u p t c o n t r o l r e g i s t e r A d d r e s s T A I C T i m e r A i n t e r r u p t c o n t r o l r e g i s t e r s e t u p I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t b b b L e v e l i n t e r r u p t d i s a b l e d L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l L e v e l I n t e r r u p t r e q u e s t b i t N o t e I n t e r r u p t n o t r e q u e s t e d N o t h i n g i s a s s i g n e d N o t e O n l y c a n b e w r i t t e n t o t h i s b i t D o n o t w r i t e T i m e r A 0 c o u n t s t a r t f l a g S t a r t s c o u n t i n g T i m e r B 2 c o u n t s t a r t f l a g S t a r t s c o u n t i n g b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t a r t D i s p l a y s t a r t b i t D i s p l a y F L D d i s p l a y s t a r t Figure 2.7.26. Set-up procedure for FLD automatic display (3)

T A i n t e r r u p t r o u t i n e P u s h re g i s t e r s a n d a n y o t h e r s e t u p R T I T i m e r B d a t a c h e c k 0 0 b M i n i t i a l i z a t i o n 0 1 b P o r t P A d d r e s s E D 1 P O u t p u t S E L s i g n a l L o f M O u t p u t R E S E T s i g n a l H o f M N o t e N o t T o r e m o v e r e s e t s t a t e a f t e r r e t a i n i n g L l e v e l f o r ms o r m o r e o u t p u t H l e v e l w h e n C L K s i g n a l L P o r t P A d d r e s s E D 1 P O u t p u t S E L s i g n a l L o f M O u t p u t R E S E T s i g n a l L o f M S e t d i s p l a y d a t a t o F L D a u t o m a t i c d i s p l a y R A M b b b b T i m e r B r e g i s t e r A d d r e s s T B S e t F F F F1 Di v i d e r a t i o ( T i m e r B 2 ) s e t - u p b C o u n t s t a r t f l a g A d d r e s s T A B S R C o u n t s t a r t f l a g s e t u p T i m e r A 0 c o u n t s t a r t f l a g S t a r t s c o u n t i n g b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t a r t D i s p l a y s t a r t b i t D i s p l a y b F L D C m o d e r e g i s t e r A d d r e s s F L D M F L D d i s p l a y s t o p D i s p l a y s t a r t b i t S t o p d i s p l a y P o p re g i s t e r s C o r r e c t d a t a F I n co r r e c t d a t a e x c e p t F Figure 2.7.27. Set-up procedure for FLD automatic display when detecting column discrepancy

2.7.7 Precautions for FLD controller

(1) Set a value of “0316” or more to the Toff1 time set register. (2) When displaying in the gradation display mode, select the 16-timing mode with the timing number control bit.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.8 A-D Converter

Table 2.8.1. Conversion time every operation clock Note 1: The number of conversion cycles per one analog input pin. Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)

2.8.1 Overview

The A-D converter used in the M30218 group operates on a successive conversion basis. The following is an overview of the A-D converter. (1) Mode The A-D converter operates in one of five modes: (a) One-shot mode Carries out A-D conversion on input level of one specified pin only once. (b) Repetition mode Repeatedly carries out A-D conversion on input level of one specified pin. (c) One-shot sweep mode Carries out A-D conversion on input level of two or more specified pins only once. (d) Repeated sweep mode 0 Repeatedly carries out A-D conversion on input level of two or more pins. (e) Repeated sweep mode 1 Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times. (2) Operation clock The operation clock can be selected from the following: f AD , divide-by-2 fAD , and divide-by-4 fAD . The fAD frequency is equal to that of the CPU’s main clock. (3) Conversion time Number of conversion for A-D convertor varies depending on resolution as given. Table 2.8.1 shows relation between the A-D converter operation clock and conversion time. Sample & Hold function selected: 33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution No Sample & Hold function: 59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution Frequency selection bit 0 A-D converter's operation clock Min. conversion cycles (Note 1) Min. conversion time (Note 2) 8-bit mode 8-bit mode 10-bit mode 10-bit mode 0 1 φAD = 4 fAD φAD = 2 fAD

28 X φAD

33 X φAD

11.2µs 13.2µs 6.6µs 5.6µs Frequency selection bit 1 0 1 Invalid φAD = fAD 2.8µs 3.3µs

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (4) Functions selection (a) Sample & Hold function Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3 cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock for A-D conversion to 1 MHz or higher. (b) 8-bit A-D to 10-bit A-D switching function Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8 higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolu- tion and 8-bit resolution are given below: 10-bit resolution (Vref X n / 2 10 ) – (Vref X 0.5 / 1010 ) (n = 1 to 1023), 0 (n = 0) 8-bit resolution (Vref X n / 28 ) – (Vref X 0.5 / 210 ) (n = 1 to 255), 0 (n = 0) (c) Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1 µs or longer after connecting Vref. The following are exsamples in which functions (a) through (c) are selected:

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.2. A-D converter-related registers (1) A - D c o n t r o l r e g i s t e r 0 ( N o t e ) S y m b o lA d d r e s sW h e n r e s e t A D C O N D 6 0 X X B i t n a m eF u n c t i o nB i t s y m b o l b A n a l o g i n p u t p i n s e l e c t b i t 0 0 0 : A N 0 i s s e l e c t e d A N 1 i s s e l e c t e d A N 2 i s s e l e c t e d A N 3 i s s e l e c t e d A N 4 i s s e l e c t e d A N 5 i s s e l e c t e d A N 6 i s s e l e c t e d A N 7 i s s e l e c t e d C H 0 C H 1 C H 2 A - D o p e r a t i o n m o d e s e l e c t b i t 0 0 0 : O n e - s h o t m o d e R e p e a t m o d e S i n g l e s w e e p m o d e R e p e a t s w e e p m o d e R e p e a t s w e e p m o d e M D 0 M D 1 M u s t a l w a y s b e “ 0 ” . A D S T A - D c o n v e r s i o n s t a r t f l a g0 : A - D c o n v e r s i o n d i s a b l e d A D c o n v e r s i o n s t a r t e d F r e q u e n c y s e l e c t b i t 00 : fA D / 4 i s s e l e c t e d fA D / i s s e l e c t e dC K S 0 WR b b b b b N o t e : I f t h e A - D c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g A - D c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.3. A-D converter-related registers (2) A - D c o n t r o l r e g i s t e r 1 ( N o t e ) S y m b o l A d d r e s sW h e n r e s e t A D C O N D 6 0 B i t n a m eF u n c t i o nB i t s y m b o l b A - D s w e e p p i n s e l e c t b i t S C A N 0 S C A N 1 M D 2 B I T S 8 / 1 0 - b i t m o d e s e l e c t b i t0 : 8 - b i t m o d e b i t m o d e V C U T V r e f c o n n e c t b i t A - D o p e r a t i o n m o d e s e l e c t b i t 0 : A n y m o d e o t h e r t h a n r e p e a t s w e e p m o d e R e p e a t s w e e p m o d e 0 : V r e f n o t c o n n e c t e d V r e f c o n n e c t e d M u s t a l w a y s b e “ 0 ” . WR W h e n s i n g l e s w e e p a n d r e p e a t s w e e p m o d e a r e s e l e c t e d 0 0 : A N 0, A N 1 ( 2 p i n s ) A N 0 t o A N 3 p i n s A N 0 t o A N 5 p i n s A N 0 t o A N 7 p i n s b b W h e n r e p e a t s w e e p m o d e 1 i s s e l e c t e d 0 0 : A N 0 ( 1 p i n ) A N 0, A N 1 p i n s A N 0 t o A N 2 p i n s A N 0 t o A N 3 p i n s b b F r e q u e n c y s e l e c t b i t 10 : fA D / 2 o r fA D / 4 i s s e l e c t e d fA D i s s e l e c t e dC K S 1 N o t e : I f t h e A - D c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g A - D c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.4. A-D converter-related registers (3) E i g h t l o w - o r d e r b i t s o f A - D c o n v e r s i o n r e s u l t A - D c o n t r o l r e g i s t e r 2 ( N o t e ) S y m b o lA d d r e s sW h e n r e s e t A D C O N D 6 X X X X X X X B i t n a m eF u n c t i o nB i t s y m b o lW R b A - D c o n v e r s i o n m e t h o d s e l e c t b i t

0 W i t h o u t s a m p l e a n d h o l d

W i t h s a m p l e a n d h o l dS M P N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e A - D r e g i s t e r i S y m b o lA d d r e s sW h e n r e s e t A D i i t o ) 0 C t o C 6 I n d e t e r m i n a t e F u n c t i o nW R b b b

• D u r i n g 1 0 - b i t m o d e T w o h i g h o r d e r b i t s o f A D c o n v e r s i o n r e s u l t N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e
• D u r i n g 8 - b i t m o d e W h e n r e a d t h e c o n t e n t i s i n d e t e r m i n a t e N o t e : I f t h e A - D c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g A - D c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In one-shot mode, choose functions from those listed in Table 2.8.2. Operations of the circled items are

2.8.2 Operation of A-D converter (one-shot mode)

Figure 2.8.5. Operation timing of one-shot mode Operation Table 2.8.2. Choosed functions (1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating. (2) After A-D conversion is completed, the content of the successive comparison register (con- version result) is transmitted to A-D register i. At this time, the A-D conversion interrupt re- quest bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter stops operating. Item Set-up Operation clock fAD Divided-by-4 fAD / divided- by-2 fAD / fAD 8-bit / 10-bit Sample & Hold Not activated Activated O O Resolution Analog input pin One of AN 0 pin to AN7 pin O O A-D conversion start flag “1” “0” A-D conversion interrupt request bit A-D register i “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Result fAD 8-bit resolution : 28 fAD cycles 10-bit resolution : 33 fAD cycles Set to “1” by software (1) Start A-D conversion (2) A-D conversion is complete Note:When fAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 fAD cycles for 8-bit resolution and 59 fAD cycles for 10-bit resolution.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.6. Set-up procedure of one-shot mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016] AD0 A-D register 1 [Address 03C316, 03C216] AD1 A-D register 2 [Address 03C516, 03C416] AD2 A-D register 3 [Address 03C716, 03C616] AD3 A-D register 4 [Address 03C916, 03C816] AD4 A-D register 5 [Address 03CB16, 03CA16] AD5 A-D register 6 [Address 03CD16, 03CC16] AD6 A-D register 7 [Address 03CF16, 03CE16] AD7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion Stop A-D conversion b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected One-shot mode is selected (Note) Nothing is arranged for this bit. Fix “0” to this bit. A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 000 0 Invalid in one-shot mode Vref connect bit 1 : Vref connected Nothing is arranged for these bits. Fix “0” to these bits. 00 0 1 b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Note: Rewrite to analog input pin select bit after changing A-D operation mode.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In repeat mode, choose functions from those listed in Table 2.8.3. Operations of the circled items are

2.8.3 Operation of A-D Converter (in repeat mode)

(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating. (2) After the first conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit does not go to “1”. (3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. The conversion result is transmitted to A-D register i every time a conversion is completed. Table 2.8.3. Choosed functions Operation Figure 2.8.7. Operation timing of repeat mode A-D conversion start flag “1” “0” A-D register i Result Set to “1” by software φAD 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (1) Start A-D conversion (2) Conversion result is transferred to the A-D register (3) A-D conversion is complete Cleared to “0” by software A-D conversion Result Stop Convert Convert Convert Stop Note:When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles Item Set-up Operation clock fAD Divided-by-4 fAD / divided- by-2 fAD / fAD 8-bit / 10-bit Sample & Hold Not activated ActivatedO O Resolution Analog input pin One of AN 0 pin to AN7 pin O O

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.8. Set-up procedure of repeat mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Transmitting conversion result to A-D register i Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016] AD0 A-D register 1 [Address 03C316, 03C216] AD1 A-D register 2 [Address 03C516, 03C416] AD2 A-D register 3 [Address 03C716, 03C616] AD3 A-D register 4 [Address 03C916, 03C816] AD4 A-D register 5 [Address 03CB16, 03CA16] AD5 A-D register 6 [Address 03CD16, 03CC16] AD6 A-D register 7 [Address 03CF16, 03CE16] AD7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b2 b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected Repeat mode is selected (Note) A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 000 1 Invalid in Repeat mode Vref connect bit 1 : Vref connected Nothing is arranged for these bits. Fix “0” to these bits 00 0 1 Nothing is arranged for this bit. Fix “0” to this bit. Start A-D conversion b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Note: Rewrite to analog input pin select bit after changing A-D operation mode.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In single sweep mode, choose functions from those listed in Table 2.8.4. Operations of the circled items

2.8.4 Operation of A-D Converter (in single sweep mode)

Figure 2.8.9. Operation timing of single sweep mode Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. The A-D converter converts all analog input pins selected by the user. The conversion result is trans- mitted to A-D register i corresponding to each pin, every time conversion on one pin is com- pleted. (3) When the A-D conversion on all the analog input pins selected is completed, the A-D conver- sion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”. The A-D converter stops operating. Table 2.8.4. Choosed functions Item ItemSet-up Set-up Operation clock fAD Divided-by-4 fAD / divided- by-2 fAD / fAD 8-bit / 10-bit O Resolution Analog input pin AN 0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) O O Sample & Hold Not activated ActivatedO Cleared to “0” when interrupt request is accepted, or cleared by software A-D conversion start flag “1” “0” A-D register 0 A-D register 1 φAD A-D register i Result Result Result Set to “1” by software 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (1) Start A-D conversion After A-D conversion on AN0 pin is complete, A-D converter begins converting all pins selected A-D conversion is complete (2) Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. (3) A-D conversion interrupt request bit “1” “0”

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.10. Set-up procedure of single sweep mode b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Reading conversion result Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016] AD0 A-D register 1 [Address 03C316, 03C216] AD1 A-D register 2 [Address 03C516, 03C416] AD2 A-D register 3 [Address 03C716, 03C616] AD3 A-D register 4 [Address 03C916, 03C816] AD4 A-D register 5 [Address 03CB16, 03CA16] AD5 A-D register 6 [Address 03CD16, 03CC16] AD6 A-D register 7 [Address 03CF16, 03CE16] AD7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion Stop A-D conversion b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 A-D sweep pin select bit (Note) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note) 0 (Must always be “0” in Single sweep mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected Single sweep mode is selected (Note) Nothing is arranged for this bit. Fix “0” to this bit. A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 0 Vref connect bit 1 : Vref connected 00 0 1 Invalid in single sweep mode b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Note: Rewrite to analog input pin select bit after changing A-D operation mode. Nothing is arranged for these bits. Fix “0” to these bits.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In repeat sweep mode 0, choose functions from those listed in Table 2.8.5. Operations of the circled items

2.8.5 Operation of A-D Converter (in repeat sweep mode 0)

Table 2.8.5. Choosed functions (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) The A-D converter converts all pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin every time A-D conversion on the pin is com- pleted. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. Figure 2.8.11. Operation timing of repeat sweep mode 0 Item ItemSet-up Set-up Operation clock fAD Divided-by-4 fAD / divided- by-2 fAD / fAD 8-bit / 10-bit O Resolution Analog input pin AN 0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) O O Sample & Hold Not activated ActivatedO (2) AN1 conversion begins after AN0 conversion is complete A-D conversion start flag “1” “0” A-D register 0 A-D register 1 φAD A-D register i Result Result Result 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (3) Consecutive conversion A-D conversion is complete (1) Start A-D conversion Set to “1” by software. Cleared to “0” by software Note:When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. (4)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.12. Set-up procedure of repeat sweep mode 0 b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Transmitting conversion result to A-D register i Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016] AD0 A-D register 1 [Address 03C316, 03C216] AD1 A-D register 2 [Address 03C516, 03C416] AD2 A-D register 3 [Address 03C716, 03C616] AD3 A-D register 4 [Address 03C916, 03C816] AD4 A-D register 5 [Address 03CB16, 03CA16] AD5 A-D register 6 [Address 03CD16, 03CC16] AD6 A-D register 7 [Address 03CF16, 03CE16] AD7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 A-D sweep pin select bit (Note) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat sweep mode 0) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : f AD /2 or fAD /4 is selected 1 : fAD is selected Repeat sweep mode 0 is selected (Note) Nothing is arranged for this bit. Fix “0” to this bit. A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 1 Vref connect bit 1 : Vref connected 00 0 1 Invalid in repeat sweep mode 0 Repeatedly carries out A-D conversion on pins selected through the A-D sweep pin select bit. Note: Rewrite to analog input pin select bit after changing A-D operation mode. Nothing is arranged for these bits. Fix “0” to these bits.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.8.6 Operation of A-D Converter (in repeat sweep mode 1)

Figure 2.8.14. Operation timing of repeat sweep mode 1 In repeat sweep mode 1, choose functions from those listed in Table 2.8.6. Operations of the circled items are 2.8.15 shows the set-up procedure. Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion on voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conver- sion from the AN0 pin again. (See Figure 2.8.13.) The conversion result is transmitted to A-D register i every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”. Table 2.8.6. Choosed functions Figure 2.8.13. ANi pin's sweep sequence in repeat sweep mode 1 Item ItemSet-up Set-up Operation clock fAD Divided-by-4 fAD / divided- by-2 fAD / fAD 8-bit / 10-bit O Resolution Analog input pin An0 (1 pin) / AN0 and AN1 (2 pins) / AN0 to AN2 (3 pins) / AN 0 to AN3 (4 pins) O O Sample & Hold Not activated ActivatedO When AN 0 is selected Converted analog input pin Time 0000000000 When AN 0, AN1 are selected Converted analog input pin Time 0000000 1111111 Converted analog input pin Time 0000000 222222 111111 When AN 0 to AN2 are selected Converted analog input pin Time 000000 3333 11111 2222 When AN 0 to AN3 are selected A-D conversion start flag “1” “0” A-D register 0 A-D register 1 fAD A-D register 2 Result Result Result Set to “1” by software Result Cleared to “0” by software (2) (3) Consecutive conversion 8-bit resolution : 28 fAD cycles 10-bit resolution : fAD cycles A-D conversion is complete (4) Conversion result is transfered to A-D conversion register 0 Note: When fAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 fAD cycles for 8-bit resolution and 59 fAD cycles for 10-bit resolution. 8-bit resolution : fAD cycles 10-bit resolution : fAD cycles 8-bit resolution : 28 fAD cycles 10-bit resolution : 33 fAD cycles 8-bit resolution :

28 AD cycles

10-bit resolution :

33 AD cycles

(1) Start AN0 pin conversion

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.15. Set-up procedure of repeat sweep mode 1 b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Transmitting conversion result to A-D register i Eight low-order bits of A-D conversion result b7 b0 (b15) (b8) b7 b0 A-D register 0 [Address 03C116, 03C016] AD0 A-D register 1 [Address 03C316, 03C216] AD1 A-D register 2 [Address 03C516, 03C416] AD2 A-D register 3 [Address 03C716, 03C616] AD3 A-D register 4 [Address 03C916, 03C816] AD4 A-D register 5 [Address 03CB16, 03CA16] AD5 A-D register 6 [Address 03CD16, 03CC16] AD6 A-D register 7 [Address 03CF16, 03CE16] AD7 During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Start A-D conversion b7 b0 Setting A-D conversion start flag A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion b7 b0 Selecting Sample and hold A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold b7 b0 Setting A-D control register 0 and A-D control register 1 A-D control register 0 [Address 03D616] ADCON0 A-D sweep pin select bit (Note) 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 b7 b0 A-D control register 1 [Address 03D716] ADCON1 A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat sweep mode 1) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selected Repeat sweep mode 1 is selected (Note) Nothing is arranged for this bit. Fix “0” to this bit. A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selected 001 1 Vref connect bit 1 : Vref connected 00 1 1 Invalid in repeat sweep mode 1 Converts non-selected pin after converting pins selected through the A-D sweep pin select bit. Note: Rewrite to analog input pin select bit after changing A-D operation mode. Nothing is arranged for these bits. Fix “0” to these bits.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.8.7 Precautions for A-D Converter

Figure 2.8.16. Use of capacitors to reduce noice (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped. In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after an elapse of 1 µs or longer. (2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the V REF pin from an independent source. It is recommended to connect a capacitor between the AVss pin and the AVcc pin, between the AVss pin and the VREF pin, and between the AVss pin and the analog input pin (ANi). Figure 2.8.16 shows an example of connecting the capacitors to these pins. (3) Set the direction register of the the port corresponding to a pin to be used as an analog input pin to input. (4) Rewrite to analog input pin after changing A-D operation mode. The two cannot be set at the same time. (5) When using the one-shot or single sweep mode Confirm that A-D conversion is complete before reading the A-D register. (Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.) (6) When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock. AV SS AV CC VREF AN i Microcomputer C1 C2 C3 C1 ‡ 0.47 mF, C2 ‡ 0.47 mF, C3 ‡ 100 pF (for reference) Use thick and shortest possible wiring to connect capacitors. Note 1: Note 2: VCC

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) The A-D converter compares the reference voltage (Vref) generated internally based on the contents of the successive comparison register with the analog input voltage (VIN) input from the analog input pin. Each bit of the comparison result is stored in the successive comparison register until analog-to-digital conversion (successive comparison method) is complete. If a trigger occurs, the A-D converter carries out the following: 1. Fixes bit 9 of the successive comparison register. Compares Vref with V IN: [In this instance, the contents of the successive comparison register are “10000000002” (default).] Bit 9 of the successive comparison register varies depending on the comparison re- sult as follows. If Vref < V IN, then “1” is assigned to bit 9. If Vref > VIN, then “0” is assigned to bit 9. 2. Fixes bit 8 of the successive comparison register. Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN. Bit 8 of the successive comparison register varies depending on the comparison result as follows: If Vref < V IN, then “1” is assigned to bit 8. If Vref > VIN, then “0” is assigned to bit 8. 3. Fixes bit 7 through bit 0 of the successive comparison register. Carries out step 2 above on bit 7 through bit 0. After bit 0 is fixed, the contents of the successive comparison register (conversion result) are transmitted to A-D register i. Vref is generated based on the latest content of the successive comparison register. Table 2.8.7 shows the relationship of the successive comparison register contents and Vref. Table 2.8.8 shows how the successive comparison register and Vref vary while A-D conversion is in progress. Figure 2.8.17 shows theoretical A-D conversion characteristics.

2.8.8 Method of A-D Conversion (10-bit mode)

Table 2.8.7. Relationship of the successive comparison register contents and Vref Successive approximation register : n Vref (V) x –1024 VREF 2048 VREFn 1 to1023

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.8.17. Theoretical A-D conversion characteristics (10-bit mode) Table 2.8.8. Variation of the successive comparison register and Vref while A-D conversion is in progress (10-bit mode) 000000000 000000000 100000000 n9 n8 10000000 n9 n8 n7 n6 n5 n4 n3 n2 n1 0 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 b9 b0 1st comparison result 2nd comparison result Successive approximation register V ref change A-D converter stopped 1st comparison 2nd comparison 3rd comparison 10th comparison Conversion complete VREF ± ±2 VREF VREF 1024 – 2048 VREF [V] 2 [V] VREF 2048 VREF [V] ± ±2 VREF VREF VREF – 2048 VREF [V] 4n9 = 1 + n9 = 0 – n8 = 1 + VREFn8 = 0 – VREF VREF – 2048 VREF [V] VREF VREF VREF This data transfers to the bit 0 to bit 9 of A-D register. 00016 00116 00216 00316 3FE 16 3FF16 Result of A-D conversion Analog input voltage VREF 1024 x 1 VREF 1024 x 2 VREF 1024 x 3 x 1021VREF 1024 VREF 1024 x 1022 VREF 1024 x 1023 VREF VREF 1024 x 0.5 Theoretical A-D conversion characteristic Ideal A-D conversion characteristic

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter, the voltage compared is different by 3 V REF /2048 (see what are underscored in Table 2.8.9), and differences in stepping points of output codes occur as shown in Figure 2.8.18.

2.8.9 Method of A-D Conversion (8-bit mode)

Figure 2.8.18. The level conversion characteristics of 8-bit mode and 8-bit A-D converter Table 2.8.9. The comparison voltage in 8-bit mode compared to 8-bit A-D converter Comparison voltage Vref 8-bit mode 8-bit A-D converter VREF 210 VREFn x 0.5 x – VREF VREFn x 0.5 n = 0 n = 1 to 255 x Analog input voltage (mV) Output code (Result of A-D conversion) Analog input voltage (mV) Output code (Result of A-D conversion) 10-bit mode 8-bit mode 8bit-mode 10bit-mode 10 30 17.5 37.5 (Note) Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V) Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V) Note: Differences in stepping points of output code for analog input voltage.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Table 2.8.10. Variation of the successive comparison register and Vref while A-D conversion is in progress (8-bit mode) Figure 2.8.19. Theoretical A-D conversion characteristics (8-bit mode) 000000000 000000000 100000000 n9 n8 10000000 n9 n8 n7 n6 n5 n4 n3 100 n9 n8 n7 n6 n5 n4 n3 n2 00 b9 b0 1st comparison result 2nd comparison result Successive approximation register Vref change A-D converter stopped 1st comparison 2nd comparison 3rd comparison 8th comparison Conversion complete ± ±2 VREF VREF 256 – 2048 VREF [V] VREF [V] VREF 2048 VREF [V] VREF VREF –2048 VREF [V] ± ±2 VREF VREF VREF – 2048 VREF [V] VREFn9 = 1 + VREF n9 = 0 – VREFn8 = 1 + VREF n8 = 0 – This data transfers to bit 0 to bit 7 of A-D register. 0016 0116 0216 0316 FE 16 FF16 Result of A-D conversion Analog input voltage x 2VREF 256 VREF 256 x 3 x 4VREF 256 VREF 256 x 254 VREF 256 x 255 VREF VREF 2048 x 3 Theoretical A-D conversion characteristic of general 8-bit A-D converter

0 VREF

Theoretical A-D conversion characteristic in the 8-bit mode

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.8.10 Absolute Accuracy and Differential Non-Linearity Error

• Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A-D conversion characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A-D conversion characteristics, is used as an ana- log input voltage. For example, if 10-bit resolution is used and if V REF (reference voltage) = 5.12 V, then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input voltages. If analog input voltage is 25 mV, “absolute accuracy =± 3LSB” refers to the fact that actual A-D conversion falls on a range from “002 16” to “00816” though an output code, “00516”, can be ex- pected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included in absolute accuracy. Also, all the output codes for analog input voltage between V REF and AVcc becomes “3FF16”. Figure 2.8.20. Absolute accuracy (10-bit resolution) 00016 00116 00216 00316 00416 00516 00616 Analog input voltage (mV) Theoretical A-D conversion characteristic 51 01 52 02 53 03 54 04 55 05 5 00716 00816 00916 00A16 00B16 +3LSB –3LSB Output code (result of A-D conversion)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

• Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical A- D conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code). If 10-bit resolution is used and if V REF (reference voltage) = 5.12 V, “differential non-linearity error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10 mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV (see 5.2 A-D converter's standard characteristics). Figure 2.8.21. Differential non-linearity error (10-bit resolution) 00016 00116 00216 00316 00416 00516 00616 Analog input voltage (mV) Differential non-linear error 5 1 01 5 2 02 5 3 03 54 0 4 5 00716 00816 00916 Output code (result of A-D conversion) 1LSB width for theoretical A-D conversion characteristic

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.8.11 Internal Equivalent Circuit of Analog Input

Figure 2.8.22 shows the internal equivalent circuit of analog input. Figure 2.8.22. Internal equivalent circuit to analog input ON resistor approx. 2kW A-D successive conversion register Analog input voltage AVcc AVss Chopper-type amplifier A-D conversion interrupt request Vcc Vss VIN A-D control register 0 Comparison voltage Comparison reference voltage (Vref) generator VREF AVss Vref b2 b1 b0 Vcc Vss AN i Wiring resistor approx. 0.2kW ON resistor approx. 0.6kW SW2 Sampling control signal SW1 C = Approx. 3.0pF SW3SW4 AMP ON resistor, approx. 5kW SW2 Reference control signal Resistor ladder Control signal for SW2 Control signal for SW3 Connect to Connect to Comparison Connect to Connect to Sampling i ladder-type switches i ladder-type wiring resistors ON resistor approx. 0.6kW AN0 Parasitic diode SW1 SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A-D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A-D conversion is not in progress. Parasitic diode Warning: Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. (i = 8) (i = 8)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.8.23 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.8.22. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D converter’s resolution be Y. Vc is generally V C = VIN {1 – e } And when t = T, VC =VIN – VIN=VIN(1 – ) e = – =ln Hence, R0 = – – R Each value is R = 7.8 kΩ , C = 3 pF, T = 0.3 us in the A-D conversion mode with sample & hold. For example, when the A-D converter’s resolution is 10 bits and precision (error) of the A-D converter is 0.1 LSB, Y = 10, X = 0.1LSB. Hence, R0 = – –7.8 X10 3 3.0 X 103

2.8.12 Sensor’s Output Impedance under A-D Conversion

Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D con- based on the LSB values. Figure 2.8.23 A circuit equivalent to the A-D conversion terminal C (R0 +R) T C (R0 + R) T C (R0 + R) t Y X Y X Y X Y X C • ln T Y X

3.0 X 10 –12 • ln

0.1

0.3 X 10-6

C (3.0pF)VIN Microprocessor's inside Sensor-equivalent circuit R (7.8kW)R 0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Table 2.8.11. Output impedance values based on the LSB values (1) Table 2.8.12. Output impedance values based on the LSB values (2) f(XIN) (MHz) Cycle (ms) Sampling time (ms) R (kohm) C (pF) Accuracy (LSB) R0 (kohm) 10 0.1 0.3 (3 5 cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 10 0.1 0.2 (2 5 cycle, sample & hold bit is disabled) 7.8 3.0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 f(XIN) (MHz) Cycle (ms) Sampling time (ms) R (kohm) C (pF) Accuracy (LSB) R0 (kohm) 10 0.1 0.3 (3 5 cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 10 0.1 0.2 (2 5 cycle, sample & hold bit is disabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.9 D-A Converter

Figure 2.9.2. D-A converter-related registers Figure 2.9.1. Memory map of D-A converter-related registers

2.9.1 Overview

The D-A converter used in the M30218 group is based on the 8-bit R-2R technique. (1) Output voltage The D-A converter outputs voltage within a range from 0 V to VREF . The output voltage is determined by VREF /(256) X the D-A register contents. The D-A converter is not effected by the Vref connection bit of the A-D converter. (2) Conversion time tsu = 3 µs (3) Output from the D-A converter and the direction register To use the D-A converter, do not set the direction register of the relevant port to output. (4) Pins related to the D-A converter

• DA0 pin, DA1 pin Output pins of the D-A converter
• AVcc pin The power source pin of the analog section
• V REF pin Input pin of the reference voltage
• AVss pin The GND pin of the analog section (5) Registers related to the D-A converter Figure 2.9.1 shows the memory map of D-A converter-related registers, and Figure 2.9.2 shows D-A converter-related registers. (6) Note D-A output pins shared with P9 7 and P96. The two pins are input ports and floating at the reset. 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) D-A control register Symbol Address When reset DACON 03DC 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 D-A0 output enable bit DA0E Bit symbol Bit name Function R W 0 : Output disabled 1 : Output enabled D-A1 output enable bit 0 : Output disabled 1 : Output enabled DA1E Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. D-A register Symbol Address When reset DAi (i = 0,1) 03D816, 03DA 16 Indeterminate WR b7 b0 Function R W Output value of D-A conversion

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R The following is the D-A converter operation. Figure 2.9.3 shows the set-up procedure.

2.9.2 D-A Converter Operation

(1) Writing a value to the D-A register i starts D-A conversion. (2) Setting the D-Ai output enable bit to “1” outputs an analog signal on the DAi pin. (3) The D-A converter continues outputting an analog signal until the D-A output enable bit is set to “0”. Operation Figure 2.9.3. Set-up procedure of D-A converter Setting D-A register D-A register 0 [Address 03D816] DA0 D-A register 1 [Address 03DA16] DA1 Output value of D-A conversion b7 b0 D-A0 output enable bit 1 : Output enabled Setting D-A control register D-A Control register [Address 03DC16] DACON b7 b0 D-A1 output enable bit 1 : Output enabled

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.10 DMAC

2.10.1 Overview

DMAC transfers one data item held in the source address to the destination address every time a transfer request is generated. The following is a DMAC overview. (1) Source address and destination address Both the register which indicates a source and the register which indicates a destination comprise of 24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the address in either the source register or the destination register can be incremented. However, both registers cannot be incremented. The links between the source and destination are as follows: (a) A fixed address from an arbitrary 1M bytes space (b) An arbitrary 1M bytes space from a fixed address (c) A fixed address from another fixed address (2) The number of bits of data transferred The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is se- lected, up to 128 K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA interrupt occurs when the transfer counter underflows. (3) DMA transfer factor The DMA transfer factor can be selected from the following 15 factors: falling edge of INT0/INT1 pin, timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt request through timer B2 interrupt request, UART0 transmission interrupt request, UART0 reception interrupt request, UART1 transmission interrupt request, UART1 reception interrupt request, A-D conversion interrupt request, and software trigger. When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interrupt request bit. When other factor is selected, DMA transfer is generated by generating corresponding interrupt request. (4) Channel priority If DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0. (5) Writing to a register When writing to the source register or the destination register with DMA enabled, the content of the register with a fixed address will change at the time of writing. Therefore, the user should not write to a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with ‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having been disabled. The reload register can be written to, as in normal conditions. (6) Reading to a register The reload register can be read to, as in normal conditions.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.10.2. DMAC-related registers (1) D M A i r e q u e s t c a u s e s e l e c t r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t D M i S L i B B 6 0 B i t n a m e F u n c t i o n RB i t s y m b o l W b 7 b 6 b 5 b 4 b 3 b 2 b 1 b D M A r e q u e s t c a u s e s e l e c t b i tD S E L 0 D S E L 1 D S E L 2 D S E L 3 S o f t w a r e D M A r e q u e s t b i t I f s o f t w a r e t r i g g e r i s s e l e c t e d , a D M A r e q u e s t i s g e n e r a t e d b y s e t t i n g t h i s b i t t o W h e n r e a d t h e v a l u e o f t h i s b i t i s a l w a y s D S R D M A i c o n t r o l r e g i s t e r S y m b o lA d d r e s sW h e n r e s e t D M i C O N i C 1 C 1 6 0 X B i t n a m e F u n c t i o nB i t s y m b o l R W b 7 b 6 b 5 b 4 b 3 b 2 b 1 b T r a n s f e r u n i t b i t s e l e c t b i t 0 : 1 6 b i t s b i t sD M B I T D M A S L D M A S D M A E R e p e a t t r a n s f e r m o d e s e l e c t b i t 0 : S i n g l e t r a n s f e r R e p e a t t r a n s f e r D M A r e q u e s t b i t ( N o t e 1 ) 0 : D M A n o t r e q u e s t e d D M A r e q u e s t e d 0 : D i s a b l e d E n a b l e d 0 : F i x e d F o r w a r d D M A e n a b l e b i t S o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t N o t e D e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t N o t e 0 : F i x e d F o r w a r d D S D D A D N o t e 1 : D M A r e q u e s t c a n b e c l e a r e d b y r e s e t t i n g t h e b i t . N o t e T h i s b i t c a n o n l y b e s e t t o N o t e S o u r c e a d d r e s s d i r e c t i o n s e l e c t b i t a n d d e s t i n a t i o n a d d r e s s d i r e c t i o n s e l e c t b i t c a n n o t b e s e t t o s i m u l t a n e o u s l y b b b b 0 0 0 0 : F a l l i n g e d g e o f I N T 0 / I N T 1 p i n N o t e S o f t w a r e t r i g g e r T i m e r A T i m e r A T i m e r A T i m e r A T i m e r A T i m e r B T i m e r B T i m e r B U A R T t r a n s m i t U A R T r e c e i v e U A R T t r a n s m i t U A R T r e c e i v e A D c o n v e r s i o n I n h i b i t e d N o t e : A d d r e s s 0 3 B 81 6 i s f o r I N T 0 ; a d d r e s s 0 3 B A1 6 i s f o r I N T 1 . N o t e N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e “ 0 ” . T h e v a l u e i f r e a d t u r n s o u t t o b e N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e “ 0 ” . T h e v a l u e i f r e a d t u r n s o u t t o b e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.10.3. DMAC-related registers (2) b7 b0 b7 b0 (b8)(b15) Function RW

• Transfer counter Set a value one less than the transfer count Symbol Address When reset TCR0 0029 16, 002816 Indeterminate TCR1 0039 16, 003816 Indeterminate DMAi transfer counter (i = 0, 1) Transfer count specification 000016 to FFFF16 (b23) b3 b0 b7 b0 b7 b0 Function RW
• Source pointer Stores the source address Symbol Address When reset SAR0 0022 16 to 002016 Indeterminate SAR1 0032 16 to 003016 Indeterminate DMAi source pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Symbol Address When reset DAR0 0026 16 to 002416 Indeterminate DAR1 0036 16 to 003416 Indeterminate b3 b0 b7 b0 b7 b0 Function RW
• Destination pointer Stores the destination address DMAi destination pointer (i = 0, 1) Transfer count specification 0000016 to FFFFF16 (b23) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In one-shot transfer mode, choose functions from the items shown in Table 2.10.1. Operations of the shows the set-up procedure.

2.10.2 Operation of DMAC (one-shot transfer mode)

Figure 2.10.4. Example of operation of one-shot transfer mode Table 2.10.1. Choosed functions Operation(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA transfer request signal. (2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi forward-direction address pointer are transferred to the address indicated by the DMAi desti- nation pointer. When data transfer starts directly after DMAC becomes active, the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer. Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up counted. (3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer is completed. The DMA interrupt request bit changes to “1” simultaneously. Item Transfer space Unit of transfer Set-up O O Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address 8 bits 16 bits Dummy cycle Source Source Dummy cycle Dummy cycle BCLK Address bus RD signal WR signal Data bus DMAi request bit DMA transfer counter DMAi interrupt request bit DMAi enable bit Write signal to software DMAi request bit CPU use Source Source Dummy cycle Indeterminate 0016

• In the case in which the number of transfer times is set to 2. (1) Request signal for a DMA transfer occurs Cleared to “0” when interrupt request is accepted, or cleared by software (2) Data transfer begins CPU use CPU use FF16 (3) Underflow CPU useCPU use CPU use Destination Destination DestinationDestination 0116

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.10.5. Set-up procedure of one-shot transfer mode When software DMA request bit = “1” Setting DMAi request cause select register DMAi request cause select register (i = 0, 1) [Address 03B816, 03BA16] DMiSL(i = 0, 1) DMA request cause select bit 0 0 0 1 : Software trigger b3 b2 b1 b0 b7 b0 01000 Software DMA request bit Set to “0” Setting DMAi control register DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 0 : Single transfer DMA request bit 0 : DMA not requested DMA enable bit 0 : Disabled Source address direction select bit 1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously) Destination address direction select bit 0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously) b7 b0 010001 Setting DMAi source pointer Source pointer Stores the source address b7 b0 (b15) (b8) b7 b0b7 b0 (b16)(b23) DMA0 source pointer [Address 002216 to 002016] SAR0 DMA1 source pointer [Address 003216 to 003016] SAR1 (b19) Setting DMAi destination pointer Destination pointer Stores the destination address b7 b0 (b15) (b8) b7 b0b7 b0 (b16)(b23) DMA0 destination pointer [Address 002616 to 002416] DAR0 DMA1 destination pointer [Address 003616 to 003416] DAR1 (b19) Setting DMAi transfer counter Transfer counter Set a value one less than the transfer count (b8) b7 b0 DMA0 transfer counter [Address 002916, 002816] TCR0 DMA1 transfer counter [Address 003916, 003816] TCR1 (b15) Setting DMAi control register DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) DMA enable bit 1 : Enabled b7 b0 Note: Clear DMA request bit simultaneously again. Start DMA transmission

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In repeat transfer mode, choose functions from the items shown in Table 2.10.2. Operations of the circled set-up procedure.

2.10.3 Operation of DMAC (repeated transfer mode)

Figure 2.10.6. Example of operation of repeated transfer mode Table 2.10.2. Choosed functions (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA transfer request signal. (2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi forward-direction address pointer are transferred to the address indicated by the DMAi desti- nation pointer. When data transfer starts directly after DMAC becomes active, the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer. Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up counted. (3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt request bit changes to “1” simultaneously. (4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA transfer is repeated from (1). Operation O Item Transfer space Unit of transfer Set-up O Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address 8 bits 16 bits Source Source Source BCLK DMAi request bit DMA transfer counter DMAi interrupt request bit DMAi enable bit

• In the case in which the number of transfer times is set to 2. RD signal WR signal Address bus Data bus “1” Write signal to software DMAi request bit Source Indeterminate 0016 Dummy cycle CPU use CPU use (3) Underflow FF16 CPU useSource CPU use Cleared to “0” when interrupt request is accepted, or cleared by software CPU use CPU use 0016 CPU use Source CPU use Destination 0116 0116 Destination Destination Dummy cycle Destination Dummy cycleDestination Dummy cycle Dummy cycle Destination Dummy cycle (1) Request signal for a DMA transfer occurs (2) Data transfer begins

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.10.7. Set-up procedure of repeated transfer mode When software DMA request bit = “1” Setting DMAi request cause select register DMAi request cause select register (i = 0, 1) [Address 03B816, 03BA16] DMiSL(i = 0, 1) b7 b0 01000 Software DMA request bit Set to “0” Setting DMAi control register DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) Transfer unit bit select bit 0 : 16 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 0 : Disabled Source address direction select bit 0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously) Destination address direction select bit 1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously) b7 b0 100010 Setting DMAi source pointer Source pointer Stores the source address b7 b0 (b15) (b8) b7 b0b7 b0 (b16)(b23) DMA0 source pointer [Address 002216 to 002016] SAR0 DMA1 source pointer [Address 003216 to 003016] SAR1 (b19) Setting DMAi destination pointer Destination pointer Stores the destination address b7 b0 (b15) (b8) b7 b0b7 b0 (b16)(b23) DMA0 destination pointer [Address 002616 to 002416] DAR0 DMA1 destination pointer [Address 003616 to 003416] DAR1 (b19) Setting DMAi transfer counter Transfer counter Set a value one less than the transfer count b0 b7 b0 DMA0 transfer counter [Address 002916, 002816] TCR0 DMA1 transfer counter [Address 003916, 003816] TCR1 (b15) Setting DMAi control register DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) DMA enable bit 1 : Enabled b7 b0 Note: Clear DMA request bit simultaneously again. DMA request cause select bit 0 0 0 1 : Software trigger b3 b2 b1 b0 Start DMA transmission (b8)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.11.1 Overview

Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using the CRC calculation circuit allows generation of CRC code. A polynomial counter is used for the polyno- mial generation. (1) Registers related to CRC calculation circuit Figure 2.11.1 shows the memory map of CRC-related registers, and Figure 2.11.2 shows CRC- re- lated registers.

2.11 CRC Calculation Circuit

Figure 2.11.1. Memory map of CRC-related registers Figure 2.11.2. CRC-related registers 03BC 16 03BD 16 03BE 16 CRC data register (CRCD) CRC input register (CRCIN) S y m b o lA d d r e s sW h e n r e s e t C R C B D 1 B C 1 6 I n d e t e r m i n a t e b b b C R C d a t a r e g i s t e r WR C R C c a l c u l a t i o n r e s u l t o u t p u t r e g i s t e r F u n c t i o n V a l u e s t h a t c a n b e s e t 0 0 0 01 6 t o F F F F1 S y m b oA d d r e s sW h e n r e s e t C R C I B 6 I n d e t e r m i n a t e b C R C i n p u t r e g i s t e r WR D a t a i n p u t r e g i s t e r F u n c t i o n V a l u e s t h a t c a n b e s e t 0 01 6 t o F F1

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2.11.2 Operation of CRC Calculation Circuit

The following describes the operation of the CRC calculation. Figure 2.11.3 shows an example of calcu- lation data 012316 using the CRC calculation circuit. Operation (1) The CRC calculation circuit sets an initial value in the CRC data register. (2) Writing 1 byte data to the CRC input register generates CRC code based on the data register. CRC code generation for 1 byte data finishes in two machine cycles. (3) The CRC calculation circuit detects an error by means of comparing the CRC-checking data with the content of the CRC data register, after the next data is written to the CRC input register. (4) The content of CRC data register after all data is written becomes CRC code. Figure 2.11.3. Calculation example using the CRC calculation circuit b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b0b7 b15 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete CRC data register CRCD [03BD16, 03BC16] 118916 Stores CRC code b0b7 b15 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete CRC data register CRCD [03BD16, 03BC16]0A4116 Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. 1 0001 0000 0010 00011000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 LSB MSB LSB MSB 98 1 1 Modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1

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2.12.1 Overview

The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF 16 and causes it to start performing a down count. The watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) Watchdog timer stop conditions The watchdog timer stops in any one of the following states: (a) Period in which the CPU is in stopped state (b) Period in which the CPU is in waiting state (c) Period in which the microcomputer is in hold state (3) Watchdog timer initialization The watchdog timer is initialized to 7FFF 16 in the cases given below, and begins a down count. (a) When the watchdog timer writes to the watchdog timer start register while a count is in progress (b) When the watchdog timer underflows (4) Runaway detection When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer interrupt, set the software reset bit to “1” to reset software. (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected.

2.12 Watchdog Timer

Table 2.12.1. The watchdog timer cycle CM07 CM06 CM17 CM16 BCLK WDC7 Period 0 0 0 10MHz 0 0 1 5MHz 0 1 0 2.5MHz 0 1 1 0.625MHz 1 Invalid Invalid 1.25MHz Invalid Invalid Invalid 32kHz Invalid Approx. 52.4ms (Note) Approx. 419.4ms (Note) Approx. 104.9ms (Note) Approx. 838.9ms (Note) Approx. 209.7ms (Note) Approx. 1.68s (Note) Approx. 838.9ms (Note) Approx. 6.71s (Note) Approx. 419.4ms (Note) Approx. 3.36s (Note) Approx. 2s (Note) Note: An error due to the prescaler occurs.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.12.1. Memory map of watchdog timer-related registers Figure 2.12.2. Watchdog timer-related registers (6) Registers related to the watchdog timer Figure 2.12.1 shows the memory map of watchdog timer-related registers, and Figure 2.12.2 shows watchdog timer-related registers. 000E16 000F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

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2.12.2 Operation of Watchdog Timer

The following is an operation of the watchdog timer. Figure 2.12.3 shows the operation timing, and Figure 2.12.4 shows the set-up procedure. (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count. (2) With a count in progress, writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting. (3) Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting. The watchdog timer resumes count- ing after returning from the execution of the WAIT instruction or from the stopped state. (4) If the watchdog timer underflows, it is initialized to 7FFF 16 and continues counting. At this time, a watchdog timer interrupt occurs. Operation Figure 2.12.3. Operation timing of watchdog timer (1) Start count Write signal to the watchdog timer start register 7FFF 000016 “H” “L” (4) Generate watchdog timer interrupt (2) Write operation (3)In stopped state, or WAIT instruction is executing, etc

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.12.4. Set-up procedure of watchdog timer Reserved bit Must always be “0” Watchdog timer control register [Address 000F16] WDC Setting watchdog timer control register b7 b0 Setting watchdog timer start register The watchdog timer is initialized and starts counting with a write instruction to this register. The watchdog timer value is always initialized to “7FFF 16” regardless of the value written. Watchdog timer start register [Address 000E16] WDTS b0b7 Software reset Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Processor mode register 0 [Address 000416] PM0 b7 b0 Generating watchdog timer interrupt Prescaler select bit 0 : Divided by 16 1 : Divided by 128

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2.13.1 Overview

The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor. The following is an overview of the address match interrupt. (1) Enabling/disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt. It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag). (2) Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the ad- dress match interrupt register. Set the first address of the instruction in the address match interrupt register. Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt. The first instruction of an interrupt routine does not generate an address match interrupt either. (3) Returning from an address match interrupt The return address put in the stack when an address match interrupt occurs depends on the instruc- tion not yet executed (the instruction the address match interrupt register indicates). The return ad- dress is not put in the stack. For this reason, to return from an address match interrupt, either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction. Figure 2.13.1 shows unexecuted instructions and corresponding the stacked addresses.

2.13 Address Match Interrupt

<Instructions whose address is added to by 2 when an address match interrupt occurs>

• 16-bit operation code instructions
• 8-bit operation code instructions given below ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B:S #IMM8,dest STNZ.B:S #IMM8,dest STZX.B:S #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0/A1) <Instructions whose address is added to by 1 when an address match interrupt occurs>
• Instructions other than those listed above Figure 2.13.1. Unexecuted instructions and corresponding stacked addresses (4) How to determine an address match interrupt Address match interrupts can be set at two different locations. However, both location will have the same vector address. Therefore, it is necessary to determine which interrupt has occurred; address match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which interrupt has occurred according to the first part of the address match interrupt routine.

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2.13.2 Operation of Address Match Interrupt

The following is an operation of address match interrupt. Figure 2.13.4 shows the set-up procedure of address match interrupt, and Figure 2.13.5 shows the overview of the address match interrupt handling routine. Operation (1) The address match interrupt handling routine sets an address to be used to cause the ad- dress match interrupt register to generate an interrupt. (2) Setting the address match enable flag to “1” enables an interrupt to occur. (3) An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed. Figure 2.13.4. Set-up procedure of address match interrupt Can be set to “0000016” to “FFFFF16” b7 b0 (b23) (b16) b7 b0 Address match interrupt register 0 [Address 001216 to 001016] RMAD0 Address match interrupt register 1 [Address 0016 16 to 001416] RMAD1 Setting address match interrupt enable register Address match interrupt enable register [Address 000916] AIER Address match interrupt 0 enable bit 1: Interrupt enabled b7 b0 Setting address match interrupt register b7 b0 (b15) (b8) (b20) (b19) Address match interrupt 1 enable bit 1: Interrupt enabled

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.13.5. Overview of the address match interrupt handling routine Address match interrupt routine [1] Storing registers [2] Determining the interrupt address Address match 0? Address match 0 program [3] Rewriting the stack Restoring registers REIT No Yes Address match 1? Address match 1 program No Yes Handling an error [1]Storing the contents of the registers holding the main program status to be kept. [2] Determining the interrupt address Determining which factor generated the interrupt. [3] Rewriting the stack Rewriting the return address. Explanation:

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.14 Power Control

2.14.1 Overview

‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: (1) Modes Power control is available in three modes. (a) Normal operation mode

• High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates according to its assigned clock.
• Low-speed mode fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock.
• Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.14.1 shows the state transition diagram of the above modes.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.14.1. State transition diagram of power control mode T r a n s i t i o n o f s t o p m o d e w a i t m o d e T r a n s i t i o n o f n o r m a l m o d e R e s e t M e d i u m s p e e d m o d e d i v i d e d b y m o d e n t e r r u p t C M A l l o s c i l l a t o r s s t o p p e dC P U o p e r a t i o n s t o p p e d M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M L o w s p e e d m o d e H i g h s p e e d m o d e M a i n c l o c k i s o s c i l l a t i n g S u b c l o c k i s s t o p p e d M a i n c l o c k i s o s c i l l a t i n g S u b c l o c k i s s t o p p e d M a i n c l o c k i s s t o p p e d S u b c l o c k i s o s c i l l a t i n g M a i n c l o c k i s o s c i l l a t i n g S u b c l o c k i s o s c i l l a t i n g L o w p o w e r d i s s i p a t i o n m o d e H i g h s p e e d m e d i u m s p e e d m o d e L o w s p e e d l o w p o w e r d i s s i p a t i o n m o d e N o r m a l m o d e S t o p m o d e S t o p m o d e S t o p m o d e A l l o s c i l l a t o r s s t o p p e d A l l o s c i l l a t o r s s t o p p e d W a i t m o d e W a i t m o d e W a i t m o d e C P U o p e r a t i o n s t o p p e d C P U o p e r a t i o n s t o p p e d I n t e r r u p t W A I T i n s t r u c t i o n I n t e r r u p t W A I T i n s t r u c t i o n I n t e r r u p t W A I T i n s t r u c t i o n C M I n t e r r u p t I n t e r r u p t C M B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M B C L K f XI N ) M e d i u m s p e e d m o d e d i v i d e d b y m o d e C M C M H i g h s p e e d m o d e B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M M e d i u m s p e e d m o d e d i v i d e d b y m o d e B C L K f XI N ) C M C M C M C M B C L K f XC I N ) C M B C L K f XC I N ) C M M a i n c l o c k i s o s c i l l a t i n g S u b c l o c k i s o s c i l l a t i n g C M N o t e C M N o t e C M C M C M N o t e C M N o t e C M N o t e C M C M N o t e C M C M M C M M C M N o t e s C M C M ” C M N o t e s N o t e w i t c h c l o c k a f t e r o s c i l l a t i o n o f m a i n c l o c k i s s u f f i c i e n t l y s t a b l e N o t e w i t c h c l o c k a f t e r o s c i l l a t i o n o f s u b c l o c k i s s u f f i c i e n t l y s t a b l e N o t e h a n g e C M a f t e r c h a n g i n g C M a n d C M N o t e r a n s i t i n a c c o r d a n c e w i t h a r r o w R e f e r t o t h e f o l l o w i n g f o r t h e t r a n s i t i o n o f n o r m a l m o d e

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (2) Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption. (3) Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table 2.14.1 shows the interrupts that can be used for clearing a stop mode and wait mode. (4) BCLK in returning from wait mode or stop mode (a) Returning from wait mode The processor immediately returns to the BCLK, which was in use before entering wait mode. (b) Returning from stop mode CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17, CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts operating in divided-by-8 mode. When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and CM07 all do not change state. In this case, when restored from stop mode, the device starts operat- ing in low-speed mode. Table 2.14.1. Interrupts available for clearing stop mode and wait mode Can be used when an external clock in clock synchronous serial I/O mode is selected. Can be used when the external signal is being counted in event counter mode. Can be used in one-shot mode and one-shot sweep mode. Note 1: Note 2: Note 3: CM02 = 0 Impossible Impossible Note 3 Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Impossible Impossible Impossible Note 1 Note 1 Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Possible Possible Possible Possible Possible Possible DMA0 interrupt DMA1 interrupt A-D interrupt UART0 transmit interrupt UART0 receive interrupt UART1 transmit interrupt UART1 receive interrupt SI/O automatic transfer interrupt FLD interrupt Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer A3 interrupt Timer A4 interrupt Timer B0 interrupt Timer B1 interrupt Timer B2 interrupt INT0 interrupt INT1 interrupt INT2 interrupt INT3 interrupt INT4 interrupt INT5 interrupt Wait modeInterrupt for clearing Stop modeCM02 = 1 Impossible Impossible Impossible Note 1 Note 1 Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Possible Possible Possible Possible Possible Possible

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2.14.2 Stop Mode Set-Up

(1) Enables the interrupt used for returning from stop mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the processor to go into stop mode. Operation Settings and operation for entering stop mode are described here. Figure 2.14.5. Example of stop mode set-up All clocks off (stop mode) b7 b0 (3) Canceling protect Protect register [Address 000A16] PRCR1 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (3) All clocks off (stop mode) b7 b0 System clock control register 1 [Address 000716] CM10000 Reserved bit Must be set to “0” All clock stop control bit 1 : All clocks off (stop mode) Interrupt control register SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0 to 4) [Address 005516 to 005916] TBiIC(i=0 to 2) [Address 005A16 to 005C16] (1) Setting interrupt to cancel stop mode Make sure that the interrupt priority level of the interrupt which is used to cancel the stop mode is higher than the processor interrupt priority(IPL). Interrupt priority level select bit b7 b0 INTiIC(i=0 to 2) [Address 005D16 to 005F16] INTiIC(i=3 to 5) [Address 004716 to 004916] Make sure that the interrupt priority level of the interrupt which is used to cancel the stop mode is higher than the processor interrupt priority(IPL). Interrupt priority level select bit b7 b0 Reserved bit Must be set to “0” System clock control register 0 [Address 000616] CM0 (3) Setting operation clock after returning from stop mode On Main clock (XIN-XOUT ) stop bit b7 b0 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with X IN (count source of BCLK is XIN), the user does not need to set it again. System clock control register 0 [Address 000616] CM0 XCIN-XCOUT generation Port XC select bit b7 b0 System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. 1 1 (When operating with XCIN after returning)(When operating with XIN after returning) (2) Interrupt enable flag (I flag) “1”

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2.14.3 Wait Mode Set-Up

Figure 2.14.6. Example of wait mode set-up Settings and operation for entering wait mode are described here. (1) Enables the interrupt used for returning from wait mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clears the protection and changes the content of the system clock control register. (4) Executes the WAIT instruction. Operation Wait mode (3) Canceling protect b7 b0 Protect register [Address 000A16] PRCR1 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (4) WAIT instruction (3) Control of CPU clock Note: When switching the system clock, it is necessary to wait for the oscillation to stabilize. b7 b0 WAIT peripheral function clock stop bit 0 : Do not stop f1, f8, f32 in wait mode 1 : Stop f1, f8, f32 in wait mode Port XC select bit 0 : I/O port 1 : X CIN-XCOUT generation Main clock (XIN-XOUT ) stop bit 0 : On 1 : Off Main clock division select bit 0 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note) 0 : XIN, XOUT 1 : XCIN, XCOUT System clock control register 0 [Address 000616] CM0 b7 b0 System clock control register 1 [Address 0007 16] CM10000 Reserved bit Must be set to “0” Main clock division select bit 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 Interrupt control register ADIC [Address 004E 16] ASIOC [Address 004F 16] FLDIC [Address 0050 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0 to 4) [Address 005516 to 005916] TBiIC(i=0 to 2) [Address 005A16 to 005C16] (1) Setting interrupt to cancel wait mode Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 INTiIC(i=0 to 2) [Address 005D16 to 005F16] INTiIC(i=3 to 5) [Address 004716 to 004916] Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit b7 b0 Reserved bit Must be set to “0” (2) Interrupt enable flag (I flag) “1”

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to 1. (3) Before the count source for BCLK can be changed from X IN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. (4) Suggestions to reduce power consumption

• Ports The processor retains the state of each programmable I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (a) A-D converter A current always flows in the V REF pin. When entering wait mode or stop mode, set the Vref connection bit to “0” so that no current flows into the VREF pin. (b) D-A converter The processor retains the D-A state even when entering wait mode or stop mode. Disable the output from the D-A converter then work on the programmable I/O ports. (c) Stopping peripheral functions In wait mode, stop non-used wait peripheral functions using the peripheral function clock stop bit. (d) Switching the oscillation-driving capacity Set the driving capacity to “LOW” when oscillation is stable. (e) External clock When using an external clock input for the CPU clock, set the main clock stop bit to “1”. Setting the main clock stop bit to “1” causes the X OUT pin not to operate and the power consumption goes down (when using an external clock input, the clock signal is input regardless of the content of the main clock stop bit).

2.14.4 Precautions in Power Control

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

2.15 Programmable I/O Ports

2.15.1 Overview

Forty-eight programmable I/O ports and forty high-breakdown-voltage output ports are available. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. Ports P2, P3, and 0–P43 are high-breakdown-voltage P-channel open-drain output structure. These ports have no pull- up resistance. The following is an overview of the programmable I/O ports: (1) Writing to a port register With the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. The output level conforms to CMOS output or P-channel open-drain output. “L” level of port which is built-in pull-down resistor is apply voltage to the V EE pin. Writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. The output level remains floating. (2) Reading a port register With the direction register set to output, reading a port register takes out the content of the port regis- ter, not the content of the pin. When the FLD controller is used, reading the port register takes out FLD output. With the direction register set to input, reading the port register takes out the content of the pin. (3) Exclusive high-breakdown-voltage output port There are 40 exclusive output Ports: P0 to P2, P5 and P6. All ports have structure of high-breakdown-voltage P-channel open drain output. Exclusive output ports except P2 have built-in pull-down resistance. (4) Setting pull-up The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is not effective in ports whose direction register is set to output. Do not set pull-up of corresponding pin when X CIN/XCOUT is set or a port is used as A-D input.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (5) I/O functions of built-in peripheral devices Table 2.15.1 shows relation between ports and I/O functions of built-in peripheral devices. Table 2.15.1. Relation between ports and I/O functions of built-in peripheral devices (6) Examples of working on non-used pins Table 2.15.2 contains examples of working on non-used pins. There are shown here for mere ex- amples. In practical use, make suitable changes and perform sufficient evaluation in compliance with you application. (a) Single-chip mode Table 2.15.2. Examples of working on unused pins in single-chip mode Port P0 to P3 Internal peripheral device I/O pins FLD controller output pins FLD controller output pinsP40 to P43 P5, P6 0 to P72 Timer B0 to B2 input pins P73 Timer A0 I/O pin P74 to P77 Timer A1 to A4 input pins/UART1 I/O pins P80 to P85 External interrupt input pins P86, P87 Sub-clock input pins P90 to P95 P96 A-D converter input pins P97 D-A converter output pin/ XIN division clock output pin / DIM signal output pin of FLD controller FLD controller output pins/UART0 I/O pinsP44 to P47 P100 to P107 D-A converter output pin/Clock I/O pin of serial I/O with automatic transfer function FLD controller output pins I/O pins of serial I/O with automatic transfer function Pin name Connection Ports P3, P4, P7 to P10 XOUT (Note 2), VEE After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. (Note 1) Open AV SS , VREF Connect to VSS If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. When an external clock is input to the X IN pin. Note 1: Note 2: Ports P0 to P2, P5, P6 Open

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 2.15.4. Programmable I/O ports-related registers (3) P u l l - u p c o n t r o l r e g i s t e r 0 S y m b o l A d d r e s s W h e n r e s et P U R FD 1 B i t n a m eF u n c t i o n B i t s y m b o l WR b P U 0 1P 44 t o P 47 p u l l - u p P U 0 6P 70 t o P 73 p u l l - u p P U 0 7P 74 t o P 77 p u l l - u p P u l l - u p c o n t r o l r e g i s t e r 1 S y m b o l A d d r e s s W h e n r e s et P U R F B i t n a m eF u n c t i o n B i t s y m b o l WR b P U 1 0P 80 t o P 83 p u l l - u p P U 1 1P 84 t o P 87 p u l l - u p P U 1 2P 90 t o P 93 p u l l - u p P U 1 3P 94 t o P 97 p u l l - u p P U 1 4P 1 00 t o P 1 03 p u l l - u p P U 1 5P 1 04 t o P 1 07 p u l l - u p T h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l u p r e s i s t o r N o t p u l l e d h i g h P u l l e d h i g h T h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l u p r e s i s t o r N o t p u l l e d h i g h P u l l e d h i g h N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e “ 0 ” . T h e v a l u e , i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h e s e b i t s w r i t e T h e v a l u e i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e T h e c o r r e s p o n d i n g p o r t i s p u l l e d h i g h w i t h a p u l l u p r e s i s t o r N o t p u l l e d h i g h P u l l e d h i g h N o t h i n g i s a s s i g n e d . I n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e “ 0 ” . T h e v a l u e , i f r e a d t u r n s o u t t o b e i n d e t e r m i n a t e

Examples of Peripheral functions Applications

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R This chapter presents applications in which peripheral functions built in the M30218 are used. They are shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For basic use, see Chapter 2 Peripheral Functions Usage. Here follows the list of applications that appear in this chapter.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E RApplications This page kept blank for layout purposes.

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3.1 Long-Period Timers

Figure 3.1.1. Operation timing of long-period timers In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit Use the following peripheral functions:

• Timer mode of timer A
• Event counter mode of timer A (1) Set timer A0 to timer mode, and set timer A1 to event counter mode. (2) Perform a count on count source f 1 using timer A0 to count for 1 ms, and perform a count on timer A0 using timer A1 to count for 1 second. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of timer A0 performs a down count on count source f1. (2) If the counter of timer A0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. The counter of timer A1 performs a down count on underflows in timer A0. (3) If the counter of timer A1 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A1 interrupt request bit goes to “1”. FFFF 16 l 000016 Timer A0 counter content (hex) l = reload register content Timer A1 count start flag “1” “0” Timer A1 interrupt request bit “1” “0” Timer A0 interrupt request bit “1” “0” Timer A0 count start flag “1” “0” Timer A1 counter content (hex)000016 n FFFF 16 Time (1) Start count Start count. Time n = reload register content Set to “1” by software Set to “1” by software Cleard “0” by software Cleared to “0” when interrupt request is accepted, or cleared by software (2) Timer A0 underflow (3) Timer A1 underflow

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.1.2. Connection diagram of long-period timers f32 fC32 Timer A0 Timer A1 Timer A0 interrupt request bit Timer A1 interrupt request bit Used for timer mode Used for event counter mode

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.1.3. Set-up procedure of long-period timers (1) Continued to the next page Setting timer A0 Selecting timer mode and functions Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Timer A0 mode register [Address 039616] TA0MR Gate function select bit 0 0 : Gate function not available (TA0IN pin is a normal port pin) b4 b3 Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 b7 b6 000 Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA02716 0F16 Selecting event counter mode and each function Setting timer A1 Pulse output function select bit 0 : Pulse is not output (TA1OUT pin is a normal port pin) Timer A1 mode register [Address 039716] TA1MR Up/down switching cause select bit 0 : Up/down flag content Selection of event counter mode Fix to “0” when counting timer overflow flag Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Count polarity select bit b7 b0 010000 0 0 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f f32 fC32

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.1.4. Set-up procedure of long-period timers (2) Start counting Continued from the previous page b7 b0 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit 1 0 : TA0 overflow is selected b1 b0 Setting trigger select register Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer A1 register [Address 038916, 038816] TA10316 E716 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM out- Use the following peripheral functions:

• Timer mode of timer A
• One-shot timer mode of timer A (1) Set timer A0 in timer mode, and set timer A1 in one-shot timer mode with pulse-output function. (2) Set 1 ms, the PWM period, to timer A0. Set 500 µs, the width of PWM “H” pulse, to timer A1. Both timer A0 and timer A1 use f1 for the count source. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the count start flag to “1” causes the counter of timer A0 to begin counting. The counter of timer A0 performs a down count on count source f1. (2) If the counter of timer A0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A0 interrupt request bit gose to “1”. (3) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When the counter of timer A1 begins counting, the output level of the TA1OUT pin gose to “H”. (4) As soon as the count of the counter of timer A1 becomes “000016”, the output level of TA1OUT pin gose to “L”, and the counter reloads the content of the reload register and stops counting. At the same time, the timer A1 interrupt request bit gose to “1”.

3.2 Variable-Period Variable-Duty PWM Output

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1) Continued to the next page Setting timer A0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Selecting timer mode and functions Timer A0 mode register [Address 039616 ] TA0MR Gate function select bit 0 0 : Gate function not available (TA0IN pin is a normal port pin) b4 b3 Selection of timer mode b7 b0 0000 0 0 (Must always be “0” in timer mode) Count source select bit 0 0 : f1 b7 b6 00 0 Setting divide ratio b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA02716 0F16 Setting timer A1 Pulse output function select bit 1 : Pulse is output Selecting one-shot timer mode and functions Timer A1 mode register [Address 039716 ] TA1MR External trigger select bit (Invalid when choosing timer's overflow as trigger) Selection of one-shot timer mode b7 b0 1001 1 0 (Must always be “0” in one-shot timer mode) Trigger select bit 1 : Selected by event/trigger select register 000 Count source select bit 0 0 : f1 b7 b6 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56m s f f32 fC32 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56m s f32 fC32

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2) Start counting Continued from the previous page b7 b0 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit 1 0 : TA0 overflow is selected b1 b0 Setting trigger select register Setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 Timer A1 register [Address 038916, 038816] TA11316 8816 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R The following are steps of outputting a pulse only once after a specified elapse since an external Use the following peripheral function:

• One-shot timer mode of timer A (1) Set timer A0 in one-shot timer mode, and set timer A1 in one-shot timer mode with pulse- output function. (2) Set 1 ms, an interval before a pulse is output, in timer A0; and set 50 µs, a pulse width, in timer A1. Both timer A0 and timer A1 use f 1 for the count source. (3) Connect a 10-MHz oscillator to XIN. (1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of timer A0 to count. (2) If an effective edge, selected by use of the external trigger select bit, is input to the TA0IN pin, the counter begins a down count. The counter of timer A0 performs a down count on count source f (3) As soon as the counter of timer A0 becomes “000016”, the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit gose to “1”. (4) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When timer A1 begins counting, the output level of the TA1OUT pin gose to “H”. (5) As soon as the counter of timer A1 becomes “000016”, the output level of the TA1OUT pin gose to “L”, the counter reloads the content of the reload register, and stops counting. At this time, timer A1 interrupt request bit gose to “1”.

3.3 Delayed One-Shot Output

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.3.3. Set-up procedure of delayed one-shot output (1) Continued to the next page Setting timer A0 Setting one-shot start flag (Select TA0IN pin to input TA0 trigger) b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) b7 b6 Note: Set the corresponding port direction register to “0”. Setting delay time b7 b0 (b15) (b8) b7 b0 Timer A0 register [Address 038716, 038616] TA02716 1016 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is normal port pin) Selecting one-shot timer mode and functions Timer A0 mode register [Address 039616] TA0MR External trigger select bit 0 : Falling edge of TA0IN pin's input signal Selection of one-shot timer mode b7 b0 1000 1 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 b7 b6 Trigger select bit 1 : Selected by event/trigger select register 000 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f32 fC32

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.3.4. Set-up procedure of delayed one-shot output (2) Start counting Continued from the previous page Setting one-shot timer's time b7 b0 (b15) (b8) b7 b0 Timer A1 register [Address 038916, 038816] TA10116 F416 Setting count start flag Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting b7 b0 Setting timer A1 Selecting one-shot timer mode and functions Pulse output function select bit 1 : Pulse is output (TA1 OUT pin is pulse output pin) Timer A1 mode register [Address 039716] TA1MR External trigger select bit Invalid when choosing timer's overflow Selection of one-shot timer mode b7 b0 1001 1 0 (Must always be “0” in one-shot timer mode) Count source select bit 0 0 : f1 b7 b6 Trigger select bit 1 : Selected by event/trigger select register 000 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f f32 fC32 Setting trigger select register (Set timer A0 to trigger timer A1) b7 b0 Trigger select register [Address 038316] TRGSR01 Timer A1 event/trigger select bit 1 0 : TA0 overflow is selected b1 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

3.4 Buzzer Output

Figure 3.4.1. Operation timing of buzzer output The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and Figure 3.4.2 shows the set-up procedure. Use the following peripheral function:

• The pulse-outputting function in timer mode of timer A. (1) Sound a 2-kHz buzz beep by use of timer A0. (2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the port high-impedance, and stabilize the potential resulting from pulling up. (3) Connect a 10-MHz oscillator to X IN. (1) The microcomputer begins performing a count on timer A0. Timer A0 has disabled interrupts. (2) The microcomputer begins pulse output by setting the pulse output function select bit to “Pulse output effected”. P75 changes into TA0OUT pin and outputs 2-kHz pulses. (3) The microcomputer stops outputting pulses by setting the pulse output function select bit to “Pulse output not effected”. P75 goes to an input pin, and the output from the pin becomes high-impedance. “0” “1” “0” “1” Timer A0 overflow timing Count start flag Pulse output function select bit P75 output “0” “1” High-impedance High-impedance (1) Start count (2) Buzzer output ON (3) Buzzer output OFF

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.4.2. Set-up procedure of buzzer output Initialization of timer A0 b7 b0 Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available (TA0IN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 0 0 : f1 Timer A0 mode register TA0MR [Address 039616 ]00 00 0000 Timer A0 register TA0 [Address 038716, 038616] b15 b8 b7 b0

0916 C4 16

Count start flag [Address 038016] TABSR b7 b0 Timer A0 count start flag 1 : Starts counting Initialization of port P7 direction register b7 b0 Port P75 direction register 0 : Input mode

0 Port P7 direction register [Address 03EF16]

Pulse output function select bit 1 : Pulse is output (Port P75 is TA0OUT output pin) Timer A0 mode register [Address 039616 ] TA0MR Buzzer ON b7 b0 Pulse output function select bit 0 : Pulse is not output Timer A0 mode register [Address 039616 ] TA0MR Buzzer OFF Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2ms 976.56ms f32 fC32

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3.5 Solution for External Interrupt Pins Shortage

The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up procedure. Use the following peripheral function:

• Event counter mode of timer A (1) Inputting a falling edge to the TA0 IN pin generates a timer A0 interrupt. (1) Set timer A0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer A0. (2) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins Initialization of timer A0 b7 b0 Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) Timer A0 mode register TA0MR [Address 039616 ]00 00 1000 Up/down flag [Address 038416] UDF b7 b0 Timer A0 up/down flag 0 : Down count Setting interrupt priority levels in timer A0 b7 b0 Timer A0 interrupt control register [Address 005516] TA0IC Interrupt control level (set a value 1 to 7) Setting interrupt enable flag (I flag) b7 b0 Timer A0 count start flag 1 : Starts counting Count start flag [Address 038016] TABSR1 Initialization of port P7 direction register b7 b0 Port P73 direction register 0 : Input mode TA0 [Address 038716, 038616] b15 b8 b7 b0 0016 0016 b7 b0

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

3.6 Memory to Memory DMA Transfer

The following are steps for changing both source address and destination address to transfer data from memory to another. The DMA transfer utilizes the workings that assign a higher priority to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure 3.6.4 show the set-up procedure. Use the following peripheral functions:

• Timer mode of timer A
• Two DMAC channels
• One-byte temporary RAM (address 0800 16) (1) Transfer the content of memory extending over 128 bytes from address F800016 to a 128- byte area starting from address 0040016. Transfer the content every time a timer A0 interrupt request occurs. (2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from built-in memory to the destination. (1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 trans- fer request occur simultaneously, the former is executed first. (2) DMA0 receives a transfer request and transfers data from the source to the built-in memory. At this time, the source address is incremented. (3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to the destination. At this time, the destination address is incremented. Overview Specifications Operation Figure 3.6.1. Operation timing of memory to memory DMA transfer DMAC Applications Timer A0 transfer request Address bus “0” “1” “0” “1” “0” “1” (1) Transfer request generation (2) Start DMA0 transferring (3) Start DMA1 transferring Instruction cycle DMA0 operation DMA1 operation F800016 080016 080016 0040016 WR signal RD signal Source address Destination address Source address Destination address The DMA0 operation and DMA1 operation are not necessarily executed in succession due to the a cycle steal operation. The instruction cycle varies from instruction to instruction. Since the parts of the RD and WR signals shown in short-dash lines vary in step with writing to the internal RAM, waveforms are not output to the RD and WR pins. Note 1: Note 2: Note 3:

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.6.2. Block diagram of memory to memory DMA transfer DMAC Applications 0040016 0047F16 Source area Data transfer by DMA0 F800016 F807F 16 Destination area Data transfer by DMA1 80016 Temporary RAM F800016 content F800116 content F800216 content F807F 16 content

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.6.3. Set-up procedure of memory to memory DMA transfer (1) DMAC applications Continued to the next page Initialization of DMA0 b7 b0 DMA request cause select bit b3 b2 b1 b0 0 0 1 0 : Timer A0 DMA0 request cause select register DM0SL [Address 03B816]01 00 0 Software DMA request bit 0 : Software is not generated b15 b8 b7 b0 8016 0016 DMA0 source pointer SAR0 [Address 0022 16, 002116, 002016] b7 b0 b23 b16 0F16 b7 b0 b15 b8 b7 b0 0816 0016 DMA0 destination DAR0 [Address 0026 16, 002516, 002416] pointer b7 b0 b23 b16 0016 b7 b0 b15 b8 b7 b0 0016 7F16 DMA0 transfer counter TCR0 [Address 0029 16, 002816] b7 b0 Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 1 : Enabled Source address direction select bit 1 : Forward Destination address direction select bit 0 : Fixed b7 b0 DMA0 control register DM0CON [Address 002C 16]110 101 b15 b8 b7 b0 0816 0016 DMA1 source pointer SAR1 [Address 003216, 003116, 003016] b7 b0 b23 b16 0016 b7 b0 b15 b8 b7 b0 0416 0016 b7 b0 b23 b16 0016 b7 b0 b15 b8 b7 b0 0016 7F16 DMA1 transfer counter TCR1 [Address 003916, 003816] b7 b0 Initialization of DMA1 b7 b0 DMA request cause select bit b3 b2 b1 b0 0 0 1 0 : Timer A0 DMA0 request cause select register DM1SL [Address 03BA16]01 00 0 Software DMA request bit 0 : Software is not generated Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 1 : Enabled Source address direction select bit 0 : Fixed Destination address direction select bit 1 : Forward b7 b0 DMA1 control register DM1CON [Address 003C 16]110 110 DMA1 destination pointer DAR1 [Address 003616, 003516, 003416]

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.6.4. Set-up procedure of memory to memory DMA transfer (2) DMAC applications Timer A0 count start flag 1 : Starts counting Continued from the previous page Initialization of timer A0 Timer A0 mode register TA0MR [Address 039616 ] Timer A0 register TA0 [Address 0387, 038616 ] b15 b8 b7 b0 2716 0F16 b7 b0 b7 b0 Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available (TA0IN pin is a normal port pin) 0 (Must always be fixed to “0” in timer mode) Count source select bit b7 b6 0 0 : f1 Count source period f(XIN) : 10MHZ f(XcIN) : 32.768kHZ b7 b6 Count source 100ns 800ns 3.2µs 976.56µs f32 fC32 b7 b0 0000 000 0 Count start flag [Address 038016] TABSR

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Overview Specifications Operation

3.7 Controlling Power Using Stop Mode

The following are steps for controlling power using stop mode. Figure 3.7.1 shows the operation procedure. Use the following peripheral functions:

• INT5 interrupt
• Stop mode (1) Use INT5 for the INT interrupt. Use the P8 5/INT5 pin as an input pin. (2) When a INT5 interrupt request occurs, the stop mode is cleared. (1) Enable INT5 interrupt and set the pull-up function to the P85 pin. (2) Stop XIN to enter the stop mode. Enable INT5 interrupt at this time. (3) When a INT5 interrupt request occurs by falling edge input to the P85 pin, the stop mode is cleared. Execute the return processing for the other interrupts, which are stopped, in the INT5 interrupt processing and others. Figure 3.7.1. Operation timing of controlling power using stop mode (1) Enter stop mode (2) Clear stop mode (3) Return processing INT5 input INT5 interrupt processing CPU clock Stop mode

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.7.2. Example of circuit of controling power using stop mode P85 / INT5 VREF I/O port Key input

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.7.3. Set-up procedure of controlling power using stop mode (1) Canceling protect Protect register [Address 000A16] PRCR b7 b0 Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Main NOP instruction X 5 INT5 interrupt request generation Initial condition b7 b0 Pull-up control register 2 [Address 03FE16] PUR2 P84 to P87 pulled high Port P8 direction register [Address 03F216] PD8 b7 b0 Set P85 to input port Interrupt enable level (IPL) = 0 Interrupt enable flag (I) = 1 INT5 interrupt control register [Address 004916] INT5IC Interrupt priority level select bit Set higher value than the present IPL b7 b0 100 Setting interrupt except stop mode cancel Interrupt control register DMiIC(i=0, 1) [Address 004B16, 004C16] ADIC [Address 004E 16] ASIOIC [Address 004F 16] FLDIC [Address 0050 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0 to 4) [Address 005516 to 005916] TBiIC(i=0 to 2) [Address 005A16 to 005C16] Interrupt priority level select bit 000 : Interrupt disabled b7 b0 000 Interrupt priority level select bit 000 : Interrupt disabled b7 b0

000 INTiIC(i=0 to 4) [Address 004716 to 004816]

[Address 005D16 to 005F16] Reserved bit Always set to “0” All clocks off (stop mode) System clock control register 1 [Address 000716] CM1 b7 b0 All clock stop control bit 1 : All clocks off (stop mode) 10000 Reserved bit Always set to “0” Setting operation clock after returning from stop mode System clock control register 0 [Address 000616] CM0 XCIN-XCOUT generation Port XC select bit b7 b0 System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. 1 1 (When operating with XCIN after returning) System clock control register 0 [Address 000616] CM0 On Main clock (XIN-XOUT ) stop bit b7 b0 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again. (When operating with XIN after returning) Polarity select bit 0 : Selects falling edge Reserved bit Always set to “0”

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.7.4. Set-up procedure of controlling power using stop mode (2) INT5 interrupt Store the registers REIT instruction Restore the registers Interrupt control register DMiIC(i=0, 1) [Address 004B16, 004C16] ADIC [Address 004E 16] ASIOIC [Address 004F 16] FLDIC [Address 0050 16] SiTIC(i=0, 1) [Address 005116, 005316] SiRIC(i=0, 1) [Address 005216, 005416] TAiIC(i=0 to 4) [Address 005516 to 005916] TBiIC(i=0 to 2) [Address 005A16 to 005C16] Interrupt priority level select bit Set interrupt priority level of used interrupt to these bits again b7 b0 Interrupt priority level select bit Set interrupt priority level of used interrupt to these bits again b7 b0 [Address 005D16 to 005F16] Always set to “0” Returning interrupt except stop mode cancel

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

3.8 Controling Power Using Wait Mode

The following are steps for controling power using wait mode. Figure 3.8.1 shows the operation Use the following peripheral functions:

• Timer mode of timer B
• Wait mode A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered; if F_WIT = “0”, the wait mode is cleared. (1) Connect a 32.768-kHz oscillator to X CIN to serve as the timer count source. As interrupts occur every one second, which is a count the timer reaches, the controller returns from wait mode and count the clock using a program. (2) Clear wait mode if a INT0 interrupt request occurs. (1) Switch the system clock from XIN to XCIN to get low-speed mode. (2) Stop XIN and enter wait mode. In this instance, enable the timer B2 interrupt and the INT0 interrupt. (3) When a timer B2 interrupt request occurs (at 1-second intervals), start supplying the BCLK from XCIN. At this time, count the clock within the routine that handles the timer B2 interrupts and enter wait mode again. (4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within the INT0 interrupt, and switch the BCLK count source to XIN after oscillation is stabilized. Overview Specifications Operation Figure 3.8.1. Operation timing of controling power using wait mode Timer B2 interrupt processing Timer B overflow XCIN XOUT BCLK INT0 (1) Shift to low-speed mode (2) Stop XIN (3) Timer B2 interrupt (4) INT0 interrupt “H” “L” High-speed Low-speed Low-speed Low-speed Low-speed High-speed

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.8.2. Set-up procedure of controlling power using wait mode (1) Main Setting interrupt except clearing wait mode Interrupt control register DMiIC (i = 0, 1) [Address 004B16, 004C16] ADIC [Address 004E 16] ASIOIC [Address 004F 16] FLDIC [Address 0050 16] SiTIC (i = 0, 1) [Address 005116, 005316] SiRIC (i = 0, 1) [Address 005216, 005416] TAiIC (i = 0 to 4) [Address 005516 to 005916] TBiIC (i = 0 to 2) [Address 005A16 to 005C16] INTiIC (i =1 to 5) [Address 004716 to 004916] [Address 005E16, 005F16] b7 b0 000 Interrupt priority level select bit b2 b1 b0 0 0 0 : Interrupt disabled Initial condition Interrupt priority level (IPL) = 0 Interrupt enable flag (I) = 1 b15 b8 b7 b0

0316 FF16 Timer B2 register [Address 039516, 039416]

1 Clock prescaler reset flag [Address 038116]

Count start flag [Address 038016] TABSR 1 TB2 start counting b7 b0

100 Timer B2 interrupt control register [Address 005C16]

TB2 interrupt priority level System clock select bit 0 : XIN-XOUT b7 b0 WAIT state internal clock stop bit 00 1 System clock control register 0 [Address 000616] CM0 Port Xc select bit 1 : Functions as XCIN-XCOUT oscillator Main clock (XIN-XOUT ) stop bit 0 : Oscillating Main clock divide ratio select bit 0 XCIN-XCOUT drive capacity select bit b7 b0 Timer B2 mode register [Address 039D16] TB2MR 10 01 Operation mode select bit b1 b0 0 0 : Timer mode Count source select bit b7 b6 1 1 : fC32 (f(XCIN) divided by 32) b7 b0

100 INT0 interrupt control register [Address 005D16]

INT0 interrupt priority level Continued to the next page

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.8.3. Set-up procedure of controlling power using wait mode (2) Canceling protect Protect register [Address 000A16] PRCR b7 b0 Enables writing to system clock control registers 0 and 1 (address 000616 and 000716) 1 : write-enabled Switching system clock b7 b0 System clock select bit 1 : XCIN-XCOUT

1 System clock control register 0 [Address 000616]

Main clock (XIN-XOUT ) stop bit 1 : Off [F_WIT] = 1 WAIT instruction Switching system clock b7 b0 System clock select bit 0 : XIN-XOUT

0 System clock control register 0 [Address 000616]

Main clock (XIN-XOUT ) stop bit 0 : On Starting main clock oscillator [F_WIT] : 1 TB2 interrupt request generated INT0 interrupt request generated NOP instruction X 5 Continued from the previous page Wait until the main clock has stabilized

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 3.8.4. Set-up procedure of controlling power using wait mode (3) Store the registers Restore the registers REIT instruction [F_WIT] = 0 INT0 interrupt Store the registers Restore the registers REIT instruction Counting clock Timer B2 interrupt

Controlling Power Applications M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R This page kept blank for layout purposes.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Figure 4.1.1. Classification of interrupts Interrupt Software Hardware Special Peripheral I/O (Note) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset DBC Watchdog timer Single step Address matched Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.

4.1 Overview of Interrupt

4.1.1 Type of Interrupts

Figure 4.1.1 lists the types of interrupts.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

4.1.2 Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

• Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re- quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

4.1.3 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

• Reset Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt Generated by the watchdog timer.
• Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.13 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• DMA0 interrupt, DMA1 interrupt These are interrupts DMA generates.
• A-D conversion interrupt This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
• SI/O automatic transfer interrupt This is an interrupt that the SI/O automatic transfer generates.
• FLD interrupt This is an interrupt that FLD generates.
• Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates.
• Timer B0 interrupt through timer B2 interrupt These are interrupts that timer B generates.
• INT0 interrupt through INT5 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use - FFFF8 16 to FFFFB16 - Reset FFFFC 16 to FFFFF16 Note: Interrupts used for debugging purposes only.

4.1.4 Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

• Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC 16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 4.1.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 4.1.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Table 4.1.2. Interrupts assigned to the variable vector tables and addresses of vector tables

• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad- dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 4.1.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0 +44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note)Software interrupt number 12 +56 to +59 (Note)Software interrupt number 14 +68 to +71 (Note)Software interrupt number 17 +72 to +75 (Note)Software interrupt number 18 +76 to +79 (Note)Software interrupt number 19 +80 to +83 (Note)Software interrupt number 20 +84 to +87 (Note)Software interrupt number 21 +88 to +91 (Note)Software interrupt number 22 +92 to +95 (Note)Software interrupt number 23 +96 to +99 (Note)Software interrupt number 24 +100 to +103 (Note)Software interrupt number 25 +104 to +107 (Note)Software interrupt number 26 +108 to +111 (Note)Software interrupt number 27 +112 to +115 (Note)Software interrupt number 28 +116 to +119 (Note)Software interrupt number 29 +120 to +123 (Note)Software interrupt number 30 +124 to +127 (Note)Software interrupt number 31 +128 to +131 (Note)Software interrupt number 32 +252 to +255 (Note)Software interrupt number 63 to Note : Address relative to address in interrupt table register (INTB). Cannot be masked I flagto A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer B0 Timer B1 INT0 INT1 Software interrupt +28 to +31 (Note) INT3Software interrupt number 7 +32 to +35 (Note) INT4Software interrupt number 8 +36 to +39 (Note) INT5Software interrupt number 9 DMA0 DMA1 +60 to +63 (Note)Software interrupt number 15 SI/O automatic transfer +64 to +67 (Note)Software interrupt number 16 FLD Timer A4 Timer B2 INT2

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.2.1. Memory map of the interrupt control registers

4.2 Interrupt Control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 4.2.1 shows the memory map of the interrupt control registers, and Figure 4.2.2 shows the interrupt control registers. 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer B2 interrupt control register (TB2IC) Timer A1 interrupt control register (TA1IC) Timer A3 interrupt control register (TA3IC) UART0 transmit interrupt control register (S0TIC) INT2 interrupt control register (INT2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Timer A0 interrupt control register (TA0IC) Timer A2 interrupt control register (TA2IC) Timer A4 interrupt control register (TA4IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) DMA1 interrupt control register (DM1IC) DMA0 interrupt control register (DM0IC) A-D conversion interrupt control register (ADIC) SI/O2 transmit interrupt control register (ASIOIC) FLD interrupt control register (FLDIC) INT4 interrupt control register (INT4IC) INT5 interrupt control register (INT5IC) INT3 interrupt control register (INT3IC)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.2.2. Interrupt control registers Symbol Address When reset INTiIC(i=0 to 5) 005D16 to 005F16 XX00X000 2 004716 to 004916 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note1 : This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. (Note1) Interrupt control register(Note2) b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Bit name FunctionBit symbol WR Symbol Address When reset DMiIC(i=0, 1) 004B 16 to 004C16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 ASIOIC 004F 16 XXXXX000 2 FLDIC 0050 16 XXXXX000 2 SiTIC(i=0, 1) 0051 16, 005316 XXXXX000 2 SiRIC(i=0, 1) 0052 16, 005416 XXXXX000 2 TAiIC(i=0 to 4) 0055 16 to 005916 XXXXX000 2 TBiIC(i=0 to 2) 005A 16 to 005C16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. (Note1) Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt

4.2.1 Interrupt Enable Flag

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. The content is changed when the I flag is changed causes the acceptance of the interrupt request in the following timing:

• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes effect as the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the acceptance of the interrupt is effective as the next instruction is executed.

4.2.2 Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Previous instruction REIT Interrupt sequence Time Interrupt request generated Determination whether or not to accept interrupt request Previous instruction FSET I Interrupt sequence Next instruction Interrupt request generated Determination whether or not to accept interrupt request When changed by REIT instruction When changed by FCLR, FSET, POPC, or LDC instruction (If I flag is changed from 0 to 1 by REIT instruction) (If I flag is changed from 0 to 1 by FSET instruction) Time

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4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels en- abled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 4.2.2. Interrupt levels enabled according to the contents of the IPL Table 4.2.1. Settings of interrupt priority levels When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used. Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL

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4.2.4 Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

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4.3.1 Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 4.3.1 shows the interrupt response time. Figure 4.3.1. Interrupt response time

4.3 Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the interrupt sequence is executed.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed

4.3.2 Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 4.3.2 is set in the IPL. Table 4.3.2. Relationship between interrupts without interrupt priority levels and IPL Table 4.3.1. Time required for executing the interrupt sequence Reset Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 4.3.1. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 4.3.2. Time required for executing the interrupt sequence Stack pointer (SP) valueInterrupt vector address 16-Bit bus, without wait 8-Bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2 W R

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4.3.3 Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 4.3.3 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 4.3.3. State of stack before and after acceptance of interrupt request Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM )

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.3.4. Operation of saving registers The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 4.3.4 shows the operation of the saving registers. Note: Stack pointer indicated by U flag. (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH )

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4.5 Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted (see Figure 4.5.1). Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 4.5.2 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.

4.4 Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruc- tion before executing the REIT instruction.

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4.6 Multiple Interrupts

The state when control branched to an interrupt routine is described below:

• The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
• The interrupt request bit of the accepted interrupt is set to “0”.
• The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned to the accepted interrupt. Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned a priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts. An interrupt request that is not accepted because of low priority will be held. If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request being held is accepted. Interrupt priority level of the interrupt request being held > Returned the IPL

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.6.1. Multiple interrupts Main routineReset I = 0 IPL = 0 I = 1 Interrupt 1 I = 0 IPL = 3 I = 1 Interrupt 2 I = 0 IPL = 5 REIT I = 1 IPL = 3 Interrupt 3 REIT I = 1 IPL = 0 Interrupt 3 I = 0 IPL = 2 REIT I = 1 IPL = 0 Interrupt 1 Interrupt priority level = 3 Interrupt 2 Interrupt 3 Interrupt priority level = 5 Interrupt priority level = 2 Not acknowledged because of low interrupt priority Interrupt request generated Nesting Time : Automatically executed. : Be sure to set in software. I : Interrupt enable flag IPL : Processor interrupt priority level Main routine instructions are not executed. Multiple interrupts

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figure 4.7.1. Switching condition of INT interrupt request

4.7 Precautions for Interrupts

(1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 00000 16 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. (3) External interrupt
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 through INT5 regardless of the CPU operation clock.
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 4.7.1 shows the procedure for changing the INT interrupt generate factor. Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt priority level to level 0 (Disable INTi interrupt) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt)

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R (4) Rewrite the interrupt control register

• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

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5.1 Standard DC Characteristics

The standard characteristics given in this section are examples of M30218MC-XXXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.

5.1.1 Standard Ports Characteristics

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5.1.2 Characteristics of ICC -f(XIN)

Figures 5.1.7. Characteristics of ICC -f(XIN) (VCC = 5V) 02 4 6 8 1 0 1 2 XIN / 1 ICC [mA] f(XIN) [MHz] VCC = 5 V

• Measurement conditions : VCC = 5V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM
• Register setting condition X IN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT ) stop bit = “0” (On) XIN / 2 XIN / 4 XIN / 8 XIN / 16 Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Figures 5.1.8. Characteristics of ICC -f(XIN) (VCC = 3V) 02 4 6 8 1 0 1 2 ICC [mA] f(XIN) [MHz]

• Measurement conditions : VCC = 3V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM
• Register setting condition X IN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT ) stop bit = “0” (On) VCC = 3 V XIN XIN / 2 XIN / 4 XIN / 8 XIN / 16 Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.

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5.2 Standard Characteristics of A-D Converter

The standard characteristics given in this section are an example of M30218MC-XXXXFP. The contents of these examples cannot be guaranteed. For standardize values, see “Electric characteristics”. The line on the top side of the graph represents absolute errors. The line on the bottom side of the graph represents the width of input voltage bearing the equal output code. Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. Measurement conditions (V CC = 5.12V, VREF = 5.12V, f(XIN) = 10MHz, Ta˚C) Figure 5.2.1. Standard characteristics of the A-D converter -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 0 256 512 768 1024 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 M30218MC with sample & hold, 10 bit characteristics of A-D conversion fAD = XIN = 10 MHz AVcc = Vcc = Vref = 5.12 V

1 LSB = 5 mV

Absolute error [LSB] A-D conversion output code Absolute error [LSB] (without a quantization error) Differential non-linearity error [LSB]

Figure 5.2.2. Standard characteristics of the A-D converter Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(XIN) = 3.5MHz, Ta = 25˚C) -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 0 64 128 192 256 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 M30218MC 8 bit, characteristics of A-D conversion AVcc = Vcc = Vref = 3.072V

1 LSB = 12 mV

fAD = XIN/2, XIN = 3.5 MHz Absolute error [LSB] A-D conversion output code Absolute error [LSB] (without a quantization error) Differential non-linearity error [LSB]

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5.3 Standard Characteristics of D-A Converter

The standard characteristics given in this section are an example of M30218MC-XXXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”. The line on the bottom side of the graph represents absolute errors. This indicates the difference between the measurement and the ideal analog value corresponding to the input code. The line on the top side of the graph represents the variation width of analog output value corresponding to 1-bit variation in the input code.

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R Measurement conditions (VCC = 5.12V, VREF = 5.12V, f(XIN) = 10MHz, Ta = 25˚C) Figure 5.3.1. Characteristics of the D-A converter Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. -30 -20 -10 0 32 64 96 128 -30 -20 -10 M30218MC 8 bit, characteristics of D-A conversion Absolute accuracy [mV]

1 LSB WIDTH = 20mV

Absolute accuracy [mV] D-A input code AVcc = Vcc = Vref = 5.12V 1LSB = 20mV XIN = 10 MHz -30 -20 -10 128 160 192 224 256 -30 -20 -10 Absolute accuracy [mV] D-A input code

Measurement conditions (VCC = 3.072V, VREF = 3.072V, f(XIN) = 3.5MHz, Ta = 25˚C) Figure 5.3.2. Characteristics of the D-A converter Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values. -50 -40 -30 -20 -10 0 32 64 96 128 -50 -40 -30 -20 -10 M30218FC/MC 8 bit, characteristics of D-A conversion Absolute accuracy [mV] Absolute accuracy [mV] D-A input code AVcc = Vcc = Vref = 3.072V 1LSB = 12mV XIN = 3.5 MHz -50 -40 -30 -20 -10 128 160 192 224 256 -50 -40 -30 -20 -10 Absolute accuracy [mV] D-A input code

M i t s u b i s h i m i c r o c o m p u t e r s M G r o u p S I N G L E C H I P B I T C M O S M I C R O C O M P U T E R

5.4 Standard Characteristics of Pull-Up Resistor

Figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor. Figure 5.4.1. Example of the standard characteristics of the pull-up resistor 5.0 –200.0 VI (V) 0 1.0 2.0 3.0 4.0 –40.0 –100.0 –160.0 II (mA) Vcc = 5 V Note: Data described here are characteristic examples. The data values are not guaranteed. Vcc = 3 V

MITSUBISHI Single-Chip Microcomputer User's Manual M30218 Group Dec. Second Edition 1999 REV.A1 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1999 MITSUBISHI ELECTRIC CORPORATION

Rev. Rev. No. date A First Edition 991125 A1 The followings are updated: 991221 Page 56 Figure 39: FLDC mode register b3b2 (at rising edge of each digit) 10 : 2 X Tdisp REVISION DESCRIPTION LIST M30218 GROUP USER’S MANUAL (1/1) Revision Description