M30201M4-XXXFP integrated circuit reference — Local datasheet available

Logic IC

M30201M4-XXXFP

Mitsubishi Electric Sem...

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic m…

Manufacturer: Mitsubishi Electric Sem...

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M30201 MITSUBISHI | Alldatasheet

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PDF pages: 159

Technical content

Features

2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version (including key input interrupt)

Clock output 1 channel for UART or clock synchronous, 1 for UART (built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Home appliances, Audio, office equipment, Automobiles Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201MX-XXXSPM30201MXT-XXXSPM30201F6SPM30201F6TSP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUT Pin Configuration Figures 1.1 to 1.2 show the pin configurations (top view). PIN CONFIGURATION (top view) Package: 52P4B Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201MX-XXXFP M30201MXT-XXXFP M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view) Package: 56P6S-A PIN CONFIGURATION (top view)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.1. Performance outline of M30201 group Performance Outline Table 1.1 is performance outline of M30201 group. Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns (f(X IN)=10MHz Memory ROM (See figure 4. ROM expansion.) capacity RAM (See figure 4. ROM expansion.) I/O port P0 to P7 43 lines Multifunction TA0 16 bits x 1 timer TB0, TB1 16 bits x 2 TX0, TX1, TX2 16 bits x 3 Serial I/O UART0 (UART or clock synchronous) x 1 UART1 UART x 1 A-D converter 10 bits x 8 channels (Expandable up to 13 channels) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 9 internal and 3 external sources, 4 software sources Clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Supply voltage 4.0 to 5.5V (f(X IN)=10MHz) :mask ROM version 2.7 to 5.5V (f(XIN)=7MHz with software one-wait) :mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version Power consumption 18mW (f(X IN)=7MHz with software one-wait, Vcc=3V) :mask ROM version 95mW (f(XIN)=10MHz no wait, Vcc=5V) :flash memory version I/O I/O withstand voltage 5V characteristicsOutput current 5mA (15mA:LED drive port) Device configuration CMOS silicon gate Package 52-pin plastic mold SDIP 56-pin plastic mold QFP

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC , VSS CNV SS XIN XOUT AV CC AV SS VREF P00 to P07 P10 to P17 P30 to P35 P40 to P45 Signal name Power supply input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input I/O port P0 I/O port P1 I/O port P3 I/O port P4 Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Function Connect it to the VSS pin. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A-D converter. Connect it to VCC . This pin is a power supply input for the A-D converter. Connect it to VSS . This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. This is an 8-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. The P4 0 pin is shared with timer A0 input and serial I/O output TxD1. The P41 pin is shared with timer A0 output. The P42 pin is shared with serial I/O input RxD1. The P43 pin is shared with external interrupt INT0 and timer X0 input/output TX0INOUT . The P44 pin is shared with external interrupt INT1 and timer X1 input/output TX1 INOUT . The P45 pin is shared with timer X2 input/output TX2 INOUT . Pin name Input Input Input Output Input Input/output Input/output I/O type Analog power supply input Input/output Input/output RESET I/O port P5 Input/output Input/output Input/output I/O port P6 I/O port P7 P50 to P54 P60 to P67 P70 to P71 This is a 5-bit I/O port equivalent to P0. The P50, P51, P52, and P53 pins are shared with serial I/O pins TxD0, RxD0, CLK0, and CLKS. The P54 pin is shared with clock output CLKOUT . Also, these pins are shared with analog input pins AN50 through AN54. This is an 8-bit I/O port equivalent to P0. These pins are shared with analog input pins AN0 through AN7. This is a 2-bit I/O port equivalent to P0 . These pins are used for input/output to and from the oscillator circuit for the clock. Connect a crystal oscillator between the X CIN and the XCOUT pins. Pin Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C 16 005D 16 005E16 005F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Processor mode register 0 (PM0) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR) Processor mode register 1(PM1) Timer X0 interrupt control register (TX0IC) UART0 transmit interrupt control register (S0TIC) Timer A0 interrupt control register (TA0IC) Timer X1 interrupt control register (TX1IC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) INT1 interrupt control register (INT1IC) Timer B0 interrupt control register (TB0IC) Timer X2 interrupt control register (TX2IC) INT0 interrupt control register (INT0IC) Timer B1 interrupt control register (TB1IC) Figure 1.7. Location of peripheral unit control registers (1)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Figure 1.8. Location of peripheral unit control registers (2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C 16 038D 16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C 16 039D 16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA 16 03AB 16 03AC 16 03AD 16 03AE 16 03AF 16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA 16 03BB 16 03BC 16 03BD 16 03BE 16 03BF 16 Timer A0 (TA0) Timer X0 (TX0) Timer X1 (TX1) Timer B0 (TB0) Timer B1 (TB1) Count start flag (TABSR) One-shot start flag (ONSF) Timer A0 mode register (TA0MR) Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Up-down flag (UDF) Timer X2 (TX2) Clock divided counter (CDC) Timer X2 mode register (TX2MR) Trigger select register (TRGSR) Clock prescaler reset flag (CPSRF) UART0 transmit/receive mode register (U0MR) UART0 transmit buffer register (U0TB) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 transmit buffer register (U1TB) UART1 receive buffer register (U1RB) UART0 bit rate generator (U0BRG) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART1 bit rate generator (U1BRG) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART transmit/receive control register 2 (UCON) Flash memory control register 0 (FCON0) (Note) Flash memory control register 1 (FCON1) (Note) Flash command register (FCMD) (Note) Note: This register is only exist in flash memory version. 03C0 16 03C1 16 03C2 16 03C3 16 03C4 16 03C5 16 03C6 16 03C7 16 03C8 16 03C9 16 03CA 16 03CB 16 03CC 16 03CD 16 03CE 16 03CF 16 03D0 16 03D1 16 03D2 16 03D3 16 03D4 16 03D5 16 03D6 16 03D7 16 03D8 16 03D9 16 03DA 16 03DB 16 03DC 16 03DD 16 03DE 16 03DF 16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA 16 03EB 16 03EC 16 03ED 16 03EE 16 03EF 16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA 16 03FB 16 03FC 16 03FD 16 03FE 16 03FF16 A-D register 7 (AD7) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) Port P0 (P0) Port P0 direction register (PD0) Port P1 (P1) Port P1 direction register (PD1) Port P2 (P2) (Reserved) Port P2 direction register (PD2) (Reserved) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P4 direction register (PD4) Port P5 (P5) Port P5 direction register (PD5) Port P6 (P6) Port P6 direction register (PD6) Port P7 (P7) Port P7 direction register (PD7) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Port P1 drive control register (DRR) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) A-D control register 2 (ADCON2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Central Processing Unit (CPU) The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H), and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0, R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Figure 1.9. Central processing unit register /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program counter Interrupt table register User stack pointer Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG Note: These registers consist of two register banks. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CDZSBOIUIPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config- ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag register (FLG). The following explains the function of each flag:

Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU

Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
Bits 8 to 11: Reserved area
Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. Figure 1.10. Flag register (FLG) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R0 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines H L b15 b8 b7 b0 R1 (Note) R2 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 R3 (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A0(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 A1(Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 FB (Note) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines b15 b0 Data registers Address registers Frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 H L Program coun Interrupt table register User stack po Interrupt stack pointer Static base register Flag register PC INTB USP ISP SB FLG /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines CDZSBOIUIPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Reset Figure 1.13. Device's internal status after a reset is cleared x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. (1) (000416)···Processor mode register 0 (2) (000516)···Processor mode register 1 (3) (000616)···System clock control register 0 (4) (000716)···System clock control register 1 (5) (6) (000916)···Address match interrupt enable register (7) (000A16)··· (9) (000F16)···Watchdog timer control register (11) (001416)··· (001516)··· (001616)··· (12) (13) (21) (22) (23) (004D16)···Key input interrupt control register (20) (8) Protect register (001016)···Address match interrupt register 0 (001116)··· (001216)··· (10) (14) (15) (16) (17) (18) (19) (24) A-D conversion interrupt control register (25) (26) (004E16)··· (27) (28) (29) (30) UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register (31) (32) (33) (34) (35) (36) (37) Timer A0 interrupt control register Timer X0 interrupt control register Timer X1 interrupt control register Timer X2 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register (38) (39) INT0 interrupt control register (40) INT1 interrupt control register (41) (0051 16)··· (005216)··· (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005A16)··· (005B16)··· (005D16)··· (005E16)··· (038316)···Trigger select flag (038416)···Up-down flag (039616)···Timer A0 mode register (039716)···Timer X0 mode register (039816)···Timer X1 mode register (039B16)···Timer B0 mode register (039C16)···Timer B1 mode register (039916)···Timer X2 mode register (038216)···One-shot start flag (03A816)··· UART1 transmit/receive control register 0 (03AD16)···UART1 transmit/receive control register 1 (03B016)···UART transmit/receive control register 2 (03A016)···UART0 transmit/receive mode register (03A416)···UART0 transmit/receive control register 0 (03A516)···UART0 transmit/receive control register 1 Count start flag (038016)··· (038116)···Clock prescaler reset flag 01001000 000 0 0001 000 0000 0016 0016 0016 0016 0016 0016 0016 0000 0016 0016 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 000? 00 000? 00 000? 0000 00 00 0 0 0 0000000 00010000 00000100 00010000 00000100 0016 0016 00 0000? 00 0000? (03AC16)··· UART1 transmit/receive mode register Address match interrupt register 1 (48) (49) (46) (47) (45) (50) (51) (52) (53) (59) (57) (58) (55) (56) (54) (64) (63) (65) (66) (62) (03D4 16)···A-D control register 2 (03D616)···A-D control register 0 (03D716)···A-D control register 1 (60) (61) (03E216)···Port P0 direction register (03E316)···Port P1 direction register (03E616)···Port P2 direction register (03E716)···Port P3 direction register (03EA16)···Port P4 direction register (03EB16)···Port P5 direction register (03EE16)···Port P6 direction register (03EF16)···Port P7 direction register (03FC16)···Pull-up control register 0 (03FD16)···Pull-up control register 1 (03FE16)···Port P1 drive capacity control register Frame base register (FB) Address registers (A0/A1) Interrupt table register (INTB) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Flag register (FLG) Data registers (R0/R1/R2/R3) 00000??? 0016 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 0000000 000000 00000 0 00000 000 (43) (44) (42) (03B416)···Flash memory control register 0 (Note ) (03B516)···Flash memory control register 1 (Note) (03B616)···Flash command register 0016 0000 0000 0100 Note: This register is only exist in flash memory version.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Wait Software wait The wait bit (bit 7) of the processor mode register 1 (address 000516)(note) allows you to insert software wait states for the internal ROM/RAM areas. If this bit is 0, the bus cycle is executed in one BCLK (internal clock) period; if the bit is 1, the bus cycle is executed in two BCLK periods. This bit is cleared to 0 after a reset. The SFR area is unaffected by this control bit; it is always accessed in two BCLK periods. Table 1.2 shows the relationship between software wait states and bus cycles. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A 16) to “1”. Area Wait bit Bus cycle 1 2 BCLK cycles SFR Internal ROM/RAM 0 1 BCLK cycle Invalid 2 BCLK cycles Table 1.2. Software waits and bus cycles

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the X IN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 0006 16), the sub-clock can be selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the X CIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. (3) BCLK The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high- speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock (f1, f8, f32, fAD ) The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006 16) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts. (6) fC This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Output The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output. Figure 1.19. Block diagram of clock output Clock source selection Reload register (8) Low-order 8 bits Data bus low-order bits P54 fC Division n+1 n=0016 to FF16 Clock divided couter (8) Example: When f(XIN)=10MHz n=0716 : approx. 16.5kHz n=2616 : approx. 4.0kHz n=4D 16 : approx. 2.0kHz n=9B 16 : approx. 1.0kHz P54/CKOUT f32 Address 038E16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin States Port Retains status before wait mode CLK OUT When fC selected Does not stop When f8, clock devided Does not stop when the WAIT counter output selected peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”,the status immedi- ately prior to entering wait mode is maintained. Wait Mode When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.5 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.5. Port status during wait mode Table 1.4. Port status during stop mode Wait Mode Pin States Port Retains status before stop mode CLK OUT When fC selected “H” When f8, clock devided Retains status before stop mode counter output selected Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom- puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of BCLK, f 1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate provided that the event counter mode is set to an external pulse, and UART0 functions provided an external clock is selected. Table 1.4 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 0 1 0 0 0 Invalid Division by 2 mode 1 0 0 0 0 Invalid Division by 4 mode Invalid Invalid 0 1 0 Invalid Division by 8 mode 1 1 0 0 0 Invalid Division by 16 mode 0 0 0 0 0 Invalid No-division mode Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.6 shows the operating modes corresponding to the settings of system clock control regis- ters 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 0006 16) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub- clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK Status Transition of BCLK Table 1.6. Operating modes dictated by settings of system clock control registers 0 and 1 Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power Saving There are three power save modes. (1) Normal operating mode

High-speed mode In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral functions operate on the clocks specified for each respective function.
Medium-speed mode In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the BCLK. The peripheral functions operated on the clocks specified for each respective function.
Low-speed mode In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function.
Low power-dissipation mode This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run. (2) Wait mode CPU operation is halted in this mode. The oscillator continues to run. (3) Stop mode All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode. Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3). Power Saving

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.20. Clock transition Transition of stop mode, wait mode Transition of normal mode Reset Medium-speed mode (divided-by-8 mode)Interrupt CM10 = “1” All oscillators stopped CPU operation stopped Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 Low-speed mode High-speed mode Main clock is oscillating Sub clock is stopped Main clock is oscillating Sub clock is stopped Main clock is stopped Sub clock is oscillating Main clock is oscillating Sub clock is oscillating Low power dissipation mode High-speed/medium- speed mode Low-speed/low power dissipation mode Normal mode Stop mode Stop mode Stop mode All oscillators stopped All oscillators stopped Wait mode Wait mode Wait mode CPU operation stopped CPU operation stopped Interrupt WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction CM10 = “1” Interrupt Interrupt CM10 = “1” BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XIN)/8 Medium-speed mode (divided-by-8 mode) CM07 = “0” CM06 = “1” High-speed mode BCLK : f(XIN)/2 Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/16 Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/4 Medium-speed mode (divided-by-4 mode) BCLK : f(XIN) BCLK : f(XCIN) CM07 = “1” BCLK : f(XCIN) CM07 = “1” Main clock is oscillating Sub clock is oscillating CM07 = “0” (Note 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” CM07 = “1” (Note 2) CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” CM07 = “1” (Note 2) CM05 = “1” CM06 = “0” (Notes 1,3) CM06 = “1” (Notes 1, 3) Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. (Refer to the following for the transition of normal mode.) Power Saving

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor mode register 0 (address 0004 16), processor mode register 1 (address 000516), system clock control reg- ister 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register (address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. There- fore, important outputs can be allocated to port P4. If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address 000A 16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register Symbol Address When reset PRCR 000A 16 XXXXX000 2 Bit nameBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : Write-inhibited 1 : Write-enabled PRC1 PRC0 PRC2 Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) Function 0 : Write-inhibited 1 : Write-enabled Enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 000716) Enables writing to port P4 direction register (address 03EA 16) (Note) 0 : Write-inhibited 1 : Write-enabled WR Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.21. Protect register Protection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction.
Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
BRK interrupt A BRK interrupt occurs when executing the BRK instruction.
INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts.

Reset Reset occurs if an “L” is input to the RESET pin.
DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances.
Watchdog timer interrupt Generated by the watchdog timer.
Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin.
A-D conversion interrupt This is an interrupt that the A-D converter generates.
UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates.
UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates.
Timer A0 interrupt This is an interrupts that timer A0 generates.
Timer B0 and timer B2 interrupt These are interrupts that timer B generates.
Timer X0 to timer X2 interrupt These are interrupts that timer X generates.
INT0 and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for specifying interrupt vector addresses. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. Interrupt source Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE0 16 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE4 16 to FFFE716 If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table Address match FFFE8 16 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC 16 to FFFEF16 Do not use Watchdog timer FFFF0 16 to FFFF316 DBC (Note) FFFF4 16 to FFFF716 Do not use - FFFF8 16 to FFFFB16 - Reset FFFFC 16 to FFFFF16 Table 1.7. Interrupt and fixed vector address Figure 1.23. Format for specifying interrupt vector addresses Note: Interrupts used for debugging purposes only. /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Mid address/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Low address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 High address /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 0 0 0 0 0 0 0 0 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 LSBMSB

Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Table 1.8. Interrupt causes (variable interrupt vector addresses) Software interrupt number Interrupt sourceVector table address Address (L) to address (H) Remarks Cannot be masked by I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0 +44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note)Software interrupt number 12 +52 to +55 (Note)Software interrupt number 13 +56 to +59 (Note)Software interrupt number 14 +68 to +71 (Note)Software interrupt number 17 +72 to +75 (Note)Software interrupt number 18 +76 to +79 (Note)Software interrupt number 19 +80 to +83 (Note)Software interrupt number 20 +84 to +87 (Note)Software interrupt number 21 +88 to +91 (Note)Software interrupt number 22 +92 to +95 (Note)Software interrupt number 23 +96 to +99 (Note)Software interrupt number 24 +100 to +103 (Note)Software interrupt number 25 +104 to +107 (Note)Software interrupt number 26 +108 to +111 (Note)Software interrupt number 27 +112 to +115 (Note)Software interrupt number 28 +116 to +119 (Note)Software interrupt number 29 +120 to +123 (Note)Software interrupt number 30 +124 to +127 (Note)Software interrupt number 31 +128 to +131 (Note)Software interrupt number 32 +252 to +255 (Note)Software interrupt number 63 to Note : Address relative to address in interrupt table register (INTB). to Key input interrupt A-D UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 INT0 INT1 Software interrupt Cannot be masked by I flag

Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.8 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indi- cated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.24 shows the interrupt control registers.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Figure 1.24. Interrupt control register Symbol Address When reset INTiIC(i=0, 1) 005D 16, 005E16 XX00X000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines ILVL0 IR POL Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Interrupt priority level select bit Interrupt request bit Polarity select bit Reserved bit 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0” ILVL1 ILVL2 Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). (Note) Interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Bit name FunctionBit symbol WR Symbol Address When reset KUPIC 004D 16 XXXXX000 2 ADIC 004E 16 XXXXX000 2 SiTIC(i=0, 1) 0051 16, 005316 XXXXX000 2 SiRIC(i=0, 1) 0052 16, 005416 XXXXX000 2 TAiIC(i=0) 0055 16 XXXXX000 2 TXiIC(i=0 to 2) 0056 16 to 005816 XXXXX000 2 TBiIC(i=0, 1) 005A 16, 005B16 XXXXX000 2 ILVL0 IR Interrupt priority level select bit Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested ILVL1 ILVL2Nothing is assigned. When write, set "0". When read, their contents are indeterminate. (Note) Note: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Enable Flag The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.9 shows the settings of interrupt priority levels and Table 1.10 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted:

interrupt enable flag (I flag) = 1
interrupt request bit = 1
interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.10. Interrupt levels enabled according to the contents of the IPL Table 1.9. Settings of interrupt priority levels Interrupt priority level select bit Interrupt priority level Priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low High b2 b1 b0 Enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled IPL2 IPL1 IPL0 IPL

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Changing the Interrupt Control Register < Program examples > The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts. The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. If changing the interrupt control register using an instruction other than the instructions listed hear, and if an interrupt occurs associated with this register during execution of the instruction, there can be instances in which the interrupt request bit is not set. To avoid this problem, use one of the instruc- tions given below to change the register. Following instructions: AND, OR, BCLR or BSET

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000 16. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time. Instruction Interrupt sequence Instruction in interrupt routine Time Interrupt response time (a) (b) Interrupt request acknowledgedInterrupt request generated (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.25. Interrupt response time After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Interrupt sources without priority levels Value set in the IPL Watchdog timer Other Not changed Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.12 is set in the IPL. Table 1.12. Relationship between interrupts without interrupt priority levels and IPL Table 1.11. Time required for executing the interrupt sequence Reset Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.11. Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. Figure 1.26. Time required for executing the interrupt sequence Stack pointer (SP) valueInterrupt vector address 16-bit bus, without wait 8-bit bus, without wait Even Even Odd (Note 2) Odd (Note 2) Even Odd Even Odd 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Indeterminate 123456789 1 0 1 1 12 13 14 15 16 17 18 The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Indeterminate SP-2

contents

000016 Indeterminate SP-2 SP-4 vec vec+2 PC

W R

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low- order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Figure 1.27. State of stack before and after acceptance of interrupt request Address Content of previous stack Stack area [SP] Stack pointer value before interrupt occurs m m – 1 m – 2 m – 3 m – 4 Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Content of previous stackm + 1 MSB LSB m m – 1 m – 2 m – 3 m – 4 Address Flag register (FLG Content of previous stack Stack area Flag register (FLGH ) Program counter (PCH ) [SP] New stack pointer value Content of previous stackm + 1 MSB LSB Program counter (PC Program counter (PCM )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Figure 1.28. Operation of saving registers The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.28 shows the operation of the saving registers. Note: Stack pointer indicated by U flag. (2) Stack pointer (SP) contains odd number [SP] (Odd) [SP] – 1 (Even) [SP] – 2(Odd) [SP] – 3 (Even) [SP] – 4(Odd) [SP] – 5 (Even) Address Sequence in which order registers are saved (2) (1) Finished saving registers in four operations. (3) (4) (1) Stack pointer (SP) contains even number [SP] (Even) [SP] – 1(Odd) [SP] – 2 (Even) [SP] – 3(Odd) [SP] – 4 (Even) [SP] – 5 (Odd) Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Address Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Sequence in which order registers are saved (2) Saved simultaneously, all 16 bits (1) Saved simultaneously, all 16 bits Finished saving registers in two operations. Program counter (PCM ) Stack area Flag register (FLGL) Program counter (PCL) Saved simultaneously, all 8 bits Flag register (FLGH ) Program counter (PCH ) Flag register (FLGH ) Program counter (PCH )

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Key Input Interrupt Key Input Interrupt If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Figure 1.31. Block diagram of key input interrupt Interrupt control circuit Key input interrupt control register (address 004D16) Key input interrupt request P07/KI7 P06/KI6 P01/KI1 P00/KI0 Port P04-P07 pull-up select bit Port P07 direction register Pull-up transistor Port P07 direction register Port P06 direction register Port P01 direction register Port P00 direction register Pull-up transistor Pull-up transistorPull-up transistor

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts Precautions for Interrupts (1) Reading address 0000016

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited. (3) External interrupt
Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 and INT1 regardless of the CPU operation clock.
When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT inter- rupt request. Figure 1.33. Switching condition of INT interrupt request (4) Changing interrupt control register See "Changing Interrupt Control Register". Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt enable flag to “1” (Enable interrupt)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog timer control register Symbol Address When reset WDC 000F 16 000XXXXX 2 FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 High-order bit of watchdog timer WDC7 Bit name Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register Symbol Address When reset WDTS 000E

16 Indeterminate

The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Reserved bit Reserved bit Must always be set to “0” Must always be set to “0” /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Figure 1.35. Watchdog timer control and start registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Timer There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers. Figure 1.36. Timer block diagram TA0 IN TX0 INOUT TB0 IN TB1 IN f1 f8 f32 fc32 1/32 fC32 f32 XIN XCIN TX1 INOUT TX2 INOUT Noise filter Noise filter Noise filter Noise filter Noise filter Noise filter

Event counter mode
Event counter mode
Event counter mode
Timer mode
One-shot mode
PWM mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Event counter mode
Event counter mode
Event counter mode
Timer mode
One-shot mode
PWM mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode
Timer mode
Pulse width measuring mode Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 Timer A0 Timer X0 Timer X1 Timer X2 Timer B0 Timer B1 Clock prescaler reset flag (bit 7 at address 038116) set to “1” Reset Clock prescaler

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.39. Timer A-related registers (2) Timer A0 up/down flag Timer A0 two-phase pulse signal processing select bit Symbol Address When reset UDF 0384

16 XXX0XXX0 2

Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 TA0UD 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0” Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. When write, set "0". When read, their contents are indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TA0 0387 16,038616 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer A0 register (Note) WR

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16 (High-order addresses) 0016 to FE16 (Low- order addresses) 000016 to FFFE16 Note: Read and write data in 16-bit units. /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.40. Timer A-related registers (3) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit WR TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set "0". When read, its content is indeterminate. WR 1 : Timer start When read, the value is “0”/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f 1, f8, f32, fc32 Count operation • Down count

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TA0IN pin function Programmable I/O port or gate input TA0OUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TA0IN pin’s input signal
Pulse output function Each time the timer underflows, the TA0OUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.13.) Figure 1.41 shows the timer A0 mode register in timer mode. Table 1.13. Specifications of timer mode Figure 1.41. Timer A0 mode register in timer mode Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0 OUT pin is a pulse output pin) Gate function select bit0 X (Note 2): Gate function not available (TA0IN pin is a normal port pin) 1 0 : Timer counts only when TA0IN pin is held “L” (Note 3) 1 1 : Timer counts only when TA0IN pin is held “H” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be fixed to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source • External signals input to TA0IN pin (effective edge can be selected by software)

TB1 overflow, TX0 overflow, TX2 overflow Count operation • Up count or down count can be selected by external signal or software
When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF 16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer overflows or underflows TA0 IN pin function Programmable I/O port or count source input TA0 OUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it
Pulse output function Each time the timer overflows or underflows, the TA0OUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a single-phase and a two-phase external signal. Table 1.14 lists timer specifications when counting a single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode. Table 1.15 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the timer A0 mode register in event counter mode. Table 1.14. Timer specifications in event counter mode (when not processing two-phase pulse signal) Figure 1.42. Timer A0 mode register in event counter mode Timer A0 mode register (When not using two-phase pulse signal processing) Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16) is set to “1” and event/trigger select bits (addresses 038316) to “00”. Symbol Address When reset TA0MR 0396 16 0016 WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 1 : Event counter mode b1 b0 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0OUT pin is a pulse output pin) Count polarity select bit (Note 2) MR2 MR1MR3 0 (Must always be fixed to “0” in event counter mode) TCK0 Count operation type select bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge Up/down switching cause select bit 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3) 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 TMOD1 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Two-phase pulse operation select bit (Note 4) 0 : Normal processing operation 1 : Multiply-by-4 processing operation

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source • Two-phase pulse signals input to TA0 IN or TA0OUT pin Count operation • Up count or down count can be selected by two-phase pulse signal

When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) Divide ratio • 1/ (FFFF 16 - n + 1) for up count
1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingTimer overflows or underflows TA0 IN pin function Two-phase pulse input TA0 OUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload regis- ter and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload regis- ter. (Transferred to counter at next reload time.) Select function • Normal processing operation The timer counts up rising edges or counts down falling edges on the TA0IN pin when input signal on the TA0OUT pin is “H”
Multiply-by-4 processing operation If the phase relationship is such that the TA0IN pin goes “H” when the input signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges on the TA0OUT and TA0IN pins. If the phase relationship is such that the TA0 IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer counts down rising and falling edges on the TA0OUT and TA0IN pins. Note: This does not apply when the free-run function is selected. Table 1.15. Timer specifications in event counter mode (when processing two-phase pulse signal) TA0 OUT Up count Up count Up count Down count Down count Down count TA0 IN TA0 OUT TA0 IN Count up all edges Count up all edges Count down all edges Count down all edges

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Figure 1.43. Timer A0 mode register in event counter mode Note: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038316) to “00”. Timer A0 mode register (When using two-phase pulse signal processing) Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) MR2 MR1 MR3 0 (Must always be “0” when using two-phase pulse signal processing) TCK1 TCK0 010 1 (Must always be “1” when using two-phase pulse signal processing) Bit name Function WR Count operation type select bit Two-phase pulse processing operation select bit (Note) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation 001 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down

When the count reaches 000016, the timer stops counting after reloading a new count
If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
The timer overflows
The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TA0 IN pin function Programmable I/O port or trigger input TA0 OUT pin function Programmable I/O port or pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Table 1.16. Timer specifications in one-shot timer mode Figure 1.44. Timer A0 mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.16.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot timer mode. Bit name Function Bit symbol Operation mode select bit1 0 : One-shot timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0 OUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select register Trigger select bit External trigger select bit (Note 2) 0 : Falling edge of TA0IN pin's input signal (Note 3) 1 : Rising edge of TA0IN pin's input signal (Note 3) WR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: Valid only when the TA0IN pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer A (4) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates. Figure 1.45. Timer A0 mode register in pulse width modulation mode Table 1.17. Timer specifications in pulse width modulation mode Item Specification Count source f 1, f8, f32, fc32 Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting 16-bit PWM • High level width n / fi n : Set value
Cycle time (216-1) / fi fixed 8-bit PWM •High level width n (m+1) / fi n : values set to timer A0 register’s high-order address
Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address Count start condition • External trigger is input
The timer overflows
The count start flag is set (= 1) Count stop condition • The count start flag is reset (= 0) 8 bits PWM • Set value of "H" level width is except FF 16, 0016 : PWM pulse goes “L”
Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 TA0 IN pin function Programmable I/O port or trigger input TA0 OUT pin function Pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped :When a value is written to timer A0 register, it is written to both reload register and counter
When counting in progress : When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Bit name FunctionBit symbol Operation mode select bit 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit WR 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit External trigger select bit (Note 1) 0: Falling edge of TA0IN pin's input signal (Note 2) 1: Rising edge of TA0IN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select register Note 1: Valid only when the TA0IN pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0” (input mode). Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Timer A0 mode register Symbol Address When reset TA0MR 0396 16 0016 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request generation timing Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. /LiteDiagLines /LiteDiagLines Symbol Address When reset TB0 0391 16, 039016 Indeterminate TB1 0393 16, 039216 Indeterminateb7 b0 b7 b0 (b15) (b8) Timer Bi register (Note) WR

Pulse period / pulse width measurement mode Measures a pulse period or width
Timer mode 0000 16 to FFFF16 Counts the timer's period Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts external pulses input or a timer overflow Note1: Read and write data in 16-bit units. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. When write, set "0". When read, their contents are indeterminate. TX2S TX1S TX0S TA0S /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 0 : Stops counting 1 : Starts counting Figure 1.50. Timer B-related registers (2)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source f 1, f8, f32, fC32 Count operation • Counts down

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.18.) Figure 1.51 shows the timer Bi mode register in timer mode. Table 1.18. Timer specifications in timer mode Timer Bi mode register Symbol Address When reset TBiMR(i=0, 1) 039B 16 to 039C16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Operation mode select bit0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Invalid in timer mode Can be “0” or “1”MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 TCK1 TCK0 Count source select bit Invalid in timer mode. This bit can neither be set nor reset. When read in timer mode, its content is indeterminate. b7 b6 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Figure 1.51. Timer Bi mode register in timer mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer B Item Specification Count source • External signals input to TBi IN pin

Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down
When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) (2) Event counter mode In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.19.) Figure 1.52 shows the timer Bi mode register in event counter mode. Table 1.19. Timer specifications in event counter mode Figure 1.52. Timer Bi mode register in event counter mode Timer Bi mode register Symbol Address When reset TBiMR(i=0, 1) 039B 16 to 039C16 00XX0000 2 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines Operation mode select bit 0 1 : Event counter mode b1 b0 TMOD1 TMOD0 MR0 Count polarity select bit (Note 1) MR1 MR3 Invalid in event counter mode. This bit can neither be set nor reset. When read in event counter mode, its content is indeterminate. TCK1 TCK0 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited b3 b2 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Set the corresponding port direction register to “0” (input mode). Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 2) 1 : TBj overflow ( j = 1 when i = 0, j = 0 when i = 1) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Figure 1.58. Timer X-related registers (2) Symbol Address When reset TABSR 0380 16 000X00002 Count start flag Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock devided count start flag Timer B1 count start flag Timer B0 count start flag Timer X2 count start flag Timer X1 count start flag Timer X0 count start flag Timer A0 count start flag0 : Stops counting 1 : Starts counting CDCS TB1S TB0S Nothing is assigned. When write, set "0" When read, their contents are indeterminate. TX2S TX1S TX0S TA0S Symbol Address When reset TX0 0389 16,038816 Indeterminate TX1 038B 16,038A16 Indeterminate TX2 038D 16,038C16 Indeterminate b7 b0 b7 b0 (b15) (b8) Timer Xi register (Note) WR

Timer mode 0000 16 to FFFF16 Counts an internal count source Function Values that can be set
Event counter mode 0000 16 to FFFF16 Counts pulses from an external source or timer overflow
One-shot timer mode 0000 16 to FFFF16 Counts a one shot width
Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator
Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 16 to FF16 (High-order addresses) 0016 to FF16 (Low- order addresses) 000016 to FFFE16 Note: Read and write data in 16-bit units. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines 0 : Stops counting 1 : Starts counting
Pulse period / pulse width measurement mode Measures a pulse period or width /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Figure 1.59. Timer X-related registers (3) Symbol Address When reset CPSRF 0381 16 0XXXXXXX 2 Clock prescaler reset flag Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Clock prescaler reset flag0 : No effect 1 : Prescaler is reset (When read, the value is “0”) CPSR WR Nothing is assigned. When write, set "0". When read, their contents are indeterminate. TA0TGL Symbol Address When reset TRGSR 0383 16 0016 Timer A0 event/trigger select bit 0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected Trigger select register Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected 0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected 0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected Timer X0 event/trigger select bit Timer X1 event/trigger select bit Timer X2 event/trigger select bit WR TA0TGH TX0TGL TX0TGH TX1TGL TX1TGH TX2TGL TX2TGH b1 b0 b3 b2 b5 b4 b7 b6 Note: Set the corresponding port direction register to “0”(input mode). TX0OS TX1OS TA0OS One-shot start flag Symbol Address When reset ONSF 0382 16 XXXX0000 2 Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag TX2OS Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 Nothing is assigned. When write, set "0". When read, its content is indeterminate. WR 1 : Timer start When read, the value is “0” /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source f 1, f8, f32, fC32 Count operation • Down count

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingWhen the timer underflows TXiINOUT pin function Programmable I/O port, gate input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Select function • Gate function Counting can be started and stopped by the TXiINOUT pin’s input signal
Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed (1) Timer mode In this mode, the timer counts an internally generated count source. (See Table 1.21.) Figure 1.60 shows the timer Xi mode register in timer mode. Table 1.21. Specifications of timer mode Figure 1.60. Timer Xi mode register in timer mode Note 1: Set the corresponding port direction register to “1” (output mode). Gate function cannot be selected when pulse output function is selected. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output function cannot be selected when gate function is selected. Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 0397 16 to 039916 0016 Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 0 : Timer mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXiINOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXi INOUT pin is a pulse output pin) Gate function select bit0 X (Note 2): Gate function not available (TXiINOUT pin is a normal port pin) 1 0 : Timer counts only when TXiINOUT pin is held “L” (Note 3) 1 1 : Timer counts only when TXiINOUT pin is held “H” (Note 3) b4 b3 MR2 MR1 MR3 0 (Must always be fixed to “0” in timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 000 /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source • External signals input to TXiINOUT pin (effective edge can be selected by software)

TB1 overflow, TA0 overflow, TXi overflow Count operation • Down count
When the timer underflows, it reloads the reload register contents before continuing counting (Note) Divide ratio 1/ (n + 1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timingThe timer underflows TXiINOUT pin function Programmable I/O port, count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer underflows, the reload register content is not reloaded to it
Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. (2) Event counter mode In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.22.) Figure 1.61 shows the timer Xi mode register in event counter mode. Table 1.22. Timer specifications in event counter mode (when not processing two-phase pulse signal) Figure 1.61. Timer Xi mode register in event counter mode Timer Xi mode register Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode. Note 2: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not selected as count source when pulse output function is selected. Note 3: This bit is valid when only counting an external signal. Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 WR b7 b6 b5 b4 b3 b2 b1 b0 Operation mode select bit 0 1 : Event counter mode (Note 1) b1 b0 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXiINOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TXiINOUT pin is a pulse output pin) Count polarity select bit (Note 3) MR2 MR1 MR3 0 (Must always be fixed to “0” in event counter mode) TCK0 Count operation type select bit 010 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Reload type 1 : Free-run type Bit symbol Bit name Function RW TCK1 TMOD1 /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Invalid in event counter mode. Can be “0” or “1”. Invalid in event counter mode. Can be “0” or “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification Count source f 1, f8, f32, fC32 Count operation • The timer counts down

When the count reaches 000016, the timer stops counting after reloading a new count
If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input
The timer overflows
The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016
The count start flag is reset (= 0) Interrupt request generation timingThe count reaches 000016 TXiINOUT pin function Programmable I/O port, trigger input or pulse output Read from timer When timer Xi register is read, it indicates an indeterminate value Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Table 1.23. Timer specifications in one-shot timer mode Figure 1.62. Timer Xi mode register in one-shot timer mode (3) One-shot timer mode In this mode, the timer operates only once. (See Table 1.23.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode. Bit name Function Bit symbol Operation mode select bit 1 0 : One-shot timer mode or pulse period / pulse width measurement mode b1 b0 TMOD1 TMOD0 MR0 Pulse output function select bit 0 : Pulse is not output (TXiINOOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXi INOOUT pin is a pulse output pin) MR2 MR1 MR3 0 (Must always be “0” in one-shot timer mode) 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit 100 0 : One-shot start flag is valid 1 : Selected by event/trigger select register (Note 4) Trigger select bit External trigger select bit (Note 2) 0 : Falling edge of TXiINOOUT pin's input signal (Note 3) 1 : Rising edge of TXiINOOUT pin's input signal (Note 3) WR /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected as count start condition when pulse output function is selected. Note 2: Valid only when the TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: Pulse output function cannot be selected when TXi INOUT pin is selected by the event/trigger select bit (addresses 038316). Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 0397 16 to 039916 0016 b7 b6 b5 b4 b3 b2 b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer X Item Specification f1, f8, f32, fC32

Down counts (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting
"H" level width n / fi n : Set value
Cycle time (216-1) / fi fixed
"H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address
Cycle time (28-1) (m+1) / fi m : values set to timer Xi register’s low-order address
The timer overflows
The count start flag is set (= 1)
The count start flag is reset (= 0)
Set value of "H" level width is except FF 16, 0016 : PWM pulse goes “L”
Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 Pulse output When timer Xi register is read, it indicates an indeterminate value
When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter
When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) (5) Pulse width modulation (PWM) mode In this mode, the timer outputs pulses of a given width in succession. (See Table 1.25.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates. Figure 1.66. Timer Xi mode register in pulse width modulation mode Table 1.25. Timer specifications in pulse width modulation mode Bit name FunctionBit symbol Operation mode select bit 1 1 : PWM mode b1 b0 TMOD1 TMOD0 MR0 MR2 MR1 MR3 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 b7 b6 TCK1 TCK0 Count source select bit WR 111 1 (Must always be “1” in PWM mode) 16/8-bit PWM mode select bit 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator Trigger select bit 0: Count start flag is valid 1: Selected by event/trigger select register Note 1: TXiINOUT pin inout cannot be selected by the event/trigger select bit(addresses 038316). Note 2: Set the corresponding port direction register to “1” (output mode). /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Timer Xi mode register Symbol Address When reset TXiMR(i = 0 to 2) 0397 16 to 039916 0016 b7 b6 b5 b4 b3 b2 b1 b0 Invalid in PWM mode. Can be “0” or “1”. (Note 1) Count source Count operation 16-bit PWM 8-bit PWM Count start condition Count stop condition 8 bits PWM 16 bits PWM TXiINOUT pin function Read from timer Write to timer Interrupt request generation timing Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.70. Block diagram of transmit/receive unit SP SP PAR 2SP 1SP UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type TxDi UARTi transmit register PAR enabled PAR disabled D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SP: Stop bit PAR: Parity bit UARTi transmit buffer register MSB/LSB conversion circuit UART (8 bits) UART (9 bits) Clock synchronous type UARTi receive buffer register UARTi receive register 2SP 1SP PAR enabled PAR disabled UART UART (7 bits) UART (9 bits) Clock synchronous type Clock synchronous type UART (7 bits) UART (8 bits) RxDi Clock synchronous type UART (8 bits) UART (9 bits) Data bus low-order bits MSB/LSB conversion circuit D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0D 80000000 SP SP PAR “0” Data bus high-order bits Note: UART1 cannot be used in clock synchronous serial I/O.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.71. Serial I/O-related registers (1) UARTi bit rate generator b0 Symbol Address When reset U0BRG 03A1 16 Indeterminate U1BRG 03A9 16 Indeterminate Function Assuming that set value = n, BRGi divides the count source by n + 1 0016 to FF16 Values that can be set WR /LiteDiagLines b7 b0 (b15) (b8) b7 b0 UARTi transmit buffer register Function Transmit data Nothing is assigned. When write, set "0". When read, their contents are indeterminate. Symbol Address When reset U0TB 03A3 16, 03A216 Indeterminate U1TB 03AB 16, 03AA16 Indeterminate WR /LiteDiagLines (b15) Symbol Address When reset U0RB 03A7 16, 03A616 Indeterminate U1RB 03AF 16, 03AE16 Indeterminate b7 b0 (b8) b7 b0 UARTi receive buffer register Function (During UART mode) Function (During clock synchronous serial I/O mode) Bit nameBit symbol 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 16, and 03AE16) is read out. Invalid Invalid Invalid OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found Nothing is assigned. When write, set "0". When read, the value of these bits is “0”. Receive data WR Receive data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.72. Serial I/O-related registers (2) UARTi transmit/receive mode register Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol WR Must be fixed to 001 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 CKDIR SMD1 SMD0 Serial I/O mode select bit (Note 1) SMD2 Internal/external clock select bit (Note 2) STPS PRY PRYE SLEP Parity enable bit 0 : Internal clock 1 : External clock Stop bit length select bit Odd/even parity select bit Sleep select bit 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited b2 b1 b0 0 : Internal clock 1 : External clock Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Invalid Invalid Must always be “0” Function (During UART mode) Function (During clock synchronous serial I/O mode) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines UARTi transmit/receive control register 0 Symbol Address When reset UiC0(i=0,1) 03A4 16, 03AC16 0816 b7 b6 b5 b4 b3 b2 b1 b0 Function (During UART mode) WR Function (Note) (During clock synchronous serial I/O mode) TXEPT CLK1 CLK0 NCH CKPOL BRG count source select bit Transmit register empty flag 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Data output select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : LSB first 1 : MSB first 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output UFORM Transfer format select bit 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected b1 b0 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output Must always be “0” Bit nameBit symbol Must always be “0” Note: UART1 cannot be used in clock synchronous serial I/O. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Set this bit to “0”. Set this bit to “1”. 1 0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O Figure 1.73. Serial I/O-related registers (3) UARTi transmit/receive control register 1 Symbol Address When reset UiC1(i=0,1) 03A5 16,03AD 16 0216 b7 b6 b5 b4 b3 b2 b1 b0 Bit nameBit symbol Function (During UART mode) Function (Note 1) (During clock synchronous serial I/O mode) TE TI RE RI Transmit enable bit Receive enable bit (Note 2) Receive complete flag Transmit buffer empty flag 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : No data present in receive buffer register 1 : Data present in receive buffer register Nothing is assigned. When write, set "0". When read, the value of these bits is “0”. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:

UART0 internal/external clock select bit (bit 3 at address 03A0 16) = “0”. UART transmit/receive control register 2 Symbol Address When reset UCON 03B0 16 XX000000 2 b7 b6 b5 b4 b3 b2 b1 b0 Bit name Bit symbol Function (During UART mode) Function (During clock synchronous serial I/O mode) CLKMD0 CLKMD1 UART0 transmit interrupt cause select bit UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable Set this bit to “0”. CLK/CLKS select bit 0 UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Normal mode (CLK output is CLK0 only) 1 : Transfer clock output from multiple pins function selected Nothing is assigned. When write, set "0". When read, its content is indeterminate. 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Must always be “0” U0IRS U1IRS U0RRM Invalid Invalid CLK/CLKS select bit 1 (Note 2) Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately. WR /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines WR /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Set this bit to “0”.

Clock synchronous serial I/O mode Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clock synchronous serial I/O mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table 1.26.) Figure 1.65 shows the UART0 transmit/receive mode register. Table 1.26. Specifications of clock synchronous serial I/O mode Specification

Transfer data length: 8 bits
When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32, fc
When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin
To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at address 03A516) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”
Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 03A516) = “1” _ Transmit enable bit (bit 0 at address 03A516) = “1” _ Transmit buffer empty flag (bit 1 at address 03A516) = “0”
Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
When transmitting _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re- quested when data transfer from UART0 transfer buffer register to UART0 transmit register is completed _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re- quested when data transmission from UART0 transfer register is completed
When receiving _ Interrupts requested when data transfer from UART0 receive register toUART0 receive buffer register is completed
Overrun error (Note 2) This error occurs when the next data is ready before contents of UART0receive buffer register are read out
CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the trans- fer clock can be selected
LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected
Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register
Transfer clock output from multiple pins selection UART0 transfer clock can be chosen by software to be output from one of the two pins set Item Transfer data format Transfer clock Transmission start condition Reception start conditio Interrupt request generation timing Error detection Select function Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the UART0 receive interrupt request bit is not set to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous serial I/O mode Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode Symbol Address When reset U0MR 03A0 16 0016 CKDIR UART0 transmit/receive mode registers Internal/external clock select bit STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 0 (Must always be “0” in clock synchronous serial I/O mode) 010 SMD0 SMD1 SMD2 Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode b2 b1 b0 Invalid in clock synchronous serial I/O mode /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Table 1.27 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.27. Input/output pin functions in clock synchronous serial I/O mode Pin name Function Method of selection TxD0 (P50) Serial data output Serial data input Transfer clock output Transfer clock input Port P50 direction register (bit 0 at address 03EB16)= “1” (Outputs dummy data when performing reception only) RxD0 (P51) CLK0 (P5 Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1” Port P52 direction register (bit 2 at address 03EB16) = “0” Port P51 direction register (bit 1 at address 03EB16)= “0” (Can be used as an input port when performing transmission only)

Clock synchronous serial I/O mode Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode

Example of transmit timing (when internal clock is selected)
Example of receive timing (when external clock is selected) Tc = TCLK = 2(n + 1) / fi fi: frequency of BRG0 count source (f1, f8, f32, fc) n: value set to BRG0 Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLK0 TxD0 Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = “0”.
Transmit interrupt cause select bit = “0”. Transmit interrupt request bit (IR) “0” “1” 1 / fEXT Dummy data is set in UART0 transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CLK0 RxD0 Receive complete flag (Rl) “0” “1” “0” “1” “0” “1” Receive enable bit (RE) “0” “1” Receive data is taken in Transferred from UART0 transmit buffer register to UART0 transmit register Read out from UART0 receive buffer register The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = “0”. f EXT : frequency of external clock Transferred from UART0 receive register to UART0 receive buffer register Receive interrupt request bit (IR)“0” “1” D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 Shown in ( ) are bit symbols. Meet the following conditions are met when the CLK input before data reception = “H”
Transmit enable bit “1”
Receive enable bit “1”
Dummy data write to UART0 transmit buffer register Shown in ( ) are bit symbols. Cleared to “0” when interrupt request is accepted, or cleared by software Tc TCLK Stopped pulsing because transfer enable bit = “0” Data is set in UART0 transmit buffer register Transferred from UART0 transmit buffer register to UART0 transmit register Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7

Clock synchronous serial I/O mode Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0 16). (See Figure 1.78.) The multiple pins function is valid only when the internal clock is selected for UART0. Figure 1.78. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. Microcomputer TXD 0 (P50) CLKS (P53) CLK 0 (P52) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Item Specification

Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Start bit: 1 bit
Parity bit: Odd, even, or nothing as selected
Stop bit: 1 bit or 2 bits as selected
When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
When external clock is selected (bit 3 at addresses 03A016=“1”) : fEXT /16(n+1) (Note 1) (Note 2)
To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1” - Start bit detection
When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed
When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed
Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out
Framing error This error occurs when the number of stop bits set is not detected
Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set
Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Sleep mode selection This mode is used to transfer data to and from one of multiple slave micro- computers (2) Clock asynchronous serial I/O (UART) mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer Table 1.28. Specifications of UART Mode Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit is not set to “1”. Transfer data format Transfer clock Transmission start condition Reception start condi- tion Interrupt request gen- eration timing Error detection Select function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode Figure 1.79. UARTi transmit/receive mode register in UART mode Symbol Address When reset UiMR(i=0,1) 03A0 16, 03A816 0016 CKDIR UARTi transmit / receive mode registers Internal / external clock select bit (Note) STPS PRY PRYE SLEP 0 : Internal clock 1 : External clock Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 SMD0 SMD1 SMD2 Serial I/O mode select bitb2 b1 b0 0 : One stop bit 1 : Two stop bits 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Note: UART1 can use only internal clock. Must set this bit to “1”. Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N- channel open-drain is selected, this pin is in floating state.) Table 1.29. Input/output pin functions in UART mode Pin name Function Method of selection TxDi (P50, P40) Serial data output Serial data input Programmable I/O port Transfer clock input RxDi (P51, P42) CLK0 (P5 Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1” Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at address 03EA16)= “0” (Can be used as an input port when performing transmission only) Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at address 03EA16)= “1” (Can be used as an input port when performing reception only)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode

Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Figure 1.80. Typical transmit timings in UART mode Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) Start bit Parity bit TxDi The above timing applies to the following settings :
Parity is enabled.
One stop bit.
Transmit interrupt cause select bit = “1”. “1” “0” “1” “0” “1” Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR)“0” “1” Cleared to “0” when interrupt request is accepted, or cleared by software Transmit enable bit(TE) Transmit buffer empty flag(TI) TxDi Transmit register empty flag (TXEPT) “0” “1” “0” “1” “0” “1” The above timing applies to the following settings :
Parity is disabled.
Two stop bits.
Transmit interrupt cause select bit = “0”. Transfer clock Tc Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Transmit interrupt request bit (IR)“0” “1” Shown in ( ) are bit symbols. Shown in ( ) are bit symbols. Tc Transfer clock D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST P D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7SP ST P SP D 0 D 1ST Stopped pulsing because transmit enable bit = “0”Stop bit Transferred from UARTi transmit buffer register to UARTi transmit register Start bit Data is set in UARTi transmit buffer register D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST SPD 8 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7ST D 8 D 0 D 1STSP SP Transferred from UARTi transmit buffer register to UARTi transmit register Stop bit Stop bit Data is set in UARTi transmit buffer register.“0” SP Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock asynchronous serial I/O (UART) mode

Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) Figure 1.81. Typical receive timing in UART mode (a) Sleep mode This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0 16, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. D 0Start bit Sampled “L” Receive data taken in BRGi count source Receive enable bit RxDi Transfer clock Receive complete flag Stop bit “1” “0” “0” “1” The above timing applies to the following settings :
Parity is disabled.
One stop bit. Receive interrupt request bit “0” “1” Transferred from UARTi receive register to UARTi receive buffer register Reception triggered when transfer clock is generated by falling edge of start bit D 7D 1 Cleared to “0” when interrupt request is accepted, or cleared by software

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1)0V to AVCC (VCC ) Operating clock fAD (Note 2)VCC = 5V f AD , divide-by-2 of fAD , divide-by-4 of fAD , fAD =f(XIN) VCC = 3V divide-by-2 of fAD , divide-by-4 of fAD , fAD =f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision V CC = 5V • Without sample and hold function –3LSB

With sample and hold function (8-bit resolution) –2LSB
With sample and hold function (10-bit resolution) –3LSB VCC = 3V • Without sample and hold function (8-bit resolution) –2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN 0 to AN7) + 5 pins (AN50 to AN54) A-D conversion start condition• Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 fAD cycles, 10-bit resolution: 59 fAD cycles
With sample and hold function 8-bit resolution: 28 fAD cycles, 10-bit resolution: 33 fAD cycles A-D Converter The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P6 0 to P67, and P50 to P54 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7 16) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF ) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF , reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF . The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.30 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D converter, and Figures 1.83 and 1.84 show the A-D converter-related registers. Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the fAD frequency to 250kHz min. With the sample and hold function, set the fAD frequency to 1MHz min. Table 1.30. Performance of A-D converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.82. Block diagram of A-D converter fAD fAD A-D conversion rate selection (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) CKS1=1 CKS0=0 A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) Resistor ladder Successive conversion register A-D control register 0 (address 03D616) A-D control register 1 (address 03D716) Vref VIN Data bus high-order Data bus low-order V REF VCUT=0 AV SS VCUT=1 CKS0=1 CKS1=0 Decoder Comparator Addresses P60/AN0 P61/AN1 P62/AN2 P63/AN3 P65/AN5 P66/AN6 P67/AN7 P64/AN4 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 P50/AN50 P52/AN52 P53/AN53 P54/AN54 P51/AN51 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 ADGSEL0=0 ADGSEL0=1 Port P6 group Port P5 group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.83. A-D converter-related registers (1) A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : Vref not connected 1 : Vref connected A-D input group select bit WR b2 b1 b0 b4 b3 When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 When repeat sweep mode 1 is selected 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If the repeat sweep mode is selected for the port P5 group, the contents of A-D registers 5 to 7 are indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Set this bit to “0”. (Note 2, 3) Set this bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Figure 1.84. A-D converter-related registers (2) A-D control register 2 (Note) Symbol Address When reset ADCON2 03D4 16 XXXX0000 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion method select bit 0 : Without sample and hold 1 : With sample and hold Bit symbol Bit name Function R W Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Nothing is assigned. When write, set "0". When read, their content is indeterminate. A-D register i Symbol Address When reset ADi(i=0 to 7) 03C0 16 to 03CF16 Indeterminate Eight low-order bits of A-D conversion result Function R W (b15) b7b7 b0 b0 (b8)

During 10-bit mode Two high-order bits of A-D conversion result Nothing is assigned. When write, set "0". When read, their content is indeterminate.
During 8-bit mode When read, the content is indeterminate /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SMP 000 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesReserved bit Always set to “0”

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (1) One-shot mode In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver- Figure 1.85. A-D conversion register in one-shot mode Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition •End of A-D conversion (A-D conversion start flag changes to “0”)

Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin One of AN 0 to AN7, as selected (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 0 : One-shot modeMD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit WR b2 b1 b0 b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN 50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Set this bit to “0”. Set this bit to “0”. Invalid in one-shot mode Set this bit to “0” in this mode. Table 1.31. One-shot mode specifications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (2) Repeat mode In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. (See Table 1.32.) Figure 1.86 shows the A-D control register in repeat mode. Figure 1.86. A-D conversion register in repeat mode Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin One of AN 0 to AN7, as selected (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin Table 1.32. Repeat mode specifications A-D control register 0 (Note 1) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bit0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected (Note 2) CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 0 1 : Repeat modeMD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bitSCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit WR b2 b1 b0 b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN 50 to AN54 can be used in the same way as for AN0 to AN4. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Set this bit to “0”. Set this bit to “0”. Invalid in repeat mode Set this bit to “0” in this mode. Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (3) Single sweep mode In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D Figure 1.87. A-D conversion register in single sweep mode Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”.)

Writing “0” to A-D conversion start flag Interrupt request generation timingEnd of A-D conversion Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converterRead A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in single sweep modeCH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 0 : Single sweep modeMD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit WR b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, do not select 6 pins and 8 pins sweep mode. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Set this bit to “0”. Set this bit to “0”. When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 (Note 2, 3) Set this bit to “0” in this mode. Table 1.33. Single sweep mode specifications

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter (4) Repeat sweep mode 0 In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep Figure 1.88. A-D conversion register in repeat sweep mode 0 Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) Table 1.34. Repeat sweep mode 0 specifications Note : AN50 to AN54 can be used in the same way as for AN0 to AN4. A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in repeat sweep mode 0CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 0MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 1 : Vref connected A-D input group select bit WR b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines Set this bit to “0”. Set this bit to “0”. When single sweep and repeat sweep mode 0 are selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) b1 b0 (Note 2, 3) Set this bit to “0” in this mode.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timingNone generated Input pin AN 0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note) Reading of result of A-D converterRead A-D register corresponding to selected pin (at any time) (5) Repeat sweep mode 1 In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. (See Table 1.35.) Figure 1.89 shows the A-D control register in repeat sweep mode Figure 1.89. A-D conversion register in repeat sweep mode 1 Table 1.35. Repeat sweep mode 1 specifications A-D control register 0 (Note) Symbol Address When reset ADCON0 03D6 16 00000XXX 2 b7 b6 b5 b4 b3 b2 b1 b0 Analog input pin select bitInvalid in repeat sweep mode 1CH0 Bit symbol Bit name Function CH1 CH2 A-D operation mode select bit 0 1 1 : Repeat sweep mode 1MD0 MD1 ADST A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0 : fAD /4 is selected 1 : fAD /2 is selectedCKS0 WR A-D control register 1 (Note 1) Symbol Address When reset ADCON1 03D7 16 0016 Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 A-D sweep pin select bit SCAN0 SCAN1 MD2 BITS 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode VCUT Vref connect bit ADGSEL0 A-D operation mode select bit 1 Set “1” in this mode. 1 : Vref connected A-D input group select bit WR b4 b3 0 : Port P6 group is selected 1 : Port P5 group is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Frequency select bit 1 0 : fAD /2 or fAD /4 is selected 1 : fAD is selectedCKS1 Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines Set this bit to “0”. Set this bit to “0”. When single sweep and repeat sweep mode 1 are selected 0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) b1 b0 (Note 2, 3) Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D Converter

Sample and hold Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 fAD cycle is achieved with 8-bit resolution and 33 fAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 100 Figure 1.90. Programmable I/O ports (1) P30 to P35 Data bus Direction register Pull-up selection Port latch P00 to P07, P42, P71 Data bus Pull-up selection Input to respective peripheral functions Direction register Port latch P41, P70 Data bus Pull-up selection output Direction register Port latch P40, P43, P44 Data bus Pull-up selection output Input to respective peripheral functions Direction register Port latch

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 101 Figure 1.91. Programmable I/O ports (2) P10 to P17 Data bus Pull-up selection Drive capacity control register Direction register Port latch P50, P53, P54 Data bus Pull-up selection output Direction register Port latch Analog input P52 Data bus Pull-up selection output Direction register Port latch Analog input Serial clock input P51 Data bus Pull-up selection Analog input Port latch Direction register Serial I/O input

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 102 Figure 1.92. Programmable I/O ports (3) P60 to P67 Data bus Pull-up selection Analog input Port latch Direction register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 103 Figure 1.93. Direction register Port Pi direction register (Note 1) Symbol Address When reset PDi (i = 0 to 7) 03E216, 03E316, 03E716, 03EA16, 0016 03EB 16, 03EE16, 03EF16 0016 Bit name FunctionBit symbol W R b7 b6 b5 b4 b3 b2 b1 b0 PDi_0 Port Pi 0 direction register PDi_1 Port Pi 1 direction register PDi_2 Port Pi 2 direction register PDi_3 Port Pi 3 direction register PDi_4 Port Pi 4 direction register PDi_5 Port Pi 5 direction register PDi_6 Port Pi 6 direction register PDi_7 Port Pi 7 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 except 2) Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P4 direction register. Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. These bits can either be set nor reset. When read, its contents are indeterminate. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 104 Figure 1.94. Port register Port Pi register Bit name FunctionBit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 Pi_0 Port Pi 0 register Pi_1 Port Pi 1 register Pi_2 Port Pi 2 register Pi_3 Port Pi 3 register Pi_4 Port Pi 4 register Pi_5 Port Pi 5 register Pi_6 Port Pi 6 register Pi_7 Port Pi 7 register Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 7 except 2) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Symbol Address When reset Pi (i = 0 to 7) 03E016, 03E116, 03E516, 03E816, Indeterminate 03E916, 03EC16, 03ED16 Indeterminate Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. This bit can either be set nor reset. When read, its content is indeterminate.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 105 Figure 1.95. Pull-up control register Pull-up control register 0 Symbol Address When reset PUR0 03FC 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU00 P0 0 to P03 pull-up PU01 P0 4 to P07 pull-up PU02 P1 0 to P13 pull-up PU03 P1 4 to P17 pull-up PU06 P3 0 to P33 pull-up PU07 P3 4 to P35 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Pull-up control register 1 Symbol Address When reset PUR1 03FD 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 PU10 P4 0 to P43 pull-up PU11 P4 4 to P47 pull-up PU12 P5 0 to P53 pull-up PU13 P5 4 pull-up PU14 P6 0 to P63 pull-up PU15 P6 4 to P67 pull-up PU16 P7 0 to P71 pull-up The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Port P1 drive capacity control register Symbol Address When reset DRR 03FE 16 0016 Bit name Function Bit symbol WR b7 b6 b5 b4 b3 b2 b1 b0 DRR0 Port P10 drive capacuty DRR1 Port P11 drive capacuty DRR2 Port P12 drive capacuty DRR3 Port P13 drive capacuty DRR4 Port P14 drive capacuty DRR5 Port P15 drive capacuty DRR6 Port P16 drive capacuty DRR7 Port P17 drive capacuty Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Port 106 Example connection of unused pins Table 1.36. Example connection of unused pins Pin name Connection Ports P0, P1, P3 to P7 XOUT (Note) AV SS , VREF AV CC After setting for input mode, connect every pin to VSS (pull-down); or after setting for output mode, leave these pins open. Open Connect to VCC Connect to VSS Note: With external clock input to XIN pin.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 107 Usage Precaution Timer A (timer mode) (1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. Timer A (event counter mode) (1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by under- flow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer A (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TA0 OUT pin outputs “L” level.
The interrupt request generated and the timer A0 interrupt request bit goes to “1”. (2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. Timer A (pulse width modulation mode) (1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:
Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TA0 OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 108 Timer B (timer mode, event counter mode) (1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value. Timer B (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. Timer X (timer mode) (1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value. Timer X (event counter mode) (1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again. Timer X (one-shot timer mode) (1) Setting the count start flag to “0” while a count is in progress causes as follows:

The counter stops counting and a content of reload register is reloaded.
The TXi INOUT pin outputs “L” level.
The interrupt request generated and the timer Xi interrupt request bit goes to “1”. (2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures:
Selecting one-shot timer mode after reset.
Changing operation mode from timer mode to one-shot timer mode.
Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 109 Timer X (pulse width modulation mode) (1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures:

Selecting PWM mode after reset.
Changing operation mode from timer mode to PWM mode.
Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TXi INOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”. Timer X (pulse period/pulse width measurement mode) (1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Xi interrupt request is not generated. A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 ms or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A- D conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock. Stop Mode and Wait Mode (1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore, insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits to “1”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Usage precaution 110 Interrupts (1) Reading address 0000016

When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 00000 16 by software. (2) Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an inter- rupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupt is prohibited. (3) External interrupt
When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. (4) Changing interrupt control register See "Changing Interrupt Control Register".

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 111 Table 1.37. Absolute maximum ratings Note 1: When writing to frash MCU, CNVss is –0.3 to 13 (V) . Note 3: Extended operating temperature version: -40 to 85 °C. Note 2: Flat package (56P6S-A) is 300 mW. Note 4: Extended operating temperature version: -65 to 150 °C. P70, P71, VREF , XIN RESET, CNVss, VO - 0.3 to Vcc + 0.3 (Note 1) - 0.3 to Vcc + 0.3 Pd Ta = 25 °C - 0.3 to 7 - 0.3 to 7 V V V VI AVcc Vcc Tstg Topr mW V - 40 to 150 (Note 4) 1000 (Note 2) - 20 to 85 (Note 3) P40 to P45, P50 to P54, P60 to P67, P00 to P07, P10 to P17, P30 to P35, P70, P71, VREF , XINP50 to P54, P60 to P67, P00 to P07, P10 to P17, P30 to P35, P40 to P45, Parameter Unit Rated valueConditionSymbol Operating ambient temperature Input voltage Analog supply voltage Supply voltage Output voltage Power dissipation Storage temperature

Electrical characteristics

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 112 VCC = 5V 2.7 5.5Vcc 5.0 VccAVcc V Vss AVss 0.8Vcc V V V Vcc 0.2Vcc0 - 5.0 - 10.0 10.0 5.0 f (XIN) MHz IOL (peak) mA f (XcIN) kHz5032.768 V Vcc=4.0V to 5.5V With wait 5 x VCC MHz P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS , VIH V IL IOH (avg) IOH (peak) IOL (peak) P10 to P17 IOL (avg) mA mA mA mA 30.0 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNV SS P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P30 to P35, P40 to P45, IOL (avg) P10 to P17 15.0 mA 10.0 HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER 5.0 0Vcc=2.7V to 4.0V - 10.000 MHz10Vcc=4.0V to 5.5V 2.31 x VCC MHz 0Vcc=2.7V to 4.0V +0.760 Without wait Typ. Max. UnitParameterSymbol Min Standard Supply voltage (Note 2) Analog supply voltage Analog supply voltage Supply voltage LOW input voltage HIGH input voltage HIGH average output current HIGH peak output current LOW peak output current Main clock input oscillation frequency LOW average output current Subclock oscillation frequency LOW peak output current LOW average output current Mask ROM version Flash memory version 4.0 5.5 5.0 Mask ROM version Flash memory version MHz10Vcc=4.0V to 5.5V 0 Mask ROM version Flash memory version MHz10Vcc=4.0V to 5.5V 0 Note 1: Unless otherwise noted: VCC = 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC). Flash version: VCC = 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC.) Note 2: Flash version: VCC = 4.0V to 5.5V Note 3: The average output current is an average value measured over 100ms. Note 4: Keep output current as follows: The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3 and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6 and P7 IOH (peak) is under 80 mA. Table 1.38. Recommended operating conditions (Note 1) /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 5.54.02.70.0 3.5 10.0 Main clock input oscillation frequency (Without wait) Power supply voltage [V] (M ain clock : no division) Highest operation frequency [MHz] 5 x Vcc - 10.000MHz /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines 5.54.02.70.0 10.0 Main clock input oscillation frequency (With wait) Power supply voltage [V] (M ain clock : no division) Highest operation frequency [MHz 7.0 2.31 x VCC + 0.760MHz

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 113 Table 1.39. Electrical characteristics (Note1) VOH VOH VOL V 4.7 V2.0 3.0IOH = - 5 mA IOH = - 200 µA IOL = 5 mA P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, V P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 VOL IOL = 200 µA 0.45 V VOL P10 to P17 IOL = 15mA V 2.0 IOL = 200 µA

0.3 VVOL

P70,P71 P70,P71 P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 IIH V RAM Icc VT+ -VT- VT+ -VT- 0.2 0.8 V 0.2 1.8 V 5.0 µA µA When clock is stopped 2.0 V 1.0 µA mA 20.0 RESET TA0 IN,TX0INOUT ,TX1INOUT ,TX2INOUT TB0 IN,TB1IN INT0,INT1,CLK0,KI0 to KI7 VI = 5V VI = 0V -5.0 19.0 38.0 4.0 µA90.0 P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67 P70,P71, RESET, CNVss IIL P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, VOH XOUT HIGHPOWER LOWPOWER V 3.0 3.0 VOL XOUT HIGHPOWER LOWPOWER V 2.0 2.0 IOH = 1 mA IOH = 0.5 mA IOH = - 1 mA IOH = - 0.5 mA HIGHPOWER IOL = 5 mA 2.0LOWPOWER IOL = 200 µA 0.45 HIGHPOWER LOWPOWER kW167.050.030.0 Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter HIGH output voltage LOW output voltage LOW output voltage LOW output voltage Hysteresis Hysteresis HIGH input current LOW input current RAM retention voltage Power supply current HIGH output voltage HIGH output voltage LOW output voltage LOW output voltage f(XIN)=10MHz Square wave, no division f(XCIN)=32kHz Square wave Ta=25 C when clock is stopped Ta=85 C when clock is stopped I/O pin has no load f(XCIN)=32kHz With wait(Note2) VOH XCOUT HIGHPOWER LOWPOWER V 3.0 1.6 No load No load HIGH output voltage VOL XOUT HIGHPOWER LOWPOWER V LOW output voltage VI = 0VR PULLUP P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67,P70,P71 Pull-up resistor P70,P71, RESET, CNVss M W1.0R XIN XINFeedback resistor M W6.0R XCIN XCINFeedback resistor µA No load No load RxD 0, RxD1 Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 10MHz) Note 2: With one timer operated using fC32 . VCC = 5V

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 114 Table 1.40. A-D conversion characteristics VCC = 5V Bits LSB VREF =VCC VREF =V CC = 5V R LADDER tCONV kohm µs V VIA VREF VCC VREF 3.3 µs2.8tCONV tSAMP 0.3 µs VREF =VCC VREF =V CC = 5V LSB±3 VREF = VCC = 5V ±2 LSB Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Resolution Absolute accuracy Ladder resistance Conversion time(10bit) Reference voltage Analog input voltage Conversion time(8bit) Sampling time Sample & hold function not available Sample & hold function available(10bit) Sample & hold function available(8bit)

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 115 Table 1.42. Timer A input (counter input in event counter mode) Table 1.43. Timer A input (gating input in timer mode) Table 1.44. Timer A input (external trigger input in one-shot timer mode) Table 1.45. Timer A input (external trigger input in pulse width modulation mode) Table 1.46. Timer A input (up/down input in event counter mode) Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.41. External clock input nstr ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol Standard UnitMin. Max. External clock input LOW pulse width External clock input HIGH pulse width External clock input cycle time External clock fall time External clock rise time 100 nstw(TAL) ns nstw(TAH) tc(TA) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns tw(TAH) tw(TAL) ns ns ns ns ns tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 100 400 200 200 200 100 100 100 100 2000 1000 1000 400 400 TA0 IN input LOW pulse width TA0 IN input HIGH pulse width ParameterSymbol TA0 IN input cycle time Standard UnitMin. Max. Symbol Symbol Symbol Symbol Parameter Parameter Parameter Parameter Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 OUT input LOW pulse width TA0 OUT input HIGH pulse width TA0 OUT input cycle time TA0 OUT input hold time TA0 OUT input setup time VCC = 5V

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 116 ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBL) tw(TBH) ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) ns ns ns tc(TB) tw(TBL) ns tw(TBH) ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tc(TX) tw(TXL) ns tw(TXH) ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) TBiIN input LOW pulse width (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input cycle time (counted on one edge) 100 200 400 200 200 400 200 200 100 400 200 200 200 100 100 Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.47. Timer B input (counter input in event counter mode) Table 1.48. Timer B input (pulse period measurement mode) Table 1.49. Timer B input (pulse width measurement mode) Table 1.50. Timer X input (counter input in event counter mode) Table 1.51. Timer X input (gate input in timer mode) Table 1.52. Timer X input (external trigger input in one-shot timer mode) VCC = 5V

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 117 Table 1.53. Timer X input (pulse period measurement mode) Table 1.54. Timer X input (pulse width measurement mode) Table 1.55. Serial I/O ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tw(INH) tw(INL) ns ns ns ns ns ns ns tc(CK) tw(CKH) tw(CKL) td(C-Q) tsu(D-C) th(C-Q) th(C-D) ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi hold time RxDi input setup time TxDi output delay time RxDi input hold time INTi input LOW pulse width INTi input HIGH pulse width 400 200 200 400 200 200 250 250 200 100 100 Table 1.56. External interrupt INTi inputs VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)

Electrical characteristics (Vcc = 5V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 118 tsu(D–C) TA0 IN input TA0 OUT input During event counter mode TBiIN input CLK0 TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TA0 IN input (When count on falling edge is selected) TA0 IN input (When count on rising edge is selected) TA0 OUT input (Up/down input) INTi input TXiINOUT input tc(TX) tw(TXH) tw(TXL) VCC = 5V

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 119 Table 1.57. Electrical characteristics (Note 1) VOH VOL V V0.5 2.5IOH = - 1mA IOL = 1 mA P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 VOL P10 to P17 IOL = 3 mA V0.5 P70,P71 IIH V RAM Icc VT+ -VT- VT+ -VT- 0.2 0.8 V 0.2 1.8 V 4.0 µA µA When clock is stopped 2.0 V 1.0 µA mA 20.0 RESET VI = 3V VI = 0V -4.0 6.0 15.0 2.8 µA 40.0 P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P70,P71, RESET, CNVss IIL P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, VOH XOUT HIGHPOWER LOWPOWER V 2.5 2.5 VOL XOUT HIGHPOWER LOWPOWER V 0.5 0.5 IOH = 0.1 mA IOH = 50 µA IOH = - 1 mA IOH = - 50 µA HIGHPOWER IOL = 1 mA 0.5LOWPOWER kW500.0120.066.0 Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter HIGH output voltage LOW output voltage LOW output voltage Hysteresis Hysteresis HIGH input current LOW input current RAM retention voltage Power supply current HIGH output voltage LOW output voltage f(XIN)=7MHz Square wave, no division f(XCIN)=32kHz With wait. Oscillation capacity HIGH (Note 2) Ta=25 C when clock is stopped Ta=85 C when clock is stopped I/O pin has no load f(XCIN)=32kHz With wait. Oscillation capacity LOW (Note 2) VOH XCOUT HIGHPOWER LOWPOWER V 3.0 1.6 No load No load HIGH output voltage VOL XOUT HIGHPOWER LOWPOWER V LOW output voltage VI = 0VR PULLUP P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67,P70,P71 Pull-up resistor P70,P71, RESET, CNVss M W3.0R XIN XINFeedback resistor M W10.0R XIN XINFeedback resistor µA No load No load f(XCIN)=32kHz Square wave 0.9 µA TA0 IN,TX0INOUT ,TX1INOUT ,TX2INOUT TB0 IN,TB1IN INT0,INT1,CLK0,KI0 to KI7 RxD 0, RxD1 Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHz, with wait) Note 2: With one timer operated using fC32 . VCC = 3V

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 120 Table 1.58. A-D conversion characteristics VCC = 3V Bits LSB VREF =VCC VREF =VCC = 3V, Ø AD = fAD /2 R LADDER kohm V VIA VREF 2.7 VCC VREF µs14.0tCONV VREF =V CC Symbol Standard Typ. UnitMeasuring condition Min. Max.Parameter Resolution Absolute accuracy Ladder resistance Reference voltage Analog input voltage Conversion time(8bit) Sample & hold function not available (8bit) VCC = 3V

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 121 Table 1.60. Timer A input (counter input in event counter mode) Table 1.61. Timer A input (gating input in timer mode) Table 1.62. Timer A input (external trigger input in one-shot timer mode) Table 1.63. Timer A input (external trigger input in pulse width modulation mode) Table 1.64. Timer A input (up/down input in event counter mode) Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.59. External clock input nstr ns ns ns ns tc tw(H) tw(L) tf ParameterSymbol Standard UnitMin. Max. External clock input LOW pulse width External clock input HIGH pulse width External clock input cycle time External clock fall time External clock rise time 143 VCC = 3V nstw(TAL) ns nstw(TAH) tc(TA) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns ns tc(TA) tw(TAH) tw(TAL) ns ns tw(TAH) tw(TAL) ns ns ns ns ns tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) 150 600 300 300 300 150 150 150 150 3000 1500 1500 600 600 TA0 IN input LOW pulse width TA0 IN input HIGH pulse width ParameterSymbol TA0 IN input cycle time Standard UnitMin. Max. Symbol Symbol Symbol Symbol Parameter Parameter Parameter Parameter Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. Standard UnitMin. Max. TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 IN input cycle time TA0 IN input LOW pulse width TA0 IN input HIGH pulse width TA0 OUT input LOW pulse width TA0 OUT input HIGH pulse width TA0 OUT input cycle time TA0 OUT input hold time TA0 OUT input setup time

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 122 ns ns ns tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBL) tw(TBH) ns ns ns ns ns tc(TB) tw(TBH) tw(TBL) ns ns ns tc(TB) tw(TBL) ns tw(TBH) ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tc(TX) tw(TXL) ns tw(TXH) ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width TBiIN input HIGH pulse width TBiIN input cycle time TBiIN input LOW pulse width (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input cycle time (counted on both edges) TBiIN input LOW pulse width (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input cycle time (counted on one edge) 150 160 160 300 600 300 300 600 300 300 150 600 300 300 300 150 150 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.65. Timer B input (counter input in event counter mode) Table 1.66. Timer B input (pulse period measurement mode) Table 1.67. Timer B input (pulse width measurement mode) Table 1.68. Timer X input (counter input in event counter mode) Table 1.69. Timer X input (gate input in timer mode) Table 1.70. Timer X input (external trigger input in one-shot timer mode) VCC = 3V

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 123 Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.71. Timer X input (pulse period measurement mode) Table 1.72. Timer X input (pulse width measurement mode) Table 1.73. Serial I/O ns ns tc(TX) tw(TXH) tw(TXL) ns ns ns tc(TX) tw(TXL) ns tw(TXH) ns ns tw(INH) tw(INL) ns ns ns ns ns ns ns tc(CK) tw(CKH) tw(CKL) td(C-Q) tsu(D-C) th(C-Q) th(C-D) ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. ParameterSymbol Standard UnitMin. Max. TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time TXiINOUT input LOW pulse width TXiINOUT input HIGH pulse width TXiINOUT input cycle time CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi hold time RxDi input setup time TxDi output delay time RxDi input hold time INTi input LOW pulse width INTi input HIGH pulse width 600 300 300 600 300 300 380 380 300 150 150 160 VCC = 3V Table 1.74. External interrupt INTi inputs

Electrical characteristics (Vcc = 3V) Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 124 tsu(D–C) TA0 IN input TA0 OUT input During event counter mode TBiIN input CLK0 TxDi RxDi tc(TA) tw(TAH) tw(TAL) tc(UP) tw(UPH) tw(UPL) tc(TB) tw(TBH) tw(TBL) tc(CK) tw(CKH) tw(CKL) tw(INL) tw(INH) td(C–Q) th(C–D) th(C–Q) th(TIN–UP) tsu(UP–TIN) TA0 IN input (When count on falling edge is selected) TA0 IN input (When count on rising edge is selected) TA0 OUT input (Up/down input) INTi input TXiINOUT input tc(TX) tw(TXH) tw(TXL) VCC = 3V

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect Performance 4.0V to 5.5 V (f(XIN)=10MHz) VPP =12V ± 5% (f(XIN)=10MHz) Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.AA.3. One division (4 Kbytes) (Note 1) In units of byte Collective erase Program/erase control by software command 6 commands 100 times Parallel I/O mode is supported. Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. User ROM area Boot ROM area VCC =5V ± 5% (f(XIN)=10MHz) Table AA-1. Outline Performance of the M30201 (flash memory version) Outline Performance Table AA-1 shows the outline performance of the M30201 (flash memory version).

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Preliminary 126 Flash Memory The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device operation. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program- mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. Figure AA-3. Block diagram of flash memory version SFR RAM SFR RAM SFR RAM 0000016 0040016 YYYYY 16 DF000 16 DFDFF 16 XXXXX 16 FFFFF 16 M30201F6 XXXXX 16 F400016 YYYYY 16 00BFF 16 Microcomputer mode Parallel I/O mode CPU rewrite mode Standard serial I/O mode Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes) User ROM area User ROM area User ROM area Collective erasable/ programmable area Type No. Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area Collective erasable/ programmable area

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 127 CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. Figure BB-1, Figure BB- 2 show the flash memory control register, and flash command register respectively. Also, in CPU rewrite mode, the CNV SS pin is used as the VPP power supply pin. Apply the power supply voltage, VPP H, from an external source to this pin. In CPU rewrite mode, only the user ROM area shown in Figure AA-3 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM before it can be executed. Flash memory control register 0 Symbol Address When reset FCON0 03B4 16 001000002 WR b7 b6 b5 b4 b3 b2 b1 b0 CPU rewrite mode select bit FCON00 Bit symbol Bit name Function RW 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid This bit can not write. The value, if read, turns out to be indeterminate. Reserved bit CPU rewrite mode monitor flag 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid Must always be set to "0". Nothing is assigned. In an attempt to write this bit, write "0". The value, if read, turns out to be "0". FCON02 /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Reserved bit Must always be set to "1".Reserved bit /LiteDiagLines/LiteDiagLines Must always be set to "0".Reserved bit Flash memory control register 1 Symbol Address When reset FCON1 03B5 16 XXXXXX00 2 WR b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol Bit name Function RW /LiteDiagLines Reserved bit /LiteDiagLines Nothing is assigned. In an attempt to write these bits, write "0". The value, if read, turns out to be indeterminate. Must always be set to "0". /LiteDiagLines Flash command register Symbol Address When reset FCMD 03B6 16 0016 WR b7 b6 b5 b4 b3 b2 b1 b0 Writing of software command <Software command name> <Command code>

Read command "00 16"
Program command "40 16"
Program verify command "C0 16"
Erase command "20 16" +"2016"
Erase verify command "A0 16"
Reset command "FF 16"+"FF6" Function RW /LiteDiagLines Figure BB-1. Flash memory control register Figure BB-2. Flash command register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 128 Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure AA-3 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV SS pin low (VSS ). In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P52 pin high (VCC ), the CNVSS pin high(VPPH ), the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. CPU rewrite mode operation procedure The internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the CPU to the flash memory control register (addresses 03B4 16, 03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom- plished, a CPU write control program must be written into the boot ROM area in parallel input/output mode. The following shows a CPU rewrite mode operation procedure. <Start procedure (Note 1)> (1) Apply VPP H to the CNVSS /VPP pin and VCC to the port P52 pin for reset release. Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program. In this case, set the CPU write mode select bit of the flash memory control register to “1” before applying V PP H to the CNVSS /VPP pin. (2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump to this control program in RAM. (The operations described below are controlled by this program.) (3) Set the CPU rewrite mode select bit to “1”. (4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled. (5) Execute operation on the flash memory by writing software commands to the flash command regis- ter. Note 1: In addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and writing to the watchdog timer. <Clearing procedure> (1) Apply VSS to the CNVSS /VPP pin. (2) Set the CPU rewrite mode select bit to “0”.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 129 Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During erase/program mode, set BCLK to one of the following frequencies by changing the divide ratio:

5 MHz or less when wait bit (bit 7 at address 0005

16) = 0 (without internal access wait state)

10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)

(2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 130 Command Program verify Read Program 03B616 First bus cycle Second bus cycle 0016 4016 C0 16 Write Write Write Program address Write Read Erase verify A016Write Verify address Verify data Read Erase 2016Write 03B616 2016Write Verify address Reset FF16Write Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) 03B616 03B616 03B616 03B616 03B616 Program data Verify data FF16Write 03B616 Software Commands Table BB-1 lists the software commands available with the M30201 (flash memory version). When CPU rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. The content of each software command is explained below. Table BB-1. List of Software Commands (CPU Rewrite Mode) Read Command (00 16) The read mode is entered by writing the command code “0016” to the flash command register in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D 0–D 7), 8 bits at a time. The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (40 16) The program mode is entered by writing the command code “4016” to the flash command register in the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g., STE instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. The program operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. During program operation, the watchdog timer remains idle, with the value “7FFF 16” set in it. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure 1.BB.3 for an example of a programming flowchart.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 131 Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” to the flash command register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. The CPU compares this read data with the data that it previously wrote to the address using the program command. If the compared data do not match, the user need to execute the program and program-verify operations one more time. Erase command (20 16 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. During erase operation, the watchdog timer remains idle, with the value “7FFF16 set in it. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure BB-3 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” to the flash command register in the first bus cycle. When the user execute an instruction to read byte data from the address to be verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out. The CPU must sequentially erase-verify memory contents one address at a time, over the entire area erased. If any address is encountered whose content is not “FF 16” (not erased), the CPU must stop erase-verify at that point and execute erase and erase-verify operations one more time. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode Preliminary 132 Start Address = first location Loop counter : X=0 Write program command Write : 4016 Duration = 20 µs Duration = 6 µs X=25 ? Verify OK ? PASS FAIL FAIL PASS YES PASS NO NO FAIL Write program data/ address Loop counter : X=X+1 Write program verify command Last address ?Next address ? Write read command Write read command Verify OK ? Write : Program data Write : C016 Write : 0016 Write:2016 Duration = 6µs X=1000 ? Verify OK? PASS FAIL FAIL PASS YES PASS NO NO FAIL Duration = 20ms YES NO Start All bytes = "0016"? Program all bytes = "0016" Address = First address Loop counter X=0 Write erase command Write erase command Loop counter X=X+1 Write erase verify command/address Verify OK? Last address?Next address Write read command Write read command Write:2016 Write:A016 Write:0016 Read: expect value=FF16 Figure BB-3. Program and erase execution flowchart in the CPU rewrite mode Program Erase Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “40 16” or “2016” twice to the flash command register, write command code “FF16” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 133 Pin name Signal name I/O Function VCC ,VSS Power supply input Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin. CNV SS CNV SS Apply 12 V ± 5 % to the CNVSS pin.I RESET Reset input Connect this pin to VSS .I XIN Clock input Connect a ceramic or crystal resonator between the XIN and XOUT pins. When entering an externally derived clock, enter it from XIN and leave XOUT open. I XOUT Clock output O AV CC , AVSS Analog power supply input VREF Reference voltage input I Connect AVSS to Vss and AVcc to Vcc, respectively. Connect this pin to VSS . P00 to P07 Data I/O D0 to D7 These are data D0–D 7 input/output pins. These are address A4–A7 input pins. IP30 to P33 P34 to P35 I P41 This is a OE input pin.I P50 Address input A17 P64 to P67 I/O Address input A4 to A7 Input port P3 OE input P42, P44, P45 Input port P4 I Enter high signals or low signals to these pins. Input port P6 Enter high signals or low signals to these pins.I P70 to P71 Input port P7 I CE input This is a CE input pin.IP43 Enter low signals to these pins. P40 WE input This is a WE input pin.I I This is address A17 input pin. P51 VRFY input I Apply VIH (5 V) to this pin when VPP = VPPH (12 V), or VIL (0 V) when VPP = VPPL (5 V). P52 IInput port P5 Enter low signal to this pin. P53, P54 Input port P5 I Enter high signals or low signals to these pins. These are address A0–A3 input pins. IP60 to P63 Address input A0 to A3 Enter high signals or low signals to these pins. P10 to P17 Address input A8 to A15 These are address A8–A15 input pins.I Description of Pin Function (Flash Memory Parallel I/O Mode)

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 134 M30201(flash memory version) M5M28F101 VCC VSS VCC VSS VCC VSS Address input Data I/O OE input CE input P60 to P63, P30 to P33, P10 to P17, P50 P00 to P07 P41 P43 A0 to A15, A17 D 0 to D7 OE CE WE input VRFY input (Note) P40 P51 WE Note: The VRFY input only selects read-only or read/write mode, and does not have any pin associated with it on the M5M28F101. Parallel I/O Mode The parallel I/O mode is entered by making connections shown in Figures CC-2 and CC-3 and then turning the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences with regard to the functions not available with the microcomputer (function of read device identification code) and matters related to memory capacity. Table CC-2 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode. Table CC-2. Pin relationship in parallel I/O mode SFR RAM SFR RAM SFR RAM 0000016 0040016 YYYYY 16 DF000 16 DFDFF 16 XXXXX 16 FFFFF 16 M30201F6 XXXXX 16 F400016 YYYYY 16 00BFF 16 Microcomputer mode Parallel I/O mode CPU rewrite mode Standard serial I/O mode Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes) User ROM area User ROM area User ROM area Collective erasable/ programmable area Type No. Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area Collective erasable/ programmable area Figure CC-1. Block diagram of flash memory version

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 135 P63/AN3 P62/AN2 P61/AN1 P60/AN0 VREF XIN XOUT P50/TXD 0/AN50 P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS RESET VCC CNV SS P51/RXD 0/AN51 P52/CLK0/AN52 AV SS P45/TX2INOUT P70/TB0IN/XCOUT P71/TB1IN/XCIN P54/CKOUT /AN54 P53/CLKS/AN53 AV CC P07/KI7 P06/KI6 P05/KI5 P04/KI4 P03/KI3 P02/KI2 P01/KI1 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201F6SPM30201F6TSP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUTCE OE WE A10 A11 A13 A14 A15 A12 A17 VSS VCC VPPH Connect oscillator circuit. VRFY Figure CC-2. Pin connection diagram in parallel I/O mode (1)

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 136 Figure CC-3. Pin connection diagram in parallel I/O mode (2) 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 XIN XOUT P50/TXD 0/AN50 P67/AN7 VSS RESET VCC CNV SS P51/RXD 0/AN51 2/CLK 0/AN P45/TX2INOUT P71/TB1IN/XCIN P70/TB0IN/XCOUT 1/TA0 OUT 0/TA0 IN XD 2/R XD 4/CK OUT /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT A17 D7A8 A10 A11 A12 A13A15 A14A4A6 A5A7 V SS VCC CE OE WE VRFY VPPH Connect oscillator circuit.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 137 Read only Read/ Write Read Write Output disabled Stand by Read Output disabled Stand by Data output Hi-Z Data output Hi-Z Data input VIL VIL VIH VIL VIL VIH VIL VIH VIL VIH VIH VIH VIL VIL VIL VIH VIH VIH VIH VIH Mode Pin name CE OE WE V RFY D 0 to D7 Note: X can be VIL or VIH. VPPH VPP VPPH VPPH VPPH VPPH VPPH VPPH XX XX Hi-Z Hi-Z VIL VIH VIL VIH User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure CC-1 can be rewritten. In the boot ROM area, an erase block operation is applied to only one 4 K byte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, the user does not need to write to the boot ROM area. Functional Outline (Parallel I/O Mode) In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by the status of the CE, OE, WE, VRFY , and CNVSS input pins. The contents of erase, program, and other operations are selected by writing a software command. The data in memory can only be read out by a read after software command input. Program and erase operations are controlled using software commands. Table CC-3. Relationship between control signals and bus operation modes

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 138 The following explains about bus operation modes, software commands, and status register. Bus Operation Modes Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin. Read-only mode has three states: Read, Output Disable, and Standby which are selected by setting the CE, OE, and WE pins high or low. Read-write mode is entered by applying V PPH to the CNVSS pin and a high voltage to the VRFY pin. Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by setting the CE, OE, and WE pins high or low. Read The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read mode, the data corresponding to each software command entered is output from the data I/O pins D 0–D 7. Output Disable The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also, the data I/O pins are placed in the high-impedance state. Standby The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the high-impedance state. Write The Write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device accepts the software commands or write data entered from the data I/O pins. A program, erase, or some other operation is initiated depending on the content of the software command entered here. The input data such as address is latched at the falling edge of WE pin. The input data such as software command is latched at the rising edge of WE pin.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 139 Command Program verify Read Program First bus cycle Second bus cycle 0016 4016 C0 16 Write Write Write Program address Write Read Erase verify A016Write Verify data Read Erase 2016Write 20 16Write Reset FF16Write Mode Address Mode Address Data (D0 to D7) Data (D0 to D7) x Program data Verify data FF16Write x x x x Verify address x x x x Software Commands Table CC-4 lists the software commands available with the M30201 (flash memory version). By entering a software command from the data I/O pins (D0–D 7) in Write mode, specify the content of the operation, such as erase or program operation, to be performed. The following explains the content of each software command. Table CC-4. Software command list (parallel I/O mode) Read Command (00 16) The read mode is entered by writing the command code “0016” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data I/O pins (D 0–D 7). The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (40 16) The program mode is entered by writing the command code “4016” in the first bus cycle. When an address and data to be program is write in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure CC-4 for an example of a programming flowchart.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 140 Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D 7) in the second bus cycle. Erase command (2016 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” in the first bus cycle and the same command code again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “00 16” written to by using the program and program-verify commands. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure CC-4 for an example of an erase flowchart. Erase-verify command (A0 16) The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D 7) in the second bus cycle. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “00 16” to memory before erasing.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 141 Start Address = first location Loop counter : X=0 Write program command Write : 4016 Duration = 20 µs Duration = 6 µs X=25 ? Verify OK ? PASS FAIL FAIL PASS YES PASS NO NO FAIL Write program data/ address Loop counter : X=X+1 Write program verify command Last address ?Next address ? Write read command Write read command Verify OK ? Write : Program data Write : C016 Write : 0016 Write:2016 Duration = 6µs X=1000 ? Verify OK? PASS FAIL FAIL PASS YES PASS NO NO FAIL Duration = 20ms YES NO Start All bytes = "0016"? Program all bytes = "0016" Address = First address Loop counter X=0 Write erase command Write erase command Loop counter X=X+1 Write erase verify command/address Verify OK? Last address?Next address Write read command Write read command Write:2016 Write:A016 Write:0016 Read: expect value=FF16 Figure CC-4. Program and erase execution flowchart in the CPU rewrite mode Program Erase Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “40 16” or “2016” twice, write command code “FF16” in the first bus cycle and the same command code again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.

Appendix Parallel I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 142 Figure CC-5. Protect control address Protect function In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects the flash memory contents from being read or rewritten easily. Depending on the content at the protect control address (FFFFF 16) in parallel I/O mode, this function inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is shown in Figure CC-5 . (This address exists in the user ROM area.) The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash memory contents are inhibited against read or modification. The protect function is disabled by setting both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or modified. Once the protect function is set, the user cannot change settings of the protect clear bits while in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode. Symbol Address When shipping ROMCP FFFFF 16 FF16 Protect control address Bit name FunctionBit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled Protect reset bit Protect set bit ROMCR ROMCP b5 b4 b7 b6 Note 1: When protect is turned on, the flash memory version is protected against readout or modification in parallel I/O mode. Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode. Reserved bit Always set to "1". 1111

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 143 Pin Description VCC ,VSS Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin. CNV SS Apply 12V ± 5 % to this pin. RESET Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. XIN Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin.XOUT AV CC , AVSS VREF Connect AVSS to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. P00 to P07 Input "H" or "L" level signal or open. P10 to P17 Input "H" or "L" level signal or open. P30 to P35 Input "H" or "L" level signal or open. P40 to P45 Input "H" or "L" level signal or open. P54 Input "H" or "L" level signal or open. P50 Serial data output pin. P51 P52 Serial clock input pin. P53 P60 to P67 Input "H" or "L" level signal or open. P70 to P71 Input "H" or "L" level signal or open. Name Power input CNV SS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P3 Input port P4 Input port P5 TxD output SCLK input BUSY output Input port P6 Input port P7 I/O I I I O I I I I I I I I I I O RxD input Serial data input pin. O BUSY signal output pin. Pin functions (Flash memory standard serial I/O mode)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 144 Figure DD-1. Pin connections for serial I/O mode (1) P63/AN3 P62/AN2 P61/AN1 P60/AN0 VREF XIN XOUT P50/TXD 0/AN50 P67/AN7 P66/AN6 P65/AN5 P64/AN4 VSS RESET VCC CNV SS P51/RXD 0/AN51 P52/CLK0/AN52 AV SS P45/TX2INOUT P70/TB0IN/XCOUT P71/TB1IN/XCIN P54/CKOUT /AN54 P53/CLKS/AN53 AV CC P07/KI7 P06/KI6 P05/KI5 P04/KI4 P03/KI3 P02/KI2 P01/KI1 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) M30201F6SPM30201F6TSP P00/KI0 P30 P31 P32P33 P34 P35 P40/TA0IN/TXD 1 P41/TA0OUT P42/RXD 1 P44/INT1/TX1INOUT P43/INT0/TX0INOUT BUSY SCLK R XD TXD VSS VCC CNV SS VSS VCC RESET CNV SS VPP H RESET V SS VCC Mode setup method Signal Value Connect oscillator circuit.

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 145 Figure DD-2. Pin connections for serial I/O mode (2) 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 56 55 54 53 27 28 XIN XOUT P50/TXD 0/AN50 P67/AN7 VSS RESET VCC CNV SS P51/RXD 0/AN51 2/CLK 0/AN P45/TX2INOUT P71/TB1IN/XCIN P70/TB0IN/XCOUT 1/TA0 OUT 0/TA0 IN XD 2/R XD 4/CK OUT /AN 3/CLKS/AN V REF 0/AN 1/AN AV SS AV CC P10(LED0) 4(LED M30201F6FP M30201F6TFP N.C. N.C. N.C. N.C. P00/KI0 2/AN 3/AN 4/AN 5/AN 6/AN P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P11(LED1) P12(LED2) P13(LED3) 5(LED 6(LED 7(LED P44/INT1/TX1INOUT P43/INT0/TX0INOUT V SSV CC BUSYSCLK R XD TXD CNV SS RESET VSS VCC CNV SS VPP H RESET V SS VCC Mode setup method Signal Value Connect oscillator circuit.

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 146 Standard Serial I/O Mode The standard serial I/O mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific serial programmer. The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard serial I/O mode is started by clearing the reset with V PPH at the CNVss pin. (For the normal microprocessor mode, set CNVss to “L”.) This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used. Figures DD-1 and DD-2 show the pin connections for the standard serial I/O mode. Serial data I/O uses three UART0 pins: CLK 0, RxD0, and TxD0 and port P53 (BUSY). The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs the CMOS signal. The P53 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level when the reception operation starts. Transmission and reception data is transferred serially in 8-byte blocks. In the standard serial I/O mode, only the user ROM area shown in Figure CC-1 can be rewritten, the boot ROM area cannot. The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code does not match the content of the flash memory, the command sent from the programmer is not accepted. Function Overview (Standard Serial I/O Mode) In the standard serial I/O mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O (UART0) and P5 3. In reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the TxD 0 pin. The TxD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first. When busy, either during transmission or reception, or while executing an erase operation or program, the P5 3 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the P53 (BUSY) pin is “L” level. Also, data in memory and the status register can be read after inputting a software command. It is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. Software commands and the status register are explained here following.

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 147 Software Commands Table DD-1 lists software commands. In the standard serial I/O mode, erase operations, programs and reading are controlled by transferring software commands via the RxD pin. Software commands are explained here below. Table DD-1. Software commands (Standard serial I/O mode) Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte

1 Page read

2 Page program

3 Erase all unlocked blocks

4 Read status register

5 Clear status register

6 Read lockbit status

7 ID check function

8 Download function

9 Version data output function

14 Boot area output function

Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is transferred from the serial programmer to the flash memory microcomputer. Note2: SRD refers to status register data. SRD1 refers to status register 1 data. Note3: All commands can be accepted when the flash memory is totally blank. When ID is not verificate Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Acceptable Not acceptable Acceptable Not acceptable Version data output to 9th byte Data output to 259th byte Data output to 259th byte Data input to 259th byte To ID7 Data output Data input ID1 To required number of times Version data output Data output Data output Data input ID size Data input Version data output Data output Data output Data input Lock bit data output Address (high) Check- sum Version data output Data output Address (high) Address (high) SRD1 output Address (high) Address (middle) Size (high) Version data output Address (high) Address (middle) Address (middle) D0 16 SRD output Address (middle) Address (low) Size (low) Version data output Address (middle) FF 16 4116 A7 16 7016 5016 7116 F516 FA 16 FB 16 FC 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 148 Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Send the “FF 16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) From the 4th byte onward, data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 CLK0 RxD0 TxD0 P53(BUSY) A8 to A15 A16 to A23FF16 SRD output SRD1 output 7016 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-3. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent in the 1st byte of the transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read. Figure DD-4. Timing for reading the status register

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 149 Figure DD-5. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Send the “4116” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively. (3) From the 4th byte onward, as write data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. 5016 CLK0 RxD0 TxD0 P53(BUSY) Clear Status Register Command This command clears the bits (SR3–SR4) which are set when the status register operation ends in error. When the “50 16” command code is sent in the 1st byte of the transmission, the aforementioned bits are cleared. When the clear status register operation ends, the P53 (BUSY) signal changes from the “H” to the “L” level. A8 to A15 A16 to A234116 data0 data255 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-6. Timing for the page program

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 150 Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status com- mand as explained here following. (1) Send the “71 16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the highest address of the specified block for addresses A8 to A23. The M30201 (flash memory version) does not have the lock bit, so the read value is always “1” (block unlock). A8 to A15 A16 to A237116 DQ6 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-8. Timing for reading lock bit status Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Send the “A7 16” command code in the 1st byte of the transmission. (2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify com- mand code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register. A716 D0 16 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-7. Timing for erasing all unlocked blocks

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 151 Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Send the “FA 16” command code in the 1st byte of the transmission. (2) Send the program size in the 2nd and 3rd bytes of the transmission. (3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent in the 5th byte onward. (4) The program to execute is sent in the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. FA 16 Program data Program data Data size (high) Data size (low) Check sum CLK0 RxD0 TxD0 P53(BUSY) Figure DD-9. Timing for download

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 152 Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Send the “FB 16” command code in the 1st byte of the transmission. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. Figure DD-10. Timing for version information output Boot Area Output Command This command outputs the control program stored in the boot area in one page blocks (256 bytes). Execute the boot area output command as explained here following. (1) Send the “FC 16” command code in the 1st byte of the transmission. (2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) From the 4th byte onward, data (D0–D 7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the rise of the clock. FB 16 'X''V' 'E' 'R' CLK0 RxD0 TxD0 P53(BUSY) data0 data255 A8 to A15 A16 to A23FC 16 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-11. Timing for boot area output

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 153 ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Send the “F516” command code in the 1st byte of the transmission. (2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd and 4th bytes of the transmission respectively. (3) Send the number of data sets of the ID code in the 5th byte. (4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code. ID size ID1 ID7F516 DF 16 FF16 0F16 CLK0 RxD0 TxD0 P53(BUSY) Figure DD-12. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the com- mand sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF 16, 0FFFE316, 0FFFEB 16, 0FFFEF 16, 0FFFF316, and 0FFFF7 16 . Write a program into the flash memory, which already has the ID code set for these addresses. Reset Watchdog timer vector Single step vector Address match vector BRK instruction vector Overflow vector Undefined instruction vector ID7 ID6 ID5 ID4 ID3 ID2 ID1 DBC vector 0FFFFF 16 to 0FFFFC16 0FFFFB 16 to 0FFFF816 0FFFF7 16 to 0FFFF416 0FFFF3 16 to 0FFFF016 0FFFEF 16 to 0FFFEC16 0FFFEB 16 to 0FFFE816 0FFFE7 16 to 0FFFE416 0FFFE3 16 to 0FFFE016 0FFFDF 16 to 0FFFDC16 4 bytes Address Figure DD-13. ID code storage addresses

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 154 Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (70 16). Also, the status register is cleared by writing the clear status register command (5016). Table DD-2 gives the definition of each status register bit. After clearing the reset, the status register outputs “80 16”. Table DD-2. Status register (SRD) Status Bit (SR7) The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Bit (SR5) The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Bit (SR4) The program bit reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Status bit Reserved Erase bit Program bit Reserved Reserved Reserved Reserved Definition "1" "0" Ready Terminated in error Terminated in error Busy Terminated normally Terminated normally

Appendix Standard Serial I/O Mode Preliminary Under development Mitsubishi microcomputers M30201 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 155 Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table DD-3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table DD-3. Status register 1 (SRD1) Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the down- load function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) SR9 (bit1) SR8 (bit0) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Data receive time out Reserved Definition "1" "0" Update completed Match Not update Mismatch Normal operation Not verified Verification mismatch Reserved Verified Time out

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix Standard Serial I/O Mode Preliminary 156 Example Circuit Application for The Standard Serial I/O Mode The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary ac- cording to programmer, therefore see the programmer manual for more information. P53(BUSY) CLK0 R XD0 TXD0 CNVss Clock input P53 output Data input Data output M30201 Flash memory version (1) Control pins and external circuitry will vary according to programmer. For more information, see the programmer manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. VPP Figure DD-14. Example circuit application for the standard serial I/O mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 157 SDIP52-P-600-1.78 Weight(g) JEDEC Code 5.1 Alloy 42/Cu Alloy 52P4B Plastic 52pin 600mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° –1 5 ° –– 5 . 5 e 52 27 261 E ce1 A2A1 bb1 b2e L A SEATING PLANE D QFP56-P-1010-0.65 0.59 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 56P6S-A Plastic 56pin 105 10mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.35 ––I2 1.3 ––M D 10.6 ––M E 10.6 10°0° 0.1 1.4 0.80.60.4 13.112.812.5 13.112.812.5 0.65 10.210.09.8 10.210.09.8 0.20.150.13 0.40.30.25 2.8 3.05 e e e E c H E 56 43 H D D M D M E A Fb A1 A2 Ly Recommended Mount Pad Detail F

Keep safety first in your circuit designs! Notes regarding these materials l Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. l These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. l Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. l All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). l When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. l Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. l If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. l Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein.

M30201 Group DATA SHEET REV.D April First Edition 1998 July Second Edition 1998 February Third Edition 1999 May Fourth Edition 1999 Editioned by Committee of editing of Mitsubishi Semiconductor DATA SHEET Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1999 MITSUBISHI ELECTRIC CORPORATION

Product Information

M30201M4-XXXFP specifications and overview.

Summary

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or 56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.

Source title M30201M4-XXXFP Datasheet(PDF) - Mitsubishi Electric Semiconductor

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