M2V56S40ATP-6

M2V56S20ATP MITSUBISHI | Alldatasheet

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Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7

256 M Synchronous DRAM

M2V56S20ATP is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40ATP achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), 166MHz(-5) and are suitable for main memory or graphic memory in computer systems. - Single 3.3v±0.3V power supply - Max. Clock frequency -5:PC166<3-3-3> / -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch Some of contents are subject to change without notice.

DESCRIPTION

FEATURES

PC100 (CL2) PC133 (CL3) PC133 (CL2)166 MHz133 MHz

100 MHz

133 MHz

Max. Frequency @CL3 Max. Frequency @CL2

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O DQM, DQMU/L : Output Disable / Write Mask A0-12 : Address Input BA0,1 : Bank Address Input Vdd : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output PIN CONFIGURATION (TOP VIEW) Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC UDQM CLK CKE A12 A11 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A12 A11 Vss Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd x16

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Speed Grade 5: 166MHz@CL3, 133MHz@CL2 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2 Type Designation Code This rule is applied to only Synchronous DRAM family. Mitsubishi Main Designation Package Type TP: TSOP(II) Process Generation A:2nd. gen. Function Reserved for Future Use Organization 2 n 2: x4, 3: x8, 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) M 2 V 56 S 4 0 A TP - 5 BLOCK DIAGRAM /CS /RAS /CAS /WE DQMU/L Memory Array Bank #0 I/O Buffer Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer A0-12 BA0,1 Clock Buffer CLK CKE Control Signal Buffer

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 VddQ and VssQ are supplied to the Output Buffers only. Power Supply for the memory array and peripheral circuitry. Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. Data In and Data out are referenced to the rising edge of CLK. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Input / Output Power Supply Power Supply Input Input Input Input VddQ, VssQ Vdd, Vss DQM DQMU/L DQ0-15 BA0,1 A0-12 /RAS, /CAS, /WE Chip Select: When /CS is high, any command means No OperationInput/CS Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Input Master Clock: All other inputs are referenced to the rising edge of CLK.Input CKE CLK PIN FUNCTION

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 The M2V56S20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto- precharge,READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically. /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @refresh command A10 Precharge Option @precharge or read/write command CLK define basic commands

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 NOTE: 1. A7-9,11-12=L, A0-A6 =Mode Address H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number COMMAND MNEMONIC CKE n-1 CKE n /CS /RAS /CAS /WE BA0,1 A10 /AP A0-9, 11-12 Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Banks PREA H X L L H L H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TBST H X L H H L X X X Mode Register Set MRS H X L L L L L L V X note

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Current State /CS /RAS /CAS /WE Address Command Action IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A10 PRE / PREA NOP*4 L L L H X REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ROW ACTIVE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST NOP L H L H BA, CA, A10 READ / READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto- Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action WRITE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin Read, Determine Auto- Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto- Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action PRE - CHARGING H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RE- COVERING H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action RE- FRESHING H X X X X DESEL NOP (Idle after tRC) L H H H X NOP NOP (Idle after tRC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 n /CS /RAS /CAS /WE Add Action SELF- REFRESH*1 H X X X X X X INVALID L H H X X X X Exit Self-Refresh (Idle after tRC) L H L H H H X Exit Self-Refresh (Idle after tRC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) ALL BANKS IDLE*2 H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down ANY STATE other than listed above H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend FUNCTION TRUTH TABLE for CKE ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 100µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. /CS /RAS /CAS /WE BA0,1 A12-A0 CLK V R: Reserved for Future Use BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 SW 0 0 LTMODE BT BL BURST LENGTH BL BT=0 BT=1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R R R Full Page R R R R BURST TYPE SEQUENTIAL INTERLEAVED LATENCY MODE CL /CAS LATENCY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R R R R R R Burst Write Single WriteSW 0

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7

• 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 Command Address CLK Read Y Write Y /CAS Latency Burst Length Burst Length DQ Burst Type CL= 3 BL= 4 Q0 Q1 Q2 Q3 D0 D1 D2 D3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-12. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. READ A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0- 9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. Bank Activation and Precharge All (BL=4, CL=3) CLK Command A0-9,11-12 A10 BA0-1 DQ ACT READACT PRE ACT Xa Xb Yb Xa 1Xa Xb 0 00 01 01 00 Qb0 Qb1 Qb2 Qb3 tRRD tRCD tRP Xa Precharge All

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 A0-9,11-12 A10 BA0-1 DQ ACT ACT Xa Xa Xa 00 00 tRCD tRP Xa Read with Auto-Precharge (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qa3 internal precharge starts BL CLK Command DQ ACT ACT tRCD Auto-Precharge Timing (READ, BL=4) READ Qa0 Qa1 Qa2 Qa3 internal precharge starts BL DQ Qa0 Qa1 Qa2 Qa3 CL=2 CL=3 CLK Command A0-9,11-12 A10 BA0-1 DQ ACT READACT PRE ACT Xa Xb Yb Xa 0Xa Xb 0 00 01 01 00 Qb0 Qb1 Qb2 Qb3 tRCD tRCD tRP Xa Multi Bank Interleaving Read (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qa3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4), A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. CLK Command A0-9,11-12 A10 BA0-1 DQ ACT PRE ACT Xa Xa 0Xa 00 00 tRCD tRP Xa Write (BL=4) Write Ya Da0 Da1 Da2 Da3 BL tWR CLK Command A0-9,11-12 A10 BA0-1 DQ ACT ACT Xa Xa Xa 00 00 tRCD tRP Xa Write with Auto-Precharge (BL=4) Write Ya Da0 Da1 Da2 Da3 BL tWR internal precharge starts

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. CLK Command A0-9,11-12 A10 BA0-1 DQ READ Yb Qc0 Qc1 Qc2 Qc3 Read interrupted by Read (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qb0 READ Yc CLK Command A0-9,11-12 A10 BA0-1 DQ ACT Xa Xa Read interrupted by Write (CL=2, BL=4) READ Ya Qa0 Da0 Da1 Da2 DQM Write Ya Da3 Output disable by DQM by WRITE

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Precharge (BL=4) CLK Command DQ PREREAD Q0 Q1 Q2 Command DQ PREREAD Q0 Q1 Command DQ PREREAD Command DQ PREREAD Q0 Q1 Q2 Command DQ PREREAD Q0 Q1 Command DQ PREREAD CL=2 CL=3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. CLK Command DQ TBSTREAD Q0 Q1 Q2 Command DQ TBSTREAD Q0 Q1 Command DQ TBSTREAD Command DQ TBSTREAD Q0 Q1 Q2 Command DQ TBSTREAD Q0 Q1 Command DQ TBSTREAD CL=2 CL=3 Read interrupted by Terminate (BL=4)

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. [ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write interrupted by Write (BL=4) CLK Command A0-9,11-12 A10 BA0-1 DQ Write Yb Dc0 Dc1 Dc2 Dc3 Write Ya Da0 Da1 Da2 Db0 Write Yc CLK Command A0-9,11-12 A10 BA0-1 DQ ACT Xa Xa Write interrupted by Read (CL=2, BL=4) READ Yb Da0 Da1 Qb0 Write Ya Qb1 Qb2 Qb3 don't care

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK. CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya Write interrupted by Precharge (BL=4) ACT Xa Da0 Da1 PRE ACT Xa tWR tRP DQM CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya Write interrupted by Terminate (BL=4) ACT Xa Da0 Da1 TBST Write Yb Db0 Db1 Db2 Db3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Write with Auto-Precharge Interrupted by Write / Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (BL=4) CLK Command A0-9,11-12 A10 BA0-1 DQ Db0 Db1 Db2 Db3 Write Ya Da0 Da1 Write Yb BL tWR tRP ACT Xa Xa interruptedauto-precharge activate WRITEA interrupted by READ to another bank (CL=2, BL=4) CLK Command A0-9,11-12 A10 BA0-1 DQ Write Ya Da0 Da1 Read Yb BL tWR tRP ACT Xa Xa interruptedauto-precharge activate Qb0 Qb1 Qb2 Qb3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 [ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA interrupted by READ to another bank (CL=2, BL=4) CLK Command A0-9,11-12 A10 BA0-1 DQ Read Ya Qa0 Qa1 Read Yb BL tRP ACT Xa Xa interruptedauto-precharge activate Qb0 Qb1 Qb2 Qb3 Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal. Single Write When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto- refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. Auto-Refresh CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 Auto Refresh on All Banks NOP or DESELECT Auto Refresh on All Banks minimum tRFC

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 Self Refresh Entry Self Refresh Exit X new command minimum tRFC for recovery Stable CLK NOP

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. Power Down by CKE CLK Command CKE Command CKE Standby Power Down Active Power Down PRE NOP NOP NOP NOP NOP NOPACT DQ Suspend by CKE CLK Command DQ CKE Write Read D0 D1 D2 D3 Q0 Q1 Q2 Q3 ext.CLK CKE int.CLK tIH tIS tIH tIS

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. DQM Function CLK Command DQ DQMU/L masked by DQMU/L=H disabled by DQMU/L=H Write Read D0 D2 D3 Q0 Q1 Q3

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 RECOMMENDED OPERATING CONDITIONS (Ta=0 ~ 70¡C, unless otherwise noted) CAPACITANCE (Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) 'C-65 ~ 150Storage TempretureTstg 'C0~ 70Operating TempratureTopr mW1000Ta=25'CPower DissipationPd mA50Output CurrentIO V-0.5 ~ VddQ+0.5with respect to VssQOutput VoltageVO V-0.5 ~ Vdd+0.5with respect to VssInput VoltageVI V-0.5 ~ 4.6with respect to VssQSupply Voltage for OutputVddQ V-0.5 ~ 4.6with respect to VssSupply VoltageVdd UnitRatingsConditionsParameterSymbol V0.8-0.3Low-Level Input Voltage all inputsVIL VVdd+0.32.0High-Level Input Voltage all inputsVIH V000Supply Voltage fo OutputVssQ V3.63.33.0Supply Voltage for OutputVddQ V000Supply VoltageVss V3.63.33.0Supply VoltageVdd Max.Typ.Min. Unit Limits ParameterSymbol pF6.54.0CI/O pF3.52.5 Input Capacitance,I/O pin Input Capacitance,CLK pinCI(K) pF3.82.5Input Capacitance,control pinCI(C) pF3.82.5 VI=1.4V f=1MHz VI=25mVrms Input Capacitance,address pinCI(A) Max.Min. Unit Limits Test ConditionParameterSymbol

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted) Notes 1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3xtCLK 4. input signals are stable 5. all banks are active AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Symbol Parameter Test Conditions Limits Min. Max. Unit VOH(DC) VOL(DC) IOZ II High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V, other input pins=0V 2.4 0.4 V V µA µA -10 -10 180 120 110 110 1.5 100 mA33-5/-6/-7CKE<0.2vSelf-Refresh Current Icc6 150 100 90140 120 115 x16 x16 Organi zation 4,5 3,5 2,4 2,3 mA mA mA mA mA mA mA mA mA 170 220 140 110 tCLK=min, tRFC=minAuto-Refresh Current Icc5 tCLK=min, BL=4, gapless data Burst Operating Current Icc4 tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS> VIHmin Active Standby Current in Normal Mode Icc3NS Icc3N tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS>VIHminIdle Standby Current in Normal Mode Icc2NS Icc2N tCLK=L, CKE<VILmax tCLK=min, CKE<VILmax Icc2PS Icc2P Idle Standby Current in Power Down Mode tCLK=min, tRC=min, BL=1Operating Current (1bank) Icc1 NoteUnit -7-5 Limits(max) Test ConditionsParameterSymbol

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 (Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V 120000 7.8 0.8 1.5 101 2.5 2.5 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs7.87.8 2015 2015 2015 2020 2020 1200005012000045 8075 7067.5 0.8 1.5 101101 2.5 2.5 7.5 Average Refresh Interval Mode Register Set Cycle time ACT to ACT Delay time Write Recovery time Row Precharge time Row Active time Row to Column Delay Refresh Cycle time Row Cycle time Input Hold time (all inputs) Input Setup time (all inputs) Transition time of CLK CLK Low pulse width CLK High pulse width tREF tRSC tRRD tWR tRP tRAS tRCD tRFC tRC tIH tIS tT tCL tCH CL=3 CL=2 CLK cycle timetCLK NoteUnit -7-6 Limits ParameterSymbol AC timing is referenced to the input signal crossing through 1.4V. CLK Signal 1.4V 1.4V

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 (Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Output Load Condition 50pF Vout tOLZ tAC tOH tOHZ CLK DQ 1.4V 1.4V ns635.435.43CL=3 CL=2 5.43 5.4 5.4 ns ns ns ns ns ns 6363 5.4 CL=3 CL=2 CL=3 CL=2 Delay Time, Output High impedannce from CLK Delay Time, Output Low impedance from CLK Output Hold Time from CLK Access Time from CLK tOHZ tOLZ tOH tAC MaxMin.MaxMin.MaxMin. -7-6 Unit Limits ParameterSymbol Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters.

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Burst Write (Single Bank) [BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 D0 D0 X Y X X 0 0 D0 D0 D0 D0 tRC tRCD tRAS tWR tRP tRCD tWR Italic paramater shows minimum case ACT#0 WRITE#0 PRE#0 ACT #0 WRITE#0 PRE#0

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Burst Write (Multi Bank) [BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 D0 D0 X Y X X 0 0 D0 D0 D0 D0 tRC tRCD tRAS tWR tRP tRCD tWR Italic paramater shows minimum case ACT#0 WRITE#0 PRE#0 ACT #0 WRITE#0 PRE#0 X X X ACT#1 tRRD tRCD Y D1 D1 D1 D1 WRITEA#1 (Auto-Precharge) ACT#1 X X X tRC

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Burst Read (Single Bank) [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y Q0 Q0 Q0 Q0 X Y X X 0 0 Q0 Q0 Q0 Q0 tRC tRCD tRAS tRP tRCD Italic paramater shows minimum case ACT#0 READ #0 PRE#0 ACT #0 READ #0 PRE#0 tRAS

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Burst Read (Multi Bank) [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y Q0 Q0 Q0 Q0 X Y X X 0 0 Q0 Q0 Q0 Q0 tRC tRCD tRCD Italic paramater shows minimum case ACT#0 READA #0 READA #1 ACT #0 READ #0 PRE#0 X X X tRRD ACT#1 Y Q1 Q1 Q1 Q1 tRCD X X X ACT #1 tRC tRAS

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Write Interrupted by Write [BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 D0 D0 Y D0 D0 D0 D0 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 WRITE #0 PRE#0 X X X tRRD ACT#1 Y D0 D1 D1 D1 X X X ACT #1 Y WRITE #0 WRITEA #1 interrupt same bank interrupt other bank interrupt other bank tWR

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Read Interrupted by Read [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y Q0 Q0 Y Q1 Q1 Q0 Q0 tRCD Italic paramater shows minimum case ACT#0 READ#0 READ #0 X X X tRRD ACT#1 Y Q0 Q1 Q1 Q1 X X X ACT #1 Y READ#1 READA #1 interrupt other bank tRCD interrupt same bank interrupt other bank Q0 Q0

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 Y D1 D1 D1 D1 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 WRITE #1 PRE#1 X X X tRRD ACT#1 Q1 Q1 Y tWR READ#1 tRCD

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Write / Read Terminated by Precharge [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 Y Q0 Q0 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 READ #0 PRE#0 PRE#0 tWR X X X ACT#0 tRP tRAS tRCD tRP X X X ACT#0 tRC Terminate Terminate

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Write / Read Terminated by Burst Terminate [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 D0 Y Q0 Q0 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 READ #0TBST PRE#0 Y TBST D0 D0 D0 D0 WRITE#0 tWR

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Single Write Burst Read [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 Q0 Q0 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 READ #0 Q0 Q0 Y

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Power-Up Sequence and Intialize CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Italic paramater shows minimum case PRE ALL REFA ACT #0MRSREFA MA X X X 100µs REFA tRP tRFC Minimum 8 REFA cycles NOP tRFC tRSC Power On

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Italic paramater shows minimum case PRE ALL REFA Y D0 D0 D0 D0 WRITE#0 X X X ACT#0 tRP tRFC tRCD All banks must be idle before REFA is issued.

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Italic paramater shows minimum case PRE ALL Self Refresh Entry Self Refresh Exit X X X ACT#0 tRP All banks must be idle before REFS is issued. tRFC

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 CLK Suspension [CL=2, BL=4] CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X X X Y D0 Q0 Q0 tRCD Italic paramater shows minimum case ACT#0 WRITE #0 READ #0 Y D0 D0 D0 internal CLK suspended internal CLK suspended

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Italic paramater shows minimum case PRE ALL ACT #0 X X X Standby Power Down Active Power Down

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 Keep safety first in your circuit designs! Notes regarding these materials1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customerÕs application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2. Mitsubishi Electric Corporati on assumes no responsibility for any damage, or infringement of any third-partyÕs rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corp oration or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Jul '01 MITSUBISHI LSIs MITSUBISHI ELECTRIC SDRAM (Rev.1.01) Single Data Rate M2V56S20/ 30/ 40 ATP -5, -6, -7 1st editionJul y / '011.01 Description Date Rev.