M2V56S30AKT-6L

M2V56S20 MITSUBISHI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 51

Technical content

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Contents are subject to change without notice.

DESCRIPTION

FEATURES

PC100 (CL2) PC133 (CL3) PC133 (CL2)133MHz133MHz 100MHz 100MHz 100MHz 133MHz M2V56S20/30/40ATP/KT-7/-7L/-7UL M2V56S20/30/40ATP/KT-6/-6L/-6UL M2V56S20/30/40ATP/KT-5/-5L/-5UL Max. Frequency @CL3 Max. Frequency @CL2 M2V56S20ATP/ KT is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP/ KT is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP/ KT is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40AKT achieve very high speed data rate up to 100MHz (-7) , 133MHz (-6), and are suitable for main memory or graphic memory in computer systems. - Single 3.3v + 0.3V power supply - Max. Clock frequency -5:PC133<2-2-2> / -6:PC133<3-3-3> / -7:PC100<2-2-2> - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmable) - Burst type- sequential / interleave (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - Auto refresh and Self refresh - Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16) - LVTTL Interface - Both 54-pin TSOP Package and 64-pin Small TSOP Package M2V56S*0ATP: 0.8mm lead pitch 54-pin TSOP Package M2V56S*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package (sTSOP) - Low Power for the Self Refresh Current ICC6 : 2.0mA (–5L,-6L,-7L) - Ultra Low Power for the Self Refresh Current ICC6 : 1.0mA (–5UL,-6UL,-7UL) Note: The –5L/-6L/-7L is Self-refresh low power. The –5LU/-6UL/-7UL is Self-refresh ultra low power.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP PIN CONFIGURATION (TOP VIEW) 400mil x 875mil 54pin 0.8mm pitch TSOP(II) Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC UDQM CLK CKE A12 A11 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE A12 A11 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE A12 A11 Vss Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd LDQM /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0 BA1 A10/AP Vdd CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O DQM, DQMU/L : Output Disable / Write Mask A0-12 : Address Input BA0,1 : Bank Address Input Vdd : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output x16

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK : Master Clock CKE : Clock Enable /CS : Chip Select /RAS : Row Address Strobe /CAS : Column Address Strobe /WE : Write Enable DQ0-15 : Data I/O DQM, DQMU/L : Output Disable / Write Mask A0-12 : Address Input BA0,1 : Bank Address Input Vdd : Power Supply VddQ : Power Supply for Output Vss : Ground VssQ : Ground for Output 64pin STSOP(II) PIN PITCH 0.4mm TOP VIEW 33 VDD VDD NC DQ0 VDDQ VDDQ NC NC DQ0 DQ1 VSSQ VSSQ NC NC NC DQ2 VDDQ VDDQ NC NC DQ1 DQ3 VSSQ VSSQ NC NC NC NC NC NC NC NC VDD VDD NC NC NC NC /WE /WE /CAS /CAS /RAS /RAS /CS /CS NC NC BA0 BA0 BA1 BA1 A10/AP A10/AP A0 A0 A1 A1 A2 A2 A3 A3 VDD VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC NC NC VDD NC LDQM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP VDD VSS VSS VSS DQ15 DQ7 NC VSSQ VSSQ VSSQ DQ14 NC NC DQ13 DQ6 DQ3 VDDQ VDDQ VDDQ DQ12 NC NC DQ11 DQ5 NC VSSQ VSSQ VSSQ DQ10 NC NC DQ9 DQ4 DQ2 VDDQ VDDQ VDDQ DQ8 NC NC NC NC NC NC NC NC NC NC NC NC NC NC VSS VSS VSS UDQM DQM DQM NC NC NC CLK CLK CLK CKE CKE CKE NC NC NC A12 A12 A12 A11 A11 A11 A9 A9 A9 A8 A8 A8 A7 A7 A7 A6 A6 A6 A5 A5 A5 A4 A4 A4 VSS VSS VSS x16

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP A 64-pin sTSOP Package Outline 10.65+0.2 9.05+0.1*2 321 Note) DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 0.125+0.05 -0.02

1.2 MAX

Detail A (NTS) 0 - 10 0.125+0.075 0.5+0.1 (1) 0.8 0.6+0.15 0.25 Detail B (NTS) 0.35

0.55 MAX

13.1+0.1*1 -0.05B 0.08 M

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Type Designation Code This rule is applied to only Synchronous DRAM family. M 2 V 56 S 4 0 A KT –5 L BLOCK DIAGRAM /CS /RAS /CAS /WE DQMU/L Memory Array Bank #0 Memory Array Bank #1 Memory Array Bank #2 Memory Array Bank #3 Mode Register Control Circuitry Address Buffer A0-12 BA0,1 Clock Buffer CLK CKE Control Signal Buffer I/O Buffer Power Grade L: Low power, Blank: standard Speed Grade 5: 133MHz@CL3, 133MHz@CL2 6: 133MHz@CL3, 100MHz@CL2 7: 100MHz@CL2 Package Type TP: TSOP(II) , KT: sTSOP Process Generation A:2nd. gen. Function Reserved for Future Use Organization 2n 2: x4, 3: x8, 4: x16 SDRAM Data Rate Type S:Single Data Rate Density 56: 256M bits Interface V:LVTTL Memory Style (DRAM) Mitsubishi Main Designation

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP VddQ and VssQ are supplied to the Output Buffers only. Power Supply for the memory array and peripheral circuitry. Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. Data In and Data out are referenced to the rising edge of CLK. Combination of /RAS, /CAS, /WE defines basic commands. A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9,11. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Input / Output Power Supply Power Supply Input Input Input Input VddQ, VssQ Vdd, Vss DQM DQMU/L DQ0-15 BA0,1 A0-12 /RAS, /CAS, /WE Chip Select: When /CS is high, any command are masked except CLK, CKE and DQM Input/CS Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Input Master Clock: All other inputs are referenced to the rising edgeof CLK.Input CKE CLK PIN FUNCTION

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP BASIC FUNCTIONS Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated byBA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto- precharge, READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated byBA. Total data length to be written is set by burst length. When A10 =H at this command, the bank isdeactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically. /CS /RAS /CAS /WE CKE A10 CLK Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands The M2V56S20/30/40A* provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP COMMAND TRUTH TABLE H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-9,11-12=L, A0-A6 =Mode Address COMMAND MNEMONIC CKE n-1 CKE n /CS /RAS /CAS /WE BA0,1 A10 /AP A0-9, 11-12 Deselect DESEL H X H X X X X X X No Operation NOP H X L H H H X X X Row Address Entry & Bank Activate ACT H X L L H H V V V Single Bank Precharge PRE H X L L H L V L X Precharge All Banks PREA H X L L H L H X Column Address Entry & Write WRITE H X L H L L V L V Column Address Entry & Write with Auto-Precharge WRITEA H X L H L L V H V Column Address Entry & Read READ H X L H L H V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V H V Auto-Refresh REFA H H L L L H X X X Self-Refresh Entry REFS H L L L L H X X X Self-Refresh Exit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TBST H X L H H L X X X Mode Register Set MRS H X L L L L L L V X note

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE Address Command Action IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT Bank Active, Latch RA L L H L BA, A10 PRE / PREA NOP*4 L L L H X REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ROW ACTIVE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST NOP L H L H BA, CA, A10 READ / READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto- Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action WRITE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST Terminate Burst L H L H BA, CA, A10 READ / READA Terminate Burst, Latch CA, Begin Read, Determine Auto- Precharge*3 L H L L BA, CA, A10 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine Auto- Precharge*3 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL for same Bank *6 L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL for same Bank *6 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ / READA ILLEGAL for same Bank *7 L H L L BA, CA, A10 WRITE / WRITEA ILLEGAL for same Bank *7 L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action PRE – CHARGING H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA NOP*4 (Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RE- COVERING H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ / WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action RE- FRESHING H X X X X DESEL NOP (Idle after tRFC) L H H H X NOP NOP (Idle after tRFC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ / WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to Read with Auto-Precharge in page 26 7. Refer to Write with Auto-Precharge in page 25 ILLEGAL = Device operation and/or data-integrity are not guaranteed.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Current State CKE n-1 CKE n /CS /RAS /CAS /WE Add Action SELF- REFRESH*1 H X X X X X X INVALID L H H X X X X Exit Self-Refresh (Idle after tRFC) L H L H H H X Exit Self-Refresh (Idle after tRFC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) POWER DOWN H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) ALL BANKS IDLE*2 H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down ANY STATE other than listed above H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend FUNCTION TRUTH TABLE for CKE ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously A minimum setup time must be satisfied before any command otherthan EXIT. 2. Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP TBST TBST PRE PRE SIMPLIFIED STATE DIAGRAM Automatic Sequence Command Sequence IDLE PRE CHARGE POWER DOWN READ READA WRITE WRITEA CKEL CKEH REFA MRS CKEL CKEH REFS CKEL CKEH WRITEA READA PRE SELF REFRESH AUTO REFRESH CLK SUSPEND WRITE SUSPEND READ SUSPEND READA SUSPEND WRITEA SUSPEND ROW ACTIVE ACT WRITE READ WRITE READ READA READAWRITEA WRITEA CKEL CKEH CKEL CKEH CKEL CKEH MODE REGISTER SET MRSPREAPOWER APPLIED PRE CHARGE ALL AUTO REFRESH REFA ( 2 or MORE ) REFSX POWER ON

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP POWER ON SEQUENCE MODE REGISTER R: Reserved for Future Use LATENCY MODE CL /CAS LATENCY 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 R R R R R R /CS /RAS /CAS /WE BA0,1 A12-A0 CLK V BURST LENGTH BL BT=0 BT=1 R R R Full Page R R R R BURST TYPE SEQUENTIAL INTERLEAVED 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 BA0 BA1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 SW 0 0 LTMODE BT BL Burst Write Single WriteSW Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP or DESEL condition at the inputs. 2. Maintain stable power, stable clock, and NOP or DESEL input conditions for a minimum of 100us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. Burst Length, Burst Type, /CAS Latency and Write Mode can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP A2 A1 A0 Initial Address BL Sequential Interleaved Column Addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 Command Address CLK DQ /CAS Latency Burst Length Burst Length Burst Type CL= 3 BL= 4 Read Y Write Y Q0 Q1 Q2 Q3 D0 D1 D2 D3

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ OPERATIONAL DESCRIPTION BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-12. Multiple banks can be active state concurrently by issuing multiple ACT commands. Minimum activation interval between one bank and another bank istRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. Minimum delay time of an ACT command after a PRE command to the same bank is tRP. READ A READ command can be issued to any active bank. The start address is specified by A0-9,11(x4), A0- 9 (x8), A0-8 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequenceof the burst data is defined by the Burst Type. Minimum delay time of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. Bank Activation and Precharge All (BL=4, CL=3) ACT READACT PRE ACT Xa Xb Yb Xa 1Xa Xb 0 00 01 01 00 Qb0 Qb1 Qb2 Qb3 tRRD tRCD tRP Xa Precharge All

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command DQ DQ CLK Command A0-9,11-12 A10 BA0-1 DQ CLK Command A0-9,11-12 A10 BA0-1 DQ ACT ACT Xa Xa Xa 00 00 Xa Read with Auto-Precharge (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qa3 internal precharge starts ACT ACT Auto-Precharge Timing (READ, BL=4) READ Qa0 Qa1 Qa2 Qa3 internal precharge starts Qa0 Qa1 Qa2 Qa3 CL=2 CL=3 ACT READACT PRE ACT Xa Xb Yb Xa 0Xa Xb 0 00 01 01 00 Qb0 Qb1 Qb2 Qb3 Xa Multi Bank Interleaving Read (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qa3 tRCD tRCD tRP tRCD tRPBL tRCD BL

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ CLK Command A0-9,11-12 A10 BA0-1 DQ WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-9,11(x4), A0-9 (x8), A0-8 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. Minimum delay time of a WRITE command after an ACT commandto the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the previous WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. ACT PRE ACT Xa Xa 0Xa 00 00 Xa Write (BL=4) Write Ya Da0 Da1 Da2 Da3 ACT ACT Xa Xa Xa 00 00 Xa Write with Auto-Precharge (BL=4) Write Ya Da0 Da1 Da2 Da3 internal precharge starts tRCD tRPBL tWR tRCD tRPBL tWR

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ DQM CLK Command A0-9,11-12 A10 BA0-1 DQ BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 2 cycle after WRITE assertion. READ Yb Qc0 Qc1 Qc2 Qc3 Read Interrupted by Read (CL=2, BL=4) READ Ya Qa0 Qa1 Qa2 Qb0 READ Yc ACT Xa Xa Read Interrupted by Write (CL=2, BL=4) READ Ya Qa0 Da0 Da1 Da2 Write Ya Da3 Output disable by DQM by WRITE

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command DQ Command DQ Command DQ Command DQ Command DQ Command DQ CL=2 CL=3 [ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read Interrupted by Precharge (BL=4) PREREAD Q0 Q1 Q2 PREREAD Q0 Q1 PREREAD PREREAD Q0 Q1 Q2 PREREAD Q0 Q1 PREREAD

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command DQ Command DQ Command DQ Command DQ Command DQ Command DQ CL=2 CL=3 [ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. TBSTREAD Q0 Q1 Q2 TBSTREAD Q0 Q1 TBSTREAD TBSTREAD Q0 Q1 Q2 TBSTREAD Q0 Q1 TBSTREAD Read Interrupted by Burst Terminate (BL=4)

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ CLK Command A0-9,11-12 A10 BA0-1 DQ [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. [ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ atthe interrupting READ cycle is "Don't Care". Write Interrupted by Write (BL=4) Write Yb Dc0 Dc1 Dc2 Dc3 Write Ya Da0 Da1 Da2 Db0 Write Yc ACT Xa Xa Write Interrupted by Read (CL=2, BL=4) READ Yb Da0 Da1 Qb0 Write Ya Qb1 Qb2 Qb3 don't care

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ CLK Command A0-9,11-12 A10 BA0-1 DQ DQM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM. [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST intervalis minimum 1 CLK. Write Ya Write Interrupted by Precharge (BL=4) ACT Xa Da0 Da1 PRE ACT Xa Write Ya Write Interrupted by Burst Terminate (BL=4) ACT Xa Da0 Da1 TBST Write Yb Db0 Db1 Db2 Db3 tWR tRP

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ CLK Command A0-9,11-12 A10 BA0-1 DQ [ Write with Auto-Precharge Interrupted by Write / Read to Different Bank ] Burst write with auto-precharge can be interrupted by write or read to different bank. Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA Interrupted by WRITE to Different Bank (BL=4) Db0 Db1 Db2 Db3 Write Ya Da0 Da1 Write Yb ACT Xa Xa interruptedauto-precharge activate WRITEA Interrupted by READ to Different Bank (CL=2, BL=4) Write Ya Da0 Da1 Read Yb ACT Xa Xa interruptedauto-precharge activate Qb0 Qb1 Qb2 Qb3 BL tWR tRP BL tWR tRP precharge precharge

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK Command A0-9,11-12 A10 BA0-1 DQ [ Read with Auto-Precharge Interrupted by Read to Different Bank ] Burst read with auto-precharge can be interrupted by read to different bank. Next ACT command can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA Interrupted by READ to Different Bank (CL=2, BL=4) Read Ya Qa0 Qa1 Read Yb ACT Xa Xa interruptedauto-precharge activate Qb0 Qb1 Qb2 Qb3 Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read / write is repeated until a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read / write with auto-precharge command is illegal. Single Write When single write mode is set, burst length for write is alwaysone, independently of Burst Length defined by (A2-0). BL tRP precharge

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Auto-Refresh CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 Auto Refresh on All Banks Auto Refresh on All Banks NOP or DESELECT minimum tRFC AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE=H) command. The refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto- refresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command.

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Self-Refresh CLK /CS /RAS /CAS /WE CKE A0-12 BA0-1 SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputsincluding CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self Refresh Entry Self Refresh Exit X minimum tRFC for recovery new command Stable CLK NOP

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP DQ Suspend by CKE CLK Command DQ CKE Power Down by CKE CLK Command CKE Command CKE CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose ofCLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. PRE NOP NOP NOP NOP NOP NOPACT Write Read D0 D1 D3 Q0 Q1 Q2 Q3 ext.CLK CKE int.CLK tIH tIS tIH tIS Standby Power Down Active Power Down

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP DQM Function CLK Command DQ DQMU/L DQM CONTROL DQMU/L is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to Data In latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. masked by DQMU/L=H disabled by DQMU/L=H Write Read D0 D2 D3 Q0 Q1 Q3

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (Ta=0 ~ 70'C, unless otherwise noted) CAPACITANCE (Ta=0 ~ 70'C, Vdd = VddQ = 3.3+0.3V, Vss = VssQ = 0V, unless otherwise noted) 'C-65~ 150Storage TemperatureTstg 'C0~ 70Operating TemperatureTopr mW1000Ta=25'CPower DissipationPd mA50Output CurrentIO V-0.5 ~ Vdd+0.5with respect to VssQOutput VoltageVO V-0.5 ~ Vdd+0.5with respect to VssInput VoltageVI V-0.5 ~ 4.6with respect to VssQSupply Voltage for OutputVddQ V-0.5 ~ 4.6with respect to VssSupply VoltageVdd UnitRatingsConditionsParameterSymbol V0.8-0.3Low-Level Input Voltage all inputsVIL VVdd+0.32.0High-Level Input Voltage all inputsVIH V000Supply Voltage for OutputVssQ V3.63.33.0Supply Voltage for OutputVddQ V000Supply VoltageVss V3.63.33.0Supply VoltageVdd Max.Typ.Min. Unit Limits ParameterSymbol pF6.54.0CI/O pF3.52.5 Input Capacitance,I/O pin Input Capacitance,CLK pinCI(K) pF3.82.5Input Capacitance,control pinCI(C) pF3.82.5 VI=1.4V f=1MHz VI=25mVrms Input Capacitance,address pinCI(A) Max.Min. Unit Limits Test ConditionParameterSymbol

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70'C, Vdd = VddQ = 3.3+0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted) Notes 1. addresses are changed 3 times during tRC, only 1 bank is active & all other banks are idle 2. all banks are idle 3. input signals are changed one time during 3xtCLK 4. input signals are stable 5. all banks are active 6. Low Power Version(-5L/-6L/-7L) 7. Ultra Low Power Version(-5UL/-6UL/-7UL) AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 + 0.3V, Vss = VssQ = 0V, unless otherwise noted) Symbol Parameter Test Conditions Limits Min. Max. Unit VOH(DC) VOL(DC) IOZ IL High-Level Output Voltage (DC) Low-Level Output Voltage (DC) Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating Vo=0 ~ VddQ VIH=0 ~ VddQ+0.3V, other input pins=0V 2.4 0.4 V V uA uA -10 -10 150 110 mA-5 / -6 / -7 CKE<0.2vSelf-Refresh CurrentIcc6 100 100 x16 x16 Organi- zation 4,5 3,5 2,4 2,3 mA mA mA mA mA mA mA mA mA 140 170 tCLK=min, tRFC=minAuto-Refresh CurrentIcc5 tCLK=min, BL=4, gapless data Burst Operating CurrentIcc4 tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS> VIHmin Active Standby Current in Normal ModeIcc3NS Icc3N tCLK=L, CKE>VIHmin tCLK=min, CKE>VIHmin, /CS>VIHminIdle Standby Current in Normal Mode Icc2NS Icc2N tCLK=L, CKE<VILmax tCLK=min, CKE<VILmax Icc2PS Icc2P Idle Standby Current in Power Down Mode tCLK=min, tRC=min, BL=1Operating Current (1bank)Icc1 NoteUnit -7-5 Limits(max) Test ConditionsParameterSymbol 2 mA-5L / -6L / -7L 6 1 mA-5UL / -6UL / -7UL 7

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP AC TIMING REQUIREMENTS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3+0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V AC timing is referenced to the input signal crossing through 1.4V. 120000 7.8 0.8 1.5 101 2.5 2.5 7.5 7.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us7.87.8 1010 2015 2015 2020 2020 1200005012000045 8075 7067.5 0.8 1.5 101101 2.5 2.5 7.5 Average Refresh Interval Mode Register Set Cycle time ACT to ACT Delay time Write Recovery time Row Precharge time Row Active time Row to Column Delay Refresh Cycle time Row Cycle time Input Hold time (all inputs) Input Setup time (all inputs) Transition time of CLK CLK Low pulse width CLK High pulse width tREF tRSC tRRD tWR tRP tRAS tRCD tRFC tRC tIH tIS tT tCL tCH CL=3 CL=2 CLK cycle timetCLK NoteUnit -7-6 Limits ParameterSymbol CLK Signal 1.4V 1.4V

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP SWITCHING CHARACTERISTICS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3+0.3V, Vss = VssQ = 0V, unless otherwise noted) Output Load Condition Note. If tr (CLK rising time) is > 1ns, (tr/2 - 0.5ns) should be added to the parameters. 50pF Vout tOLZ tAC tOH tOHZ CLK DQ 1.4V 1.4V ns635.435.43CL=3 CL=2 5.43 5.4 5.4 ns ns ns ns ns ns 6363 5.4 CL=3 CL=2 CL=3 CL=2 Delay Time, Output High impedance from CLK Delay Time, Output Low impedance from CLK Output Hold Time from CLK Access Time from CLK tOHZ tOLZ tOH tAC MaxMin.MaxMin.MaxMin. -7-6 Unit Limits ParameterSymbol

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Burst Write (Single Bank) [BL=4] Italic parameter shows minimum case ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0 PRE#0 tRC tRAS tRP tRCD tRCD tWR tWR 0 00 0 0 0 D0 D0 D0 D0 D0 D0 D0 D0 X Y X Y X X X X

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Burst Write (Multi Bank) [BL=4] ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0 PRE#0 tRC tRAS tRP tRCD tRCD tWR tWR tRC tRRD tRCD X Y X YX Y X X XX X X XX X 0 00 0 0 01 1 1 D0 D0 D0 D0 D0 D0 D0 D0D1D1 D1 D1 ACT#1 WRITEA#1 (Auto-Precharge) ACT#1 Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Burst Read (Single Bank) [CL=2,BL=4] ACT#0 READ#0 PRE#0 ACT#0 READ#0 PRE#0 tRC tRAS tRP tRCD tRCD 0 00 0 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q0 Q0 X Y X Y X X X X tRAS Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Burst Read (Multi Bank) [CL=2,BL=4] ACT#0 READA#0 ACT#0 READ#0 PRE#0 tRC tRAS tRCD tRCD tRC tRRD tRCD X Y X YX Y X X XX X X XX X 0 00 0 01 1 1 Q0 Q0 Q0 Q0 Q0 Q0 Q0 Q0Q1Q1 Q1 Q1 ACT#1 READA#1 ACT#1 Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Write Interrupted by Write [BL=4] ACT#0 WRITE#0 WRITE#0 interrupt same bank PRE#0 tRRD tRCD tWR X Y XYX Y Y X XX X X X 0 0 0 0 11 1 0 D0 D0 D0 D0 D0 D0 D0 D0D0 D1 D1 D1 ACT#1ACT#1 WRITEA#1 interrupt other bank WRITE#0 interrupt other bank Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Read Interrupted by Read [CL=2,BL=4] ACT#0 READ#0 READ#1 interrupt other bank tRRD tRCD X Y XYX Y Y X XX X X X 0 0 1 0 11 1 Q0 Q0 Q0 Q1 Q0 Q0 Q0 Q0Q1 Q1 Q1 Q1 ACT#1ACT#1 READA#1 interrupt same bank READ#0 interrupt other bank tRCD Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Write Interrupted by Read, Read Interrupted by Write [CL=2,BL=4] Italic parameter shows minimum case ACT#0 READ#1WRITE#0 PRE#1 tRRD tRCD tWR X X YY Y X X 0 1 1 10 1 D0 D0 D1 D1 D1 D1Q1 Q1 ACT#1 WRITE#1 tRCD X X

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Write / Read Terminated by Precharge [CL=2,BL=4] ACT#0 WRITE#0 PRE#0 Terminate tRP tRCD X Y XYX X X X ACT#0 READ#0 tRCD tRC tRAS tRP tWR X XX 0 0 0 0 00 0 D0 D0 Q0 Q0 PRE#0 Terminate ACT#0 Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Write / Read Terminated by Burst Terminate [CL=2,BL=4] ACT#0 WRITE#0 READ#0 tRCD X Y YY X TBST WRITE#0 tWR X 0 0 0 0 0 PRE#0 D0 D0 Q0 Q0 D0 D0 D0 D0 TBST Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Single Write Burst Read [CL=2,BL=4] ACT#0 WRITE#0 tRCD X Y Y X READ#0 X 0 0 0 D0 Q0 Q0 Q0 Q0 Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Power-Up Sequence and Initialize Power On PRE ALL tRP REFA 100us tRFC tRFC tRSC XMA NOP REFA REFA MRS ACT#0 Minimum 2 REFA cycles Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Auto Refresh ACT#0 WRITE#0 tRP X Y X REFA X 0 0 D0 D0 D0 D0 tRFC tRCD PRE ALL All banks must be idle before REFA is issued. Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Self Refresh ACT#0PRE ALL X X X Self Refresh Entry Self Refresh Exit All banks must be idle before REFS is issued. tRP tRFC Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ CLK Suspension [CL=2, BL=4] ACT#0 WRITE#0 tRCD X Y Y X READ#0 X 0 0 0 D0 D0 Q0 Q0D0 D0 Q0 Q0Q0 Internal CLK suspended Internal CLK suspended Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE CKE DQM A0-9,11 A10 A12 BA0,1 DQ Power Down ACT#0PRE ALL Standby Power Down X X X Active Power Down Italic parameter shows minimum case

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Keep safety first in your circuit designs! 1. These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2. Mitsubishi Electric Corporation assumes no responsibility forany damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to informationpublished by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Mitsubishi Electric Corporationis necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japaneseexport control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. Notes regarding these materials

Apr. '02 MITSUBISHI LSIs SDRAM (Rev.1.31) Single Data Rate M2V56S20/ 30/ 40 AKT 256M Synchronous DRAM M2V56S20/ 30/ 40 ATP

Revision History

-Add Ultra Low Power Version for the self-refresh current ICC6 : 1mAApr. / ‘021.31 -Unify *ATP’s spec. with *AKT’s spec. (Add *AKT spec to *ATP spec.) -Change -5 spec. tCLK=6ns to 7.5ns @ CL=3 tRAS=42ns to 45ns tWR=12ns to 15ns tRRD=12ns to 15ns -Modify Average Supply Current from Vdd ICC1 X4 Limits (from 110 / 90 / 80mA to 90 / 80 / 75mA) ICC1 X8 Limits (from 115 / 95 / 85mA to 95 / 85 / 80mA) ICC1 X16 Limits (from 120 / 100 / 90mA to 100 / 90 / 85mA) ICC2P Limits (from 2 / 1.5 / 1mA to 1 / 1mA) ICC2N Limits (from 30 / 25 / 20mA to 12 / 10mA) ICC2NS Limits (from 6 / 6 / 6mA to 3 / 3mA) ICC3N Limits (from 35 / 30 / 25mA to 20 / 15mA) ICC3NS Limits (from 15 / 15 / 15mA to 10 / 10mA) ICC4 X4 Limits (from 140 / 110 / 90mA to 80 / 70mA) ICC4 X8 Limits (from 140 / 110 / 90mA to 90 / 80mA) ICC4 X16 Limits (from 150 / 120 / 100mA to 110 / 100mA) ICC5 Limits (from 220 / 180 / 170mA to 170 / 150 / 140mA) -Change Truth Table (Read & Write with Auto-Precharge) -Change AC timing Requirements tRFC of -5 from 60ns to 66ns -Change AC timing Requirements tRSC of (-5/-6/-7) from (12ns/15ns/20ns) to (10ns/10ns/10ns) -Change Simplified state Diagram (Add Power On Sequence) -Change Page15 (Power On Sequence) Dec. / ‘011.22 -Add -5L/-6L/-7L spec. for M2V56S20ATP/30ATP/40ATPAug. / ‘011.1 -1st editionJuly / ‘011.0 DescriptionDataRev.