Power Management

LTM4645

Linear Technology

Dual 10A or Single 20A 關Module Regulator

Manufacturer: Linear Technology

Document: 34 Pages / 533Kb

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For more information www.linear.com/LTM4646 TYPICAL APPLICATION FEATURES DESCRIPTION Dual 10A or Single 20A µModule Regulator

APPLICATIONS

The LT M®4646 is a complete dual 10A output switching mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductors, and all supporting components. Operating from an input voltage range of 4.5V to 20V, the LTM4646 supports two outputs each with an output voltage range of 0.6V to 5.5V, set by external resistors. Its high efficiency design delivers up to 10A continuous current for each output. Only a few input and output capacitors are needed. The device supports frequency synchronization, multiphase operation, high efficiency light load operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode per channel for device tempera- ture monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcur- rent protection. The power module is offered in a small footprint 11.25mm × 15mm × 5.01mm BGA package. The LTM4646 is available with SnPb or RoHS compliant terminal finish. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. nDual 10A or Single 20A Output nWide Input Voltage Range: 4.5V to 20V n2.375VMIN with CPWR Bias nOutput Voltage Range: 0.6V to 5.5V n±1.5% Maximum Total DC Output Error nMultiphase Current Sharing nDifferential Remote Sense Amplifier , Each Channel nCurrent Mode Control/Fast T ransient Response nUp to 96% Efficiency nAdjustable Switching Frequency (250kHz to 1.3MHz) nFrequency Synchronization nOvercurrent Foldback Protection nOutput Overvoltage Protection nInternal or External Compensation nBuilt-In Temperature Monitoring Diode nSnPb or RoHS Compliant Finish n11.25mm × 15mm × 5.01mm BGA Package nPoint-of-Load Power Supplies nTelecom and Networking Equipment nIndustrial Equipment nMedical Equipment Click to view associated TechClip Videos. Efficiency, 12V to 0.9V, 1.2V at 10A Each RUN1 RUN2 VOUT1 VOUTS1 VIN1 VIN2 CPWR DRVCC INTVCC VFB1 VRNG VOUTS1– COMP1A COMP1B TRACK/SS1 VOUT2 VOUTS2 VFB2 VOUTS2– COMP2A COMP2B TRACK/SS2 MODE_PLLIN L TM4646

4646 TA01a

100µF 115k VOUT2 1.2V AT 10A 60.4k 30.1k 0.1µF PINS NOT USED IN THIS CIRCUIT : PGOOD1, PGOOD2, EXTV CC, TEMP1+, TEMP1–, TEMP2+, TEMP2– PHASMD, CLKOUT , SW1, SW2 0.1µF 4.7µF SGNDFREQ GND 121k100/uni03BCF 10/uni03BCF VIN 4.5V TO 20V VOUT1 0.9V AT 10A 130k OUTPUT CURRENT (A) 1 2 3 4 5 6 7 8 9 10 95EFFICIENCY (%)

4646 TA01b

12VIN TO 1.2V EFF, 500kHz 12VIN TO 0.9V EFF, 400kHz

For more information www.linear.com/LTM4646 PGOOD1, PGOOD2, RUN1, RUN2, DRVCC, INTVCC, EXTVCC, VOUT1, VOUT2, VOUTS1, FREQ, VRNG, PHASMD, Internal Operating Temperature Peak Solder Reflow Package Body Temperature ....245°C PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS (Note 1) ORDER INFORMATION A B C D E F G H J K L 2 3 4 5 TOP VIEW BGA PACKAGE 88-LEAD (15mm = 11.25mm = 5..01mm) 6 7 8 VIN1 SW1 RUN1 SW2 VOUT1 TEMP1– TEMP1+ TEMP2– TEMP2+ VOUTS1– VOUTS1 PHASMD SGND TRACK/SS1 PGOOD1 DRVCCVFB1COMP1B COMP1A FREQ CPWRINTVCCTRACK/SS2 MODE_ PLLIN CLKOUT EXTVCCPGOOD2VFB2VOUTS2 COMP2ACOMP2B VRNG RUN2SGND VOUTS2– VOUT2 VIN2 GND GND GND GND TJMAX = 125°C, eJCtop = 12.6°C/W , eJCbottom = 1.8°C/W , eJB = 2.3°C/W , eJA = 9.6°C/W e VALUES DEFINED PER JESD51-12 WEIGHT = 2.1g PART NUMBER BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4646EY#PBF SAC305 (RoHS) LTM4646Y BGA 3 –40°C to 125°CLTM4646IY#PBF LTM4646Y LTM4646IY SnPb (63/37) LTM4646Y e0

Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Ball finish code is per IPC/JEDEC J-STD-609.
Terminal Finish Part Marking: www.linear .com/leadfree
Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear .com/umodule/pcbassembly
BGA Package and T ray Drawings: www.linear .com/packaging http://www.linear .com/product/LTM4646#orderinfo

For more information www.linear.com/LTM4646 ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 18. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage 2.375V with 5V External Bias on CPWR, 4.5V Min without Bias l 2.375 20 V VCPWR(DC) Input Control Power Voltage Input Range of Bias Normally Connected to VIN 4.5 20 V VOUT1, 2 (Range) Output Voltage Range (Note 8) l 0.6 5.5 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load C IN = 10µF =4, COUT = 100µF =4, Ceramic VOUT = 1.5V l 1.4775 1.5 1.5225 V Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.2 1.3 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 160 mV RRUN1, RRUN2 RUN1, RUN2 Resistance Pull-Down Resistance 100 kΩ IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 10µF ×4, CSS = 0.01µF, COUT = 100µF ×4, VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V 1 A IQ(VIN) Input Supply Bias Current I OUT = 0.1A, fSW = 1MHz, Pulse-Skipping Mode IOUT = 0.1A, fSW = 1MHz, Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA µA I S(VIN) Input Supply Current VIN = 4.5V, VOUT = 1.5V, IOUT = 10A, fSW = 1MHz VIN = 12V, VOUT = 1.5V, IOUT = 10A, fSW = 1MHz 3.9 1.45 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Notes 7, 8) 0 10 A ∆VOUT1(LINE)/VOUT1 ∆VOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 20V IOUT = 0A for Each Output l 0.01 0.025 %/V ∆VOUT1(LOAD)/VOUT1 ∆VOUT2(LOAD)/VOUT2 Load Regulation Accuracy For Each Output, V OUT = 1.5V, 0A to 10A VIN = 12V (Note 7) l 0.15 0.3 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×4, VOUT = 1.5V, Frequency = 350kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V, VOUT = 1.5V, RFREQ = 115kΩ (Note 4) 350 kHz ∆VOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF ×4, VOUT = 1.5V, IOUT = 0A VIN = 12V, CSS = 0.01µF 10 mV tSTART (Each Channel) Turn-On Time COUT = 100µF ×4, No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 ms ∆VOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0A to 6A to 0A COUT = 100µF ×4 VIN = 12V, VOUT = 1.5V 50 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0A to 6A to 0A COUT = 100µF ×4 VIN = 12V, VOUT = 1.5V 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 20 A

For more information www.linear.com/LTM4646 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 18. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section VFB1 Voltage at VFB1 Pin IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.608 V VFB2 Voltage at VFB2 Pin IOUT = 0A, VOUT = 1.5V VFB2 is Gained Back Up by 2x Internal to 0.6V l 0.296 0.3 0.304 V IFB1, IFB2 (Note 6) 0 ±50 nA VOVL1, VOVL2 Feedback Overvoltage Lockout V FB1 Rising VFB2 Rising l l 0.630 0.315 0.645 0.323 0.660 0.330 V V I TRACK/SS1, ITRACK/SS2 T rack Pin Soft-Start Pull-Up Current TRACK/SS1,TRACK/SS2 = 0V 1.0 µA UVLO INTVCC Undervoltage Lockout INTV CC Falling VIN (Note 6) INTVCC Rising VIN (Note 6) 3.3 3.7 4.2 4.5 V V t OFF(MIN) Minimum Top Gate Off-Time (Note 6) 90 ns tON(MIN) Minimum Top Gate On-Time (Note 6) 30 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V –2 0 2 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –7.5 7.5 Internal Linear Regulator DRV CC Internal DRVCC Voltage 6V < CPWR < 20V 5.0 5.3 5.6 V DRVCC Load Regulation DRVCC Load Regulation ICC = 0mA to 100mA –1.3 –3.0 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.4 4.6 4.8 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 80 120 mV VEXTVCC(HYST) EXTVCC Hysteresis 200 mV Frequency and Clock Synchronization Frequency Nominal Nominal Frequency R FREQ = 115kΩ 300 350 400 kHz Frequency Low Lowest Frequency RFREQ = 165kΩ (Note 5) 250 kHz Frequency High Highest Frequency RFREQ = 29.4kΩ 1.17 1.3 1.43 MHz RMODE_PLLIN MODE_PLLIN Input Resistance MODE_PLLIN to SGND 600 k/uni03A9 Channel 2 Phase V OUT2 Phase Relative to VOUT1 PHASMD = SGND PHASMD = Float PHASMD = INTV CC 180 180 240 Deg Deg Deg CLKOUT Phase Phase (Relative to V OUT1) PHASMD = SGND PHASMD = Float PHASMD = INTV CC 120 Deg Deg Deg V PLLIN High VPLLIN Low Clock Input High Level to MODE_PLLIN Clock Input Low Level to MODE_PLLIN 0.5 V V

For more information www.linear.com/LTM4646 ELECTRICAL CHARACTERISTICSThe l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel. TA = 25°C, VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 18. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4646 is tested under pulsed load conditions such that T J ≈ TA. The LTM4646E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4646I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 250kHz to/uni00A01.3MHz. Note 5: LTM4646 device is optimized to operate from 300kHz to 750kHz. Note 6: These parameters are tested at wafer sort. Note 7: See output current derating curves for different V IN, VOUT and TA. Note 8: For 6V ≤ VIN ≤ 20V, the 3.3 to 5V output current needs to be limited to 9A/channel. All other input and output combinations are 10A/ channel with recommended switching frequency included in the efficiency graphs. Derating curves and airflow apply. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSYNC (Each Channel) Frequency SYNC Capture Range MODE_PLLIN Clock Duty Cycle = 50% 250 1300 kHz VRNG ILIMIT SET Current Limit Per Channel VRNG = INTVCC, IOUT to 10A, ILIMIT ~22A VRNG = SGND, IOUT to 5A, ILIMIT ~11A A A t D(PGOOD) Delay from VFB Fault (OV/UV) to PGOOD Falling (Note 6) 50 /uni03BCs tD(PGOOD) Delay from VFB Fault (OV/UV Clear) to PGOOD (Note 6) 20 /uni03BCs VTEMP1, VTEMP2 TEMP Diode Voltage ITEMP = 100µA 0.598 V TC VTEMP1,2 VTEMP Temperature Coefficient –2.0 mV/°C

For more information www.linear.com/LTM4646 TYPICAL PERFORMANCE CHARACTERISTICS 0.9V Single Phase Single Output Load T ransient Response 1V Single Phase Single Output Load T ransient Response 1.2V Single Phase Single Output Load T ransient Response 1.5V Single Phase Single Output Load T ransient Response 1.8V Single Phase Single Output Load T ransient Response Efficiency vs Output Current, V IN = 5V Efficiency vs Output Current, V IN = 8V Dual Phase Single Output Efficiency vs Output Current, V IN = 12V Efficiency vs Output Current, V IN = 12V 5.0VOUT, 1.3MHz 3.3VOUT, 1.1MHz 2.5VOUT, 850kHz 1.8VOUT, 700kHz 1.5VOUT, 600kHz 1.2VOUT, 500kHz 1.0VOUT, 400kHz 0.9VOUT, 400kHz OUTPUT CURRENT (A) 2 4 6 8 10 12 14 16 18 20 100EFFICIENCY (%)

4646 G04

EXTVCC = 5V 50µs/DIV IOUT 5A/DIV 0.9VOUT 33mV/DIV

4646 G05

COUT = 470µF POSCAP , 5mΩ, 100µF ×4, CERAMIC CCOMP = 100pF , f = 350kHz 50µs/DIV IOUT 5A/DIV 1VOUT 33mV/DIV

4646 G06

COUT = 470µF POSCAP , 5mΩ, 100µF ×4, CERAMIC C COMP = 100pF , f = 350kHz 50µs/DIV IOUT 5A/DIV 1.2VOUT 33mV/DIV

4646 G07

COUT = 470µF POSCAP , 5mΩ, 100µF ×4, CERAMIC C COMP = 100pF , f = 350kHz 50µs/DIV IOUT 5A/DIV 1.8VOUT 33mV/DIV

4646 G09

COUT = 100µF ×3, CERAMIC CCOMP = 100pF , CFF = 47pF f = 500kHz 50µs/DIV IOUT 5A/DIV 1.5VOUT 33mV/DIV

4646 G08

COUT = 100µF ×3, CERAMIC CCOMP = 100pF , CFF = 47pF f = 450kHz 50µs/DIV IOUT 5A/DIV 1.5VOUT 33mV/DIV COUT = 100µF ×3, CERAMIC CCOMP = 100pF , CFF = 47pF f = 450kHz OUTPUT CURRENT (A) 1 2 3 4 5 6 7 8 9 10 100EFFICIENCY (%)

4646 G01

3.3VOUT, 550kHz 2.5VOUT, 550kHz 1.8VOUT, 500kHz 1.5VOUT, 450kHz 1.2VOUT, 400kHz 1.0VOUT, 350kHz 0.9VOUT, 350kHz 5.0VOUT, 900kHz 3.3VOUT, 850kHz 2.5VOUT, 750kHz 1.8VOUT, 600kHz 1.5VOUT, 550kHz 1.2VOUT, 475kHz 1.0VOUT, 400kHz 0.9VOUT, 400kHz OUTPUT CURRENT (A) 1 2 3 4 5 6 7 8 9 10 100EFFICIENCY (%)

4646 G02

5.0VOUT, 1.3MHz 3.3VOUT, 1.1MHz 2.5VOUT, 850kHz 1.8VOUT, 700kHz 1.5VOUT, 600kHz 1.2VOUT, 500kHz 1.0VOUT, 400kHz 0.9VOUT, 400kHz OUTPUT CURRENT (A) 1 2 3 4 5 6 7 8 9 10 100EFFICIENCY (%)

4646 G03

For more information www.linear.com/LTM4646 TYPICAL PERFORMANCE CHARACTERISTICS T wo-Phase Switching and Ripple Short-Circuit Protection, No Load Short-Circuit Protection, 10A Load Single Phase Single Output Start-Up, No Load Single Phase Single Output Start-Up, 10A Load 50µs/DIV IOUT 5A/DIV 2.5VOUT 67mV/DIV

4646 G10

COUT = 100µF ×2, CERAMIC CCOMP = 100pF , CFF = 47pF f = 500kHz 50µs/DIV IOUT 3.3A/DIV 3.3VOUT 67mV/DIV

4646 G11

COUT = 100µF ×1, CERAMIC CCOMP = 100pF , CFF = 47pF f = 750kHz 50µs/DIV IOUT 3.3A/DIV 5VOUT 67mV/DIV

4646 G12

COUT = 100µF ×1, CERAMIC CCOMP = 100pF , CFF = 47pF f = 950kHz 50ms/DIV VOUT 0.5V/DIV IOUT 6.7A/DIV

4646 G13

12VIN, 1.5VOUT AT NO LOAD COUT = 470µF ×1, 2.5V , SANYO POSCAP , 100µF ×4, 6.3V , CERAMIC SOFT-START CAPACITOR = 0.1µF USE RUN PIN TO CONTROL START-UP 20ms/DIV 4646 G14 VOUT 0.5V/DIV IOUT 6.7A/DIV 12VIN, 1.5VOUT AT 10A LOAD COUT = 470µF ×1, 2.5V , SANYO POSCAP , 100µF ×4, 6.3V , CERAMIC SOFT-START CAPACITOR = 0.1µF USE RUN PIN TO CONTROL START-UP 1µs/DIV VOUT 5V/DIV VOUT 10mV/DIV

4646 G15

12V TO 1V AT 20A TWO-PHASE 12V TO 1V AT 350kHz RIPPLE AT 20A LOAD C OUT = 330/uni03BCF , 9mΩ, 100/uni03BCF ×4, CERAMIC 20ms/DIV VOUT 500mV/DIV IIN 1A/DIV

4646 G16

VIN = 12V VOUT = 1.5V IOUT = NO LOAD 20ms/DIV VOUT 500mV/DIV IIN 1A/DIV

4646 G17

VIN = 12V VOUT = 1.5V IOUT = 10A 2.5V Single Phase Single Output Load T ransient Response 3.3V Single Phase Single Output Load T ransient Response 5V Single Phase Single Output Load T ransient Response

For more information www.linear.com/LTM4646 PIN FUNCTIONS VOUT1 (H1, J1-J2, K1-K2, L1-L2): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. There is a 49.9Ω resistor connected between V OUT1 and VOUTS1 to protect the output from an open VOUTS1. Review Table/uni00A05. See Note 8 in the Electrical Characteristics section for output current guideline. GND (A3, A6-A7, B3, B6-B7, C3-C7, D6-D7, E6, E8, F5, F7, G6, G8, H6-H7, J4-J7, K3, K6-K7, L3, L6-L7 ): Power Ground Pins for Both Input and Output Returns. V OUT2 (A1-A2, B1-B2, C1-C2, D1): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. There is a 49.9Ω resistor connected between V OUT2 and VOUTS2 to protect the output from an open VOUTS2. Review Table/uni00A05. See Note 8 in the Electrical Characteristics section for output current guideline. VOUTS1, VOUTS2 (G2, E2): These pins are connected to the top of the internal top feedback resistor for each out- put. Each pin can be directly connected to its specific output, or connected to the remote sense point of V OUT. It is important to connect these pins to their designated outputs for proper regulation. In paralleling modules, the V OUTS1 pin is left floating, and the VFB1 pin is connected to INTVCC. This will disable chan- nel 1’s error amplifier and internally connect COMP1A to COMP2A. The PGOOD1 and TRACK/SS1 will be disabled in this mode. Channel 2’s error amplifier will regulate the two channel single output. See V FB pin description and Applications Information section. FREQ (F1): Frequency Set Pin. A resistor from this pin to SGND sets the operating frequency. The Equation: 41550 f(kHz) – 2.2 = R FREQ (kΩ) An external clock applied to MODE_PLLIN should be within ±30% of this programmed frequency to ensure frequency lock. See the Applications Information section. SGND (D3, H3): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single con - nection to the output capacitor GND in the application. See layout guidelines in Figure 17. VFB1 (G4): This pin is the + input to a unity gain differen- tial amplifier . This pin is connected to VOUTS1 with a 60.4k precision resistor internal. Different output voltages can be programmed with an additional resistor between VFB1 and VOUTS1– pins. The differential amplifier is feeding back the divided down output voltage from a remote sense divider network to compare to the internal 0.6V reference. In 2-phase single output operation, tie the V FB1 pin to INTV CC. See Figure/uni00A01 and Applications Information section for details. VFB2 (E4): This pin is the + input to a non-inverting gain of two amplifier utilizing three resistors in the feedback network to develop a remote sense divider network. This pin is connected to V OUTS2 with an internal 60.4k preci- sion resistor . The VOUT2 voltage is divided down to 0.3V then gained back up to 0.6V to compare with the internal 0.6V reference. This technique provides for equivalent remote sensing on VOUT2. See Figure 1 and Applications Information section for/uni00A0details. TRACK/SS1,TRACK/SS2 (H4, F2): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.0/uni03BCA pull-up current source. Each pin can be programmed with a soft- start ramp rate up to the 0.6V internal reference level, then beyond this point the internal 0.6V reference will control the feedback loop. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set the soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. (Recommended to use test points to monitor signal pin connections.) DRVCC (G7): Internal 5.3V regulator output used to source the power MOSFET drivers, and supply power to the INTVCC input. A 4.7µF ceramic capacitor is needed on this pin to GND. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

For more information www.linear.com/LTM4646 PIN FUNCTIONS CPWR (F8): Input Power to the Control IC, and Power to the DRVCC Regulator . This pin is connected to VIN for normal 4.5V to 20V operation. For lower voltage inputs below 4.5V, CPWR can be powered with an external 5V bias. See Application section. COMP1A, COMP2A (G3, E3): Current Control Threshold. These pins are the output of the error amplifier and the switching regulator’s compensation point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V. COMP1B, COMP2B (G1, E1): Internal Compensation Network .These pins are to be connected to their respected COMPA pins. When Utilizing specific external compensa- tion, then float these pins. MODE_PLLIN (F3): Operation Mode Selection or External Clock Synchronization Input. When this pin is tied to INTVCC, forced continuous mode operation is selected. Tying this pin to SGND allows discontinuous mode operation. When an external clock is applied at this pin, both channels operate in forced continuous mode and synchronize to the external clock. This pin has an internal 600k pull-down resistor to SGND. An external clock applied to MODE_PLLIN should be within ±30% of this programmed frequency to ensure frequency lock. CLKOUT (F4): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. Its output level swings between INTVCC and SGND. If clock input is present at the MODE_PLLIN pin, it will be synchronized to the input clock, with phase set by the PHASMD pin. If no clock is present at MODE_PLLIN, its frequency will be set by the FREQ pin. To synchronize other controllers, it can be connected to their MODE_PLLIN pins. See the Applications Information section. RUN1, RUN2 (H5, D5): Run Control Pins. A voltage above 1.3V will turn on each channel in the module. A voltage below 1.0V on the RUN pin will turn off the related channel. Each RUN pin has a 1.2/uni03BCA pull-up current, once the RUN pin reaches 1.2V an additional 4.5/uni03BCA pull-up current is added to this pin. A 100k resistor to ground is internal, and can be used with a pull-up resistor to VIN to turn on the module using the external and internal resistor to program under voltage lockout. Otherwise, an external enable signal or source can drive these pins directly below the 6V max. Enabling either RUN pin will turn on the DRV CC, and turn on the INTVCC path for operation. See Figure/uni00A01 and Applications section. PHASMD (H2 ): Connect this pin to SGND, INTV CC, or floating this pin to select the phase of CLKOUT and chan- nel 2. See Electrical Characteristics table and Application section. PGOOD1, PGOOD2 (G5, E5): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regula- tion point. See Applications section. INTVCC ( F6): Supply Input for Internal Circuitry (Not Including Gate Drivers). This bias is derived from DRVCC internally. EXTVCC (E7): External Power Input. When EXTVCC exceeds the switchover voltage (typically 4.6V), an internal switch connects this pin to DRVCC and shuts down the internal regulator so that INTV CC and gate drivers draw power from EXTVCC. The V IN pin still needs to be powered up but draws minimum current. TEMP1+,TEMP1– and TEMP2 +, TEM P2– ( L8, K8 and B8, A8): Onboard temperature diode for monitoring each channel with differential connections for noise immunity. VIN1 (K4-K5, L4-L5) and V IN2 (A4-A5, B4-B5): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capaci- tance directly between V IN pins and GND pins. VOUTS1– (J3): Differential Output Sense Amplifier (–) Input of channel 1. Connect this pin to the negative terminal of the output load capacitor of V OUT1. VOUTS2– ( D4): Differential Output Sense Amplifier (–) Input of channel 2. Connect this pin to the negative ter - minal of the output load capacitor of VOUT2. SW1 (H8, J8) and SW2 (C8, D8): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. VRNG (D2): Current Limit Adjustment Range. Tying this pin to INTV CC sets full 10A current, or tying to SGND will lower the current limit to 5A. Default to INTVCC. (Recommended to Use Test Points to Monitor Signal Pin Connections.)

Figure 1. Simplified LTM4646 Block Diagram

4646 F01

TA = 25°C. Use Figure 1 configuration. Figure 18. See Note 8 in the Electrical Characteristics sec- tion for output current guideline. constant frequency switching at steady load condition. Applications Information section. by disconnecting the internal compensation. age protect is feedback voltage referred. into a shutdown state, by turning off both MOSFETs. have remote sense capability. different levels. See the Applications Information section.

requirements for particular applications. down ratio that can be achieved for a given input voltage. The PWM controller has an internal 0.6V reference voltage. connects between the VOUTS1 to VFB1 and VOUTS2 to VFB2. protect the output if VOUTSn is open or left unconnected. (60.4k/uni00A0||/uni00A0RFB2) to equal the 0.3V reference. Table 1. VFB1, VFB2, Resistor Table vs Various Output/uni00A0Voltages

Tie the COMP2 pin to the COMP2 pin of the first/uni00A0module.
Tie the RUN2 pin to the RUN pins of the first module. Use 1/2 the value for R FB2 and RFB3.
Tie VOUTS2 of the additional channel to VOUTS2 of the first module then to remote sense point.
Tie the VFB2 pin to the VFB2 pin of the first module.
Tie the V OUTS2– pin to the V OUTS2– pin of the first/uni00A0module.
Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the first module. If both channels are needed for four phases, the addi - tional LTM4646 module should be tied the same way as the first as shown in Figure 2 to disable the second channel/uni00A01’s /uni00A0EA:
Tie the VFB1 pin to the module’s own INTVCC.

Figure 2. 2-Phase Parallel Configurations

Tie the COMP2 pin to the COMP2 pin of the first/uni00A0module.
Tie the RUN pins to the RUN pins of the first module.
Tie the VFB2 pin to the V FB2 pin of the first module. Use 1/2 the value for RFB2 and RFB3.
Tie the V OUTS2– pin to the V OUTS2– pin of the first/uni00A0module.
Tie V OUTS2 of both modules together then to the remote sense output.
Tie the TRACK/SS2 pin to the TRACK/SS2 pin of the first module. See Figure 20 for an example. Input Capacitors The LTM4646 module should be connected to a low AC impedance DC source. For the regulator input, four 10/uni03BCF input ceramic capacitors are used for RMS ripple current. A 47/uni03BCF to 100/uni03BCF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low imped - ance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: D VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) IOUT(MAX)
D • 1 <D( ) In the above equation, d% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated aluminum electrolytic capacitor , polymer capacitor . The LTM4646 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low RUN1 PGOOD1 SW1 V OUT1 VOUTS1 FREQ V IN1 VIN2 CPWR DRVCC INTVCC INTVCC EXTVCC PHASMD VFB1 VRNG VOUTS1– COMP1A COMP1B TRACK/SS1 RUN2 PGOOD2 SW2 V OUT2 VOUTS2 VFB2 VOUTS2– COMP2A COMP COMP2B TRACK/SS2 MODE_PLLIN TEMP1 + TEMP1– SGND GND TEMP2 + TEMP2– CLKOUT L TM4646

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For more information www.linear.com/LTM4646 APPLICATIONS INFORMATION ESR tantalum capacitor , low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 200/uni03BCF to 470/uni03BCF. Additional output filtering may be required by the system designer , if further reduction of output ripples or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7.5A//uni03BCs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and L TpowerCAD will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the num - ber of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. L TpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. Continuous and Discontinuous Mode Operation If the MODE_PLLIN pin is tied to INTV CC or an external clock is applied to MODE_PLLIN, the LTM4646 will be forced to operate in continuous mode. With load current less than one-half of the full load peak-to-peak ripple, the inductor current valley can drop to zero or become nega- tive. This allows constant-frequency operation but at the cost of low efficiency at light loads. If the MODE_PLLIN pin is left open or connected to sig - nal ground, the channel will transition into discontinu - ous mode operation, where a current reversal compara - tor shuts off the bottom MOSFET as the inductor current approaches zero, thus preventing negative inductor cur- rent and improving light-load efficiency. In this mode, both switches can remain off for extended periods of time. As the output capacitor discharges by load current and the output voltage droops lower , EA will eventually move the ITH voltage above the zero current level (0.8V) to initiate another switching cycle. Multiphase Operation For output loads that demand more than 10A of current, two outputs in LTM4646 or even multiple LTM4646s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripple. The MODE_PLLIN pin allows the LTM4646 to synchronize to an external clock (between 250kHz and 1.3MHz) and the internal phase-locked loop allows the LTM4646 to lock onto an incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTV CC, SGND, or floating the pin will select VOUT2 and CLKOUT phases relative to VOUT1. Up to of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4646 channel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input volt - age is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The LTM4646 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 19 shows an example of parallel operation and pin connection. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current can- cellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple cur - rent reduction as a function of the number of interleaved phases. Figure/uni00A04 shows this graph.

Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

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180 DEGREES0 DEGREES

90 DEGREES

270 DEGREES90 DEGREES

60 DEGREES 120 DEGREES

240 DEGREES60 DEGREES

300 DEGREES120 DEGREES

For more information www.linear.com/LTM4646 APPLICATIONS INFORMATION Frequency Selection and Phase-Locked Loop/uni00A0(MODE_ PLLIN and fSET Pins) The LTM4646 device is operated over a range of frequen- cies to improve power conversion efficiency . It is recom- mended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power MOSFET switching losses. Higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. The efficiency graphs will show an operat- ing frequency chosen for that condition An internal oscil- lator (clock generator) provides phase interleaved internal clock signals for individual channels to lock up to. The switching frequency and phase of each switching channel is independently controlled by adjusting the top MOSFET turn-on time (on-time) through the one-shot timer . This is achieved by sensing the phase relationship between a top MOSFET turn-on signal and its internal reference clock through a phase detector , and the time interval of the one-shot timer is adjusted on a cycle-by-cycle basis, so that the rising edge of the top MOSFET turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. The frequency of the internal oscillator can be pro - grammed from 250kHz to 1.3MHz by connecting a resis- tor , RT , from the FREQ pin to signal ground (SGND). The FREQ pin is regulated to 1.2V internally. The value of this resistor can be chosen according to the formula: RT(kΩ) = 41550 f(kHz) – 2.2 For applications with stringent frequency or interfer - ence requirements, an external clock source connected to the MODE_PLLIN pin can be used to synchronize the internal clock signals through a clock phase-locked loop (Clock/uni00A0PLL). The LTM4646 operates in forced continuous mode of operation when it is synchronized to the exter - nal clock. The external clock frequency has to be within ±30% of the internal oscillator frequency for successful synchronization. The clock input levels should be no less than 2V for “high” and no greater than 0.5V for “low”. The MODE_PLLIN pin has an internal 600k pull-down resistor . During dynamic transient conditions either in the line volt- age or load current (e.g., load step or release), the top switch will turn on more or less frequently in response to achieve faster transient response. This is the benefit of the LTM4646’s controlled on-time, valley current mode architecture. However , this process may understandably lose phase and even frequency lock momentarily. For relatively slow changes, phase and frequency lock can still be maintained. For large load current steps with fast slew rates, phase lock will be lost until the system returns back to a steady-state condition . It may take up to several hundred microseconds to fully resume the phase lock, but the frequency lock generally recovers quickly, long before phase lock does. Minimum On-Time and Minimum Off-Time Minimum on-time tON is the smallest time duration that the LTM4646 is capable of turning on the top MOSFET on either channel. It is determined by internal timing delays, and the gate charge required to turn on the top MOSFET . The LTM4646 has a minimum on time of ~30ns, and far lower than what would be a concern based on the maxi- mum operating frequency of 1.3MHz . The below equation can be checked against the VIN , VOUT, and (FREQ) frequency of operation to insure the minimum on time tON(MIN) is above 30ns. VOUT VIN • FREQ tON(MIN) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the output ripple will increase. The on-time can be increased by lowering the switching frequency. The below equation can be checked against the V IN , V OUT , and (FREQ) frequency of operation to insure the minimum off time tOFF(MIN) is above 90ns. VOUT(MAX) VIN(MAX) DMAX DMAX 1 – FREQ • tOFF(MIN)

For more information www.linear.com/LTM4646 APPLICATIONS INFORMATION Output Voltage Soft Starting and T racking Output voltage tracking can be programmed externally using the TRACK/SS pins. The output can be tracked up and down with another regulator . The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider for to implement coincident tracking. The LTM4646 uses an accurate 60.4k resistor internally for the top feedback resistor for each channel. Figure 5 shows an example of coincident tracking. SLAVE 1 60.4k RFB ´• VTRACK VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Voltage tracking is disabled when V TRACK/SS is more than 0.6V. RTB/uni00A0in Figure 5 will be equal to the RFB for coincident track- ing. Figure 6 shows the coincident tracking waveforms. The TRACK/SS pins can be controlled by a capacitor placed on the regulator TRACK/SS pin to ground. A 1.0/uni03BCA current source will charge the TRACK/SS pin up to the voltage reference and then proceed up to INTVCC. After the 0.6V ramp, the TRACK/SS pin will no longer be in control, and the internal voltage reference will control output regu- lation from the feedback divider . Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK/SS pins are pulled low when the RUN pin is below 1.2V. The total soft-start time can be calculated as: tSOFT-START CSS 1.0µA ²²² ´´´ • 0.6V Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the mas - ter’s TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0 to 0.6V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in volts per second. The equation: MR SR

60.4k RTA where MR is the master’ s output slew rate and SR is the slave’s output slew rate in volts per second. When coincident tracking is desired, then MR and SR are equal, thus RTA is equal to 60.4k. RTB is derived from equation: RTB 0.6V VFB 60.4k VFB RFB < VTRACK RTA where VFB is the feedback voltage reference of the regula- tor , and VTRACK/SS is 0.6V. Since RTA is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TB is equal to RFB with VFB = VTRACK/SS. In ratiometric tracking, a different slew rate may be desired for the slave regulator . RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 20V/s, and SR = 15V/s. Then R TA = 80.6k. Solve for RTB to equal to 80.6k. Each of the TRACK/SS pins will have the 1.0/uni03BCA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an off- set on the TRACK/SS pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK/SS pin offset to a negligible value. Power Good Each PGOOD pin is connected to an internal open-drain N-channel MOSFET . An external resistor or current source can be used to pull this pin up to 6V (e.g., V OUT1,2 or DRVCC). Overvoltage or undervoltage comparators (OV , UV) turn on the MOSFET and pull the PGOOD pin low when the feedback voltage is outside the ±7.5% window of the reference voltage. The PGOOD pin is also pulled low when the channel’s RUN pin is below the 1.2V threshold

Figure 6. Output Coincident T racking Waveform Figure 5. Example of Output T racking Application Circuit

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For more information www.linear.com/LTM4646 APPLICATIONS INFORMATION (hysteresis applies), or in undervoltage lockout (UVLO). In an overvoltage (OV) condition, MT is turned off and MB is turned on immediately without delay and held on until the overvoltage condition clears. This happens regardless of any other condition as long as the RUN pin is enabled. For example, upon enabling the RUN1 pin, if VOUT is prebi- ased at more than 7.5% above the programmed regulated voltage, the OV stays triggered and BG forced on until VOUT is pulled a ~ 2.5% hysteresis below the 7.5% OV threshold. Stability Compensation The module has already been internally compensated for all output voltages. Table 5 is provided for most applica- tion requirements. L TpowerCAD will be provided for other control loop optimization. Use L TpowerCAD when tying output in parallel for higher current. External compensa- tion may be necessary. Run Enable The RUN pins have an enable threshold of 1.3V maximum, typically 1.2V with 100mV of hysteresis. They control the turn on each of the channels and DRV CC and INTVCC. A 100k resistor to ground is internal, and can be used with a pull-up resistor to V IN to turn on the module using the external and internal resistor to program under voltage lock out. Otherwise an external enable signal or source can drive these pins directly below the 6V max. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Application circuits in Figure 21. DRVCC, INTVCC, and EXTVCC The LTM4646 module has an internal 5.3V low dropout regulator (DRVCC) that is derived from the input voltage through the CPWR (control power) pin. This regulator is used to power the INTV CC control circuitry and the power MOSFET drivers. This regulator can source up to 100mA, and typically uses ~50mA for powering the device at the maximum frequency. This internal 5.3V supply is enabled by either RUN1 or RUN2. EXTVCC allows an external 5V supply to power the LTM4646 and reduce power dissipation from the internal low dropout 5V regulator . The power loss savings can be calculated by: (CPWR – 5V) • 50mA = P LOSS EXTVCC has a threshold of 4.6V for activation, and a maxi- mum rating of 6V. When using a 5V input, connect this 5V input to EXTV CC also to maintain a 5V gate drive level. EXTVCC must sequence on after CPWR, and EXTVCC must sequence off before CPWR. CPWR (Control Power) The LTM4646 module has a CPWR pin that is biased with a supply voltage minimum of 4.5V, and up to V IN maxi- mum in normal operation. When operating at lower input voltages below the 4.5V minimum, this pin can biased with an alternate source to power the controller section while operating down to the 2.375V minimum. For example, if 3.3V is supplied to VIN, and a 5V bias with a 50mA capability was used to source the CPWR pin, then 3.3V input power conversion can be implemented. Even though the CPWR can operate from 4.5V to 20V, a lower bias will lower the power loss if the module. See Figure/uni00A021 for an example. Output Remote Sense The LTM4646’s differential output sensing schemes are distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistor divider and fed into the error amplifier input. This conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. The LTM4646 allows for seamless differential output sensing by sensing the resistively divided feedback volt- age differentially. This allows for differential sensing in the full output range from 0.6V to 5.5V. Channel 1’s difference amplifier (DIFFAMP) has a bandwidth of around 8MHz, and channel 2’s feedback amplifier has a bandwidth of around 4MHz, both high enough so as to not affect main loop compensation and transient behavior .

For more information www.linear.com/LTM4646 APPLICATIONS INFORMATION The LTM4646 differential output sensing can correct for up to ±300mV of common-mode deviation in the output’s power and ground lines on channel 1, and ±200mV on channel 2. To avoid noise coupling into the feedback voltages, the resistor dividers should be placed close to the VOUTS1 and VOUTS1–, or VOUTS2 and VOUTS2– pins. Remote output and ground traces should be routed together as a differential pair to the remote output. For best accuracy, these traces to the remote output and ground should be connected as close as possible to the desired regulation point. Review the parallel schematics in Figure 20. OUTPUT CURRENT RANGE PIN (VRNG) Tying the VRNG pin to SGND will set the output current to 5A, and ~9A current limit. Tying the VRNG pin to INTV CC will set the output current to 10A, and ~20A current limit. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET inter- connect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high fre - quency scope probe. The ring frequency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Temperature Monitoring (TEMP1 and TEMP2) A diode connected PNP transistor is used for tempera - ture monitoring. Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: ID IS • e VD d• VT or VD d• VT • lnID IS where ID is the diode current, V D is the diode voltage, d is the ideality factor (typically close to 1.0) and I S (satu- ration current) is a process dependent parameter . VT can be broken out to: VT k • T q where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable tem- perature sensors. The IS term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The I S term varies from process to process, varies with temperature, and by definition must always be less than I D. Combining all of the constants into one term: KD d• k q where K D = 8.62 – 5, and knowing ln(I D/IS) is always positive because I D is always greater than I S, leaves us with the equation that:

Figure 7. Diode Voltage VD vs Temperature T(°C) are at a 10:1 ratio. See LTC2997 data sheet. /uni03BCModule® package mounted to a hardware test board.

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remove the IS dependency from the following equation. two currents I1, and I2, where I1 = 10 • I2.

eJA, the thermal resistance from junction to ambient,

mounted to a 95mm × 76mm PCB with four layers.

eJCbottom, the thermal resistance from junction to the

the heat flows from the junction to the top of the part. generally match the user’s application.

eJB, the thermal resistance from junction to the

resistances are external to the /uni03BCModule package. Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

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For more information www.linear.com/LTM4646 for eJCtop and eJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4646, be aware there are multiple power devices and components dissipating power , with a con- sequence that the thermal resistances relative to differ - ent junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity— but also, not ignoring practical realities— an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA soft - ware is used to accurately build the mechanical geometry of the LTM4646 and the specified PCB with all of the cor- rect material coefficients along with accurate power loss source definitions; (2) this model simulates a software- defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4646 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory tests have been performed, then the e JB and eBA are summed together to correlate quite well with the LTM4646 model with no airflow or heat sinking in a define chamber . This eJB + eBA value should accurately equal the eJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. The LTM4646 has been designed to effectively remove heat from both the top and bottom of the package. The APPLICATIONS INFORMATION bottom substrate material has very low thermal resistance to the printed circuit board. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. Safety Considerations The LTM4646 modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large cur - rents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET . This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The device does support over current protection. Temperature diodes are provided for monitoring inter - nal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. Power Derating The 5V, 8V and 12V power loss curves in Figures 9 through 11 can be used in coordination with the load current derating curves in Figures 12 to 16 for calculating an approximate eJA thermal resistance for the LTM4646 with airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125°C. These factors come from the fact that the power loss of the regulator increases about 45% from 25°C to 150°C , thus a 50% spread

For more information www.linear.com/LTM4646 over 125°C delta equates to ~0.35%/°C loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multi- plied by 0.35%/°C equals a 35% power loss increase at the 125°C junction, thus the 1.35 multiplier . The derating curves are plotted with V OUT1 and VOUT2 in parallel single output operation starting at 20A of load with low ambient temperature. The output voltages are 1V, 2.5V and 5V. These are chosen to include the lower and higher output voltage ranges for correlating the ther- mal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~ 120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much tem- perature rise can be allowed. As an example in Figure 13, the load current is derated to ~14.5A at ~95°C with no air or heat sink and the power loss for the 12V to 1.0V at 14.5A output is a ~ 3.04W loss. The ~ 3.04W loss is calculated with the ~2.25W room temperature loss from the 12V to 1.0V power loss curve at 14.5A, and the 1.35 multiplying factor at 125°C ambient. If the 95°C ambient temperature is subtracted from the 125°C junction tem - perature, then the difference of 30°C divided by 3.04W equals a 9.9°C/W e JA thermal resistance. Table 2 speci- fies a 10.1°C/W value which is pretty close. The airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. As an example in Figure 13, the load current is derated to ~16.5A at ~95°C with 200LFM of airflow and the power loss for the 12V to 1.0V at 16.5A output is a 3.7W loss. The 3.7W loss is calculated with the ~2.75W room tem - perature loss from the 12V to 1.0V power loss curve at 16.5A, and the 1.35 multiplying factor at 125°C ambient. If the 95°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of 30°C divided by 3.7W equals a 8.1°C/W eJA thermal resistance. Table 2 specifies a 8.1°C/W value which is pretty close. Tables 2 through 4 provide equivalent thermal resistances for 1V, 2.5V and 5V outputs with and without airflow. The derived thermal resistances in Tables 2 through 4 for the various conditions can be multiplied by the calcu- lated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the power loss curves and adjusted with APPLICATIONS INFORMATION

Table 2. 1.0V Output Table 3. 2.5V Output Table 5. Capacitor Matrix (All Parameters Are Typical and Dependent on Board Layout) **Bulk capacitance is optional if VIN has very low input impedance. Table 4. 5V Output (EXTVCC electrically connected to 5VOUT)

Figure 9. 5VIN Power Loss Curve Figure 10. 8VIN Power Loss Curve Figure 12. 5V to 1V Derating Figure 13. 12V to 1V Derating Curve, Figure 14. 5V to 2.5V Derating Figure 15. 12V to 2.5V Derating Figure 11. 12VIN Power Loss Curve Figure 16. 12V to 5V Derating

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ounce copper for the two inner layers.

For parallel modules, tie the V OUT , VFB, and COMP pins together . Use an internal layer to closely connect these pins together . The TRACK/SS pin can be tied a common capacitor for regulator soft-start.
Bring out test points on the signal pins for monitoring. Figures 17a and 17b give a good example of the recom - mended layout. Layout Checklist/Example The high integration of LTM4646 makes the PCB board layout very simple and easy. However , to optimize its electrical and thermal performance, some layout consid- erations are still necessary.
Use large PCB copper areas for high current paths, including VIN, GND, VOUT1 and VOUT2. It helps to mini- mize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capac- itors next to the VIN, GND and VOUT pins to minimize high frequency noise.
Place a dedicated power ground layer underneath the unit.
To minimize the via conduction loss and reduce mod- ule thermal stress, use multiple vias for interconnec- tion between top layer and other power layers.
Do not put vias directly on the pads, unless they are capped or plated over . APPLICATIONS INFORMATION

Figure 17. Recommended PCB Layout

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Figure 19. 12V Input to 0.75V at 20A T wo Phase Figure 18. 4.5V to 20V Input to 1.5V Dual Output, at 10A Each

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Figure 20. Four Phase Design 1V at 40A

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Figure 21. 3.3V to 1.8V, and 2.5V at 10A each with PGOOD Power Up Sequencing Figure 22. Efficiency, 3.3VIN

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Figure 23. 12V to 3.3V Up to 10A, 5V to 1.8V at 10A

4646 F23

For more information www.linear.com/LTM4646 LTM4646 Component BGA Pinout PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT2 B1 V OUT2 C1 V OUT2 D1 V OUT2 E1 COMP2B F1 FREQ A2 V OUT2 B2 V OUT2 C2 V OUT2 D2 VRNG E2 V OUTS2 F2 TRACK/SS2 A3 GND B3 GND C3 GND D3 SGND E3 COMP2A F3 MODE_PLLIN A4 V IN2 B4 V IN2 C4 GND D4 V OUTS2– E4 V FB2 F4 CLKOUT A5 V IN2 B5 V IN2 C5 GND D5 RUN2 E5 PGOOD2 F5 GND A6 GND B6 GND C6 GND D6 GND E6 GND F6 INTV CC A7 GND B7 GND C7 GND D7 GND E7 EXTV CC F7 GND A8 TEMP2 – B8 TEMP2 + C8 SW2 D8 SW2 E8 GND F8 CPWR PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 COMP1B H1 V OUT1 J1 V OUT1 K1 V OUT1 L1 V OUT1 G2 V OUTS1 H2 PHASMD J2 V OUT1 K2 V OUT1 L2 V OUT1 G3 COMP1A H3 SGND J3 V OUTS1– K3 GND L3 GND G4 V FB1 H4 TRACK/SS1 J4 GND K4 V IN1 L4 V IN1 G5 PGOOD1 H5 RUN1 J5 GND K5 V IN1 L5 V IN1 G6 GND H6 GND J6 GND K6 GND L6 GND G7 DRVCC H7 GND J7 GND K7 GND L7 GND G8 GND H8 SW1 J8 SW1 K8 TEMP1 – L8 TEMP1 +

For more information www.linear.com/LTM4646 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4646#packaging for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 88 0517 REV A L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 3.810 2.540 1.270 1.270 2.540 3.810 5.080 0.000 DETAIL A Øb (88 PLACES) F G H L J K E A B C D 2 14 35 6 7 8 D A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee 0.630 ±0.025 Ø 88x E b e e b F G 88-Lead (15mm × 11.25mm × 5.01mm) (Reference LTC DWG # 05-08-1541 Rev A) SEE NOTES SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 11.25 1.27 12.70 8.89 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 88 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y

For more information www.linear.com/LTM4646 ¶LINEAR TECHNOLOGY CORPORATION 2018 LT 0118 • PRINTED IN USA www.linear.com/LTM4646 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS x 15mm × 4.92 BGA LTM4620A Dual 13A or Single 26A Step-Down µModule Regulator 4.5V ≤ V IN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm LGA, 15mm × 15mm × 5.01mm BGA LTM4630A Dual 18A or Single 36A Step-Down µModule Regulator 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V, 16mm × 16mm × 4.41mm LGA, 16mm × 16mm × 5.01mm BGA LTM4644 Quad 4A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm BGA LTM4637 Single 20A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LGA, 15mm × 15mm x 4.92mm BGA LTM4645 Single 25A Step-Down µModule Regulator 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 9mm × 15mm × 3.51mm BGA LTM4647 Single 30A Step-Down µModule Regulator 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 9mm × 15mm × 5.01mm BGA PACKAGE PHOTO DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. BGA

Product Information

LTM4645 specifications and overview.

Summary

Dual 10A or Single 20A 關Module Regulator

Description

Dual 10A or Single 20A 關Module Regulator

Source title LTM4645 Datasheet(PDF) - Linear Technology

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