LTM4630-1B

LTC3774 LINER | Alldatasheet

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Technical content

3774fcFor more information www.linear .com/L TC3774 TYPICAL APPLICATION FEATURES DESCRIPTION Dual, Multiphase Current Mode Synchronous Controller for Sub-Milliohm DCR Sensing The LT C®3774 is a dual PolyPhase ® current mode syn- chronous step-down switching regulator controller that drives power blocks, DRMOS or external gate drivers and power MOSFETs. It offers an L TC-proprietary technique that enhances the signal-to-noise ratio of the current sense signal, allowing the use of inductors with very low DC winding resistances as the current sense element for maximum efficiency and reduced jitter. The maximum current sense voltage is programmable from 10mV to 30mV. High speed, low offset remote sense differential amplifiers and a precise 0.6V reference provide accurate output voltages between 0.6V and 3.5V from a wide 4.5V to 38V input supply range. Soft recovery from output shorts or overcurrent minimizes output overshoot. Burst Mode ® operation, continuous and pulse-skipping modes are supported. The constant operating frequency can be synchronized to an external clock or linearly programmed from 200kHz to 1.2MHz. Up to six LTC3774 controllers can be paralleled for 1-, 2-, 3-, 4-, 6-, 8- or 12-phase operation. The LTC3774 is available in a 36-lead (5mm × 6mm) QFN package. High Efficiency Dual Phase 1.5V/60A Step-Down Converter

APPLICATIONS

n Sub-Milliohm DCR Current Sensing n Operates with Power Blocks, DRMOS or External Gate Drivers and MOSFETs n Supports Phase Shedding and N+1 Phase Redundancy n Programmable DCR Temperature Compensation n ±0.75% Maximum Total DC Output Error Over Temperature n Dual Differential Remote Output Voltage Sense Amplifiers n Phase-Lockable Fixed Frequency Range: 200kHz to 1.2MHz n VIN Range: 4.5V to 38V n VOUT Range: 0.6V to 3.5V n Supports Smooth Start-Up into Pre-Biased Outputs n Programmable Soft-Start or VOUT Tracking n Hiccup Mode /Soft Recovery from Output Overcurrent n 36-Lead (5mm × 6mm) QFN Package n Computer Systems n Telecom and Datacom Systems n Industrial Equipment n DC Power Distribution Systems L, LT, LT C, LT M, Linear Technology, the Linear logo, PolyPhase and Burst Mode are registered trademarks and No RSENSE and Hot Swap are trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending.

3774 TA01a

4.5V TO 20V RUN1, 2 ILIM1, 2 HIZB1 HIZB2 PWM1 PWMEN1 V OSNS1– SNSA1+ SNS1– SNSD1+ VOSNS1+ ITH1 PHSMD CLKOUT PGOOD1,2 MODE/PLLIN PWM2 PWMEN2 GND VOSNS2– SNSA2+ SNS2– SNSD2+ FREQ VOSNS2+ ITH2 L TC3774 VIN 1/4 INTVCC TK/SS2TK/SS1 INTVCC 37.5k 15k DRMOS DRMOS fIN 500kHz 0.33µH (0.32mΩ DCR) 0.33µH (0.32mΩ DCR) 10k300µF 330µF 4V15k 0.1µF 4.7µF 2200pF ++ VOUT 1.5V 60A 22µF 50V

3774fc For more information www.linear .com/L TC3774 http://www.linear.com/product/LTC3774#orderinfo PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS 40V SNSA1+, SNSA2+, SNSD1+, 0.3V to INTVCC Operating Junction Temperature Range C to 125°C C to 150°C (Note 1) 11 12 13 14 TOP VIEW GND UHE PACKAGE 36-LEAD (5mm × 6mm) PLASTIC QFN 15 16 17 18 36 35 34 33 32 31 30 29

1 ITEMP2

V OSNS2– VOSNS2+ TK/SS2 HIZB2 PWMEN2 PWM2 RUN2 GND ITEMP1 ITH1 V OSNS1– VOSNS1+ TK/SS1 HIZB1 PWMEN1 PWM1 RUN1 GND ILIM2 V IN INTVCC CLKOUT MODE/PLLIN FREQ PHSMD ILIM1 SNSD2 SNS2– SNSA2+ PGOOD2 PGOOD1 SNSA1 SNS1– SNSD1+ TJMAX = 125°C, θJA = 43°C/W EXPOSED PAD (PIN 37) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3774EUHE#PBF LTC3774EUHE#TRPBF 3774 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C LTC3774IUHE#PBF LTC3774IUHE#TRPBF 3774 36-Lead (5mm × 6mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

3774fcFor more information www.linear .com/L TC3774 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop/Whole System VIN Input Voltage Range 4.5 38 V VOUT Output Voltage Range l 0.6 3.5 V VOSNS+ Regulated Feedback Voltage I TH = 1.2V (Note 3) l 595.5 600 604.5 mV IOSNS+ Feedback Current –30 –100 nA VREFLNREG Reference Voltage Line Regulation V IN = 4.5V to 38V 0.002 0.01 %/V VLOADREG Output Voltage Load Regulation ∆I TH = 1.2V to 0.7V ∆ITH = 1.2V to 1.6V l l 0.01 0.01 0.1 0.1 g m T ransconductance Amplifier gm ITH = 1.2V, Sink/Source 5µA 2 mmho f0dB DA Unity-Gain Crossover Frequency (Note 5) 4 MHz VOVL Feedback Overvoltage Lockout Measured at V OSNS+ l 5 7.5 10 % IQ Input DC Supply Current Normal Mode Shutdown (Note 4) V RUN = 0V mA µA DF MAX Maximum Duty Factor In Dropout 96 98 % UVLO Undervoltage Lockout VINTVCC Falling 3.5 3.75 4.0 V UVLOHYS UVLO Hysteresis 500 mV ISNSA+ Sense Pin Bias Currents VSNSA+ = 3.3V ±0.5 ±2 µA ISNSD+ Sense Pin Bias Currents VSNSD+ = 3.3V 30 nA ISNS– Sense Pin Bias Currents VSNS– = 3.3V 10 µA AVT_SNS Total Sense Signal Gain to Current Comparator

5 V/V

I TEMP DCR Tempco Compensation Current V ITEMP = 0.5V l 27 30 33 µA ITK/SS Soft-Start Charge Current VTK/SS = 0V l 1 1.25 1.5 µA tSS(INTERNAL) Internal Soft-Start Time VTK/SS = 5V 600 µs VHIZB HIZB Pin On Threshold VHIZB Rising 2.2 V VHIZB_HYS HIZB Pin On Hysteresis 600 mV VRUN RUN Pin On Threshold VRUN Rising l 1.1 1.22 1.34 V VRUN_HYS RUN Pin On Hysteresis 80 mV IRUN RUN Pin Pull-Up Current RUN < On Threshold RUN > On Threshold RUN < 1.1V RUN > 1.34V µA µA V SENSE(MAX) Maximum Current Sense Threshold I TH = 2V, VSNS– = 3.3V ILIM = 0V ILIM = 1/4 INTVCC ILIM = Float ILIM = 3/4 INTVCC ILIM = INTVCC l l l l l 9.25 28.25 10.25 29.75 11.25 31.25 mV mV mV mV mV Power Good V PGOOD(ON) PGOOD Pull-Down Resistance 90 200 Ω IPGOOD(OFF) PGOOD Leakage Current VPGOOD = 5V –2 2 µA tPGOOD VPGOOD High to Low Delay 45 µs VPGOOD PGOOD T rip Level VOSNS+ with Respect to Set Output Voltage VOSNS+ Ramping Up VOSNS+ Ramping Down 7.5 –7.5 –10

3774fc For more information www.linear .com/L TC3774 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPG(HYST) PGOOD T rip Level Hysteresis 2 % INTVCC Linear Regulator VINTVCC Linear Regulator Voltage 6V < VIN < 38V 5.3 5.5 5.7 V VLDO INT INTV CC Load Regulation ICC = 0mA to 20mA 0.5 2 % Oscillator and Phase-Locked Loop fOSC Oscillator Frequency VPHSMD = 0V RFREQ < 23.2kΩ RFREQ = 30.1kΩ RFREQ = 47.5kΩ RFREQ = 54.9kΩ RFREQ = 75.0kΩ Maximum Frequency Minimum Frequency l l 540 1.2 150 250 600 750 1.05 660 0.2 kHz kHz kHz kHz MHz MHz MHz I FREQ FREQ Pin Output Current VFREQ = 0.8V 19 20 21 µA RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ VMODE/PLLIN PLLIN Input Threshold VMODE/PLLIN Rising VMODE/PLLIN Falling 1.2 V V V CLKOUT Low Output Voltage High Output Voltage I LOAD = –500µA ILOAD = 500µA 0.2 5.2 V V θ 2 – θ1 Channel 1-2 Phase Delay VPHSMD = 0V VPHSMD = 1/4 INTVCC VPHSMD = Float VPHSMD = 3/4 INTVCC VPHSMD = INTVCC 180 180 180 180 120 Deg Deg Deg Deg Deg θ CLKOUT – θ1 CLKOUT to Channel 1 Phase Delay V PHSMD = 0V VPHSMD = 1/4 INTVCC VPHSMD = Float VPHSMD = 3/4 INTVCC VPHSMD = INTVCC 240 Deg Deg Deg Deg Deg θ 1 – θCLKIN Channel 1 to CLKIN Phase Delay V PHSMD = 0V VPHSMD = 1/4 INTVCC VPHSMD = Float VPHSMD = 3/4 INTVCC VPHSMD = INTVCC Deg Deg Deg Deg Deg PWM/P WMEN Outputs PWM PWM Output High Voltage ILOAD = 500µA l 5.0 V PWM Output Low Voltage ILOAD = –500µA l 0.5 V PWM Output Current in Hi-Z State l –5 5 µA PWMEN PWMEN Output High Voltage I LOAD = 500µA l 5.0 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3774 is tested under pulsed load conditions such that T J ≈ TA. The LTC3774E is guaranteed to meet performance specifications from 0°C to 85°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3774I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. T J is calculated from the ambient temperature, TA, and power dissipation, PD, according to the following formula: LTC3774UHE: TJ = TA + (PD • 43°C/W) Note 3: The LTC3774 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: Guaranteed by design.

3774fcFor more information www.linear .com/L TC3774 TYPICAL PERFORMANCE CHARACTERISTICS Input Quiescent Current vs Input Voltage Shutdown Current vs Input Voltage INTV CC Line Regulation Oscillator Frequency vs Input Voltage Maximum Current Sense Threshold vs Common Mode Voltage Maximum Current Sense Threshold vs Feedback Voltage (Current Foldback) Current Sense Threshold vs I TH Voltage COMMON MODE VOLTAGE (V) MAXIMUM CURRENT SENSE THRESHOLD (mV) 1.5 2 2.5 3

3774 G01

0.5 1 3.5 INTVCC 3/4 INTVCC 1/2 INTVCC 1/4 INTVCC FEEDBACK VOLTAGE (V) MAXIMUM CURRENT SENSE THRESHOLD (mV) 0.2 0.3 0.4 0.5

3774 G02

0.1 0.6 ILIM = 0 ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC ILIM = 3/4 INTVCC ILIM = INTVCC V(ITH) (V) CURRENT SENSE THRESHOLD (mV) 0.75 1 1.5 1.25 1.75

3774 G03

0.25 0.5 2 –10 ILIM = 0 ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC ILIM = 3/4 INTVCC ILIM = INTVCC INPUT VOLTAGE (V) QUIESCENT CURRENT (mA) 15 20 30 25 35

3774 G04

INPUT VOLTAGE (V) SHUTDOWN CURRENT (µA) 15 20 30 25 35

3774 G05

INPUT VOLTAGE (V) INTVCC VOLTAGE (V) 15 20 30 25 35

3774 G06

INPUT VOLTAGE (V) FREQUENCY (kHz) 15 20 30 25 35

3774 G07

23.2k/uni03A9 47.5k/uni03A9 75k/uni03A9 Load Step (Continuous Conduction Mode) 50µs/DIV

3774 G08

VOUT = 1.5V 50mV/DIV AC-COUPLED ILOAD 5A-DIV 15A TO 30A VIN = 12V

3774fc For more information www.linear .com/L TC3774 TYPICAL PERFORMANCE CHARACTERISTICS Power Loss TK/SS Pull-Up Current vs Temperature RUN Threshold vs Temperature Regulated Feedback Voltage vs Temperature Oscillator Frequency vs Temperature Undervoltage Lockout Threshold (INTV CC) vs Temperature Efficiency Power Loss Efficiency ILOAD (A) 0.01 EFFICIENCY (%)

3774 G09

0.1 1 100 100 BURST MODE PULSE-SKIPPING CCM VIN = 7V VOUT = 1.5V ILOAD (A) 0.01 POWER LOSS (W)

3774 G10

4.5 4.0 3.0 2.0 0.1 1 100 1.0 0.5 3.5 2.5 1.5 5.0 BURST MODE PULSE-SKIPPING CCM VIN = 7V VOUT = 1.5V ILOAD (A) 0.01 EFFICIENCY (%)

3774 G11

0.1 1 100 100 VIN = 12V VOUT = 1.5V BURST MODE PULSE-SKIPPING CCM ILOAD (A) 0.01 POWER LOSS (W)

3774 G12

4.5 4.0 3.0 2.0 0.1 1 100 1.0 0.5 3.5 2.5 1.5 5.0 BURST MODE PULSE-SKIPPING CCM VIN = 12V VOUT = 1.5V TEMPERATURE (°C) –50 ITK/SS (µA)

3774 G13

1.4 –25 0 50 12575 100 150 1.2 1.1 1.3 1.5 TEMPERATURE (°C) –50 RUN THRESHOLD (V)

3774 G14

1.3 –25 0 50 12575 100 150 1.1 1.0 1.2 0.9 1.4 ON OFF TEMPERATURE (°C) –50 REGULATED FEEDBACK VOLTAGE (mV)

3774 G15

603.0 –25 0 50 12575 100 150 600.0 598.5 597.0 601.5 595.5 604.5 TEMPERATURE (°C) –50 FREQUENCY (kHz)

3774 G16

–25 0 50 12575 100 150 575 550 675 650 525 600 500 700 TEMPERATURE (°C) –50

3.0 UVLO THRESHOLD (V)

3.2 3.6 3.8 4.0 5.0 4.4 0 50 75

3774 G17

3.4 4.6 4.8 4.2 –25 25 100 125 150 RISE FALL

3774fcFor more information www.linear .com/L TC3774 TYPICAL PERFORMANCE CHARACTERISTICS Prebiased Output at 0.5V Quiescent Current vs Temperature Shutdown Current vs Temperature FREQ Pin Source Current vs Temperature TEMPERATURE (°C) –50 QUIESCENT CURRENT (mA)

3774 G18

9.75 –25 0 50 12575 100 150 9.25 9.50 9.00 8.50 8.25 8.75 8.00 10.00 TEMPERATURE (°C) –50 SHUTDOWN CURRENT (µA)

3774 G19

–25 0 50 12575 100 150 TEMPERATURE (°C) –50 FREQ PIN CURRENT (µA)

3774 G20

–25 0 50 12575 100 150 21.0 20.5 19.5 19.0 20.0 18.5 21.5 50ms/DIV

3774fc For more information www.linear .com/L TC3774 PIN FUNCTIONS PGOOD1, PGOOD2 (Pin 15, Pin 14): Power Good Indica- tor Outputs. Open drain outputs that pull to ground when output voltage is not in regulation. SNSA1+, SNSA2 + (Pin 16, Pin 13): AC Current Sense Comparator (+) Inputs. This input senses the signal from the output inductor’s DCR with a filter bandwidth of five times larger than the inductor’s L/DCR value. SNS1 –, SNS2– (Pin 17, Pin 12): Negative current Sense Inputs. The negative input of the current comparator is normally connected to the output. SNSD1+, SNSD2+ (Pin 18, Pin 11): DC Current Sense Comparator (+) Inputs. This input senses the signal from the output inductor’s DCR with a filter bandwidth equal to the inductor’s L/DCR value. RUN1, RUN2 (Pin 20, Pin 9): Run Control Inputs. A volt- age above 1.22V turns on the IC. There is a 1µA pull-up current on this pin . Once the RUN pin rises above the 1.22V threshold the pull-up increases to 5µA. PMW1, PWM2 (Pin 21, Pin 8): (Top) Gate Signal Outputs. This signal goes to the PWM or top gate input of the ex- ternal gate driver or integrated driver MOSFET or Power Block. This is a three-state compatible output. P WMEN1, PWMEN2 (Pin 22, Pin 7): Enable pins for non- three-state compatible drivers. This pin has an internal open-drain pull-up to INTV CC. An external resistor to GND is required. This pin is low when the corresponding PWM pin is high impedance. HIZB1, HIZB2 (Pin 23, Pin 6): Phase Shedding Input Pins. When this pin is low, the corresponding PWM pin goes high impedance and PWMEN goes low. Tie to INTV CC or VIN to disable this function. TK/SS1, TK/SS2 (Pin 24, Pin 5): Output Voltage T racking and Soft-Start Inputs. The voltage ramp rate at this pin sets the voltage ramp rate of the output. A capacitor to ground accomplishes soft-start. This pin has a 1.25µA pull-up current. V OSNS1+, VOSNS2+ (Pin 25, Pin 4): Remote Sense Differ- ential Amplifier Non-inverting Inputs. Connect to Feedback divider center tap with the divider across the output load The remote sense differential amplifier’s output is internally connected to the error amplifier inverting input. VOSNS1–, VOSNS2– (Pin 26, Pin 3): Remote Sense Differ- ential Amplifier Inverting inputs. Connect to sense ground at the output load. ITH1, ITH2 (Pin 27, Pin 2): Current Control Thresholds and Error Amplifier Compensation Points. The current comparator’s threshold increases with the ITH control voltage. ITEMP1, ITEMP2 (Pin 28, Pin 1): Input of the temperature sensing comparators. Connect this pin to an external NTC resistor placed near the inductors. Floating this pin disables the DCR temperature compensation function. ILIM1, ILIM2 (Pin 29, Pin 36): Current Comparator Sense Voltage Limit Selection pins. PHSMD (Pin 30): Phase Mode Pin. This pin selects CH1- CH2 and CH1-CLKOUT phase relationships. FREQ (Pin 31): Frequency Set /Select Pin . A resistor between this pin and GND sets the switching frequency. This pin sources 20uA. MODE/PLLIN (Pin 32): Dual Function Pin. Tying this pin to GND, INTV CC or floating it enables forced continuous mode, pulse-skipping mode or Burst Mode operation re- spectively. Applying a clock signal to this pin causes the internal PLL to synchronize the internal oscillator to the clock signal and forces for ced continuous mode. The PLL compensation network is integrated on to the IC. CLKOUT (Pin 33): Clock Output Pin. This pin is used to synchronize other LTC3774s. INTVCC (Pin 34): Internal 5.5V Regulator Output. The con- trol circuits are powered from this voltage. Decouple this pin to GND with a minimum of 4.7µF low ESR tantalum or ceramic capacitor. This pin is intended to be used as a reference only. Please do not bias other applications off this voltage! V IN (Pin 35): Main Input Supply. Decouple this pin to GND with a capacitor (0.1µF to 1µF) GND (Pins 19, 10, Exposed Pad Pin 37): Ground. All small-signal components and compensation components should be connected here. The exposed pad must be soldered to the PCB ground for electrical connection and rated thermal performance.

3774fcFor more information www.linear .com/L TC3774 FUNCTIONAL BLOCK DIAGRAM – + –+ + SLEEP INTVCC 0.55V NOTE: FUNCTIONAL BLOCK DIAGRAM SHOWS 1 CHANNEL ONL Y. THE 2 CHANNELS ARE IDENTICAL. – + – + 0.5V SS – + 1.22V RUN 1.25µA VIN EA ITH RC CC1 CSSRUN TK/SS 0.6V REF S R Q PHSMD 5.5V REG ACTIVE CLAMP OSC MODE/SYNC DETECT SLOPE COMPENSATION UVLO R ITHB 1µA/5µA FREQ CLKOUT MODE/PLLIN ITEMP 0.6V BURST EN ILIM + – ICMP IREV F OV UV DIFFAMP AMP 0.555V PGOOD SNS– SNSA+ PWM INTVCC VOSNS– VOSNS+ SNSD+ 3774 BD GND 0.645V 20k 20k OV RUN ON FCNT PLL-SYNC TEMPSNS VIN SNS– PWMEN SWITCH LOGIC HIZB INTVCC

3774fc For more information www.linear .com/L TC3774 OPERATION Main Control Loop The LTC3774 uses an L TC proprietary current sensing, current mode step-down architecture. During normal operation, the top MOSFET is turned on every cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I CMP , resets the RS latch. The peak inductor current at which I CMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The remote sense amplifier (diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re-references it to the local IC ground reference. The error amplifier receives this feedback signal and compares it to the internal 0.6V reference. When the load current increases, it causes a slight decrease in the V OSNS+ pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the inductor’s average current equals the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, I REV , or the beginning of the next cycle. The main control loop is shut down by pulling the RUN pin low. Releasing RUN allows an internal 1.0µA current source to pull up the RUN pin. When the RUN pin reaches 1.22V, the main control loop is enabled and the IC is powered up. When the RUN pin is low, all functions are kept in a controlled state. Sensing Signal of Very Low DCR The LTC3774 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor DCR, 1mΩ or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. The LTC3774 can sense a DCR value as low as 0. 2mΩ with careful PCB layout.The LTC3774 comprises two positive sense pins, SNSD + and SNSA +, to acquire signals and processes them internally to provide the response as with a DCR sense signal that has a 14dB signal-to-noise ratio improvement. In the meantime, the current limit threshold is still a function of the inductor peak current and its DCR value, and can be accurately set from 10mV to 30mV in 5mV steps with the ILIM pin. The filter time constant, R1C1, of the SNSD + should match the L/DCR of the output inductor, while the filter at SNSA+ should have a bandwidth of five times larger than SNSD+, R2• C2 equals R1•C1/5. Internal Soft-Start By default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. The internal soft- start ramp represents a noninverting input to the error amplifier. The V OSNS+ pin is regulated to the lower of the error amplifier’s three noninverting inputs (the internal soft-start ramp, the TK/SS pin or the internal 600mV ref- erence). As the ramp voltage rises from 0V to 0.6V over approximately 600µs, the output voltage rises smoothly from its prebiased value to its final set value. Certain applications can result in the start-up of the con- verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the bottom MOSFET is disabled until soft-start is greater than V OSNS+. Shutdown and Start-Up (RUN and TK/SS Pins) The LTC3774 can be shut down using the RUN pin. Pulling the RUN pin below 1.14V shuts down the main control loop for the controller and most internal circuits, including the INTV CC regulator. Releasing the RUN pin allows an internal 1.0µA current to pull up the pin and enable the controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage, V OUT , is controlled by the voltage on the TK/SS pin. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC3774 regulates the V OSNS+ voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to GND. An internal 1.25µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage, V OUT , rises smoothly from zero to its final value. Alternatively, the TK/SS pin can be

3774fcFor more information www.linear .com/L TC3774 OPERATION used to cause the start-up of VOUT to track that of another supply. Typically, this requires connecting to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the RUN pin is pulled low to disable the controller, or when INTV CC drops below its undervoltage lockout threshold of 3.75V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the external MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Continuous Conduction) The LTC3774 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE pin to GND. To select pulse-skipping mode of operation, tie the MODE/PLLIN pin to INTV CC. To select Burst Mode operation, float the MODE/PLLIN pin. When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the I TH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the I TH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both external MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator REV) turns off the bottom external MOSFET just before the inductor current reaches zero, preventing it from re - versing and going negative. Thus, the controller operates in discontinuous operation. In for ced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the I TH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTV CC, the LTC3774 operates in PWM pulse skipping mode at light loads. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size . Low frequency opera - tion increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 200kHz to 1.2MHz. There is a precision 20µA current flowing out of the FREQ pin so that the user can program the controller’s switching frequency with a single resistor to GND. A curve is provided later in the Applications Information section showing the relationship between the voltage on the FREQ pin and switching frequency. A phase-locked loop (PLL) is available on the LTC3774 to synchronize the internal oscillator to an external clock source that is connected to the MODE/PLLIN pin. The PLL loop filter network is integrated inside the LTC3774. The phase -locked loop is capable of locking any frequency within the range of 200kHz to 1.2MHz. The frequency setting resistor should always be present to set the controller’s initial switching frequency before locking to the external clock. The controller operates in forced continuous mode when it is synchronized.

3774fc For more information www.linear .com/L TC3774 L TC3774

3774 F01a

+240CLKOUT L TC3774 0,120 240,60 MODE/PLLIN PHSMD CLKOUT INTV CC L TC3774

3774 F01b

+90CLKOUT L TC3774 0,180 90,270 MODE/PLLIN PHSMD CLKOUT L TC3774 MODE/PLLIN PHSMD +60 CLKOUT L TC3774 0,180 60,240 MODE/PLLIN PHSMD CLKOUT

3774 F01c

+60 L TC3774 120,300 MODE/PLLIN PHSMD CLKOUT L TC3774

3774 F01d

+90CLKOUT L TC3774 135,315 L TC3774 MODE/PLLIN PHSMD3/4 INTV CC +45CLKOUT 90,270 L TC3774 MODE/PLLIN PHSMD +90CLKOUT 0,180 225,45 MODE/PLLIN PHSMD CLKOUT OPERATION Figure 1a. 3-Phase Operation Figure 1b. 4-Phase Operation Figure 1c. 6-Phase Operation Figure 1d. 8-Phase Operation Figure 1e. 12-Phase Operation L TC3774 MODE/PLLIN PHSMD +60 CLKOUT L TC3774 0,180 60,240 MODE/PLLIN PHSMD CLKOUT +60 L TC3774 120,300 MODE/PLLIN PHSMD CLKOUT L TC3774 MODE/PLLIN PHSMD1/4 INTV CC +60CLKOUT L TC3774 150,330 210,30 MODE/PLLIN PHSMD CLKOUT

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+60 L TC3774 270,90 MODE/PLLIN PHSMD CLKOUT

out of phase with respect to each other. the load ground. See Figure 2. the error amplifier inverting input. Figure 2. Differential Amplifier Connection

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3774fc For more information www.linear .com/L TC3774 OPERATION Power Good (PGOOD Pin) The PGOOD pin is connected to the open drain of an inter- nal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the V OSNS+ pin voltage is not within ±7.5% of the 0.6V reference voltage. The PGOOD pin is also pulled low when the RUN pin is below 1.14V or when the LTC3774 is in the soft-start or tracking up phase. When the V OSNS+ pin voltage is within the ±7.5% regulation window, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when the V OSNS+ pin is within the regulation window. However, there is an internal 45µs power-bad mask when the V OSNS+ goes out of the window. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>7.5%) as well as other more serious condi- tions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the over voltage condition is cleared. Undervoltage Lockout The LTC3774 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTV CC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTV CC is below 3.75V. To prevent oscillation when there is a disturbance on the INTV CC, the UVLO comparator has 500mV of preci- sion hysteresis. Another way to detect an under voltage condition is to monitor the VIN supply. Because the RUN pin has a preci- sion turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. The RUN comparator itself has about 80mV of hysteresis. One can program additional hysteresis for the RUN comparator by adjusting the values of the resistive divider. For accurate V IN undervoltage detection, V IN needs to be higher than 4.75V. Always set the VIN undervoltage detection threshold higher than the power stage UVLO threshold so that the LTC3774 is enabled after the power stage is.

nection underneath the current sense element (Figure 3). the IC pins to prevent noise coupling to the sense signal. Figure 3. Sense Lines Placement with Inductor DCR

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+ and SNS– is from 0V to 5.25V. Figure 4. Inductor DCR Current Sensing

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3774fcFor more information www.linear .com/L TC3774 APPLICATIONS INFORMATION To ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of DCR resistance, approximately 0.4%/°C, should be taken into account. The LTC3774 features a DCR temperature compensation circuit that uses an NTC temperature sensing resistor for this purpose. See the Inductor DCR Sensing Temperature Compensation section for details. Typically, C1 and C2 are selected in the range of 0.047µF to 0.47µF. If C1 and C2 are chosen to be 220nF, and an inductor of 330nH with 0.32mΩ DCR is selected, R1 and R2 will be 4.7k and 942Ω respectively. The bias current at SNSD + and SNSA+ is about 30nA and 500nA respectively, and it causes some small error to the sense signal. There will be some power loss in R1 and R2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: PLOSS R( )= VIN(MAX) – VOUT( ) • VOUT R Ensure that R1 and R2 have a power rating higher than this value. However, DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. To maintain a good signal-to-noise ratio for the current sense signal, using a minimum ∆V SENSE of 2mV for duty cycles less than 40% is desirable. The actual ripple voltage will be determined by the following equation: ∆VSENSE = VOUT VIN

• VIN – VOUT R1• C1• fOSC Inductor DCR Sensing Temperature Compensation and the ITEMP Pin Inductor DCR current sensing provides a lossless method of sensing the instantaneous current. Therefore, it can provide higher efficiency for applications of high output currents. However, the DCR of the inductor, which is the small amount of DC winding resistance of the copper, typically has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced. The LTC3774 offers a method to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor to actively correct this error. The ITEMP pin, when left floating, is at a voltage around 5V and DCR temperature compensation is disabled. The ITEMP pin has a constant 30µA precision current flowing out the pin. By connecting an NTC resistor from the ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according the following equation: VSENSEMAX(ADJ) = VSENSE(MAX)  2– VITEMP 2.8 1.5 where: VSENSEMAX(ADJ) is the maximum adjusted current sense threshold. VSENSE(MAX) is the maximum current sense threshold specified in the Electrical Characteristics table. It is typi- cally 30mV, 25mV, 20mV, 15mV or 10mV depending on the setting ILIM pins. VITEMP is the voltage of the ITEMP pin. The valid voltage range for DCR temperature compensation on the ITEMP pin is 1.4V to 0.6V, with 1.4V or above being no DCR temperature correction and 0.6V the maximum correction. However, if the duty cycle of the controller is less than 25%, the ITEMP range is extended from 1.4V to 0V. The NTC resistor has a negative temperature coefficient, meaning its value decreases as temperature rises. The V ITEMP voltage, therefore , decreases as temperature

3774fc For more information www.linear .com/L TC3774 APPLICATIONS INFORMATION increases and in turn, the VSENSEMAX(ADJ) will increase to compensate the DCR temperature coefficient. The NTC resistor, however, is nonlinear and the user can linear - ize its value by building a resistor network with regular resistors. Consult the NTC manufacturer’s data sheets for detailed information. Another use for the ITEMP pins, in addition to NTC com- pensated DCR sensing, is adjusting VSENSE(MAX) to values between the nominal values of 10mV, 15mV, 20mV, 25mV and 30mV for a more precise current limit. This is done by applying a voltage less than 1. 4V to the ITEMP pin. VSENSE(MAX) will be varied per the previous equation and the same duty cycle limitations will apply. The current limit can be adjusted using this method either with a sense resistor or DCR sensing. NTC Compensated DCR Sensing For DCR sensing applications where a more accurate current limit is required, a network consisting of an NTC thermistor placed from the ITEMP pin to ground will provide correction of the current limit over temperature. Figure 4 shows this network. Resistors R S and R P will linearize the impedance the ITEMP pin sees. To implement NTC compensated DCR sensing, design the DCR sense filter network per the same procedure mentioned in the previous selection, except calculate the divider components using the room temperature value of the DCR. Set the ITEMP pin resistance to 46.7k at 25°C. With 30µA flowing out of the ITEMP pin, the voltage on the ITEMP pin will be 1.4V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C. Calculate the ITEMP pin resistance and the maximum inductor temperature which is typically 100°C. Use the equations: RITEMP100C = VITEMP100C 30µA VITEMP100C = 1.4V – 4.2IMAX DCR(MAX)R2 / R1+R2( )  100° C– 25°C( )0.4 / 100 VSENSE(MAX) Calculate the values for RP and RS. A simple method is to graph the following R S versus RP equations with R S on the y-axis and RP on the x-axis. RS = RITEMP25C – RNTC25C || RP RS = RITEMP100C – RNTC100C || RP Next, find the value of R P that satisfies both equations which will be the point where the curves intersect. Once R P is known, solve for RS. The resistance of the NTC thermistor can be obtained from the vendor’s data sheet either in the form of graphs, tabulated data or formulas. The approximate value for the NTC thermistor for a given temperature can be calculated from the following equation: R =RO exp B 1 T +273 – 1 TO +273 where: R = resistance at temperature T , which is in degrees C RO = resistance at temperature TO, typically 25°C B = B-constant of the thermistor. Figure 5 shows a typical resistance cur ve for a 100k thermistor and the ITEMP pin network over temperature. Starting values for the NTC compensation network are listed below: NTC RO = 100k RS = 20k RP = 50k But, the final values should be calculated using the above equations and checked at 25°C and 100°C.

Use typical values for VSENSE(MAX). MAX for inductor temperatures between 25°C and 100°C. Figure 7. Take care to keep the ITEMP pin away from the

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Figure 5. Resistance Versus Temperature for the ITEMP Pin

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Figure 6. Worst-Case IMAX Versus Inductor Temperature Curve Figure 7. Thermistor Location. Place Thermistor Next to

3774fc For more information www.linear .com/L TC3774 APPLICATIONS INFORMATION Pre-Biased Output Start-Up There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging that output pre-bias. The LTC3774 can safely power up into a pre-biased output without discharging it. The LTC3774 accomplishes this by disabling both the top and bottom MOSFETs until the TK/SS pin voltage and the internal soft-start voltage are above the V OSNS+ pin volt- age. When V OSNS+ is higher than TK/SS or the internal soft-start voltage, the error amp output is railed low. The control loop would like to turn the bottom MOSFET on, which would discharge the output. Disabling both top and bottom MOSFETs prevents the pre-biased output voltage from being discharged. When TK/SS and the internal soft-start both cross 500mV or V OSNS+, whichever is lower, both top and bottom MOSFETs are enabled. If the pre-bias is higher than the OV threshold, the bottom gate is turned on immediately to pull the output back into the regulation window. Overcurrent Fault Recovery When the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will col- lapse depending on the load. The output may be shorted to ground through a ver y low impedance path or it may be a resistive short , in which case the output will collapse partially, until the load current equals the preset current limit. The controller will continue to source current into the short. The amount of current sourced depends on the ILIM pin setting and the V OSNS+ voltage as shown in the Current Foldback graph in the Typical Performance Characteristics section. Upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. In the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. Current limit foldback is not disabled during an overcurrent recovery. The load must step below the folded back current limit threshold in order to restart from a hard short. Phase Shedding/n+1 Redundancy (HIZB Pin) Unlike the RUN pins, the HIZB pins cause the PWM to enter its high impedance state while not pulling down on ITH or TK/SS. This allows two possibilities: First, one can shed a phase based on load requirements via the HIZB pin. This im- proves low current efficiency in a single output multiphase case by reducing switching losses. Second , for applications that require n+1 redundancy, it is now easy to disconnect a channel with damaged MOSFETs or drivers. When com- bined with a Hot Swap™ controller, such as the LTC4226, the HIZB pin could be connected to the gate of the Hot Swap switch. When a damaged MOSFET triggers the Hot Swap controller, it also disables the corresponding chan- nel’s power stage, disconnecting it. Since ITH and TK/SS are unaffected, it does not affect the rest of the system. The propagation delay from HIZB falling to high impedance on P WM is <200ns. Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency, f OSC, directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN VIN – VOUT fOSC •L Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however, requires a large inductor. A reasonable starting point is to choose a ripple current that is about 40% of I OUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: L ≥ VIN – VOUT fOSC •IRIPPLE

• VOUT VIN Inductor Core Selection Once the inductance value is determined, the type of in - ductor must be selected. Core loss is independent of core

more turns of wire and therefore copper losses will increase. not represent a heavy capacitive load. and require an appropriate external pull-down resistor. and high at any other PWM state. factory applications support for assistance. switch application in switching regulators. Figure 8. Gate Charge Characteristic

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3774fc For more information www.linear .com/L TC3774 APPLICATIONS INFORMATION The initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. The flat portion of the curve is the result of the Miller multiplication effect of the drain-to-gate capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given V DS drain voltage, but can be adjusted for different VDS voltages by multiplying the ratio of the application V DS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturer’s data sheet and divide by the stated V DS voltage specified. CMILLER is the most important se- lection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle= VOUT VIN Synchronous Switch Duty Cycle= VIN – VOUT VIN The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT VIN IMAX( ) 1+ δ( ) RDS(ON) + VIN( )

2 IMAX

⎟ RDR( ) CMILLER( ) • VINTVCC – VTH(MIN) + 1 VTH(MIN)

• f PSYNC = VIN – VOUT VIN IMAX( ) 1+ δ( ) RDS(ON) where δ is the temperature dependency of R DS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. V TH(MIN) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. C MILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I 2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For V IN < 20V, the high current efficiency generally improves with larger MOSFETs, while for V IN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ ) is generally given for a MOSFET in the form of a normalized R DS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. An optional Schottky diode across the synchronous MOSFET conducts during the dead time between the con- duction of the two large power MOSFETs. This pre vents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse-recovery period which could cost as much as several percent in effi- ciency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance. MOSFET Driver Selection Gate driver ICs, DrMOSs and power blocks with an interface compatible with the LTC3774's three-state PWM outputs or the LTC3774's PWM/PWMEN outputs can be used. Always enable the power stage first, before the LTC3774 is enabled. C IN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (V OUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the

3774fcFor more information www.linear .com/L TC3774 maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ IMAX VIN VOUT( ) VIN – VOUT( )⎡⎣ ⎤ This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3774, ceramic capacitors can also be used for C IN. Always consult the manufacturer if there is any question. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. X7R, X5R and Y5V are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input volt- age on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase a t a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low ESR. A small (0.1µF to 1µF) bypass capacitor, C IN, between the chip VIN pin and ground, placed close to the LTC3774, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN and VIN pin provides further isolation. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR require- ment is satisfied the capacitance is adequate for filtering. The steady-state output ripple ( ∆VOUT) is determined by: ∆VOUT ≈ ∆IRIPPLE ESR+ 1 8fCOUT where f = operating frequency, COUT = output capacitance and ∆IRIPPLE = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IRIPPLE increases with input voltage. The output ripple will be less than 50mV at maximum VIN with ∆IRIPPLE = 0.4IOUT(MAX) assuming: COUT required ESR < N • RSENSE and COUT > 1 8f( ) RSENSE( ) The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementa- tions possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristic of each capacitor type is significantly differ- ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitors available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for C OUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) require- ment. Ceramic capacitors from AVX, Taiyo Yuden, Murata and TDK offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application . Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In APPLICATIONS INFORMATION

3774fc For more information www.linear .com/L TC3774 APPLICATIONS INFORMATION the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POSCAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturers for other specific recommendations. Differential Amplifier The LTC3774 has true remote voltage sense capability. The sense connections should be returned from the load, back to the differential amplifier’s inputs through a common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The LTC3774 diffamp has high input impedance on V OSNS+ pin. The output of the diffamp con- nects to the inverting input of the error amplifier internally. Setting Output Voltage The LTC3774 output voltage is set by an external feed - back resistive divider carefully placed across the output, as shown in Figure 2. The regulated output voltage is determined by: VOUT = 0.6V • 1 + RD1 RD2 To improve the frequency response, a feedforward ca - pacitor, CF1 , may be used. Great care should be taken to route the VOSNS+ line away from noise sources, such as the inductor or the SW line. To minimize the effect of the voltage drop caused by high current flowing through board conductance; connect VOSNS– and VOSNS+ sense lines close to the ground and the load output respectively. External Soft-Start and T racking The LTC3774 has the ability to either soft-start by itself or track the output of another channel or external supply. When the controller is configured to soft-start by itself, a capacitor may be connected to its TK/SS pin or the internal soft-start may be used. The controller is in the shutdown state if its RUN pin voltage is below 1.22V and its TK/SS pin is actively pulled to ground in this shutdown state. If the RUN pin voltage is above 1.22V, the controller powers up. A soft-start current of 1.25µA then starts to charge the TK/SS soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the TK/SS pin. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: tSOFTSTART = 0.6 • CSS 1.25µA Regardless of the mode selected by the MODE/PLLIN pin, the controller always starts in discontinuous mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.565V, it will operate in for ced continuous mode and revert to the selected mode once TK/SS > 0.565V. The output ripple is minimized during the 65mV forced continuous mode window, ensuring a clean PGOOD signal. When the chan- nel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/ SS pin. Therefore, the volt- age ramp rate on this pin is determined by the ramp rate of the other supply’ s voltage. It is only possible to track another supply that is slower than the internal soft-start ramp. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC3774 is forced into continuous mode of operation as soon as V OSNS+ is below the power good lower threshold regardless of the setting on the MODE/PLLIN pin. However, the LTC3774 should always be set in forced continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, the controller operates in discontinuous mode. The LTC3774 allows the user to program how its output ramps up and down by means of the TK/SS pin. Through these pins, the output can be set up to either coincidentally

Figure 9. T wo Different Modes of Output Voltage T racking Figure 10. Setup and Coincident and Ratiometric T racking

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including the two in Figure 9. the coincident tracking mode instead of ratiometric.

current takes the folded-back current limit into account. phase shift between the external and internal oscillators. harmonics of the external clock. Figure 11. Setup for a 5V Input

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cycle skipping in order to limit the short-circuit current.

3774fcFor more information www.linear .com/L TC3774 Figure 12. Relationship Between Oscillator Figure 13. Phase-Locked Loop Block Diagram

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high threshold is 1.6V, while the input low threshold is 1V. The LTC3774 features CLKOUT and PHSMD pins that allow multiple LTC3774 ICs to be daisy chained together in multiphase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional ICs in a 3-, 4-, 6-, 8- or 12-phase power supply solution feeding a single high current output, or even several outputs from the same input supply. The PHSMD pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and CLKOUT. The phases are calculated relative to zero degrees, defined as the rising edge of PWM1. Refer to the Applications Information section for more details on how to create multiphase applications. Minimum On-Time Considerations Minimum on-time, t ON(MIN), is the smallest time duration that the LTC3774 is capable of turning on the top MOSFET. It is determined by internal timing delays, power stage timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN f( ) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the voltage ripple and current ripple will increase.

3774fc For more information www.linear .com/L TC3774 The minimum on-time for the LTC3774 is approximately 90ns, with good PCB layout, minimum 30% inductor current ripple and at least 2mV ripple on the current sense signal. The minimum on-time can be affected by PCB switching noise in the voltage and current loop. As the peak sense voltage decreases the minimum on- time gradually increases This is of particular concern in forced continuous applications with low ripple current at light loads . If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percent- age of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3774 circuits: 1) IC VIN current, 2) MOSFET driver current, 3) I2R losses, 4) topside MOSFET transi - tion losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table. V IN current typically results in a small (<0.1%) loss. 2. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from the driver supply to ground. The resulting dQ/dt is a current out of the driver supply that is typically much larger than the control circuit current. In continuous mode, I GATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. APPLICATIONS INFORMATION 3. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET, inductor and current sense re- sistor. In continuous mode, the average output current flows through L and R SENSE, but is chopped between the topside MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same R DS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and R SENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. Efficiency varies as the inverse square of VOUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! T ransition losses apply only to the topside MOSFET (s), and become significant only when operating at high input voltages (typically 15V or greater). T ransition losses can be estimated from: T ransition Loss = (1.7) VIN2 • IO(MAX) • CRSS • f Other hidden losses such as copper trace and internal batter y resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these system level losses during the design phase. The internal battery and fuse resistance losses can be minimized by making sure that C IN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 20mΩ to 50mΩ of ESR. Other losses including Schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss.

3774fcFor more information www.linear .com/L TC3774 APPLICATIONS INFORMATION Checking T ransient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, V OUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT . ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return V OUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the I TH pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The I TH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The I TH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1µs to 10µs will produce output voltage and I TH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the I TH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing R C and the bandwidth of the loop will be increased by decreasing C C. If R C is increased by the same factor that C C is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with C OUT , causing a rapid drop in VOUT . No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of C LOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • C LOAD. Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 14. Check the following in the PC layout: The INTV CC decoupling capacitor should be placed immediately adjacent to the IC between the INTVCC pin and GND plane. A 1µF ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC. An additional 4.7µF to 10µF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet.

1. Place the feedback divider between the + and – terminals

trace spacing from the IC to the feedback divider.

1. Are the SNSA+, SNSD+ and SNS– printed circuit traces

should be as close as possible to the pins of the IC. provides the pulsed current to the MOSFET. +, SNSA+, SNS–, VOSNS+, VOSNS–). Figure 14. Branch Current Waveforms

3774 F14

3774fcFor more information www.linear .com/L TC3774 8. Are the signal and power grounds kept separate? The IC ground pin and the ground return of C INTVCC must return to the combined COUT (–) terminals. The VOSNS+ and ITH traces should be as short as possible. The path formed by the top N-channel MOSFET, Schottky diode and the C IN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. Use a modified “ star ground” technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INT V CC decoupling capacitor, the bottom of the voltage feedback resistive divider and the GND pin of the IC. Design Example As a design example of the front page circuit for a two- channel high current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), V OUT = 1.5V, I MAX = 60A, and f = 400kHz (see front page schematic). The regulated output voltage is determined by: VOUT = 0.6V • 1 + RB RA Using a 10k 1% resistor from the VFB node to ground, the top feedback resistor is 15k. The frequency is set by biasing the FREQ pin to 0.75V (see Figure 12). The inductance value is based on a 35% maximum ripple current assumption (10.5A per phase). The highest value of ripple current occurs at the maximum input voltage: L = VOUT f • ∆IL(MAX) 1− VOUT VIN(MAX) This design will require 0.33µH. The Würth 744301033, 0.32µH inductor is chosen. At the nominal input voltage (12V), the ripple current will be: ∆IL(NOM) = VOUT f • L 1− VOUT VIN(NOM) It will have 10A (33%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or 35A per phase. The minimum on-time occurs at the maximum V IN, and should not be less than 100ns (includes margin): tON(MIN) = VOUT VIN(MAX) f = 1.5V 20V(400kHz) = 187ns DCR sensing is used in this circuit. If C1 and C2 are chosen to be 220nF, based on the chosen 0.33µH inductor with 0.32mΩ DCR, R1 and R2 can be calculated as: R1= L DCR • C1= 4.69k R2 = L DCR • C2 • 5= 937Ω Choose R1 = 4.64k and R2 = 931Ω. APPLICATIONS INFORMATION

3774fc For more information www.linear .com/L TC3774 The maximum DCR of the inductor is 0.34mΩ. The VSENSE(MAX) is calculated as: VSENSE(MAX) = IPEAK • DCRMAX = 12mV The current limit is chosen to be 15mV. If temperature variation is considered, please refer to Inductor DCR Sensing Temperature Compensation with NTC Thermistor. The power dissipation on the topside MOSFET can be easily estimated. Choosing an Infineon BSC050NE2LS MOSFET results in: R DS(ON) = 7.1mΩ (max), V MILLER = 2.8V, CMILLER ≅ 108pF. At maximum input voltage with TJ (estimated) = 75°C: PMAIN = 1.5V 20V 30A( ) 2 30A ⎝⎜ ⎞ 5.5V – 2.8V + 1 2.8V ⎦⎥ 400kHz( ) = 599mW + 377mW = 976mW / phase For a 0.32mΩ DCR, a short-circuit to ground will result in a folded back current of: ISC = 1/ 3( ) 15mV 0.00032Ω – 1 90ns(20V) 0.33µH ⎟ = 12.9A / phase An Infineon BSC010NE2LS, RDS(ON) = 1.1mΩ, is chosen for the bottom FET. The resulting power loss is: PSYNC = 20V – 1.5V 20V 30A( ) 2 • ⎦ • 0.0011Ω PSYNC = 1.14W/phase CIN is chosen for an equivalent RMS current rating of at least 13.7A. C OUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continu- ous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) = 0.0045Ω • 10A = 45mVP-P Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across C OUT. APPLICATIONS INFORMATION

3774fcFor more information www.linear .com/L TC3774 TYPICAL APPLICATIONS

3774 TA02

V OSNS2– VOSNS2+ TK/SS2 HIZB2 PWMEN2 PWM2 RUN2 GND ITEMP1 ITH1 V OSNS1– VOSNS1+ TK/SS1 HIZB1 PWMEN1 PWM1 RUN1 GND SNSD1+ SNS1– SNSA1+ PGOOD1 PGOOD2 SNSA2+ SNS2– SNSD2+ L TC3774 37.4k 10k RS1 20k RNTC1 100k RP1 43.2k RS2 20k RNTC2 100k RP2 43.2k 1µF 2.2/uni03A9 30.1k 4.7µF 10k VIN RUN2 RUN1 INTVCC 220pF 0.01µF 22pF 15k 1.5nF 180µF 10k 10k 100k 100k 10k 220pF1.5nF VIN VIN 0.22µF 0.22µF 0.22µF 0.22µF VIN PHASE VSWH CGND PGND SMOD DISB V CIN VDRV 22µF 2.2µF 1/uni03A9 2.2µF 5V BIAS 22µF 10k VIN 7V TO 14V INTVCC INTVCC 0.22µF L1 0.33µH 10k 10k 4.64k 931/uni03A9 COUT1 100µF COUT2 330µF 1.5V/30A V OUT1 1.2V/30A V OUT2 VIN PHASE VSWH CGND PGND SMOD DISB V CIN VDRV 22µF 2.2µF 1/uni03A9 2.2µF 22µF 0.22µF L2 0.33µH 10k 10k 4.64k 931/uni03A9 22pF 10k 10k COUT3 100µF 0.01µF L1, L2: WÜRTH 744301033 C OUT1,3: MURATA GRM31CR60J107ME39L COUT2,4: SANYO 2R5TPE330M9 5V BIAS VIN FDMF6820A FDMF6820A PWM BOOT PWM BOOT COUT4 330µF Dual 1.5V/30A and 1.2V/30A LTC3774 Converter with DRMOS and DCR Temperature Coefficient Compensation

3774fc For more information www.linear .com/L TC3774 TYPICAL APPLICATIONS

3774 TA03

V OSNS2– VOSNS2+ TK/SS2 HIZB2 PWMEN2 PWM2 RUN2 GND ITEMP1 ITH1 V OSNS1– VOSNS1+ TK/SS1 HIZB1 PWMEN1 PWM1 RUN1 GND SNSD1+ SNS1– SNSA1+ PGOOD1 PGOOD2 SNSA2+ SNS2– SNSD2+ L TC3774 37.4k 3.01k 1µF 2.2/uni03A9 4.7µF VIN RUN1 INTVCC 330pF 0.01µF 22pF 10k 3.3nF 180µF 10k 10k 10k 10k VIN VIN 0.22µF 0.22µF 0.22µF 0.22µF VIN PHASE VSWH CGND PGND SMOD DISB V CIN VDRV 22µF 2.2µF 1/uni03A9 2.2µF 5V BIAS 22µF 10k VIN 7V TO 14V INTVCC INTVCC 0.22µF 0.33µH 10k 10k 4.64k 931/uni03A9 COUT1 100µF 1.2V/60A V OUT VIN PHASE VSWH CGND PGND SMOD DISB V CIN VDRV 22µF 2.2µF 1/uni03A9 2.2µF 22µF 0.22µF L2 0.33µH 10k 10k 4.64k 931/uni03A9 COUT2 330µF 5V BIAS VIN PWM BOOT FDMF6820A FDMF6820A PWM BOOT L1, L2: WÜRTH 744301033 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9 2-Phase 1.2V/60A LTC3774 Converter with DRMOS

3774fcFor more information www.linear .com/L TC3774 TYPICAL APPLICATIONS 2-Phase 1.2V/60A LTC3774 Converter with Discrete Drivers with MOSFETs

3774 TA04

V OSNS2– VOSNS2+ TK/SS2 HIZB2 PWMEN2 PWM2 RUN2 GND ITEMP1 ITH1 V OSNS1– VOSNS1+ TK/SS1 HIZB1 PWMEN1 PWM1 RUN1 GND SNSD1+ SNS1– SNSA1+ PGOOD1 PGOOD2 SNSA2+ SNS2– SNSD2+ L TC3774 37.4k 3.01k 1µF 2.2/uni03A9 4.7µF VIN RUN INTVCC 330pF 0.01µF 22pF 10k 3.3nF 180µF 10k 10k 100k 100k VIN VIN 0.22µF 4.7nF 1µF 0.22µF 0.22µF 0.22nF 0.22µF IN VLOGIC VCC BOOST GND BG TS TG 10k INTVCC VCC VIN 7V TO 14V VIN INTVCC 0.33µH L TC4449 4.64k 931/uni03A9 COUT1 COUT2 330µF 1.2V/60A V OUT 4.64k 931/uni03A9 22nF BSC050NE2LS BSC010NE2LS 4.7nF 1µF 0.22nF IN VLOGIC VCC BOOST GND BG TS TG VCC 22nF BSC050NE2LS BSC010NE2LS 0.33µH 2.2/uni03A9 2.2/uni03A9 L TC4449 L1, L2: WÜRTH 744301033 COUT1: MURATA GRM31CR60J107ME39L COUT2: SANYO 2R5TPE330M9

3774fc For more information www.linear .com/L TC3774 PACKAGE DESCRIPTION 36-Lead Plastic QFN (5mm × 6mm) (Reference L TC DWG # 05-08-1876 Rev Ø) 5.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 1020 1119 3629 BOTTOM VIEW—EXPOSED PAD 4.50 REF6.00 ±0.10 R = 0.125 TYP 0.25 ±0.05 4.60 ±0.10 3.60 ±0.10 (UHE36) QFN 0410 REV Ø

0.50 BSC

4.60 ±0.05 3.60 ±0.05 0.75 ±0.05 0.00 – 0.05

0.200 REF

RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.50 REF

0.40 ±0.10 0.70 ±0.05

4.50 REF

4.10 ±0.05 5.50 ±0.05 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.10 TYP Please refer to http://www.linear.com/product/LTC3774#packaging for the most recent package drawings.

3774fcFor more information www.linear .com/L TC3774 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/14 Replaced Undervoltage Lockout curve Revised Inductor DCR Sensing Temp Comp and NTC Compensated DCR Sensing sections 17, 18 B 07/15 Minor typographical changes Changed INTVCC pin description 3, 4, 6, 9 C 04/17 Claification on selecting DrMOS Devices 21

3774fc For more information www.linear .com/L TC3774  LINEAR TECHNOLOGY CORPORATION 2013 LT 0417 REV C • PRINTED IN USA www.linear .com/L TC3774 TYPICAL APPLICATION RELATED PARTS Dual Phase 1.2V/30A LTC3774 Converter with Hot Swap Circuits On the Input of Each Phase

3774 TA05

RUN1, 2 VIN INTVCC FREQ PHSMD TK/SS1,2 I TEMP1,2 VOSNS1,2+ VOSNS1,2– ITH1,2 ILIM1,2 ON1 CLS GND ON2 FTMR1 FAUL T1 FAUL T2 FTMR2 SNSD1 SNS1– SNSA1+ PGOOD1 PGOOD2 SNSA2 SNS2– SNSD2+ CLKOUT MODE/PLLIN L TC3774 L TC422664.9k 10k 0.007/uni03A9 FDMS86500DC D17 CMHZ4690 0.007/uni03A9 FDMS86500DC PWM2HIZB2 PWMEN2 PWM1HIZB1 HIZB1 HIZB2 1µF PWMEN1 GND 4.7µF 10k 0.1µF 37.4k 330pF L1, L2: WÜRTH 744301033 COUTCER1,2: MURATA GRM31CR60J107ME39L COUTBLK: SANYO 2R5TPE330M9 3.01k 2.2k 3.3nF 10k VCC2 SENSE2 GATE2 OUT2 V CC1 SENSE1 GATE1 OUT1 10k 10k 100pF 22µF 25V VIN 10V TO 14V 150µF 25V 5VBIAS VIN1 VIN2 30.1k 100pF 2.4M CMHZ4690 1N4448HWT 1N4448HWT PWM VIN BOOT PHASE VSWH FDMF6820 DrMOS 5V BIAS 1ΩCGND PGND VCIN VDRV 0.22µF 0.33µH 2.2µF 22µF 25V 2.2µF 0.22µF 0.22µF 0.22µF 0.22µF 931Ω 4.64k 931Ω 4.64k PWM VIN BOOT PHASE VSWH FDMF6820 DrMOS 5V BIAS 1ΩCGND PGND VCIN VDRV 0.22µF 2.2µF 22µF 25V 2.2µF COUTCER1 100µF 6.3V COUTCER1 330µF 2.5V V OUT 1.2V/30A 0.33µH COUTCER2 100µF 6.3V 1N4448HWT 1N4448HWT 1µF10k VIN1 VIN2 37.4k PART NUMBER DESCRIPTION COMMENTS LTM4630 LTM4630-1A LTM4630-1B Dual 18A or Single 36A DC/DC μModule Regulator 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V ±1.5% Max VOUT Error Over Line, Load and Temp –1A Version: ±0.8% Max VOUT Error Over Line, Load and Temp LTC3887 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management and ±0.5% Accuracy 4.5V≤ VIN ≤ 24V, 0.5V ≤ VOUT ≤ 5.5V, Analog Control Loop, 70ms Start-Up, I2C/PMBus Interface with EEPROM and 16-bit ADC LTC3875 Dual, Multiphase Synchronous Controller with Sub Milliohm DCR Sensing and Temperature Compensation 4.75V≤ V IN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V/5V Excellent Current Share when Paralleled LTC3861 Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Diff Amp and T ri-State Output Drive Operates with Power Blocks, DrMOS or External MOSFET s 3V≤ VIN ≤ 24V LTC3855 Dual Output, 2-phase, Synchronous Step-Down DC/DC Controller with Diff Amp and DCR Temperature Compensation 4.5V≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 12V PLL Fixed Frequency 250kHz to 770kHz, LTC3856 Single Output 2-Phase Synchronous Step-Down DC/DC Controller with Diff Amp and DCR T emperature Compensation 4.5V≤ VIN ≤ 38V, 0.8V≤ VOUT ≤ 5V PLL Fixed 250kHz to 770kHz Frequency LTC3838 Dual Output, 2-phase, Synchronous Step-Down DC/DC Controller with Diff Amp and Controlled On-T ime 4.5V≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.5V PLL, Up to 2MHz Switching Frequency LTC3869/ LTC3869-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller, with Accurate Current Share 4V≤ VIN ≤ 38V, VOUT3 up to 12.5V PLL Fixed 250kHz to 750kHz Frequency LTC4449 High Speed Synchronous N-Channel MOSFET Driver VIN up to 38V, 4V ≤ VCC ≤ 6.5V Adaptive Shoot-Through Protection, 2mm x 3mm DFN-8