LTM4643 LINER | Alldatasheet
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For more information www.linear.com/LTM4643 n Quad Output Step-Down µModule® Regulator with 3A per Output n Wide Input Voltage Range: 4V to 20V n 2.375V to 20V with External Bias n 0.6V to 3.3V Output Voltage n 3A DC Output Current Each Channel n ±1.5% Total Output Voltage Regulation n Current Mode Control, Fast T ransient Response n Parallelable for Higher Output Current n Output Voltage T racking n Internal Temperature Sensing Diode Output n External Frequency Synchronization n Overvoltage, Current and Temperature Protection n 9mm × 15mm × 1.82mm LGA and 9mm × 15mm × 2.42mm BGA Packages TYPICAL APPLICATION FEATURES DESCRIPTION Ultrathin Quad µModule Regulator with Configurable 3A Output Array The LT M®4643 is a quad DC/DC step-down µModule (power module) regulator with 3A per output. Outputs can be paralleled in an array for up to 12A capability. Included in the package are the switching controllers, power FETs, inductors and support components. Operating over an input voltage range of 4V to 20V or 2.375V to 20V with an external bias supply, the LTM4643 supports an output voltage range of 0.6V to 3.3V each set by a single external resistor . Its high efficiency design delivers 3A continuous output current per channel. Only bulk input and output capacitors are needed. Fault protection features include overvoltage, overcurrent and overtemperature protection. The LTM4643 is offered in a 9mm ×15mm × 1.82mm LGA and 9mm × 15mm × 2.42mm BGA packages with SnPb (BGA) or RoHS compli- ant terminal finish. Configurable Output Array* 12A * Note 4 1.5V Output Efficiency and Power Loss (Each Channel)
APPLICATIONS
n FPGAs, GPUs and ASICs Applications n PCIe and Backside PCB Mounting 4V to 20V Input, Quad 0.9V, 1V, 1.2V and 1.5V Output DC/DC µModule Regulator L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule, L TpowerCAD and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.
4643 TA01a
22µF 25V CLKOUT TEMP GND V OUT1 FB1 PGOOD1 VOUT2 FB2 PGOOD2 VOUT3 FB3 PGOOD3 VOUT4 FB4 PGOOD4 47µF 1.5V/3A4V to 20V 40.2k 47µF 1.2V/3A 60.4k 47µF 1V/3A 90.9k 47µF 0.9V/3A 121k NOT ALL PINS ARE SHOWN LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)
4643 TA01b
0.0 0.6 0.4 0.2 1.2 1.0 0.8 1.6 1.4 320.5 1.5 2.5 VIN = 5V VIN = 12V
For more information www.linear.com/LTM4643 ABSOLUTE MAXIMUM RATINGS 3V to 22V PGOOD, MODE, TRACK/SS, 3V to INTVCC Internal Operating Temperature Range (Notes 2, 5) C to 125°C C to 125°C C (Note 1) ORDER INFORMATION LGA PACKAGE (WEIGHT = 0.70g) 77-LEAD (9mm × 15mm × 1.82mm) BGA PACKAGE (WEIGHT = 0.83g) 77-LEAD (9mm × 15mm × 2.42mm) 1 2 3 4 5 6 7 B C D E F G H J K L A TOP VIEW VOUT1 SVIN1 MODE1 RUN1 COMP1 INTVCC1 GND PGOOD2 PGOOD1 INTVCC2PGOOD3 TEMP INTVCC3 PGOOD4 CLKOUT FB1 TRACK/SS1 GND CLKIN TRACK/SS2 FB2 RUN2 SGND TRACK/SS3 FB3 TRACK/SS4 INTVCC4 RUN4 MODE2 SVIN2 COMP2 RUN3 FB4 MODE3 SV IN3 COMP3 COMP4 MODE4SVIN4VIN4 VIN1 GND GND GND VIN3 VIN2 VOUT4 VOUT3 VOUT2 TJMAX = 125°C, θJCtop = 17°C/W , θJCbottom = 2.75°C/W , θJB + θBA = 11°C/W , θJA = 10°C/W θ VALUES PER JESD 51-12 PIN CONFIGURATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4643EV#PBF Au (RoHS) LTM4643V e4 LGA 3 –40°C to 125°C LTM4643IV#PBF Au (RoHS) LTM4643V e4 LGA 3 –40°C to 125°C LTM4643MPV#PBF Au (RoHS) LTM4643V e4 LGA 3 –55°C to 125°C LTM4643EY#PBF SAC305 (RoHS) LTM4643Y e1 BGA 3 –40°C to 125°C LTM4643IY#PBF SAC305 (RoHS) LTM4643Y e1 BGA 3 –40°C to 125°C LTM4643MPY#PBF SAC305 (RoHS) LTM4643Y e1 BGA 3 –55°C to 125°C LTM4643IY SnPb (63/37) LTM4643Y e0 BGA 3 –40°C to 125°C LTM4643MPY SnPb (63/37) LTM4643Y e0 BGA 3 –55°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Terminal Finish Part Markings: www.linear .com/leadfree
- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www .linear .com/umodule/pcbassembly
- Package and T ray Drawings: www.linear .com/packaging http://www.linear .com/product/LTM4643#orderinfo
For more information www.linear.com/LTM4643 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Regulator Section: per Channel VIN, SVIN Input DC Voltage SVIN = VIN l 4 20 V VOUT(RANGE) Output Voltage Range l 0.6 3.3 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF, COUT = 100µF Ceramic, RFB = 40.2k, MODE = INT V CC,VIN = 4V to 20V, IOUT = 0A to 3A (Note 4) l 1.477 1.50 1.523 V VRUN RUN Pin On Threshold VRUN Rising 1.1 1.2 1.3 V IQ(SVIN) Input Supply Bias Current V IN = 12V, VOUT = 1.5V, MODE = INTVCC VIN = 12V, VOUT = 1.5V, MODE = GND Shutdown, RUN = 0, VIN = 12V mA mA µA I S(VIN) Input Supply Current VIN = 12V, VOUT = 1.5V, IOUT = 3A 0.45 A IOUT(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Note 4) 0 3 A ΔVOUT (Line)/VOUT Line Regulation Accuracy V OUT = 1.5V, VIN = 4V to 20V, IOUT = 0A l 0.01 0.05 %/V ΔVOUT (Load)/VOUT Load Regulation Accuracy V OUT = 1.5V, IOUT = 0A to 3A l 0.5 1.0 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V 5 mV ΔVOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 100µF Ceramic, VIN = 12V, VOUT = 1.5V 30 mV tSTART Turn-On Time COUT = 100µF Ceramic, No Load, TRACK/SS = 0.01µF, VIN = 12V, VOUT = 1.5V 2.5 ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, C OUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V 160 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, C OUT = 47µF Ceramic, VIN = 12V, VOUT = 1.5V 40 µs IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V 3.5 5 A VFB Voltage at FB Pin IOUT = 0A, VOUT = 1.5V, –40°C to 125°C l 0.593 0.60 0.607 V IFB Current at FB Pin (Note 3) ±30 nA RFBHI Resistor Between VOUT and FB Pins 60.05 60.40 60.75 kΩ ITRACK/SS T rack Pin Soft-Start Pull-Up Current TRACK/SS = 0V 2.5 4 µA V IN(UVLO) VIN Undervoltage Lockout V IN Falling VIN Hysteresis 2.4 2.6 350 2.8 V mV tON(MIN) Minimum On-Time (Note 3) 40 ns tOFF(MIN) Minimum Off-Time (Note 3) 70 ns VPGOOD PGOOD T rip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –13 –10 I PGOOD PGOOD Leakage 2 µA VPGL PGOOD Voltage Low IPGOOD = 1mA 0.02 0.1 V VINTVCC Internal VCC Voltage SVIN = 4V to 20V 3.1 3.3 3.4 V VINTVCC Load Reg INTV CC Load Regulation I CC = 0mA to 20mA 0.5 % fOSC Oscillator Frequency 1.2 MHz CLKIN CLKIN Threshold 0.7 V
For more information www.linear.com/LTM4643 1.0V Output T ransient Response 1.2V Output T ransient Response 1.5V Output T ransient Response Efficiency vs Load Current from 5VIN (One Channel Operating) Efficiency vs Load Current from 12V IN (One Channel Operating) DCM Mode Efficiency from 1.5V OUT
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4643 is tested under pulsed load conditions such that T J ≈ TA. The LTM4643E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4643I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. The LTM4643MP is guaranteed to meet specifications over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level. Note 4: See output current derating curves for different V IN, VOUT and TA. Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT CURRENT (A) EFFICIENCY (%) 100 10.5 1.5
4643 G01
32 2.5 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT OUTPUT CURRENT (A) EFFICIENCY (%)70 10.5 1.5
4643 G02
32 2.5 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT LOAD CURRENT (A) 0.001 EFFICIENCY (%) 100 0.01
4643 G03
100.1 1 5VIN 12VIN VOUT 50mV/DIV AC-COUPLED LOAD STEP 1A/DIV VIN = 12V VOUT = 1.0V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV 4643 G04 (Per Channel) VOUT 50mV/DIV AC-COUPLED LOAD STEP 1A/DIV VIN = 12V VOUT = 1.2V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV
4643 G05
VIN = 12V VOUT = 1.5V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV
4643 G06
For more information www.linear.com/LTM4643 TYPICAL PERFORMANCE CHARACTERISTICS 1.8V Output T ransient Response 2.5V Output T ransient Response 3.3V Output T ransient Response Start-Up with No Load Applied Start-Up with 3A Load Applied Short-Circuit with No Load Applied VOUT 50mV/DIV AC-COUPLED LOAD STEP 1A/DIV VIN = 12V VOUT = 2.5V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV 4643 G08 VOUT 50mV/DIV AC-COUPLED LOAD STEP 1A/DIV VIN = 12V VOUT = 3.3V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV
4643 G09
0.5A/DIV VOUT 0.5V/DIV VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 1 × 22µF CERAMIC CAP OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP SOFT START = 0.1µF 5ms/DIV
4643 G10
0.5A/DIV VOUT 0.5V/DIV VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 1 × 22µF CERAMIC CAP OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP SOFT START = 0.1µF 5ms/DIV
4643 G11
0.5A/DIV VOUT 0.5V/DIV VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 1 × 22µF CERAMIC CAP OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP 5ms/DIV
4643 G12
VIN = 12V VOUT = 1.8V OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP LOAD STEP = 2A TO 3A WITH 1A/µS SLEW RATE FEED FORWARD CAP = 100pF 20µs/DIV
4643 G07
Short-Circuit with 3A Load Applied Short-Circuit with 3A Load Applied IIN 0.5A/DIV VOUT 0.5V/DIV VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 1 × 22µF CERAMIC CAP OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP 20µs/DIV 4643 G13 IIN 0.5A/DIV VOUT 0.5V/DIV VIN = 12V VOUT = 1.5V INPUT CAPACITOR = 1 × 22µF CERAMIC CAP OUTPUT CAPACITOR = 1 × 47µF CERAMIC CAP 20µs/DIV
4643 G14
VIN = 12V VOUT = 1.5V OUTPUT CAPACITOR = 2 × 47µF CERAMIC CAP 2µs/DIV 4643 G15
For more information www.linear.com/LTM4643 PIN FUNCTIONS VOUT1 (A1, A2, A3), V OUT2 (C1, D1, D2), V OUT3 (F1, G1, G2), VOUT4 (J1, K1, K2): Power Output Pins of Each Switching Mode Regulator Channel. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See the Applications Information section for paralleling outputs. GND (A4-A5, B1-B2, C5, D3-D5, E1-E2, F5, G3-G5, H1-H2, J5, K3-K4, L1-L2): Power Ground Pins for Both Input and Output Returns. Use large PCB copper areas to connect all GND together . V IN1 (B3, B4), VIN2 (E3, E4), VIN3 (H3, H4), VIN4 (L3, L4): Power input pins connect to the drain of the internal top MOSFET for each switching mode regulator channel. Apply input voltages between these pins and GND pins. Recommend placing input decoupling capacitance directly between each of V IN pins and GND pins. PGOOD1, PGOOD2, PGOOD3, PGOOD4 (C3, C2, F2, J2): Output Power Good with Open-Drain Logic of Each Switching Mode Regulator Channel. PGOOD is pulled to ground when the voltage on the FB pin is not within ±10% of the internal 0.6V reference. CLKOUT (J3): Output Clock Signal for PolyPhase ® Opera- tion of the Module. The phase of CLKOUT with respect to CLKIN is set to 180° . CLKOUT’s peak-to-peak amplitude is INTVCC to GND. See the Application Information section for details. Strictly output; do not drive this pin. INTVCC1, INTVCC2, INTVCC3, INTVCC4 (C4, F4, J4, K5): Internal 3.3V Regulator Output of Each Switching Mode Regulator Channel. The internal power drivers and con - trol circuits are powered from this voltage. Each pin is internally decoupled to GND with 1µF low ESR ceramic capacitor already. SVIN1, SVIN2, SVIN, SVIN4 (B5, E5, H5, L5): Signal V IN. Filtered input voltage to the internal 3.3V regulator for the control circuitry of each Switching mode Regulator Channel. Tie this pin to the V IN pin respectively in most applications. Connect SVIN to an external voltage supply of at least 4V which must also be greater than VOUT. TRACK/SS1, TRACK/SS2, TRACK/SS3, TRACK/SS4 (A6, D6, G6, K6): Output T racking and Soft-Start Pin of Each Switching Mode Regulator Channel. Allows the user to control the rise time of the output voltage. Putting a volt- age below 0.6V on this pin bypasses the internal reference input to the error amplifier , instead it servos the FB pin to match the TRACK voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier . There’s an internal 2.5µA pull-up current from INTV CC on this pin, so putting a capacitor here provides soft-start function. MODE1, MODE2, MODE3, MODE4 (B6, E6, H6, L6): Operation Mode Select for Each Switching Mode Regula- tor Channel. Tie this pin to INTV CC to force continuous synchronous operation at all output loads. Tying it to SGND enables discontinuous current mode operation at light loads. Do not leave floating. RUN1, RUN2, RUN3, RUN4 (C6, F6, J6, K7): Run Control Input of Each Switching Mode Regulator Channel. Enable regulator operation by tying the specific RUN pin above 1.2V. Pulling it below 1.1V shuts down the respective regulator channel. Do not leave floating. FB1, FB2, FB3, FB4 (A7, D7, G7, J7): The Negative Input of the Error Amplifier for Each Switching Mode Regulator Channel. Internally, this pin is connected to V OUT of each channel with a 60.4kΩ precision resistor . Different output voltages can be programmed with an additional resistor between the FB and GND pins. In PolyPhase operation, tying the FB pins together allows for parallel operation. See the Applications Information section for details. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .
For more information www.linear.com/LTM4643 PIN FUNCTIONS COMP1, COMP2, COMP3, COMP4 (B7, E7, H7, L7): Cur- rent Control Threshold and Error Amplifier Compensation Point of Each Switching Mode Regulator Channel. The internal current comparator threshold is proportional to this voltage. Tie the COMP pins together for parallel opera- tion. The device is internally compensated. CLKIN ( C7): External Synchronization Input to Phase Detector of the Module. This pin is internally terminated to SGND with 20kΩ. The phase-locked loop will force the channel 1 turn-on signal to be synchronized with the rising edge of the CLKIN signal. Channel 2, channel 3 and channel 4 will also be synchronized with the rising edge of the CLKIN signal with a pre-determined phase shift. See the Applications Information section for details. SGND (F7): Signal Ground Connection. SGND is connected to GND internally through single point. Use a separated SGND ground copper area for the ground of the feedback resistor and other components connected to signal pins. A second connection between the PGND plane and SGND plane is recommended on the backside of the PCB under- neath the module. TEMP (F3): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section.
For more information www.linear.com/LTM4643 BLOCK DIAGRAM 4643 BD POWER CONTROL CLKOUT FB1 CLKIN MODE1 TRACK/SS1 RUN1 COMP1 INTV CC1 INTERNAL FIL TER INTERNAL COMP VOUT1 1µF 0.22µF 1µH 100k 100k 100k 100k 10µF 47µF FREQ1 133k 60.4k 60.4k 0.1µF VIN 4V TO 20V VOUT1 1.2V INTVCC1 PGOOD1 SVIN1 VIN1 VOUT1 GND SGND GND POWER CONTROL FB2 MODE2 TRACK/SS2 RUN2 COMP2 INTV CC2 INTERNAL FIL TER INTERNAL COMP VOUT2 1µF 0.22µF 1µH 10µF 47µF FREQ2 133k 60.4k 40.2k 0.1µF VIN VOUT2 1.5V INTVCC2 PGOOD2 SVIN2 VIN2 VOUT2 GND POWER CONTROL FB3 MODE3 TRACK/SS3 RUN3 COMP3 INTVCC3 INTERNAL FIL TER INTERNAL COMP VOUT3 1µF 0.22µF 1µH 10µF 47µF FREQ3 133k 60.4k 30.1k 0.1µF VIN VOUT3 1.8V INTVCC3 PGOOD3 SVIN3 VIN3 VOUT3 GND POWER CONTROL FB4 MODE4 TRACK/SS4 RUN4 COMP4 INTVCC4 INTERNAL FIL TER INTERNAL COMP VOUT4 1µF 0.22µF 1µH 10µF 47µF 1µF FREQ4 133k 60.4k 90.9k 0.1µF VIN VOUT4 INTVCC4 PGOOD4 SVIN4 VIN4 VOUT4 GND TEMP CLKOUT CLKOUT CLKIN CLKOUT CLKIN CLKOUT CLKIN 1µF 1µF 1µF
For more information www.linear.com/LTM4643 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4V to 20V, VOUT = 1.5V) IOUT = 3A 4.7 10 µF COUT External Output Capacitor Requirement IN = 4V to 20V, VOUT = 1.5V) IOUT = 3A 22 47 µF DECOUPLING REQUIREMENTS OPERATION The LTM4643 is a quad output standalone non-isolated switch mode DC/DC power supply in 9mm × 15mm × 1.82mm ultrathin package. It has four separate regula- tor channels with each of them capable of delivering up to 3A continuous output current with few external input and output capacitors. Each regulator provides precisely regulated output voltage programmable from 0.6V to 3.3V via a single external resistor over 4V to 20V input voltage range. With an external bias voltage, this module can operate from an input voltage as low as 2.375V. The typical application schematic is shown in Figure 29. The LTM4643 integrates four separate constant frequency controlled on-time valley current mode regulators, power MOSFETs, inductors, and other supporting discrete com- ponents. The typical switching frequency is set to 1.2MHz. For switching noise-sensitive applications, the µModule regulator can be externally synchronized to a clock from 850kHz to 1.5MHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4643 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides the flexibility of paralleling any of the separate regulator channels with accurate cur- rent sharing. With a built-in clock interleaving between regulator channels, the LTM4643 can easily be configured for 2+2, 3+1 or 4 channels parallel operation providing more design flexibility for multirail POL applications. Fur- thermore, the LTM4643 has CLKIN and CLKOUT pins for frequency synchronization or polyphasing multiple devices which allow up to 8 phases cascaded to run simultaneously. Current mode control also provides cycle-by-cycle fast current monitoring. Foldback current limiting is provided in an overcurrent condition to reduce the inductor valley current to approximately 40% of the original value when V FB drops. An internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Continuous conduction mode (CCM) operation is forced during OV and UV conditions except during start-up when the TRACK pin is ramping up to 0.6V. Pulling the RUN pin below 1.1V forces the controller into its shutdown state, turning off both power MOSFETs and most of the internal control circuitry. At light load cur - rents, discontinuous conduction mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous conduction mode (CCM) by setting the MODE pin to SGND. The TRACK/SS pin is used for power supply tracking and soft-start programming. See the Applications Information section. A temperature diode is included inside the module to moni- tor the temperature of the module. See the Applications Information section for details. (per Channel)
Figure 29. External component selection is primarily and Output Current Derating section in this data sheet. The PWM controller has an internal 0.6V reference voltage. Table 1. VFB Resistor Table vs Various Output Voltages inductive leads, traces or not enough source capacitance. where η% is the estimated efficiency of the power module. of phases implemented increases by N times.
output voltage is in regulation. applications, no additional frequency adjusting is required. synchronized to a clock from 850kHz to 1.5MHz. control to maintain output voltage regulation at no load. be locked to the rising edge of the same external clock. the regulator , the phase-locked loop function is disabled. difference between regulator channels. Table 2. Phase Difference Between Regulator Channels schematic for clock phasing. than the number of phases used times the output voltage). to achieve a single high output current design.
Figure 2. Normalized RMS Ripple Current for Single Phase or Polyphase Applications reduction as a function of the number of interleaved phases.
4643 F02
Figure 1. 2+2 and 4 Channels Parallel Concept Schematic
4643 F01
during the soft-start process. proportional to the master’s (VOUT1).
4643 F04
4643 F03TIME
Figure 3. Output Ratiometric T racking Waveform Figure 4. Output Ratiometric T racking Schematic the following equation during the start-up.
the slave regulator , as shown in Figure 4. Figure 4. From the equation, we could solve out that offset to a negligible value. slew rate (SR), as waveform shown in Figure 5. = 3.3V and VOUT(SL) = 1.2V application. phase margin in all ceramic output capacitors application. power MOSFETs and most of its internal control circuitry. will turn on the entire regulator channel. Figure 5. Output Coincident T racking Waveform
4643 F05TIME
For more information www.linear.com/LTM4643 APPLICATIONS INFORMATION Pre-Biased Output Start-Up There may be situations that require the power supply to start up with some charge on the output capacitors. The LTM4643 can safely power up into a pre-biased output without discharging it. The LTM4643 accomplishes this by forcing discontinuous mode (DCM) operation until the TRACK/SS pin voltage reaches 0.6V reference voltage. This will prevent the BG from turning on during the pre-biased output start-up which would discharge the output. Do not pre-bias LTM4643 with an output voltage higher than INTV CC (3.3V). Overtemperature Protection The internal overtemperature protection monitors the junc- tion temperature of the module. If the junction temperature reac hes approximately 160°C, both power switches will be turned off until the temperature drops about 15°C cooler . Low Input Application The LTM4643 module has a separate SV IN pin for each regulator channel which makes it compatible with opera- tion from an input voltage as low as 2.375V. The SVIN pin is the signal input of the regulator control circuitry while the VIN pin is the power input which directly connected to the drain of the top MOSFET . In most application with input voltage ranges from 4V to 20V, connect the SV IN pin directly to the V IN pin of each regulator channel. An optional filter , consisting of a resistor (1Ω to 10Ω) between SVIN and VIN ground, can be placed for additional noise immunity. This filter is not necessary in most cases if good PCB layout practices are followed (see Figure 28). In a low input voltage (2.375V to 4V) application, or to reduce power dissipation by the internal bias LDO, connect SV IN to an external voltage higher than 4V with a 0.1µF local bypass capacitor . Figure 30 shows an example of a low input voltage application. Please note, SV IN voltage cannot go below VOUT voltage. Temperature Monitoring A diode connected PNP transistor is used for the TEMP monitor function by monitoring its voltage over tempera- ture. The temperature dependence of this diode voltage can be understood in the equation: VD = nVT ln ID IS where VT is the thermal voltage (kT/q), and n, the ideality factor , is 1 for the diode connected PNP transistor be- ing used in the LTM4643. I S is expressed by the typical empirical equation: IS = I0 exp –VG0 VT where I0 is a process and geometry dependent current, (I0 is typically around 20k orders of magnitude larger than IS at room temperature) and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero or –273°C. If we take the IS equation and substitute into the VD equa- tion, then we get: VD = VG0 – kT q ln I0 ID , VT = kT q The expression shows that the diode voltage decreases (linearly if I0 were constant) with increasing temperature and constant diode current. Figure 6 shows a plot of V D vs Temperature over the operating temperature range of the LTM4643. If we take this equation and differentiate it with respect to temperature T , then: dVD dT = – VG0 – VD T This dVD/dT term is the temperature coefficient equal to about –2mV/K or –2mV/°C. The equation is simplified for the first order derivation. Solving for T , T = –(V G0 – V D)/(dVD/dT) provides the temperature.
Kelvin temp and subtracting 273 from it. temperature will provide a general temperature monitor . rent to 100µA. See Figure 31 for an example. Electronic Package Thermal Information”). thermal performance to one’s own application. conditions don’t generally match the user’s application.
- θJCtop, the thermal resistance from junction to top of
Figure 6. Diode Voltage VD vs Temperature T(°C)
4643 F06
Array Surface Mount Package Thermal Measurements”).
Figure 7. Graphical Representation of JESD 51-12 Thermal Coefficients
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conditions don’t generally match the user’s application. resistances are external to the µModule package. airflow, a majority of the heat flow is into the board.
For more information www.linear.com/LTM4643 as that which was simulated. An outcome of this process and due diligence yields the set of derating curves shown in this data sheet. The 1V to 3.3V power loss curves in Figures 8 to 13 can be used in coordination with the load current derating curves in Figures 14 to 25 for calculating an approximate θ JA thermal resistance for the LTM4643 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a multi- plicative factor according to the junction temperature. This approximate factor is 1.3 for 120°C . The derating curves are plotted with the output current starting at 12A and the ambient temperature starting at 30°C. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal mod- eling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow . The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operat- ing temperature specifies how much module temperature rise can be allowed. As an example, in Figure 19 the load current is derated to 10A at ~67°C with 200LFM of airflow and no heat sink and the power loss for the 12V to 1.5V at 10A output is about 4.5W. The 4.5W loss is calculated with 4 times the 0.87W room temperature loss from the 12V to 1.5V power loss curve each channel at 2.5A, and the 1.3 multiplying factor at 120°C junction. If the 67°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 53°C divided by 4.5W equals 11.7°C/W θ JA thermal resistance. Table 3 specifies a 12°C/W value which is very close. Tables 3 to 5 provide equivalent thermal resistances for the different outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 3 to 6 for the various condi- tions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the T ypical Performance Characteristics section and adjusted with the above junction temperature multiplicative factor . The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The 12A represents all four channels in parallel at 3A each. The four parallel channels have their currents reduced at the same rate to develop an equivalent θ JA circuit evalu- ation with thermal couples or IR camera used to validate the thermal resistance values. Maximum Operating Ambient Temperature Figures 26 and 27 display the Maximum Power Loss Allowance Cur ves vs ambient temperature with various heat sinking and airflow conditions. This data was derived from the thermal impedance generated by various ther - mal derating examinations with the junction temperature measured at 120°C . This maximum power loss limitation serves as a guideline when designing multiple output rails with different voltages and currents by calculating the total power loss. For example, to determine the maximum ambient tem - perature when V OUT1 = 2.5V at 0.6A, VOUT2 = 3.3V at 3A, VOUT3 = 1.8V at 1A, V OUT4 = 1.2V at 3A, without a heat sink and 400LFM airflow, simply add up the total power loss for each channel read from Figure 8 to Figure 13 which in this example equals 3.0W, then multiply by the 1.3 coefficient for 120°C junction temperature and com- pare the total power loss number , 3.9W, with Figure 26. Figure 26 indicates with a 3.9W total power loss, the maximum ambient temperature for this particular ap - plication is around 77°C. Also from Figure 26, it is easy to determine with a 3.4W total power loss, the maximum ambient temperature is around 63°C with no airflow and 73°C with 200LFM airflow. APPLICATIONS INFORMATION
Figure 8. Power Loss at 1.0V
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Figure 9. Power Loss at 1.2V Figure 10. Power Loss at 1.5V Figure 11. Power Loss at 1.8V Figure 12. Power Loss at 2.5V Figure 13. Power Loss at 3.3V
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Figure 14. 5VIN to 1.0VOUT Derating
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Figure 15. 12VIN to 1.0VOUT Derating Figure 16. 5VIN to 1.0VOUT Derating Figure 17. 12V Figure 18. 5V Figure 19. 12V Figure 20. 5V
Figure 21. 12VIN to 1.5VOUT Derating Figure 22. 5VIN to 3.3VOUT Derating Figure 23. 12V Figure 24. 5V
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Figure 25. 12VIN to 3.3VOUT Derating Figure 26. Power Loss Allowance vs. Figure 27. Power Loss Allowance vs.
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Table 3. 1.0V Output Table 4. 1.5V Output Table 5. 3.3V Output
For more information www.linear.com/LTM4643 APPLICATIONS INFORMATION VOUT (V) CIN (CERAMIC) (µF) COUT1 (µF) CFF (pF) VIN (V) DROOP (mv) P-P DERIVA TION (mV) RECOVERY TIME (µs) LOAD STEP (A) LOAD STEP SLEW RATE (A/µs) RFB (kΩ) CERAMIC ONL Y 1 10 47 100 5, 12 1 59 40 2A to 3A 0 90.9 1.2 10 47 100 5, 12 1 59 40 2A to 3A 0 60.4 1.5 10 47 100 5, 12 1 66 40 2A to 3A 0 40.2 1.8 10 47 100 5, 12 1 75 40 2A to 3A 0 30.1 2.5 10 47 100 5, 12 2 108 50 2A to 3A 0 19.1 3.3 10 47 100 5, 12 3 111 60 2A to 3A 0 13.3 POSCAP 1 10 100 5, 12 1 89 40 2A to 3A 0 90.9 1.2 10 100 5, 12 1 94 40 2A to 3A 0 60.4 1.5 10 100 5, 12 1 108 40 2A to 3A 0 40.2 1.8 10 100 5, 12 1 120 40 2A to 3A 0 30.1 2.5 10 100 5, 12 2 144 50 2A to 3A 0 19.1 3.3 10 100 5, 12 3 161 60 2A to 3A 0 13.3 Table 6 CIN PART NUMBER VALUE C OUT1 (CERAMIC) PART NUMBER VALUE C OUT1 (POSCAP) PART NUMBER VALUE Murata GRM21BR61E106KA73L 10µF, 25V, 0805, X5R Murata GRM21BR60J476ME15 47µF, 6.3V, 0805, X5R Sanyo 4TPE100MZB 4V 100µF Taiyo Yuden TMK212BBJ106KG-T 10µF, 25V, 0805, X5R Taiyo Yuden JMK212BJ476MG-T 47µF, 6.3V, 0805, X5R Murata GRM31CR61C226ME15L 22µF, 25V, 1206, X5R Taiyo Yuden TMK316BBJ226ML-T 22µF, 25V, 1206, X5R
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Figure 31. 4V to 20V Input, 4-Phase, 1.2V at 12A Design with Temperature Monitoring
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Figure 32. 12V and 5V T wo Separate Input Rails, 1.2V at 6A and 3.3V at 6A Output
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For more information www.linear.com/LTM4643 LTM4643 Component LGA and BGA Pinout PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 V OUT1 B1 GND C1 V OUT2 D1 V OUT2 E1 GND F1 V OUT3 A2 V OUT1 B2 GND C2 PGOOD2 D2 V OUT2 E2 GND F2 PGOOD3 A3 V OUT1 B3 V IN1 C3 PGOOD1 D3 GND E3 V IN2 F3 TEMP A4 GND B4 V IN1 C4 INTV CC1 D4 GND E4 V IN2 F4 INTV CC2 A5 GND B5 SV IN1 C5 GND D5 GND E5 SV IN2 F5 GND A6 TRACK/SS1 B6 MODE1 C6 RUN1 D6 TRACK/SS2 E6 MODE2 F6 RUN2 A7 FB1 B7 COMP1 C7 CLKIN D7 FB2 E7 COMP2 F7 SGND PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 V OUT3 H1 GND J1 V OUT4 K1 V OUT4 L1 GND G2 V OUT3 H2 GND J2 PGOOD4 K2 V OUT4 L2 GND G3 GND H3 V IN3 J3 CLKOUT K3 GND L3 V IN4 G4 GND H4 V IN3 J4 INTV CC3 K4 GND L4 V IN4 G5 GND H5 SV IN3 J5 GND K5 INTV CC4 L5 SV IN4 G6 TRACK/SS3 H6 MODE3 J6 RUN3 K6 TRACK/SS4 L6 MODE4 G7 FB3 H7 COMP3 J7 FB4 K7 RUN4 L7 COMP4
For more information www.linear.com/LTM4643 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4643#packaging for the most recent package drawings. 77-Lead (15.00mm × 9.00mm ×1.82mm) (Reference L TC DWG # 05-08-1508 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 77-Lead (15.00mm × 9.00mm × 1.82mm) (Reference LTC DWG# 05-08-1508 Rev Ø) D E LGA 77 0715 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PACKAGE BOTTOM VIEW SEE NOTES A B C D E F G H J K L PIN 1 e b F G 7 6 5 4 3 2 1 SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 ±0.025 Ø 77x SEE NOTES DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A SYMBOL A b D E e F G aaa bbb eee MIN 1.72 0.60 0.27 1.45 NOM 1.82 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 MAX 1.92 0.66 0.37 1.55 0.15 0.10 0.15 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 77 0.630 ±0.025 Ø 77x S Y XZ Ø eee DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. PAD FINISH: Au DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y
For more information www.linear.com/LTM4643 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4643#packaging for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 77-Lead (15.00mm × 9.00mm × 2.42mm) (Reference LTC DWG# 05-08-1559 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (77 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.22 0.50 1.72 0.60 0.60 0.27 1.45 NOM 2.42 0.60 1.82 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 1.50 MAX 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 77 D E // bbb Z Z BGA 77 0916 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PACKAGE BOTTOM VIEW SEE NOTES A B C D E F G H J K L PIN 1 e b F G 7 6 5 4 3 2 1 SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 ±0.025 Ø 77x AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES
For more information www.linear.com/LTM4643 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 03/17 Added the BGA package 1, 2, 28, 30 B 6/17 Corrected Output Current from 4A to 3A on Figure 4 Corrected Output Voltage from 1.2V to 1.0V on Title of Figure 29
For more information www.linear.com/LTM4643 LINEAR TECHNOLOGY CORPORATION 2016 LT 0617 REV B • PRINTED IN USA www.linear .com/L TM4643 SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
- Selector Guides
- Demo Boards and Gerber Files
- Free Simulation Tools Manufacturing:
- Quick Start Guide
- PCB Design, Assembly and Manufacturing Guidelines
- Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PACKAGE PHOTOS RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4644 Higher Power , Quad Quad 4A, Pin Compatible, 9mm × 15mm × 5.01mm BGA 6.25mm × 2.42mm BGA LTM4631 Higher Power , Dual, Ultrathin Dual 10A or Single 20A, , 16mm × 16mm × 1.91mm LGA DESIGN RESOURCES