LTM4636

LTM4647 LINER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 34

Technical content

4647fbFor more information www.linear .com/L TM4647 TYPICAL APPLICATION FEATURES DESCRIPTION 30A DC/DC Step-Down µModule Regulator The LT M®4647 is a complete 30A output switching mode step-down DC/DC µModule ® (power module) regulator. Included in the package are the switching controller, power FETs, inductor and all supporting components. Operating over an input voltage range of 4.7V to 15V, the LTM4647 supports an output voltage range of 0.6V to 1.8V, set by a single external resistor. Only a few input and output capacitors are needed. Its high efficiency design delivers 87% efficiency from 12V input to 1.0V output with 30A continuous load current. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, programmable multiphase operation, N+1 phase redundancy, and output voltage tracking for supply rail sequencing. Fault protection features include overvoltage and overcur- rent protection. The power module is offered in a space saving 9mm × 15mm × 5.01mm BGA package. The LTM4647 is available with SnPb (BGA) or RoHS compli- ant terminal finish. 12VIN, 1VOUT, 30A DC/DC µModule Regulator

APPLICATIONS

n 4.7V to 15V Input Voltage Range n 0.6V to 1.8V Output Voltage Range n 30A DC Output Current n ±1.2% Total DC Output Voltage Error (–40°C to 125°C) n High Reliability N + 1 Phase Redundancy Supported n Internal or External Control Loop Compensation n Differential Remote Sense Amplifier for Precision Regulation n Current Mode Control/Fast T ransient Response n Multiphase Current Sharing Up to 180A n Built-In Temperature Monitoring n Selectable Pulse-Skipping, Burst Mode® Operation n Soft-Start/Voltage T racking n Frequency Synchronization n Output Overvoltage Protection n Output Overcurrent Foldback Protection n 9mm × 15mm × 5.01mm BGA Package n Telecom, Networking and Industrial Equipment n Point-of-Load Regulation L, LT, LT C, LT M, Linear Technology, the Linear logo, Burst Mode, µModule, L TpowerCAD and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. 1VOUT Efficiency vs Load Current LOAD CURRENT (A) *5V INPUT SEE FIGURE 24 EFFICIENCY (%)

4647 TA01b

5V INPUT* 12V INPUT HIZB VIN SVIN FREQ COMPa COMPb TRACK/SS PINS NOT USED IN THIS CIRCUIT : CLKOUT , MODE/PLLIN, PGOOD, PHASMD, PWM, RUN, SW , TEMP +, TEMP– VOUT VOSNS+ VFB VOSNS– 22µF 25V 2.2/uni03A9 4.7µF 6.3V 1µF 0.1µF VIN 6V TO 15V 43.2k DRVCC INTVCC L TM4647 SGND GND 90.9k

4647 TA01a

100µF 6.3V 47pF VOUT 30A

4647fb For more information www.linear .com/L TM4647 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS MODE/PLLIN, TRACK/SS, VOSNS+, VOSNS–, CLKOUT, COMPa, COMPb, VFB, PHASMD, 0.3V to INTVCC Internal Operating Temperature Range (Note 2) ....–4 0 to 125°C 55 to 125°C (Note 1) BGA PACKAGE 77-LEAD (9mm × 15mm × 5.01mm) VIN DRVCC VOUT GND GND GND L K J H G F E D C B A 2 3 4 GND PWM CLKOUT TEST1 MODE/PLLIN PHASMD INTVCC FREQ SGND TEST3 PGOOD COMPb GND GND SV IN HIZB GND RUN 5 6 7 TOP VIEW VFB VOSNS+ COMPa TEST2 VOSNS– TEMP– TEMP+ TRACK/SSSW TJ(MAX) = 125°C, θJA = 9.5°C/W , θJCbottom = 4°C/W , θJCtop = 6.7°C/W , θJB = 4.5°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH SIX LAYERS; WEIGHT = 2g θ VALUES DETERMINED PER JESD51-12 PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RA TING TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE LT M4647EY#PBF SAC305 (RoHS) LT M4647Y e1 BGA 3 –40°C to 125°C LT M4647IY#PBF SAC305 (RoHS) LT M4647Y e1 BGA 3 –40°C to 125°C LT M4647IY SnPb (63/37) LT M4647Y e0 BGA 3 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking: www.linear .com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www .linear .com/umodule/pcbassembly
• LGA and BGA Package and T ray Drawings: www.linear .com/packaging ORDER INFORMATION http://www.linear.com/product/LTM4647#orderinfo

4647fbFor more information www.linear .com/L TM4647 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage VIN = 4.7V to 6V per Figure 24 Schematic VIN = 6V to 15V per Figure 23 Schematic l 4.7 15 V VOUT(RANGE) Output Voltage Range V IN = 4.7V to 15V l 0.6 1.8 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 4, COUT = 100µF Ceramic, 470µF POSCAP, RFB = 60.4k, MODE = GND,VIN = 4.7V to 15V, IOUT = 0A to 30A l 1.196 1.186 1.200 1.200 1.204 1.214 V V Input Specifications I Q(VIN) Input Supply Bias Current V IN = 12V, VOUT = 1.2V, Burst Mode Operation, IOUT = 0A VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode, IOUT = 0A VIN = 12V, VOUT = 1.2V, Switching Continuous, IOUT = 0A Shutdown, RUN = 0, VIN = 12V 130 mA mA mA µA I S(VIN) Input Supply Current V IN = 12V, VOUT = 1.2V, IOUT = 30A 3.6 A Output Specifications IOUT(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.2V (Note 4) 0 30 A ∆VOUT(LINE)/VOUT Line Regulation Accuracy V OUT = 1.2V, VIN from 4.7V to 15V, IOUT = 0A l 0.005 0.02 %/V ∆VOUT(LOAD)/ VOUT Load Regulation Accuracy V OUT = 1.2V, IOUT = 0A to 30A, VIN = 12V (Note 4) l 0.1 0.3 % VOUT(AC) Output Ripple Voltage COUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V, IOUT = 0A 15 mV ∆VOUT(START) Turn-On Overshoot COUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V, IOUT = 0A 20 mV tSTART Turn-On Time COUT = 100µF Ceramic × 6 VIN = 12V, VOUT = 1.2V, No Load, TRACK/SS = 0.01µF 5 ms ∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V 36 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 6, VIN = 12V, VOUT = 1.2V 15 µs IOUTPK Output Current Limit V IN = 12V, VOUT = 1.2V 34 A Control Specifications VFB Voltage at VFB Pin IOUT = 0A, VOUT = 1.2V l 597.5 595 600 600 602.5 605 mV IFB Current at VFB Pin (Note 7) –30 –100 nA ITRACK/SS T rack Pin Soft-Start Pull-Up Current TRACK/SS = 0V 1.25 µA t ON(MIN) Minimum On-Time (Notes 3, 7) 90 ns RFBHI Resistor Between VOUT_LCL and VFB Pins 60.05 60.40 60.75 kΩ VRUN RUN Pin On Threshold V RUN Rising 1.2 1.35 1.45 V VRUNHYS RUN Pin On Hysteresis 180 mV UVLO Undervoltage Lockout V INTVCC Falling 4 V UVLOHYS UVLO Hysteresis 300 mV VHIZB HIZB Pin On Threshold V HIZB Rising 2.3 V VHIZBHYS HIZB Pin On Hysteresis 800 mV

4647fb For more information www.linear .com/L TM4647 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, per the typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PGOOD RPGOOD PGOOD Pull-Down Resistance 90 200 Ω VPGOOD PGOOD T rip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –7.5 7.5 VPGL PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Internal VCC Voltage VIN ≥ 12V 5.3 5.5 5.7 V VINTVCC Load Reg INTV CC Load Regulation I CC = 0mA to 10mA 0.5 % Oscillator and Phase-Locked Loop fSYNC SYNC Capture Range 400 800 kHz fSW Switching Frequency R FREQ = 47.5kΩ 540 600 660 kHz IFREQ FREQ Pin Current VFREQ = 0.8V 20 µA RMODE_PLLIN Mode_PLLIN Input Resistance 250 kΩ VIH_MODE_PLLIN Clock Input Level High 2.0 V VIL_MODE_PLLIN Clock Input Level Low 1.2 V θCLKOUT CLKOUT to SW Phase Delay V PHSMD = 0V VPHSMD = 1/4 INTVCC VPHSMD = Float VPHSMD = 3/4 INTVCC VPHSMD = INTVCC 120 180 Deg Deg Deg Deg Deg Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4647 is tested under pulsed load conditions such that T J ≈ TA. The LTM4647E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4647I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of IMAX Load. (See the Applications Information section) Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: Limit current into the RUN pin to less than 2mA. Note 6: Guaranteed by design. Note 7: 100% tested at wafer level.

4647fbFor more information www.linear .com/L TM4647 TYPICAL PERFORMANCE CHARACTERISTICS 0.8V Output Load Stop T ransient Response 1V Output Load Step T ransient Response 1.2V Output Load Step T ransient Response 1.5V Output Load Step T ransient Response Efficiency vs Output Current, V IN = 5V Efficiency vs Output Current, V IN = 12V CCM, Burst Mode and Pulse- Skipping Mode Efficiency V IN = 12V, VOUT = 1.2V, 500kHz LOAD CURRENT (A) EFFICIENCY (%) 100 2010 25

4647 G01

0.8VOUT, 400kHz 1VOUT, 500kHz 1.2VOUT, 500kHz 1.5VOUT, 600kHz 1.8VOUT, 700kHz LOAD CURRENT (A) EFFICIENCY (%) 100 2010 25

4647 G02

0.8VOUT, 400kHz 1VOUT, 500kHz 1.2VOUT, 500kHz 1.5VOUT, 600kHz 1.8VOUT, 700kHz LOAD CURRENT (A) EFFICIENCY (%)

4647 G03

0.1 10 1001 CCM Burst Mode OPERATION PULSE-SKIPPING MODE

4647 G07

VIN = 12V , VOUT = 1.5V , FS = 600kHz COUT = 6 × 100µF CERAMIC 0A to 7.5A LOAD STEP , 10A/µs 20µs/DIV VOUT 50mV/DIV AC-COUPLED LOAD STEP 10A/DIV SW 20V/DIV 1.8V Output Load Step T ransient Response

4647 G08

VIN = 12V , VOUT = 1.8V , FS = 700kHz COUT = 6 × 100µF CERAMIC 0A to 7.5A LOAD STEP , 10A/µs 20µs/DIV VOUT 50mV/DIV AC-COUPLED LOAD STEP 10A/DIV SW 20V/DIV

4647 G04

VIN = 12V , VOUT = 0.8V , FS = 400kHz COUT = 6 × 100µF CERAMIC 0A to 7.5A LOAD STEP , 10A/µs 20µs/DIV VOUT 50mV/DIV AC-COUPLED SW 20V/DIV LOAD STEP 10A/DIV

4647 G05

VIN = 12V , VOUT = 1V , FS = 500kHz COUT = 6 × 100µF CERAMIC 0A to 7.5A LOAD STEP , 10A/µs 20µs/DIV VOUT 50mV/DIV AC-COUPLED LOAD STEP 10A/DIV SW 20V/DIV

4647 G06

VIN = 12V , VOUT = 1.2V , FS = 500kHz COUT = 6 × 100µF CERAMIC 0A to 7.5A LOAD STEP , 10A/µs 20µs/DIV VOUT 50mV/DIV AC-COUPLED LOAD STEP 10A/DIV SW 20V/DIV

4647fb For more information www.linear .com/L TM4647 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with 30A Load AppliedStart-Up with No Load Applied

4647 G09

VIN = 12V , VOUT = 1.2V , FS = 500kHz, NO LOAD COUT = 1 × 47µF CERAMIC + 1 × 470µF SPCAP CSS = 0.1µF 20ms/DIV SW 10V/DIV VOUT 500m/DIV LIN 200mA/DIV

4647 G10

VIN = 12V , VOUT = 1.2V , FS = 500kHz, NO LOAD COUT = 1 × 47µF CERAMIC + 1 × 470µF SPCAP CSS = 0.1µF 20ms/DIV SW 10V/DIV VOUT 500m/DIV LIN 2A/DIV

4647fbFor more information www.linear .com/L TM4647 PIN FUNCTIONS VIN (A1-A3, B1-B2, C1-C2): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. GND (A4, A7, B3, C3, C4, D1-D4, E2-E4, F2, F4, F6, G1- G4, H1-H5, J5-J7, K5-K7): Ground Pins for Both Input and Output Returns. All ground pins need to connect with large copper areas underneath the unit. RUN (A6): Run Control Pin. A voltage above 1.35V will turn on the module. This is a 1µA pull-up current on this pin. Once the RUN pin rises above the 1.35V threshold the pull-up current increases to 5µA. PWM (B4): Control PWM Three-State Output Signal. For monitor and test purpose only. Do not drive this pin. CLKOUT (B5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. TEST1, TEST2, TEST3 (B6, D5, F7): These pins are for µModule initial test purposes. Please connect these pins to GND with a large GND copper area. MODE/PLLIN ( B7): Mode Selection Pin and External Synchronization Pin. Connect this pin to SGND to force the module into force continuous current mode (CCM) of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force the module into continuous current mode of operation and synchronized to the external clock applied to this pin. See the Applications Information section. SV IN (D6): Signal V IN. Input voltage to the internal 5.5V regulator for the control circuitry of the regulator. Tie this pin to VIN pin through a 2.2Ω plus 1µF R-C filter in most application. See the Application Information section. DRV CC (C5): Power Input Pin for the MOSFET driver cir- cuitry. Connect to INTVCC output for the application with the input voltage 6V and above or connect this pin to an external supply 4.5V or above through a 2.2Ω plus 1µF R-C filter. See the Application Information section. INTV CC (C6): Internal 5.5V LDO for driving the control circuitry decouple with pin to GND with a minimum of 2.2µF low ESR ceramic capacitor. The 5.5V LDO has a 10mA current limit. PHASMD (C7): This pin determines the relative phases between the internal controllers and the phasing of the CLKOUT signal. See Table 2 in the Application Informa- tion section. FREQ (D7): Frequency Set Pin. A 20µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. HIZB (E5): Phase Shedding Input Pin. When this pin is low, TRACK/SS, COMP and PWM pin go to high impedance. Tie to INTV CC or VIN to disable this function. VFB (E6): The Negative Input of the Error Amplifier. Inter- nally, this pin is connected to VOSNS+ with a 60.4k 0.5% precision resistor. Different output voltages can be pro- grammed with an additional resistor between V FB and VSNS– pins. In PolyPhase ® operation, tying the V FB pins together allows for parallel operation. See the Applications Information section for details. SGND (E7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 22. SW (F3): Switching node of the circuit is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. TRACK/SS (F5): Output Voltage T racking Pin and Soft-Start Inputs. The pin has a 1.25µA pull-up current. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The voltage ramp rate at his pin sets the voltage ramp rate of the output. See the Applications Information section. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

PGOOD ( G7): Output Voltage Power Good Indicator. output voltage is not within ±7.5% of the regulation point. the Applications Information section. not used. See COMPa description. these pins and GND pins. See Table 1. – (E1): Low Side of the Internal Temperature Monitor. Figure 1. Simplified LTM4647 Block Diagram

4647 F01

4647fbFor more information www.linear .com/L TM4647 OPERATION Power Module Description The LTM4647 is a high performance single output stand- alone nonisolated switching mode DC/DC power supply. It can provide a 30A output with few external input and output capacitors. This module provides precisely regu - lated output voltages programmable via external resistors from 0.6V DC to 1.8V DC over a 4.7V to 15V input range. The typical application schematic is shown in Figure 23 and Figure 24. The LTM4647 has an integrated constant-frequency cur- rent mode regulator, power MOSFETs, inductor, and other supporting discrete components. The switching frequency range is optimized from 400kHz to 700kHz, depending on output voltage. For switching noise-sensitive applications, it can externally program to or be synchronized to a clock from 400kHz to 800kHz subject to minimum on-time and inductor ripple current limitations. See the Applications Information section. The LTM4647 is designed to use either external or internal control loop compensation by shorting COMPb and COMPa pins together. With current mode control, the internal loop compensation has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Table 5 provides a guideline for input and output capacitances for several different output conditions using the internal loop compensation. The L TpowerCAD ® design tool is available to download for optimizing the loop stability and transient response. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUN pin below 1.35V forces the regulator into a shutdown state. The TRACK/SS pin is used for pro- gramming the output voltage ramp and voltage tracking during start-up. See the Application Information section. Multiphase operation can be easily employed by cascad- ing the MODE/PLLIN input to the CLKOUT output. See the Information section and Figure 25 for example. For high reliability environment, N+1 phase redundancy can be easily implemented in LTM4647 together with a hot swap controller, such as the LT C®4226, for extra system protection. By connecting the HIZB pin to the gate of the hot swap switch, any fault channel can be disconnected while the rest of the system is not affected. See Applica- tions Information section and Figure 27 for example. High efficiency at light loads can be accomplished with phase shedding in multiphase operation or with selectable pulse-skipping mode or Burst Mode operation in single phase operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. A remote sense amplifier is provided for accurately sensing output voltages at the load point. A TEMP + and TEMP– pins are provided to allow the internal device temperature to be monitored using an onboard diode connected PNP transistor. DECOUPLING REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4.7V to 15V, VOUT = 1V) IOUT = 30A 44 µF COUT External Output Capacitor Requirement (VIN = 4.7V to 15V, VOUT = 1V) IOUT = 30A 440 µF

capacitor requirements for particular applications. lowering the switching frequency. The PWM controller has an internal 0.6V reference voltage. Table 1. VFB Resistor Table vs Various Output Voltages bulk capacitor can be used for more input bulk capacitance. planes are used, then this bulk capacitor is not needed.

4647fbFor more information www.linear .com/L TM4647 APPLICATIONS INFORMATION 22pF to 47pF feedforward capacitor (CFF) is necessary for all ceramic output application to achieve enough phase margin. The typical output capacitance range is from 400µF to 600µF. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7.5A/ µs transient (at 10A/µs slew rate). The table optimizes total equivalent ESR and total output capacitance to optimize the transient performance. Multiphase operation will re - duce effective output ripple as a function of the number of phases. Application Note 77 discusses this reduction versus output ripple current cancellation. But the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology L TpowerCAD Design Tool can calculate the output ripple reduction as the number of implemented phase’s increases by N times and provide stability analysis. Burst Mode Operation The LTM4647 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply float the MODE_PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately one-third of the maximum peak current value in normal operation even though the voltage at the COMPa pin indicates a lower value. The voltage at the COMPa pin drops when the inductor’s aver- age current is greater than the load requirement. As the COMPa voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMPa to rise, the internal sleep line goes low, and the LTM4647 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse- skipping mode should be used. Pulse-skipping operation allows the LTM4647 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMPa voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4647’s output voltage is in regulation. Frequency Selection The LTM4647 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the lower output voltages or lower duty cycle conversions at lower frequencies to improve efficiency by lowering power MOSFET switching losses. Higher output voltages or higher duty cycle conversions can be operated at higher frequencies to limit inductor ripple current. The efficiency graphs will show an operating frequency chosen for that condition. See Table 1 for optimized frequency for various output voltages. The LTM4647 switching frequency can be set with an external resistor from the fSET pin to SGND. An accurate 20µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 2 s hows a graph of frequency setting verses programming voltage.

to limit inductor ripple current.

4647 F02

Figure 2. Relationship Between Switching Frequency Figure 3. Phase Selection Examples

180 PHASE

240 PHASE

300 PHASE

4647 F03

0 PHASE

90 PHASE

270 PHASE

60 PHASE

120 PHASE

show a schematic of the parallel design. Table 2. PHASMD and CLKOUT Signal Relationship

4647 F04

1 PHASE

2 PHASE

3 PHASE

4 PHASE

6 PHASE

Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

during the soft-start process. proportional to the master’s. Figure 5. Output Ratiometric T racking Waveform Figure 6. Example Schematic of Ratiometric Output Voltage T racking the slave regulator, as shown in Figure 6.

4647 F06

4647 F05

slew rate (SR), waveform as shown in Figure 7. the RUN pin has an ABSMAX voltage of 6V. Figure 25 for paralleling application. than 6V maximum for monitoring. rent limit is disabled during soft-start or tracking start-up.

4647 F07

Figure 7. Output Coincident T racking Waveform =1 .5V and VOUT(SL) = 1.2V application. pin can also be used for output voltage sequencing.

4647fb For more information www.linear .com/L TM4647 APPLICATIONS INFORMATION The LTM4647 accomplishes this by disabling both the top and bottom MOSFETs until the TRACK/SS pin voltage and the internal soft-start voltage are above the VFB pin voltage. N+1 Phase Redundancy and Hot Swap The HIZB pin can be used to force both top and bottom MOSFET to turn off while not pulling down the COMPa and TRACK/SS pins. In a multiphase system N+1 redundancy can be achieved via the HIZB pin. When combined with a hot swap controller, such as the LTC4211, the HIZB pin could be connected to the gate of the hot swap switch. When a damaged MOSFET triggers the hot swap control- ler, it also disables the corresponding channel’s power, disconnecting it. Since COMPa and TRACK/SS pins are unaffected, it does not affect the rest of the system. The propagation delay from HIZB falling to both top and bottom MOSFET turned off is <200ns. See Figure 27 for example. SW Pins and Snubbering Circuit The SW pin is generally for testing purposes by monitor- ing the pin. The SW pin can also be used to dampen out switch node ringing caused by LC parasitic in the switched current path. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: ZL = 2π • f • L where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1 2π • f •C These values are a good place to start. Modification to these components should be made to attenuate the ring- ing with the least amount the power loss. Stability Compensation The LTM4647 has already been internally optimized and compensated for all output voltages and capacitor combi- nations including all ceramic capacitor applications when COMPb is tied to COMPa. Please note that a 22pF to 47pF feedforward capacitor (CFF) is required connecting from VOUT to VFB pin for all ceramic capacitor application to achieve high bandwidth control loop compensation with enough phase margin. Table 5 is provided for most application requirements using the optimized internal compensation. For specific optimized requirement, dis - connect COMPb from COMPa and apply a Type II C-R-C compensation network from COMPa to SGND to achieve external compensation. The L TpowerCAD design tool is available to download online to perform specific control loop optimization and analyze the control stability and load transient performance. SV IN, PVIN, INTVCC AND DRVCC SVIN is the filtered input voltage to the internal 5.5V LDO regulator to power the control circuitry of the regulator. Connect SVIN to VIN through a 2.2Ω and 1µF R-C filter. INTVCC is the output of the 5.5 V LDO. Decouple it with a minimum 2.2µF ceramic capacitor. Connect INTVCC to SVIN directly if SVIN is less than 6V. PVIN is the power input connected to power MOSFETs and the DRVCC is the supply voltage for the driver circuity to drive both power MOSFETs. DRVCC could connect to an

to INTVCC 5.5V output directly. composite diode voltage slope. Figure 8. Diode Voltage VD vs Temperature T(°C)

4647 F08

4647fb For more information www.linear .com/L TM4647 APPLICATIONS INFORMATION Combining like terms, then simplifying the natural log terms yields: VD = T(KELVIN) • KD • lN(10) and redefining constant K'D =KD •IN(10) = 198µV K yields VD = K'D • T(KELVIN) Solving for temperature: T(KELVIN)= ∆VD K'D (°CELSIUS)= T(KELVIN)– 273.15 where 300° K = 27°C means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. The diode connected PNP transistor between the TEMP+ and TEMP– pin can be used to monitor the internal tem- perature of the LTM4647. See Figure 23 for an example. Thermal Considerations The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on an µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a man- ner that yields insight and guidance pertaining to one’s application usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi - cients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with six layers. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. The board temperature is measured a specified distance from the package.

airflow, a majority of the heat flow is into the board.

4647 F09

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients yields the set of derating curves shown in this data sheet.

4.7W of internal dissipation. to be provided to protect each unit from catastrophic failure. shutdown that can be done by controlling the HIZB pin. output voltage ranges for correlating the thermal resistance. Figure 10. LTM4647 12VIN to 1VOUT at 30A with No Air Flow

4647 F10

Figure 11. LTM4647 12VIN to 1VOUT at 30A with 200LFM

4647 F11

Figure 15. 5V to 1V Derating Curve, Figure 16. 12V to 1V Derating Curve, Figure 17. 5V to 1V Derating Curve, Figure 18. 12V to 1.5V Derating Curve, Figure 19. 5V to 1.5V Derating Curve,

4647 F12

4647 F13

4647 F14

4647 F15

4647 F16

4647 F17

4647 F18

4647 F19

Figure 20. 12V to 1.5V Derating Curve, BGA Heat Sink Figure 21 5V to 1.5V Derating Curve, BGA Heat Sink Table 3. 1.0V Output Table 4. 1.5V Output

4647 F20

4647 F21

Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values

4647fb For more information www.linear .com/L TM4647 APPLICATIONS INFORMATION ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed, as an example, in Figure 14 the load current is derated to ~26A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 26A output is about 4.6W. The 4.6W loss is calculated with the ~3.6W room temperature loss from the 12V to 1.0V power loss curve at 26A, from Figure 21, and the 1.3 multiplying factor at 120°C junction. If the 80°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided by 4.6W equals a 8.8°C/W θJA thermal resistance. Table 3 specifies a 9°C/W value which is very close. Table 3 provides equivalent thermal resistances for 1.0V and 1.5V outputs with and without airflow and heat sinking. The de- rived thermal resistances in Tables 3 and 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the ef- ficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick six layer board with two ounce copper for all layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed in Table 4. Layout Checklist/Example The high integration of LTM4647 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout consid- erations are still necessary. Use large PCB copper areas for high current paths, including VIN, GND, and VOUT. It helps to minimize the PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put via directly on the pad, unless they are capped or plated over.
• Use a separated SGND ground copper area for com - ponents connected to signal pins. Connect the SGND to GND underneath the unit.
• For parallel modules, tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start.
• Bring out test points on the signal pins for monitoring. Figure 22 gives a good example of the recommended layout.

Figure 22. Recommended PCB Layout

4647 F22

Figure 23. Typical 6V to 15V Input 1.0V at 30A Output Design Figure 24. Typical 4.7V to 5.5V Input 1.2V at 30A Output Design

4647 F23

4647 F24

Figure 25. 6V to 15V Input, 1.0V Output at 60A

4647 F25

Figure 26. 6V to 15V Input, 1.0V and 1.2V Output with T racking

Figure 27. 3-Phase 1V at 90A Design with Extra 1 Phase 30A Redundancy

4647 F27

Figure 28. 4 Phase 1V at 120A Design

4647 F28

4647fbFor more information www.linear .com/L TM4647 PACKAGE DESCRIPTION LTM4647 Component BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V IN B1 V IN C1 V IN D1 GND E1 TEMP – F1 TEMP + A2 V IN B2 V IN C2 V IN D2 GND E2 GND F2 GND A3 V IN B3 GND C3 GND D3 GND E3 GND F3 SW A4 GND B4 PWM C4 GND D4 GND E4 GND F4 GND A5 GND B5 CLKOUT C5 DRVCC D5 TEST2 E5 HIZB F5 TRACK/SS A6 RUN B6 TEST1 C6 INTV CC D6 SV IN E6 V FB F6 GND A7 GND B7 MODE/PLLIN C7 PHASMD D7 FREQ E7 SGND F7 TEST3 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 V OUT K1 V OUT L1 V OUT G2 GND H2 GND J2 V OUT K2 V OUT L2 V OUT G3 GND H3 GND J3 V OUT K3 V OUT L3 V OUT G4 GND H4 GND J4 V OUT K4 V OUT L4 V OUT G5 V OSNS– H5 GND J5 GND K5 GND L5 V OUT G6 V OSNS+ H6 COMPa J6 GND K6 GND L6 V OUT G7 PGOOD H7 COMPb J7 GND K7 GND L7 V OUT PACKAGE PHOTO

4647fb For more information www.linear .com/L TM4647 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 77-Lead (15.00mm × 9.00mm × 5.01mm) (Reference LTC DWG# 05-08-1900 Rev D) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (77 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 77 D E // bbb Z Z BGA 77 0113 REV D TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PACKAGE BOTTOM VIEW SEE NOTES A B C D E F G H J K L PIN 1 e b F G 7 6 5 4 3 2 1 SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 ±0.025 Ø 77x

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES Please refer to http://www.linear.com/product/LTM4647#packaging for the most recent package drawings.

4647fbFor more information www.linear .com/L TM4647

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 12/16 Changed V OUT(DC) MIN from 1.97 to 1.96 and MAX from 1.203 to 1.204 3 B 05/17 Changed MLS Rating from 4 to 3 2

4647fb For more information www.linear .com/L TM4647  LINEAR TECHNOLOGY CORPORATION 2016 LT 0517 REV B • PRINTED IN USA www.linear .com/L TM4647 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4627 15A µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, 15mm × 15mm × 4.32mm (LGA), 15mm × 15mm × 4.92mm (BGA) LTM4636 40A µModule Regulator, ±1.3% VOUT Accuracy 4.75V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.12mm (BGA) LTM4631 Dual 10A, Single 20A µModule Regulator, 1.91mm Package Height 4.5V ≤ V IN ≤ 15V. 0.6V ≤ VOUT ≤ 1.8V, 16mm x 16mm × 1.91mm (LGA) LTM4620A Dual 13A or Single 26A µModule Regulator, V OUT ≤ 5.3V LTM4630 Dual 18A or Single 36A µModule Regulator 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA) LTM4630A Dual 18A or Single 36A µModule Regulator V OUT ≤ 5.3V 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V, 16mm × 16mm × 4.41mm (LGA) LTM4630-1 Dual 18A or Single 36A µModule Regulator ±0.8V V OUT Accuracy (–1A), External Compensation 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) LTM4650 Dual 25A or Single 50A µModule Regulator 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) LTM4650-1 Dual 25A or Single 50A µModule Regulator ±0.8V V OUT Accuracy (–1A), External Compensation 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) LTM4675 Dual 9A or Single 18A µModule Regulator with PSM 4.5V ≤ V IN ≤ 17V, 0.5V ≤ VOUT ≤ 5.5V, 16mm × 11.9mm × 3.51mm (BGA) LTM4676A Dual 13A or Single 26A µModule Regulator with PSM 4.5V ≤ V IN ≤ 17V, 0.5V ≤ VOUT ≤ 5.5V, 16mm × 16mm × 5.01mm (BGA) LTM4677 Dual 25A or Single 50A µModule Regulator with PSM 4.5V ≤ V IN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.