Power Management

LTM4636

Linear Technology

40A DC/DC 關Module Regulator

Manufacturer: Linear Technology

Document: 36 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Linear Technology Browse L parts

Online Datasheet

Read LTM4636 online.

LTM4636 LINER | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 36

Technical content

4636fFor more information www.linear .com/L TM4636 Typical applicaTion

DescripTion

40A DC/DC µModule Regulator The LT M®4636 is a 40A step-down µModule (power module) switching regulator with a stacked inductor as a heat sink for quicker heat dissipation and cooler operation in a small package. The exposed inductor permits direct contact with airflow from any direction. The LTM4636 can deliver 40W (12VIN, 1VOUT, 40A, 200LFM) with only 40°C rise over the ambient temperature. Full-power 40W is delivered, up to 83°C ambient and half-power 20W is supported at 110°C ambient. The LTM4636 operates at 92%, 90% and 88% efficiency, delivering 15A, 30A and 40A, respectively, to a 1V load (12VIN). The µModule regulator is scalable such that four µModules in current sharing mode deliver 160W with only 40°C rise and 88% efficiency (12V IN, 1VOUT, 400LFM). The LTM4636 is offered in a 16mm × 16mm × 7.07mm BGA package. L, LT, LT C, LT M, PolyPhase, Burst Mode, µModule, Linear Technology, L TpowerCAD and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643. 1V, 40A DC/DC µModule Regulator

FeaTures

applicaTions

n Stacked Inductor Acts as Heat Sink n Wide Input Voltage Range: 4.7V to 15V n 0.6V to 3.3V Output Voltage Range n ±1.3% Total DC Output Voltage Error Over Line, Load and T emperature (–40°C to 125°C) n Differential Remote Sense Amplifier for Precision Regulation n Current Mode Control/Fast T ransient Response n Frequency Synchronization n Parallel Current Sharing (Up to 240A) n Internal or External Compensation n 88% Efficiency (12VIN, 1VOUT) at 40A n Overcurrent Foldback Protection n 16mm × 16mm × 7.07mm BGA Package n Telecom Servers and Networking Equipment n Industrial Equipment and Medical Systems 12VIN , 1VOUT Efficiency vs Output Current RUNC RUNP HIZREG FREQ TEMP+ TEMP– SGND VIN 34.8k 22µF 0.1µF 22µF 16V 4.70V TO 15V 100µF 25V INTV CC PVCC VIN ≤ 5.5V , TIE VIN, INTVCC AND PVCC TOGETHER, TIE RUNP TO GND. VIN > 5.5V , THEN OPERATE AS SHOWN OPTIONAL TEMP MONITOR INTVCC INTVCC PVCC L TM4636 PVCC PGND VOUTS1+ VOUT VOUTS1– VFB 470µF 6.3V 7.5k 100µF 6.3V V OUT 1V, 40A

4636 TA01a

PINS NOT USED IN THIS CIRCUIT : CLKOUT , GMON, PGOOD, PHMODE, PWM, SW , TEST1, TEST2, TEST3, TEST4, TMON COMPA COMPB SNSP1 SNSP2 MODE/PLLIN TRACK/SS 15k OUTPUT CURRENT (A) EFFICIENCY (%) 100 15 25

4636 TA01b

4636f For more information www.linear .com/L TM4636 absoluTe MaxiMuM raTings PGOOD, RUNC, TMON, PVCC, MODE/PLLIN, PHMODE, FREQ, TRACK/SS, TEST1, TEST2, VOUTS1–, VOUTS1+, 0.3V to INTVCC (5V) (Note 1) pin conFiguraTion M L K J H G F E D C B A TOP VIEW BGA PACKAGE 144-LEAD (16mm × 16mm × 7.07mm) VOUT GND GND GND GND SWVIN 2 3 4 5 6 7 8 9 10 11 12 PGOOD RUNC SNSP2 SNSP1 COMPB TEST2 TEST4 (FLOAT PIN) INTVCC TEMP– TEMP+CLKOUT SGND VFB VOUTS1+ HIZREG TRACK/SS COMPA VOUTS1– FREQ PWMTEST3 MODE/PLLIN TEST1 TMON NC GMON PHASMD RUNP PVCC TJMAX = 125°C, θJA = 7.5°C/W, θJCbottom = 3°C/W, θJCtop = 15°C/W, θJBA = 12°C/W θJA = DERIVED FROM 95mm × 76mm PCB WITH 6 LAYERS, WEIGHT = 3.95g θ VALUES DETERMINED PER JESD51-12 Note: θJA = (θJCbottom + θJBA)||θJCtop; θJBA is Board to Ambient I nternal Operating Temperature Range 40°C to 125°C 55°C to 125°C 0°C orDer inForMaTion http://www.linear.com/product/LTM4636#orderinfo Note: PWM, CLKOUT, and GMON are outputs only. PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RA TING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4636EY#PBF SAC305 (RoHS) LTM4636 BGA –40°C to 125°C LTM4636IY#PBF –40°C to 125°C

Device temperature grade is indicated by a label on the shipping container.
Pad or ball finish code is per IPC/JEDEC J-STD-609.
Terminal Finish Part Marking: www.linear.com/leadfree
This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy
Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy
BGA Package and T ray Drawings: www.linear.com/packaging
This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy

4636fFor more information www.linear .com/L TM4636 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the Typical Application in Figure 20. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage VIN ≤ 5.5V, Tie VIN, INTVCC and PVCC Together, Tie RUNP to GND l 4.7 15 V VOUT VOUT Range l 0.6 3.3 V VOUT(DC) DC Output Voltage, Total Variation with Line and Load CIN = 22µF × 5 COUT = 100µF × 4 Ceramic, 470µF POSCAP × 3 RFB = 40.2k, MODE_PLLIN = GND VIN = 4.75V to 15V, IOUT = 0A to 40A (Note 4) l 1.4805 1.5 1.5195 V Input Specifications VRUNC RUNC Pin On Threshold V RUNC Rising 1.1 1.22 1.35 V VRUNCHYS RUNC Pin On Hysteresis 150 mV VRUNP RUNP Pin On Threshold RUNP Pin Rising l 0.7 0.8 0.9 V RUNP HYS RUNP Pin Hysteresis 60 mV HIZREG HIZREG Input Threshold VIN = 12V, RUNC = 5V, RUNP = VIN, VOUT = 1.5V 2.3 V HIZREG HYS HIZREG Hysteresis VIN = 12V, RUNC = 5V, RUNP = VIN, VOUT = 1.5V 0.8 V IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A Shutdown, RUN = 0, VIN = 12V 105 mA mA mA µA I S(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 40A VIN = 12V, VOUT = 1.5V, IOUT = 40A 14.7 5.66 A A Output Specifications I OUT(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Note 4) 0 40 A ∆VOUT (Line) VOUT Line Regulation Accuracy V OUT = 1.5V, VIN from 4.75V to 15V IOUT = 0A l 0.02 0.06 %/V ∆VOUT (Load) VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 40A, VIN = 12V (Note 4) l 0.2 0.35 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF × 3 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V 15 mVP-P ∆VOUT(START) Turn-On Overshoot COUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VOUT = 1.5V, IOUT = 0A, VIN = 12V, TRACK/SS = 0.1µF 5 mV tSTART Turn-On Time COUT = 100µF × 3 Ceramic, 470µF × 3 POSCAP, No Load, TRACK/SS = 0.001µF, VIN = 12V 50 ms ∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load C OUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V, CFF = 22pF 45 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V IN = 5V, COUT = 100µF × 4 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V, CFF = 22pF 25 µs IOUTPK Output Current Limit V IN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V A A Control Section V FB Voltage at VFB Pin I OUT = 0A, VOUT = 1.5V l 0.594 0.600 0.606 V IFB Current at VFB Pin (Note 6) –30 –100 nA VOVL Feedback Overvoltage Lockout Measure at V OUTS1 l 5 7.5 10 % ITRACK/SS T rack Pin Soft-Start Pull-Up Current TRACK/SS = 0V, Default 750µs Turn on with TRACK/SS Tied to INTV CC 1.1 1.35 1.6 µA tON(MIN) Minimum On-Time (Note 3) 100 ns RFBHI Resistor Between VOUTS1 and VFB Pins 4.99 kΩ

4636f For more information www.linear .com/L TM4636 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Remote Sense Amplifier AV(VFB) VFB Differential Gain (Note 6) 1 V/V GBP VFB Path Gain Bandwidth Product (Note 5) 4 MHz General Control or Monitor Pins I TMON Temperature Monitor Current, TJ = 25°C Into 25kΩ Temperature Monitor Current, TJ = 150°C Into 25kΩ 38 40.3 44 µA µA ITMON(SLOPE) Temperature Monitor Current Slope, RTMON = 25kΩ 0.144 µA/°C VPGOOD PGOOD T rip Level V FB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –7.5 7.5 V PGL PGOOD Voltage Low I PGOOD = 2mA 0.2 0.4 V tPGOOD VPGOOD High-to-Low Delay 65 µs IPGOOD(OFF) PGOOD Leakage Current V PGOOD = 5V –2 2 µA VPG1(HYST) PGOOD T rip Level Hysteresis 2.5 % INTV CC Linear Regulator VINTVCC Internal VCC Voltage Source 6V < V IN < 15V 5.3 5.5 5.7 V VINTVCC Load Reg INTV CC Load Regulation I CC = 0mA to 10mA 0.5 % UVLO HYS Controller UVLO Hysteresis (Note 6) 0.5 V PVCC(UVLO) Drivers and Power MOSFETs UVLO PV CC Rising 3.5 3.8 4.1 V PVCC(HYS) PVCC UVLO Hysteresis 0.45 V PVCC Power Stage Bias 12V Input, PVCC Load = 50mm 5.0 V Oscillator and Phase-Locked Loop fOSC Oscillator Frequency VPHSMD = 0V RFREQ = 30.1kΩ RFREQ = 47.5kΩ RFREQ = 54.9kΩ RFREQ = 75.0kΩ Maximum Frequency Minimum Frequency l l 210 540 625 945 1.2 250 600 750 1.05 290 660 825 1.155 0.2 kHz kHz kHz MHz MHz MHz I FREQ FREQ Pin Output Current V FREQ = 0.8V 19 20 21 µA RMODE/PLLIN MODE_PLLIN Input Resistance 250 kΩ V MODE/PLLIN PLLIN Input Threshold VMODE/PLLIN Rising VMODE/PLLIN Falling 1.2 V V VCLKOUT Low Output Voltage High Output Voltage Verified Levels Measurements on CLKOUT 0.2 5.2 V V PWM-CLKOUT PWM to Clockout Phase Delay VPHSMD = 0V VPHSMD = 1/4 INTVCC VPHSMD = Float VPHSMD = 3/4 INTVCC VPHSMD = INTVCC 120 180 Deg Deg Deg Deg Deg PWM/PWMEN Outputs PWM PWM Output High Voltage ILOAD = 500µA 5.0 V PWM Output Low Voltage ILOAD = –500µA 0.5 V elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 20.

4636 G01

3.3VOUT, 500kHz 2.5VOUT, 500kHz 1.8VOUT, 450kHz 1.5VOUT, 425kHz 1.2VOUT, 300kHz 1VOUT, 300kHz OUTPUT CURRENT (A) EFFICIENCY (%) 100 2515 35

4636 G02

3.3VOUT, 700kHz 2.5VOUT, 600kHz 1.8VOUT, 500kHz 1.5VOUT, 450kHz 1.2VOUT, 400kHz 1VOUT, 350kHz OUTPUT CURRENT (A) EFFICIENCY (%) 100 2515 35

4636 G03

3.3VOUT, 750kHz 2.5VOUT, 650kHz 1.8VOUT, 600kHz 1.5VOUT, 550kHz 1.2VOUT, 400kHz 1VOUT, 350kHz OUTPUT CURRENT (A) EFFICIENCY (%) 100 3 2 4

4636 G04

VOUT 1.5V 12V TO 1V TRANSIENT RESPONSE C OUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 400kHz 10A/DIV 18A/µs STEP 50mV/DIV 50µs/DIV

4636 G05

12V TO 1.2V TRANSIENT RESPONSE C OUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 400kHz CCOMP = 100pF 10A/DIV 18A/µs STEP 50mV/DIV 50µs/DIV

4636 G06

4636f For more information www.linear .com/L TM4636 Typical perForMance characTerisTics 2.5V T ransient Response1.5V T ransient Response 3.3V T ransient Response 40A Load Short-Circuit 1.8V T ransient Response Start-Up with Soft-Start No-Load Start-Up with 0.5V Output Pre-Bias Start-Up with Soft-Start Full Load No-Load Short-Circuit RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF C OUT = 4 × 100µF CERAMIC AND 3 × 470µF POSCAP 20ms/DIV VIN 5V/DIV VOUT 0.5V/DIV

4636 G11

RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF C OUT = 4 × 100µF CERAMIC AND 3 × 470µF POSCAP 20ms/DIV VIN 5V/DIV VOUT 0.5V/DIV

4636 G12

100µs/DIV LIN 200mA/DIV VOUT 0.5V/DIV

4636 G13

RUN PIN CAPACITOR = 0.1µF TRACK/SS CAPACITOR = 0.1µF C OUT = 4 × 100µF CERAMIC AND 3 × 470µF 20ms/DIV VIN 5V/DIV VOUT 0.5V/DIV

4636 G14

100µs/DIV LIN 200mA/DIV VOUT 0.5V/DIV

4636 G15

12V TO 1.5V TRANSIENT RESPONSE C OUT = 4 × 100µF CERAMIC, 3 × 470µF 2.5V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 425kHz CCOMP = 100pF 10A/DIV 18A/µs STEP 50mV/DIV 50µs/DIV

4636 G07

12V TO 1.8V TRANSIENT RESPONSE C OUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 500kHz CCOMP = 100pF 10A/DIV 18A/µs STEP 50mV/DIV 100µs/DIV

4636 G08

12V TO 2.5V TRANSIENT RESPONSE C OUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 650kHz CCOMP = 100pF 10A/DIV 18A/µs STEP 100mV/DIV 100µs/DIV

4636 G09

12V TO 3.3V TRANSIENT RESPONSE C OUT = 6 × 100µF CERAMIC, 2 × 470µF 4V POSCAP 5m/uni03A9 C FF = 22pF , SW FREQ = 750kHz CCOMP = 100pF 10A/DIV 18A/µs STEP 100mV/DIV 100µs/DIV

4636 G10

4636fFor more information www.linear .com/L TM4636 pin FuncTions VOUT (A1-A12, B1-B12, C1-C12, D1-D2, D11-D12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance between these pins and GND pins. Review Table 4. MODE_PLLIN (H3): Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to enable pulse-skipping mode of operation. Connect to ground to enable forced continuous mode of operation. Floating this pin will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section. V OUTS1– (D3): VOUT Sense Ground for the Remote Sense Amplifier. This pin connects to the ground remote sense point. Connect to ground when not used. See the Applica- tions Information section. V OUTS1+ (D4): This pin should connect to V OUT and is connected to V FB through a 4.99k resistor. This pin is used to connect to a remote sense point of the load for accurate voltage sensing. Either connect to remote sense point or directly to VOUT. See the Applications Information section for details. COMPB (D5): Internal compensation network provided that coincides with proper stability utilizing the values in Table 5. Just connect this pin to COMPA for internal compensa- tion. In parallel operation with other LTM4636 devices, connect COMPA and COMPB pins together for internal compensation, then connect all COMPA pins together. GND (D6-D10, E6-E10, E12, F7, F8, F10-F12, G1-G2, G6 G10, H1, H10-H12, J1-J3, J8-J12, K1-K3, K9-K10, K12, L1-L3, L9-L10, L12, M1-M3, M9-M12): Ground Pins for Both Input and Output Returns. PGOOD (E1): Output Voltage Power Good Indicator. Open- drain logic output is pulled to ground when the output voltage exceeds a ±7.5% regulation window. RUNC (E2): Run Control Pin. A voltage above 1.35V will turn on the control section of the module. A 10k resistor to ground is internal to the module for setting the RUN pin threshold with a resistor to 5V, and allowing a pull- up resistor to PV CC for enabling the device. See Figure 1 Block Diagram. TRACK/SS (E3): Output Voltage T racking Pin and Soft-Start Inputs. The pin has a 1.25µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The different voltage is applied to a voltage divider then to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. Default soft-start of 750µs with TRACK/SS pin connected to INTVCC pin. See the Applica- tions Information section. In PolyPhase® applications tie the TRACK/SS pins together. VFB (E4): The Negative Input of the Error Amplifier. Inter- nally, this pin is connected to VOUTS1 with a 4.99k precision resistor. Different output voltages can be programmed with an additional resistor between V FB and VOUTS1–. In PolyPhase operation, tying the VFB pins together allows for parallel operation. See the Applications Information section. COMPA (E5): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMPA pins together for parallel operation. This pin allows external compensation. See the Applications Information section. SNSP2 (F1): Current Sense Signal Path. Connect this pin to SNSP1 (F2). SNSP1 (F2): Current Sense Signal Path. Connect this pin to SNSP2 (F 1). Both pins are used to calibrate current sense matching and current limit at final test. HIZREG (F3): When this pin is pulled low the power stage is disabled into high impedance. Tie this pin to VIN or in TVCC for normal operation. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

4636f For more information www.linear .com/L TM4636 pin FuncTions SGND (F4, G4): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 18. INTVCC (F6): Internal 5.5V LDO for Driving the Control Circuitry in the LTM4636. INTVCC is controlled and enabled when RUNC is activated high. Tie to VIN, when 4.7V ≤ VIN ≤ 5.5V, minimum VIN = 4.2V. FREQ (G5): A resistor can be applied from this pin to ground to set the operating frequency. This pin sources 20µA. See the Applications Information section. PHASMD (G7): This pin can be voltage programmed to change the phase relationship of the CLKOUT pin with reference to the internal clock or an input synchronized clock. The INTV CC (5.5V) output can be voltage divided down to the PHASMD pin to set the particular phase. The Electrical Characteristics show the different settings to select a particular phase. See the Applications Informa - tion section. RUNP ( G8): This pin enables the PVCC supply. This pin can be connected to VIN, or tie to ground when connecting PVCC to VIN ≤ 5.5V. RUNP needs to sequence up before RUNC. A 15k resistor from PVCC to RUNC with a 0.1µF capacitor will provide enough delay. In parallel operation with multiple LTM4636s, the resistor can be reduced in value by N times and the 0.1µF can be increased N times. See Applications Information section. RUNP can be used to set the minimum UVLO with a voltage divider. See Figure 1. NC (G9): No Connection. PV CC (F9): 5V Power Output and Power for Internal Power MOSFET Drivers. The regulator can power 50mA of external sourcing for additional use. Place a 22µF ceramic filter capacitor on this pin to ground. When VIN < 5.5V, tie VIN and PVCC together along with INTVCC. Then tie RUNP to GND. If VIN > 5.5V then operate PVCC regulator as normal. See the Typical Application examples. TEMP + (G12): Temperature Monitor. An internal diode connected NPN transistor. See the Applications Informa- tion section. TEMP – (G11): Low Side of the Internal Temperature Monitor. CLKOUT (G3): Clock out signal that can be phase selected to the main internal clock or synchronized clock using the PHASMD pin. CLKOUT can be used for multiphase applications. See the Applications Information section. TEST1 (H4), TEST2 (F5), TEST3 (H2), TEST4 (E11), GMON (H9): These are test pins used in the final production test of the part. Leave floating. V IN (H5-H6, J4-J7, K4-K8, L4-L8, M4-M8): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN and GND pins. PWM (H7): PWM output that drives the power stage. Primarily used for test, but can be monitored in debug or testing. TMON (H8): Temperature Monitor Pin. Internal temperature monitor, varies from 1V at 25°C to 1.44V at 150°C, disables power stage at 150°C. If this feature is not desired, then tie the TMON pin to GND. SW (L11, K11): These are pin connections to the internal switch node for test evaluation and monitoring. An R-C snubber can be placed from the switch pins to GND to eliminate any high frequency ringing. See the Applications Information section.

Figure 1. Simplified LTM4636 Block Diagram

4636 F01

4636f For more information www.linear .com/L TM4636 Decoupling requireMenTs SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4.70V to 16V, VOUT = 1.5V) IOUT = 40A, 6 × 22µF Ceramic X7R Capacitors (See Table 4) 100 µF COUT External Output Capacitor Requirement (VIN = 4.70V to 16V, VOUT = 1.5V) IOUT = 40A (See Table 4) 1000 µF TA = 25°C. Use Figure 1 configuration . Power Module Description The LTM4636 is a high efficiency regulator that can provide a 40A output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 3.3V DC over a 4.70V to 15V input range. The Typical Applica- tion schematic is shown in Figure 20. The LTM4636 has an integrated constant-frequency cur- rent mode regulator, power MOSFETs, 0.18µH inductor, protection circuitry, 5V regulator and other supporting discrete components. The switching frequency range is from 250kHz to 770kHz, and the typical operating frequency is 400kHz. For switching noise-sensitive applications, it can be externally synchronized from 250kHz to 800kHz, subject to minimum on-time limitations and limiting the inductor ripple current to less than 40% of maximum output current. A single resistor is used to program the frequency. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4636 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. An option has been provided for external loop compensation. L TpowerCAD® can be used to optimize the external compensation option. See the Applications Information section. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage operaTion monitor feedback pin referred will attempt to protect the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUNC pin below 1.1V forces the regulator con- troller into a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The LTM4636 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating condi- tions. L TpowerCAD is available for transient and stability analysis. This tool can be used to optimize the regulators loop response. A remote sense amplifier is provided for accurately sensing output voltages at the load point. Multiphase operation can be easily employed with the internal clock source or a synchronization clock applied to the MODE/PLLIN input using an external clock source, and connecting the CLKOUT pins. See the Applications Information section. Review Figure 4. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load op- eration in the Typical Performance Characteristics section. A TEMP+ and TEMP– pins are provided to allow the internal device temperature to be monitored using an onboard diode connected NPN transistor.

Figure 20. External component selection is primarily requirements for particular applications. ment section and temperature derating curves. points. If no remote sense the VOUTS1+ connects to VOUT. Table 1. VFB Resistor Table vs Various Output Voltages pins together utilizing a single feedback resistor. good choice with RMS ripple current ratings of ~4A each. capacitor can be used for more input bulk capacitance. planes are used, then this bulk capacitor is not needed. electrolytic capacitor or a Polymer capacitor.

4636f For more information www.linear .com/L TM4636 applicaTions inForMaTion Output Capacitors The LTM4636 is designed for low output voltage ripple noise. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient require - ments. COUT can be a low ESR tantalum capacitor, low ESR Polymer capacitor or ceramic capacitors. The typi- cal output capacitance range is from 400µF to 1000µF. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of dif- ferent output voltages and output capacitors to minimize the voltage droop and overshoot during a 15A/µs tran- sient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and L TpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancel- lation, but the output capacitance should be considered carefully as a function of stability and transient response. L TpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increases by N times. External loop compensation can be used for transient response optimization. Burst Mode Operation The LTM4636 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply float the MODE_PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMPA pin indicates a lower value. The voltage at the COMPA pin drops when the inductor’s aver- age current is greater than the load requirement. As the COMP A voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMPA to rise, the internal sleep line goes low, and the LTM4636 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse- skipping mode should be used. Pulse-skipping operation allows the LTM4636 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMPA voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4636’s output voltage is in regulation.

device over the specified range. than the number of phases used times the output voltage). of phases used. See Application Note 77. only tie COMP A pins together with external compensation. Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

4636 F02

1 PHASE

2 PHASE

3 PHASE

4 PHASE

6 PHASE

inductor current to about 45% of maximum load current. For output voltages from 1.5V to 1.8V, 500kHz is optimal. For output voltages from 2.5V to 3.3V, 700kHz is optimal. the 2.5V and 3.3V outputs to 35A. programmed with a voltage divider from the INTVCC pin. connections. See Figure 27 for example design. Figure 3. FREQ Voltage to Switching Frequency

4636 F03

resistor. Figure 5 shows an example of coincident tracking. VTRACK is the track ramp applied to the slave’s track pin. Figure 4. Phase Selection Examples

180 PHASE

240 PHASE

300 PHASE

4636 F04

0 PHASE

90 PHASE

270 PHASE

60 PHASE

120 PHASE

Figure 5. Dual Outputs (1.5V and 1.2V) with Tracking Figure 6. Output Voltage Coincident T racking Characteristics

4636 F06TIME

4636 F05

4636fFor more information www.linear .com/L TM4636 applicaTions inForMaTion Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0V to 0.6V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in volts/time. The equation: MR SR •4.99k= RTB where MR is the master’s output slew rate and SR is the slave’s output slew rate in volts/time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal to 4.99k. RTA is derived from equation: RTA = 0.6V VFB 4.99k + VFB RFB1 – VTRACK RTB where VFB is the feedback voltage reference of the regula- tor, and VTRACK is 0.6V . Since RTB is equal to the 4.99k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 4.99k, and RTA = 4.99k in Figure 5. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R TB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB = 6.19k. Solve for RTA to equal 4.22k. For applications that do not require tracking or sequenc- ing, simply tie the TRACK/SS pin to INTV CC to let RUN control the turn on/off. When the RUN pin is below its threshold or the V IN undervoltage lockout, then TRACK/SS is pulled low. Default Overcurrent and Overvoltage Protection The LTM4636 has overcurrent protection (OCP) in a short circuit. The internal current comparator threshold folds back during a short to reduce the output current. An over voltage condition (OVP) above 10% of the regulated output voltage will force the top MOSFET off and the bottom MOSFET on until the condition is cleared. Foldback current limiting is disabled during soft-start or tracking start-up. Temperature Monitoring Measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation: ID = IS •e VD η •VT or VD = η•VT •InID IS where ID is the diode current, V D is the diode voltage, η is the ideality factor (typically close to 1.0) and IS (satura- tion current) is a process dependent parameter. V T can be broken out to: VT = k •T q where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. V T is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable tem- perature sensors. The IS term in the previous equation is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and by definition must always be less than ID. Combining all of the constants into one term: KD = η •k q where KD = 8.62−5, and knowing ln(ID/IS) is always posi- tive because ID is always greater than I S, leaves us with the equation that: VD = T KELVIN( ) •KD •InID IS

composite diode voltage slope. Figure 7. Diode Voltage VD vs Temperature T(°C)

4636 F07

a zero intercept at 0 Kelvin. used to monitor the internal temperature of the LTM4636. Figure 8. The Tw o Images Show the LTM4636 Operating at 1V at

4636fFor more information www.linear .com/L TM4636 applicaTions inForMaTion Overtemperature Protection The LTM4636 has an overtemperature enhanced protec- tion features that can be used to detect overtemperature. The overtemperature feature uses the TMON pin voltage to monitor temperature. This pin varies from 0.994V at 25°C to 1.494 at 150°C, and will tripoff at ≥ 150°C. Tying TMON to ground disable this feature. RUNP and RUNC Enable The RUNP pin is used to enable the 5V PVCC supply that powers the power driver stage and enables the power stage ~1ms later. The RUNC pin is used to enable the control section that drives the power stage. The RUNP needs to be enabled first, and then RUNC. RUNP has a 0.85V threshold and can be connected to the input volt - age and RUNC has a 1.35V threshold and a 10k resistor to ground. See the Block Diagram for details. A 0.1µF capacitor from the RUNC pin to ground is used to set the delay for RUNC enable. INTVCC and PVCC Regulators The LTM4636 has an internal low dropout regulator from VIN called INTV CC. This regulator output has a 4.7μF ceramic capacitor internal. This regulator powers the control section. The PV CC 5V regulator supplies power to the power MOSFET driver stage. An additional 50mA can be used from this 5V PV CC supply for other needs. The input supply source resistance needs to be very low in order to minimize IR drops when operating from a 5V input source. Depending on the output voltage and current, the input supply can source large current,and PV CC 5V regulator needs a minimum 4.70V supply. Additional input capacitance maybe needed for 5V inputs to limit the input droop. Stability Compensation The LTM4636 has already been internally compensated when COMPB is tied to COMPA for all output voltages. Table 5 is provided for most application requirements. For specific optimized requirements, disconnect COMPB from COMPA, and use LTpowerCAD to perform specific control loop optimization. Then select the desired external compensation and output capacitance for the desired optimized response. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. A recommended value of 2.2Ω in series with 2200pF to ground should work for most ap - plications. See Figure 19 for guideline. The 2.2Ω resistor should be an 0805 size. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”).

performance to one’s own application.

θJA, the thermal resistance from junction to ambient, is

to a 95mm × 76mm PCB with four layers. conditions don’t generally match the user’s application. the heat flows from the junction to the top of the part. generally match the user’s application. a specified distance from the package. resistances are external to the µModule package. Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

4637 F09

4636fFor more information www.linear .com/L TM4636 applicaTions inForMaTion As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal op - erating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally con- duct exclusively through the top or exclusively through the bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4636, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4636 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4636 with heat sink and airflow; (4) having solved for and analyzed these thermal resis - tance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operat - ing the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves shown in this data sheet. The power loss curves in Figures 10 to 12 can be used in coordination with the load current derating curves in Figures 13 to 18 for calculating an approximate θJA thermal resistance for the LTM4636 with various airflow conditions. The p ower loss curves are taken at room temperature and can be increased with a multiplicative factor according to the junction temperature, which is ~1.4 for 120° C. The derating curves are plotted with the output current starting at 40 A and the ambient temperature increased. The output voltages are 1 V, 2.5V and 3.3V. These are chosen to include the lower, middle and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power lo ss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~125°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased . The monitored j unction temperature of 125° C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 14 the l oad current is derated to ~30A at ~94°C with no air flow and the power loss for the 12V to 1.0V at 30A output is about 4.2 W. The 4.2W loss is calculated with the ~3 W room temperature loss from the 12V to 1.0V power loss curve at 30 A, and the 1.4 multiplying factor at 125°C junction. If the 94°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of 31°C divided by 4.2W equals a 7.4°C/W θJA thermal resistance. Table 2 specifies a 7.2°C/W value which is very close. Tables 2, 3, and 4 provide equivalent thermal resistances for 1V, 1.5V and 3.3V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2 thru 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above

4636 F13

4636 F14

4636 F15

4636 F16

4636 F17

4636 F18

Figure 13. 5VIN, 1VOUT Derate Figure 15. 5VIN, 1.5VOUT Derate Figure 14. 12VIN, 1VOUT Derate Figure 10. 5V Input Power Loss Curves Figure 11.8V Input Power Loss Curves Figure 12. 12V Input Power Loss Curves

4636 F10

4636 F11

4636 F12

Figure 16. 12VIN, 1.5VOUT Derate Figure 17. 5VIN, 3.3VOUT Derate Figure 18. 12VIN, 3.3VOUT Derate

Table 2. 1V Output Table 3. 1.5V Output Table 4. 3.3V Table 5. LTM4636 Capacitor Matrix, All Below Parameters are Typical and are Dependent on Board Layout

Table 6. Enhanced External Compensation, Lower Voltage T ransition During T ransient. Careful Power Integrity Layout Required † Bulk capacitance is optional if VIN has very low input impedance. CFF is a capacitor from VOUT to VFB pin.

4636fFor more information www.linear .com/L TM4636 applicaTions inForMaTion ambient, thus maximum junction temperature. Room temperature power loss curves are provided in Figures 10 through 12. The printed circuit board is a 1.6mm thick six layer board with two ounce copper for all layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. Safety Considerations The LTM4636 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be us ed as a secondary fault protector in this situation. The LTM4636 has the enhanced over temperature protection discussed earlier and schematic applications will be shown at the end of the data sheet. Layout Checklist/Example The high integration of the LTM4636 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.

Use large PCB copper areas for high current paths, including V IN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capacitors next to the V IN, GND and V OUT pins to minimize high frequency noise.
Place a dedicated power ground layer underneath the unit.
To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
Do not put vias directly on the pad, unless they are capped or plated over.
Place test points on signal pins for testing.
Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit.
For parallel modules, tie the COMP and V FB pins together. Use an internal layer to closely connect these pins together.
RSNUB and CSNUB (2.2Ω and 2200pf) values to dampen switch ringing. Figure 19 gives a good example of the recommended layout.

Figure 19. Recommended PCB Layout

4636 F19

Figure 20. 4.70V to 15V, 1V at 40A Design

4636 F20

VIN ≤ 5.5V , TIE VIN, INTVCC AND PVCC TOGETHER, TIE RUNP TO GND.

Figure 21. 2-Phase 1V, 80A Regulator Design

4636 F21

VIN ≤ 5.5V , TIE VIN, INTVCC AND PVCC TOGETHER, TIE RUNP TO GND.

Figure 22. 3-Phase 0.9V at 120A with Protection

4636 F22

Figure 24. Thermal Plot , 12V to 0.9V at Figure 23. Demo Board Figure 25. Efficiency, 12V to 0.9V at 120A Figure 26. 12V to 0.9V 30A/µs Load Step

4636 F244636 F23

4636 F25

4636 F26

Figure 27. Four Phase 0.9V at 160A Design

4636 F27

Figure 30. Efficiency, 12V to 0.9V at 160A Figure 31. 12 to 0.9V 30A/µs Load Step Figure 29. Thermal Plot , 12V to 0.9V at

4636 F29

4636 F28

4636 F30

4636 F31

4636fFor more information www.linear .com/L TM4636 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT B1 V OUT C1 V OUT D1 V OUT E1 PGOOD F1 SNSP2 A2 V OUT B2 V OUT C2 V OUT D2 V OUT E2 RUNC F2 SNSP1 A3 V OUT B3 V OUT C3 V OUT D3 V OUTS1– E3 TRACK/SS F3 HIZREG A4 V OUT B4 V OUT C4 V OUT D4 V OUTS1+ E4 V FB F4 SGND A5 V OUT B5 V OUT C5 V OUT D5 COMPB E5 COMPA F5 TEST2 A6 V OUT B6 V OUT C6 V OUT D6 GND E6 GND F6 INTV CC A7 V OUT B7 V OUT C7 V OUT D7 GND E7 GND F7 GND A8 V OUT B8 V OUT C8 V OUT D8 GND E8 GND F8 GND A9 V OUT B9 V OUT C9 V OUT D9 GND E9 GND F9 PVCC A10 V OUT B10 V OUT C10 V OUT D10 GND E10 GND F10 GND A11 V OUT B11 V OUT C11 V OUT D11 V OUT E11 TEST 4 F11 GND A12 V OUT B12 V OUT C12 V OUT D12 V OUT E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 GND H2 TEST3 J2 GND K2 GND L2 GND M2 GND G3 CLKOUT H3 MODE/PLLIN J3 GND K3 GND L3 GND M3 GND G4 SGND H4 TEST1 J4 V IN K4 V IN L4 V IN M4 V IN G5 FREQ H5 V IN J5 V IN K5 V IN L5 V IN M5 V IN G6 GND H6 V IN J6 V IN K6 V IN L6 V IN M6 V IN G7 PHASMD H7 PWM J7 V IN K7 V IN L7 V IN M7 V IN G8 RUNP H8 TMON J8 GND K8 V IN L8 V IN M8 V IN G9 NC H9 GMON J9 GND K9 GND L9 GND M9 GND G10 GND H10 GND J10 GND K10 GND L10 GND M10 GND G11 TEMP – H11 GND J11 GND K11 SW L11 SW M11 GND G12 TEMP + H12 GND J12 GND K12 GND L12 GND M12 GND package DescripTion Pin Assignment Table (Arranged by Pin Number) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

4636f For more information www.linear .com/L TM4636 package DescripTion package phoTo VOUT VOUT VOUTVOUT VOUT VOUT PGOOD RUNC SNSP2 SNSP1 1 2 3 4 5 6 7 TOP VIEW 8 9 10 11 12 M L K J H G F E D C B A COMPB TEST2 TEST4GND GNDINTVCC PVCC PHASMD RUNP TEMP– TEMP+NCCLKOUT SGND SGND VFB VOUTS1+ HIZREG TRACK/SS COMPA VOUTS1– FREQ PWMTEST3 MODE/PLLIN TEST1 TMON GMON GND GND GND GND GND GND GND VIN VIN VIN VIN VINGND GND GND SW SW GND

4636fFor more information www.linear .com/L TM4636 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear.com/product/LTM4636#packaging for the most recent package drawings. PIN “A1” CORNER NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE BALL DESIGNATION PER JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 144 1016 REV D TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.0000 0.0000 DETAIL A Øb (144 PLACES) D (3.0)(2.4) (2.4) A DETAIL B PACKAGE SIDE VIEW Z Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 144x E b e e b F G 144-Lead (16mm × 16mm × 7.07mm) (Reference LTC DWG # 05-08-1937 Rev D) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 G F E A B D C H M L K J 2 14 35 6 712 8 9 10 11 SEE NOTES DETAIL B SUBSTRATE ccc Z // bbb Z SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 6.57 0.50 2.31 0.60 0.60 0.36 1.95 3.76 NOM 7.07 0.60 2.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 2.00 4.06 MAX 7.42 0.70 2.51 0.90 0.66 0.46 2.05 4.21 0.15 0.10 0.20 0.30 0.15 NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT INDUCTOR HT DIMENSIONS TOTAL NUMBER OF BALLS: 144 EPOXY/SOLDER (11.20) (10.0) (3.0) µModule 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y MOLD CAP

4636f For more information www.linear .com/L TM4636  LINEAR TECHNOLOGY CORPORATION 2016 LT 1216 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4636 relaTeD parTs Design resources Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LTM4650/ LTM4650-1 More Current Up to 50A µModule Regulator Dual 25A or Single 50A, 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm BGA LTM4630/ LTM4630-1/ LTM4630A Less Current Up to 36A µModule Regulator LTM4650 Pin-Compatible; Same VIN and VOUT Range; LTM4630A 0.6V ≤ VOUT ≤ 5.3V, 16mm × 16mm × 4.41mm LGA 5.01mm BGA LTM4647 Smaller Package Up to 30A µModule Regulator Single 30A, 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 9mm × 15mm × 5.01mm BGA 5V to 2.5V at 35A Design SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. COMPA COMPB TK/SS RUNC RUNP HIZREG FREQ MODE/PLLIN TMON V OUT TEMP+ TEMP– SNSP1 SNSP2 SGND VIN 15k 47k CSS 0.1µF 22µF 2.5V AT 35A VOL TAGE OUT TEMP MONITOR 0.1µF 22µF 16V 22µF 16V 22µF 16V 22µF 16V 22µF 16V 100µF 25V INTV CC OPTIONAL TEMP MONITOR FOR TELEMETRY READBACK ICs INTVCC INTVCC L TM4636 PVCC PGND VOUTS1+ VOUTS1– VFB 470µF 470µF RFB 1.58k 100µF ×3 6.3V CFF 47pF

4636 TA02

PINS NOT USED IN CIRCUIT L TM4636: CLKOUT , GMON, PGOOD, PHMODE, PWM, SW , TEST1, TEST2, TEST3, TEST4 SGND SGND SGND

Product Information

LTM4636 specifications and overview.

Summary

40A DC/DC 關Module Regulator

Description

40A DC/DC 關Module Regulator

Source title LTM4636 Datasheet(PDF) - Linear Technology

Related Parts

More parts from the same family.

Browse manufacturer