LTM4636-1

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Technical content

7820fcFor more information www.linear.com/LTC7820 TYPICAL APPLICATION FEATURES DESCRIPTION Fixed Ratio High Power Inductorless (Charge Pump) DC/DC Controller The LT C®7820 is a fixed ratio high voltage high power switched capacitor/charge pump controller . The device includes four N-channel MOSFET gate drivers to drive external power MOSFETs in voltage divider , doubler or inverter configurations. The device achieves a 2:1 step- down ratio from an input voltage as high as 72V, a 1:2 step-up ratio from an input voltage as high as 36V, or a 1:1 inverting ratio from an input voltage up to 36V. Each power MOSFET is switched with 50% duty cycle at a constant pre-programmed switching frequency. System efficiency can be optimized to over 99%. The LTC7820 provides a small and cost effective solution for high power , non-isolated intermediate bus applications with fault protection. The LTC7820 switching frequency can be linearly programmed from 100kHz to 1MHz. The device is available in a thermally enhanced 28-lead QFN package with some no-connect pins for high voltage compatible pin spacing. Efficiency and Power Loss vs Load Current

APPLICATIONS

n Low Profile, High Power Density, Capable of 500W+ n Soft Switching: 99% Peak Efficiency and Low EMI n VIN Max for Voltage Divider (2:1): 72V n VIN Max for Voltage Doubler (1:2)/Inverter (1:1): 36V n Wide Bias VCC Range: 6V to 72V n Soft Startup into Steady State Operation n 6.5V to 40V EXTVCC Input for Improved Efficiency n Input Current Sensing and Overcurrent Protection n Wide Operating Frequency Range: 100kHz to 1MHz n Output Short-Circuit/OV/UV Protections with Programmable Timer and Retry n Thermally Enhanced 28-Pin 4mm × 5mm QFN Package n Bus Converters n High Power Distributed Power Systems n Communications Systems n Industrial Applications All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 9484799. Very High Efficiency 5A Voltage Divider 0.1µF 10k 10k 10k 40k 4.7µF 10/uni03A9 10µF

7820 TA01a

1µF 1µF 0.1µF 0.1µF 0.1µF 10/uni03A9 100/uni03A9 0.1µF 12V 10µF 10k VCC VHIGH_SENSE UV HYS_PRGM PGOOD FREQ FAUL T GND INTV CC INTVCC TIMER L TC7820 BOOST3 SW3 VLOW_SENSE VLOW BOOST2 BOOST1 SW1 INTV CC EXTV CC RUN ISENSE+ ISENSE– VIN 48V/24V VOUT 24V/12V 5A* * LOAD CURRENT APPLIED AFTER STARTUP RSENSE 0.005/uni03A9 EFFICIENCY POWER LOSS f s = 100kHz LOAD CURRENT (A) 100 0.4 0.8 1.2 1.6 2.0 VIN = 48V VOUT = 24V VIN = 24V VOUT = 12V EFFICIENCY (%) POWER LOSS (W)

7820 TA01b

7820fc For more information www.linear.com/LTC7820 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS 3V to 86V 3V to 51V 80V 45V 3V to 6V 3V to INTVCC Operating Junction Temperature C to 125°C C to 150°C (Notes 1, 3) 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1VHIGH_SENSE NC HYS_PRGM TIMER FREQ RUN PGOOD UV BOOST2 V LOW VLOW_SENSE BOOST3 SW3 GND ISENSE– ISENSE+ NC SW1 BOOST1 FAULT NC EXTV CC INTVCC NC VCC 8 15 TJMAX = 125°C, θJA = 43°C/W , θJC(bottom) = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7820EUFD#PBF LTC7820EUFD#TRPBF 7820 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC7820IUFD#PBF LTC7820IUFD#TRPBF 7820 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear .com/product/LTC7820#orderinfo

7820fcFor more information www.linear.com/LTC7820

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input/Output Voltage VCC IC Bias Voltage Range 6 72 V VVHIGH_SENSE VHIGH_SENSE Voltage Range (Note 6) 0 72 V VVLOW_SENSE VLOW_SENSE Voltage Range 0 36 V VVLOW VLOW Voltage Range (Note 5) 0 36 V IQ Input DC Supply Current Shutdown Normal Operation V RUN = 0V VRUN = 5V, No Switching 1.5 µA mA VUVLO Undervoltage Lockout Threshold VINTVCC Falling VINTVCC Rising 4.85 5.05 V V Overcurrent Protection I ISENSE+ ISENSE+ Pin Current ISENSE+ = ISENSE– = 24V 220 350 µA Pre-Balance Phase, VHIGH_SENSE = 24V, ISENSE+ = ISENSE– = 24V, VVLOW = 12V, VVLOW_SENSE = 11V 93 mA IISENSE– ISENSE– Pin Current l –5 1 5 µA VISENSE Current Limit Threshold (VISNESE+ – VISENSE–) l 45 50 55 mV Gate Drivers R G2,4 Pull-Up On-Resistance Pull-Down On-Resistance 2.5 1.5 Ω Ω R G1,3 Pull-Up On-Resistance Pull-Down On-Resistance 2.4 1.1 Ω Ω G1/G2 t D G1 Off to G2 On Delay Time G2 Off to G1 On Delay Time (Note 4) 50 ns ns G3/G4 t D G3 Off to G4 On Delay Time G4 Off to G3 On Delay Time (Note 4) 60 ns ns G1/G3 t D G1 On to G3 On Delay Time G3 Off to G1 Off Delay Time (Note 4) 5 ns ns G2/G4 t D G2 On to G4 On Delay Time G4 Off to G2 Off Delay Time (Note 4) 5 ns ns RUN Pin V RUN Run Pin On Threshold VRUN Rising l 1.1 1.22 1.35 V VRUN,HYS Run Pin On Hysteresis 80 mV INTVCC Regulator VINTVCC_VCC INTVCC Voltage No Load 6V < VCC < 72V, VEXTVCC = 0V 5.4 5.6 5.9 V INTVCC Load Regulation ICC = 0 to 60mA, VEXTVCC = 0V 0.8 ±2 % VINTVCC_EXT INTVCC Voltage No Load with EXTVCC 12V < VEXTVCC < 45V (Note 7) 5.4 5.6 5.9 V INTVCC Load Regulation with EXTVCC ICC = 0 to 50mA, VEXTVCC = 12V 0.5 ±2 % EXTVCC Switchover Voltage VEXTVCC Ramping Positive (Note 9) 6.35 6.5 6.65 V EXTVCC HYSTERESIS 400 mV VHIGH_SENSE and VLOW_SENSE RVHIGH_SENSE VHIGH_SENSE to GND Resistance 1 MΩ IVLOW_SENSE VLOW_SENSE Pin Current VCC = 51V, VLOW_SENSE = 45V ±1 ±10 µA The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = 12V, VRUN = 5V, unless otherwise specified.

7820fc For more information www.linear.com/LTC7820 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7820 is tested under pulsed load conditions such that T J ≈ TA. The LTC7820E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7820I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. T J is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 43°C/W). Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: Delay times are measured using 50% levels with SW3 = V LOW = 6V, SW1 = 12V. Note 5: The maximum output operating voltage for divider applications is 36V, the maximum input operating voltage for doubler applications is 36V. Note 6: The maximum input operating voltage for divider applications is 72V, the maximum output operating voltage for doubler applications is 72V. Note 7: When V CC > 15V, EXTVCC lower than VCC is recommended to improve efficiency and reduce IC Temperature. Note 8: All the voltage is referred to the GND pin unless otherwise specified. Note 9: EXTV CC is enabled only if VCC is higher than 7V. Note 10: Guaranteed by design. Note 11: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability or permanently damage the device. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VLOW ISOURCEVLOW Source Current to VLOW Pin from ISENSE+ ISENSE+ = VHIGH_SENSE = 24V, VLOW_SENSE = 11V, VLOW = 12V, Timer = 1V 93 mA ISINKVLOW Sink Current from VLOW Pin to GND I SENSE+ = VHIGH_SENSE = 24V, VLOW_SENSE = 13V, VLOW = 12V, Timer = 1V 50 mA Oscillator fs Oscillator Frequency Range 100 1000 kHz fNOM Nominal Frequency VFREQ = 1.02V 500 kHz IFREQ FREQ Setting Current VFREQ = 1.02V (Note 3) –9.5 –10 –10.5 µA FAUL TB and HYS_PRGM R FAUL T FAUL T Pull-Down Resistance VFAUL T = 0.5V 200 400 Ω IFAULT_LEAK FAUL T Leakage Current VFAUL T = 80V ±2 µA IHYS_PRGM HYS_PRGM Setting Current VHYS_PRGM = 1V (Note 3) l –9.3 –10 –10.7 µA VVLOW_SENSE_FAULT VLOW_SENSE Voltage T rigger Fault VVHIGH_SENSE = 24V, VHYS_PRGM = 0V VVLOW_SENSE Ramp Up VVLOW_SENSE Ramp Down l l 12.2 11.6 12.3 11.7 12.4 11.8 V V V VHIGH_SENSE = 24V, VHYS_PRGM = 5V VVLOW_SENSE Ramp Up VVLOW_SENSE Ramp Down l l 12.7 11.1 12.8 11.2 12.9 11.3 V V V VHIGH_SENSE = 24V, VHYS_PRGM = 2.4V VVLOW_SENSE Ramp Up VVLOW_SENSE Ramp Down l l 14.15 9.5 14.3 9.65 14.45 9.8 V V UV Comparator and PGOOD V UVTH UV Pin Comparator Threshold UV Pin Voltage Rising 0.985 1.01 1.035 V VUVHYS Undervoltage Hysteresis 120 mV RPGOOD PGOOD Pull-Down Resistance VPGOOD = 0.5V 150 300 Ω IPGOOD_LEAK PGOOD Leakage Current VPGOOD = 45V ±1 µA Timer I TIMER Timer Pin Current VTIMER < 0.5V or VTIMER > 1.2V (Note 3) –3.5 µA 0.5V < VTIMER < 1.2V (Note 3) –7 µA The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VCC = 12V, VRUN = 5V, unless otherwise specified.

7820fcFor more information www.linear.com/LTC7820 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current 48V to 24V Voltage Divider in Figure 7 Efficiency vs Load Current 24V to 12V Voltage Divider in Figure 7 Efficiency vs Load Current 24V to 48V Voltage Doubler in Figure 8 Efficiency vs Load Current 24V to –24V Inverter in Figure 9 Steady State Output Ripple in Figure 7 Output Voltage vs Load Current 24V to –24V Inverter in Figure 9 Output Voltage vs Load Current 48V to 24V Voltage Divider in Figure 7 Output Voltage vs Load Current 24V to 48V Voltage Doubler in Figure 8 LOAD CURRENT (A) EFFICIENCY (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 117

7820 G01

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) EFFICIENCY (%) 98.0 93.5 97.5 96.5 95.5 94.5 97.0 96.0 95.0 94.0 93.0

7820 G04

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) OUTPUT VOL TAGE (V) –22.8 –23.8 –23.0 –23.4 –23.2 –23.6 –24.2 –24.0 6 4

7820 G07

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) 0 1 OUTPUT VOL TAGE (V) 48.1 47.2 48.0 47.8 47.6 47.4 47.9 47.7 47.5 47.3 47.1

7820 G06

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) –1 1 OUTPUT VOL TAGE (V) 24.05 23.60 24.00 23.90 23.80 23.70 23.95 23.85 23.75 23.65 23.55 117

7820 G05

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) EFFICIENCY (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 117

7820 G02

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz LOAD CURRENT (A) 0.5 EFFICIENCY (%) 100.0 95.5 99.5 98.5 97.5 96.5 99.0 98.0 97.0 96.0 95.0 5.53.5

7820 G03

fS = 150kHz fS = 200kHz fS = 250kHz fS = 300kHz 10µs/DIV VIN = 48V VOUT = 24V ILOAD = 10A 150kHz 200mV/DIV AC-COUPLED 200kHz 200mV/DIV AC-COUPLED 250kHz 200mV/DIV AC-COUPLED

7820 G08

TA = 25°C, unless otherwise noted. Load T ransient 0A-10A-0A 48V to 24V Divider in Figure 7 50µs/DIV fS = 250kHz V OUT 200mV/DIV AC-COUPLED I LOAD 5A/DIV

7820 G09

7820fc For more information www.linear.com/LTC7820 TYPICAL PERFORMANCE CHARACTERISTICS Driver Voltage vs Frequency, in Figure 7 VCC Shutdown Current vs Temperature Short-Circuit and Retry 24V to 12V Divider Shutdown 48V to 24V Voltage Divider , RUN Pin FLOAT INTV CC Line Regulation 200ms/DIV V OUT 10V/DIV FAUL T 10V/DIV TIMER 5V/DIV SW3 20V/DIV

7820 G13

VCC VOL TAGE (V) 0 10 INTVCC VOL TAGE (V) 6040

7820 G10

TEMPERATURE (°C) –50 VCC CURRENT AT SHUTDOWN (µA) 10050

7820 G11

VCC = 12V VCC = 48V VCC = 72V FREQUENCY (kHz) DRIVER VOL TAGE (V) 5.8 4.8 5.6 5.2 5.4 5.0 4.0 4.4 4.2 4.6 1000 800 600 400

7820 G12

25°C 125°C –45°C 25°C 125°C –45°C 25°C 125°C –45°C 25°C 125°C –45°C 100ms/DIV V OUT 20V/DIV V IN 20V/DIV RUN 5V/DIV SW3 20V/DIV

7820 G15

TA = 25°C, unless otherwise noted. Start-Up 48V to 24V Voltage Divider , RUN Pin FLOAT 100ms/DIV V OUT 20V/DIV V IN 20V/DIV RUN 5V/DIV SW3 20V/DIV

7820 G14

Input Current During Short Circuit 48V to 24V Divider Divider Efficiency vs C F LY in Figure 11 Voltage Divider Line T ransient t r = tr = 100µs, fS = 500kHz 5µs/DIV V IN 20V/DIV V OUT 20V/DIV SW3 50V/DIV I IN 20A/DIV

7820 G16

100µs/DIV V IN 5V/DIV V OUT 5V/DIV SW3 10V/DIV

7820 G17

QUANTITY OF 10µF CF LY IN PARALLEL 100 EFFICIENCY (%)

7820 G18

7820fcFor more information www.linear.com/LTC7820 PIN FUNCTIONS UV (Pin 8): Undervoltage Comparator Input. If the UV pin voltage is lower than 0.9V, the PGOOD pin is pulled down while the controller keeps switching. If the UV pin voltage is higher than 1V and no faults exist, PGOOD pin is released. Connect to INTV CC if not used. ISENSE+ (Pin 27): Current Sense Comparator Positive Input. Kelvin connected to the positive node of the cur - rent sensing resistor . The current sensing resistor has to be connected to the drain of the very top MOSFET . When the voltage between ISENSE+ pin and ISENSE– pin is higher than 50mV, the controller indicates an overcurrent fault by pulling the FAUL T pin down. The I SENSE+ pin is also used to source 93mA current to the VLOW pin during the capacitor’s pre-balancing time at power-up in voltage divider applications. Connect directly to the drain of the very top MOSFET if not used. I SENSE– (Pin 28): Current Sense Comparator Negative Input. Kelvin connected to the negative node of the current sensing resistor . Short to ISENSE+ if not used. RUN (Pin 6): Run Control Input. Forcing RUN below 1.14V shuts down the controller . When RUN is higher than 1.22V, internal circuitry starts up. There is a 1µA pull-up current flowing out of RUN pin when the RUN pin voltage is below 1.14V and additional 5µA current flowing out of RUN pin when the Run pin voltage is above 1.22V. TIMER (Pin 4): Charge Balance and Fault Timer Control Input. A capacitor between this pin and ground sets the amount of time to charge V LOW to VHIGH_SENSE/2 voltage during power-up. It also sets the short-circuit retry time. See the Application Information section for details. FAUL T (Pin 9): Open Drain Output Pin. FAUL T is pulled to ground when the V LOW_SENSE voltage is out of its window thresholds or the voltage between ISENSE+ and ISENSE– is higher than 50mV. FAUL T pin is also pulled to ground under INTVCC UVLO. PGOOD (Pin 7): Open Drain Output Pin. PGOOD is pulled to ground if there are any faults or if the UV pin indicates an undervoltage condition. HYS_PRGM (Pin 3): A resistor connected between this pin and ground will program the two thresholds of the window comparator that monitors the voltage difference between V HIGH_SENSE/2 and VLOW_SENSE. There is a 10µA current flowing out of this pin. G4 (Pin 15): High Current Gate Drive for the Bottom (Synchronous) N-Channel MOSFET . Voltage swing at this pin is from ground to INTV CC. G3 (Pin 17): High Current Gate Drive for the Third Upper Most N-Channel MOSFET . This is the output of the floating driver with a voltage swing from BOOST3 to SW3. G2 (Pin 21): High Current Gate Drive for the Second Upper most N-Channel MOSFET . This is the output of the floating driver with a voltage swing from BOOST2 to V LOW. G1 (Pin 24): High Current Gate Drive for the Upper most N-Channel MOSFET . This is the output of the floating driver with a voltage swing from BOOST1 to SW1. SW1/SW3 (Pin 25/Pin 16): Switch Node Connections. BOOST1, BOOST2, BOOST3 (Pins 23, 22, 18): Boot - strapped supplies to the floating drivers. Capacitors are connected between these BOOST pins and their respective SWn and V LOW pins. EXTVCC (Pin 11): External Power Input to EXTV CC LDO. This LDO supplies INTV CC power whenever EXTV CC is higher than 6.5V and VCC is higher than 7V. Do not exceed 40V on this pin. INTVCC (Pin 12): Output of the Internal Linear Low Dropout Regulator . The driver and control circuits are powered from this voltage source. Must be bypassed to power ground with a minimum of 4.7µF ceramic or other low ESR capacitor. V CC (Pin 14): Power Supply for Internal Circuitry and INTVCC Linear Regulator . A bypass capacitor should be tied between this pin and the power ground. V HIGH_SENSE (Pin 1): Kelvin Sensing Input. Monitor the voltage of the drain of the top MOSFET .

7820fc For more information www.linear.com/LTC7820 PIN FUNCTIONS VLOW (Pin 20): Half Supply from VHIGH_SENSE. Connect a bypass capacitor from this node to PGND. VLOW_SENSE (Pin 19): Kelvin Sensing Input. Monitors the voltage on VLOW. FREQ (Pin 5): Frequency Set Pin. There is a precision 10µA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. See the Applications Information section for detailed information. NC (Pins 2, 10, 13, 26): No Connection. Always keep these pins floating. These pins are intentionally skipped to isolate adjacent high voltage pins. GND (Exposed Pad Pin 29): Signal and Power Ground. All small-signal components should connect to this ground, which in turn connects to system power ground at one point. The exposed pad must be soldered to the PCB, providing a local ground for the control components of the IC, which should be tied to system power ground under the IC. For inverter applications, GND should connect to the negative output and all small signal components still referred to GND pin.

7820fcFor more information www.linear.com/LTC7820 BLOCK DIAGRAM VHIGH RF RSENSE CB1 0.1µF CF DB1 CONTROL LOGIC ANTI- SHOOT-THROUGH BOOST1 23 ISENSE– ISENSE+ SW1 25 CB2 1µF CF LY DB2 VLOW_SENSE 19 BOOST2 50mA VLOW CB3 1µF CVLOW VLOW DB3 BOOST3 18 SW3 16 FAUL T9 CINTVCC 4.7µF INTVCC EXTVCC > 6.5V AND VCC > 7V GND 7820 BD VHIGH_SENSE VLOW_SENSE VHYS_PRGM 500k UVLO 120mV HYSTERESIS OVERCURRENT COMPARATOR 50mV THRESHOLD VCC LDO VCC EXTVCC LDO EXTVCC INTVCC 3.5µA ~ 7µA PGOOD 1.01V 500k 93mA UV8 TIMER4 VCC 1µA ~ 6µARUN6 INTVCC 10µAFREQ5 INTVCC 10µA HYS_PRGM3 OSC

duty cycle at a pre-programmed switching frequency. drive waveforms are shown in Figure 1. and the EXTVCC pin voltage has to be higher than 6.5V. 1µA current to pull up this pin and enable the controller . Absolute Maximum Rating of 6V on this pin. capacitors at different initial conditions. Figure 1. Gate Drive Waveforms the output voltage with a closed-loop feedback system. overcurrent event or an overtemperature protection event.

7820 F01

IC temperature has to be lower than 165°C. has to be placed at the drain of the very top MOSFET M1. to the drain of the top MOSFET M1 directly. on the FREQ pin and switching frequency. the RUN pin is low or when the LTC7820 is starting up. will flag power bad immediately when the UV pin is low. with ENABLE/RUN pins, this allows easy for interfacing. to achieve higher step-down ratios. Figure 2. Relationship Between Switching Frequency

7820 F02

7820fc For more information www.linear.com/LTC7820 The Typical Application on the first page of this data sheet is a LTC7820 voltage divider circuit. For voltage divider applications, the input voltage is at the drain of very top MOSFET M1 and the output voltage is at the V LOW pin, which is connected to the source of MOSFET M2 and the drain of MOSFET M3. The output voltage is around half of the input voltage in steady state. Alternately, by swap- ping the input and output voltages, the voltage divider circuit can be transformed into a voltage doubler cir cuit. For voltage doubler applications, the input voltage is at the V LOW pin while output voltage is available at the drain of the top MOSFET M1 and equals two times the input voltage as shown in Figure 8. Similarly, for inverter ap - plications, the input voltage is applied between the drain of the top MOSFET M1 and VLOW, and the output voltage equals the negative input voltage at the GND pin with respect to the V LOW pin as shown in Figure 9. For divider applications, if the load current is applied before startup or heavy resistive loads are connected to the VLOW pin, the LTC7820 may not start up due to the limited drive ability of the pre-balance circuit. A disconnect FET may be used at the output for soft-start up. For doubler and inverter applications, a disconnect FET may also be required for soft start-up and shutdown. The disconnect FETs in divider/ doubler/inverter applications may be also controlled by hot swap controllers to achieve more programmable slew rates and fault protections. Voltage Divider Pre-Balance before Switching In voltage divider applications, the V LOW_SENSE voltage should be always close to VHIGH_SENSE/2 in steady state. The voltages across the flying capacitors and V LOW ca- pacitors are close to each other and close to half of the input voltage. The charging inrush current is minimized during each switching cycle because the voltage difference between capacitors is small. However , without special methods such as the LTC7820 pre-charging circuitry, during start-up or fault conditions such as V LOW short to GND, the difference between capacitors can be large and charging currents may be great enough to cause permanent MOSFET damage. APPLICATIONS INFORMATION When the power MOSFETs are on, ideally, the inrush charge current, I = VIN – VCFLY – VLOW RON _M1 +RON _M3 when switches M1 and M3 are on and: I = VCFLY – VLOW RON _M2 +RON _M4 when switches M2 and M4 are on. Both currents are lim- ited by the power MOSFET saturation current. With very low RDS(ON) of the external power MOSFETs, the inrush charge current could easily achieve several hundreds of Amperes which can be higher than the MOSFET’s Safe Operating Area (SOA). The LTC7820 provides a proprietary pre-balance method to minimize the inrush charging current in voltage divider applications. The LTC7820 controller detects the V LOW_SENSE pin voltage before switching and compares it with the VHIGH_SENSE/2 internally. If the VLOW_SENSE pin voltage is much lower than the VHIGH_SENSE/2, a current source will source 93mA current to the V LOW pin to pull the VLOW pin up. If the V LOW_SENSE pin voltage is much higher than the V HIGH_SENSE/2, another current source will sink 50mA from VLOW pin to pull the VLOW pin down. If the VLOW_SENSE pin voltage is close to VHIGH_SENSE/2 and within the pre-programmed window, both current sources are disabled and LTC7820 starts switching. If the V LOW_SENSE voltage is still within the window after 36 switching cycles, the FAUL T pin is released. For voltage divider with pre-balance startup, the LTC7820 assumes no load current or a very small load current (less than 50mA) at the VLOW (output) otherwise the VLOW volt- age cannot reach VHIGH_SENSE/2 and the LTC7820 never starts up. This no load condition can be achieved by con- necting the FAUL T pin to the enable pins of the following electrical loads such as switching regulators and LDOs. If load current cannot be controlled off such as resistive loads, a disconnect FET is required to disconnect the load during startup as shown in the typical applications.

7820fcFor more information www.linear.com/LTC7820 APPLICATIONS INFORMATION If the LTC7820 divider input voltage is controlled by a front end supply or hot swap controller and ramps up slowly, the LTC7820 capacitor voltages are naturally bal- anced. In this case the pre-balance and no load start-up requirements are not necessary Voltage Doubler and Inverter Startup and Disconnect In voltage doubler and inverter applications, LTC7820 can startup without capacitor inrush charging current if the input voltage is ramping slowly up from zero. As long as the input voltage ramps up slow (in milliseconds), the output voltage can track the input voltage and the voltage difference between capacitors are always small resulting in no huge inrush currents. The slew rate control of the input voltage can be achieved by using a disconnect FET at input or using hot swap controllers as shown in the typical application section. Different from voltage dividers, the voltage doubler and inverter applications have to start up from zero input voltage every time, but they can start up with heavy load currents directly. Note that voltage divider applications can also startup with a slow ramping input voltage from zero to the steady state operation if there is a hot swap in front of the LTC7820, (pre-balance is not required). Overcurrent Protection The LTC7820 provides overcurrent protection through a sensing resistor placed on the high voltage side. A precision rail to rail comparator monitors the differential voltage between the I SENSE+ pin and the ISENSE– pin which are Kelvin connected to a sensing resistor . Whenever the I SENSE+ pin voltage is 50mV higher than the I SENSE– pin voltage, an over current fault is triggered and the FAUL T pin is pulled down to ground. At the same time the LTC7820 stops switching and starts retry mode based on the timer pin setup. The overcurrent fault will be cleared when the timer pin voltage reaches 4V and the voltage across the sensing resistor is less than 50mV. The current through the sensing resistor is a pulse current during charging/ discharging of the flying capacitors, which may result a voltage higher than the 50mV threshold at heavy loads. To prevent the inrush current from falsely triggering the overcurrent protection, an RC filter is required at the I SENSE+ pin and ISENSE–. The RC filter timer constant has to be larger than a switching period. Typically a 100Ω and 0.1µF filter is good for most of applications. Due to the current flowing into the I SENSE+ pin, the resistor of the RC filter has to be placed at the I SENSE– pin. ISENSE+ pin needs to be connected to the sensing resistor directly. The current limit can be selected by choosing different sense resistor values. For example, the 10mΩ sense resistor sets current limit at 50mV/10mΩ = 5A ideally. Due to the switching ripple, the actual current limit is always lower than the ideal case. In real circuits, the current limit is around 4.2A with 0.1µF/100Ω filter and 200kHz switch - ing frequency. The L Tspice ® simulation tool can be used to quantify the switching ripple. The overcurrent protection can also be used in doubler and inverter applications for overcurrent and short-circuit conditions at both startup and steady state operation. If over current protection is not used, short the I SENSE+ pin and the ISENSE– pin together and connect them to the drain of the top MOSFET M1. Window Comparator Programming In normal operation, VLOW_SENSE voltage should be always close to half of the V HIGH_SENSE voltage. A floating win - dow comparator monitors the voltage on the VLOW_SENSE pin and compares it with V HIGH_SENSE/2. The hysteresis window voltage can be programmed and is equal to the voltage at the HYS_PRGM pin. There is a precision 10µA current flowing out of HYS_PRGM pin. A single resistor from HYS_PRGM pin to GND sets the HYS_PRGM pin voltage, which equals the resistor value multiplied by 10µA current (e.g. the voltage is 1V with a 100k resistor from the HYS_PRGM pin to GND). With a 100k resistor on the HYS_PRGM pin, the V HIGH_SENSE/2 voltage has to be within a (VLOW_SENSE ±1V) window during startup and normal operation, otherwise a fault is triggered and the LTC7820 stops switching.

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age ripple and voltage drop at maximum load conditions. circuit of voltage divider circuit is shown in the Figure 4.

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retry sequence based on the TIMER pin setup. noise higher than the switching frequency. Figure 3. Relationship Between HYS_PRGM Pin Voltage and Figure 4. Thevenin Equivalent Circuit of Voltage Divider

7820fcFor more information www.linear.com/LTC7820 At low switching frequencies, R OUT = 1/(4f SCF LY). As frequency increases, R OUT finally approaches 2R DS(ON). In high power applications, it is suggested to select the switching frequency around 1/(16CF LYRDS(ON)) or higher for decent load regulation and efficiency. At heavy load conditions, the output voltage will drop from V IN/2 by ROUT • I LOAD. In many applications, multi-layer ceramic capacitors (MLCC) are selected as flying capacitors. The voltage coefficients of MLCC capacitors strongly depend on the type and size of capacitors. Normally larger size X7R MLCC capacitors are better than X5R in terms of voltage coefficient. The capacitance still drops 20% to 30% with high DC bias voltage. Capacitance derating needs to be considered when estimating the output resistance of these switched capacitor circuits. INTV CC Regulators and EXTVCC The LTC7820 features an internal PMOS LDO that supplies power to INTVCC from the VCC supply. INTVCC powers the gate drivers and most of the LTC7820’s internal circuitry. The linear regulator regulates the voltage at the INTV CC pin to 5.5V when VCC is greater than 6V. EXTVCC connects to INTVCC through another PMOS LDO and can supply the needed power when its voltage is higher than 6.5V and V CC is higher than 7V. Each of these can supply a peak current of 150mA and must be bypassed to ground with a minimum of 4.7µF ceramic capacitor or low ESR electrolytic capacitor . No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTV CC and GND pins is highly recommended. Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7820 to be exceeded. The INTV CC current, which is dominated by the gate charge current, may be supplied by either the 5.5V linear regula- tor from VCC or the linear regulator from EXTV CC. When the voltage on the EXTVCC pin is less than 6.5V, the linear regulator from VCC is enabled. Power dissipation for the IC in this case is highest and is equal to VCC • IINTVCC. The gate charge current is dependent on operating frequency. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC7820 INTV CC current is limited to less than 27mA from a 48V supply in the UFD package and not using the EXTV CC supply: Where ambient temperature is 70°C and thermal resistance from junction to ambient is 43°C/W To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating at maximum V IN. When the voltage applied to EXTVCC rises above 6.5V and V CC above 7V, the INTVCC linear regulator is turned off and the EXTVCC linear regu- lator is turned on. Using the EXTVCC allows the MOSFET driver and control power to be derived from other high efficiency sources such as the V LOW pin of a 48V to 24V voltage divider or other voltage rails in the system. Using EXTV CC can significantly reduce the IC temperature in high VIN applications. Tying EXTVCC to the output (24V) reduces the junction temperature in the previous example to: = 98°C Do not apply more than 40V to the EXT VCC pin. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors C B1/CB2/CB3 in the Block Diagram, connected to the BOOST pins, supply the gate drive voltages for the top side MOSFETs M1/M2/M3. Capacitor C B3 in the Block Diagram is charged though external Schottky diode DB3 from INTVCC when the SW3 pin is low. Capacitor C B2 is charged through D B2 from BOOST3 when the SW3 pin is high. Capacitor CB1 is charged through DB1 from BOOST2 when the SW1 pin is low. When the MOSFETs M1/M2/M3 are to be turned on, the driver places the CB1/CB2/CB3 voltage across the gate source of the MOSFETs M1/M2/M3. This enhances the MOSFETs and turns them on. The switch node voltage, SW1/SW3, rises to ISENSE+/VLOW and the BOOST pin follows. With continuous switching, the gate driver voltages on CB1/CB2/CB3 are: VCB3 = VINTVCC – VDB3 VCB2 = VINTVCC – VDB3 – VDB2 VCB1 = VINTVCC – VDB3 – VDB2 – VDB1 APPLICATIONS INFORMATION

necessary to raise the gate driver voltages. parator has 200mV of precision hysteresis. adjusting the values of the resistive divider . TIMER pin during a fault condition is shown in Figure 5.

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Figure 5. Timer Behavior During Fault or Startup

7820fcFor more information www.linear.com/LTC7820 Select the CTIMER such that the t CHARGE < tPRE-BALANCE. If the flying capacitor C F LY and the output capacitor are very large and input voltage is high, it may take several pre-balance time periods to pre-balance the VLOW pin to VHIGH_SENSE/2 with a fixed CTIMER. A longer start-up time is expected. If there is a resistive load on the output, the load current needs to be smaller than 93mA and still meet t CHARGE = (C OUT + C F LY) • V IN/2/(93mA – I LOAD) < t PRE- BALANCE. Otherwise a disconnect FET may be required to disconnect the load during startup. Input/Output Capacitor and Flying Capacitor Selection In high power switched capacitor applications, large AC currents flow through the flying capacitors and input/ output capacitors. Low ESR ceramic capacitors are highly recommended for high power switch capacitor applica - tions. Make sure the maximum RMS capacitor current is within the spec; or higher RMS current rated capacitors are preferred. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor , or to choose capacitors rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. The RMS current on the flying capacitors depends on their capacitance and the switching frequency. Higher capaci- tance and higher switching frequency results in lower RMS current. For a good trade-off between efficiency and power density, the RMS current on the flying capacitors should be lower than 140% of the maximum load current. If there are N identical flying capacitors in parallel, the maximum RMS current through each capacitor is: IRMS_CFLY = IOUT(MAX) • 140%/N The input capacitor RMS current is approximately half of the load current. The input capacitor has to be selected to accommodate the maximum load conditions. L Tspice simulation tool can be used to quantify the RMS current. APPLICATIONS INFORMATION Power MOSFETs and Schottky Diodes Selection Four external N-channel MOSFETs must be selected for each LTC7820 controller . Four internal gate drivers are designed to drive the MOSFETs. The driver voltages are decided by the INTV CC voltage, schottky diodes forward voltage drop and switching frequency. The lowest driver voltage is the top MOSFET M1 drive voltage running at high switching frequency and cold temperature. It is normally around 4.2V. Consequently, logic-level threshold MOSFETs must be used in most applications. Be aware that the threshold voltage of some logic-level MOSFET varies with temperature. If switching frequency is high and temperature range is wide for specific applications, the top driver voltage of MOSFET M1 may be as low as 4V, and sub-logic level threshold MOSFETs (V GS(TH) < 3V) should be used. Selection criteria for the power MOSFETs also include the on-resistance R DS(ON), output capacitance COSS, input voltage, and maximum output current. Gener- ally, low RDS(ON) and low COSS MOSFETs are preferred in switched capacitor applications since they will minimize both conduction loss and switching loss. For a given input and output voltage, the uppermost MOSFET M1 always sees high voltage during start-up and shutdown. The Drain to Source voltage of M1 has to be high enough to survive at full input voltage range. Other MOSFETs normally only see half of the input voltage, so the breakdown voltage of M2/M3/M4 can be lower than M1 to optimize R DS(ON) and COSS. If the reliability of M1 is a major concern, the same high voltage MOSFETs could also be used as M2/ M3/M4 to protect against M1 short conditions. External schottky diodes are needed for the bootstrap circuits, and provide voltage for the floating drivers. To minimize the voltage drop on the top gate driver , low forward voltage drop schottky diodes are preferred with load current in the range of 10mA to 50mA. The reverse breakdown voltage of the diodes should be high enough to survive at the maximum operation voltage between the V LOW and GND pins.

7820fc For more information www.linear.com/LTC7820 APPLICATIONS INFORMATION PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. Are the top 2 N-channel MOSFETs M1 and M2 located within 1cm of each other? Are the bottom 2 N-channel MOSFETs M3 and M4 located within 1cm of each other? 2. Is the exposed GND pad solid connected to the source of bottom MOSFET M4 and the negative terminal of CVLOW capacitors? In divider and doubler applications, a solid ground plane is preferred for noise and thermal improvement. Are the I SENSE+ and I SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between I SENSE+ and I SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor . Is the INTVCC bypassing capacitor connected close to the IC, between the INTVCC and the ground plane? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTV CC and GND can substantially improve noise performance. 5. Keep the switching nodes (SW1, SW3), top gate nodes (G1, G2, G3), and boost nodes (BOOST1, BOOST3) away from sensitive small-signal nodes. All of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC7820 and occupy minimum PC trace area. Use a modified star ground technique: a low impedance, large copper area central grounding point on the same side of the PC board as the input and output capaci- tors with tie-ins for the bottom of the INTVCC bypass capacitor . Figure 6 illustrates the high current paths requiring thick and wide copper trace connection. Refer to demo boards on www .linear .com/demo for PCB layout examples. PC Board Layout Debugging Start with one controller at a time. Monitor the switching nodes (SW1/SW3 pin) and probe the V LOW voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the full input voltage range down to dropout. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Reduce V IN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output cur - rents, look for capacitive coupling between the BOOST , SW , G1/2/3/4 connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C IN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC.

Figure 6. High Current Path in Printed Circuit Board Layout Diagram

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7820fc For more information www.linear.com/LTC7820 APPLICATIONS INFORMATION Design Example As a design example using LTC7820 for a high voltage high power voltage divider , assume VIN = 48V (nominal), VIN = 55V (maximum), VOUT = 24V (nominal), IOUT = 15A (maximum). For high power and high voltage applications, always start with a low switching frequency e.g. 200kHz to minimize the switching losses. To set the 200kHz switching frequency, a 60.4k/1% resistor is connected from Freq pin to ground. Setting the C F LY voltage ripple to be 2% of the output voltage is a good starting point with trade-off between efficiency and power density. The CF LY can be calculated based on the equation below: CFLY = IOUT(MAX) 2fSVCFLY(RIPPLE) = 15A 2 • 200kHz • 0.48V = 78.125µF Considering the ceramic capacitance derating at 24V DC bias voltage, 16 of 10µF/X7R/50V ceramic capacitors are paralleled as flying capacitors. The worst case RMS current may be 40% higher than the maximum output current. So the worst case RMS on each capacitor can be estimated by this equation: IRMS(MAX) = IOUT(MAX) • 140% N = 15A • 140% 16 = 1.3125A where N is the number of flying capacitors. Double check and make sure the RMS current on each capacitor is below the ripple current ratings and temperature rise is below the limits. The output capacitor selection is similar to the flying capacitor selection. More output capacitors resulting smaller output voltage ripple. Because of the lower RMS current, the output capacitor value can be much less than the flying capacitor . Some of the capacitors may be con- nected between input and output to serve as input/output capacitors at th e same time, as shown in Figure 6. However the voltage rating of those capacitors has to be selected based on the input voltage instead of the output voltage. For MOSFET selection, the top MOSFET M1 drain to source voltage has to be higher than the maximum input voltage, while the other three MOSFETs drain to source voltage only needs to be higher than half of the maximum input voltage. Since logic level FETs are preferred, an Infineon BSC100N06LS is chosen as the top MOSFET M1 and BSC032N04LS are used as M2/3/4. Based on the output resistance equation in the application section, the output resistance is around 20mΩ, which will result 300mV drop at the 24V output at 15A load current. In reality, due to the finite dead time and parasitic resistance on the PCB, the voltage drop may be higher than the calculated value. Taking into account the output voltage ripple, a window comparator with ±1V programmed hysteresis is used to monitor the output voltage and compares it with the half of the input voltage during operation. To set the 1V hys- teresis, a 100k/1% resistor is connected from HYS_PRGM pin to ground.

Figure 7. High Efficiency 48V/24V to 24V/12V, 15A Voltage Divider

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Figure 8. High Efficiency 24V to 48V, 7.5A Voltage Doubler with Disconnect FET at Input

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Figure 9. High Efficiency 24V to –24V, 10A Voltage Inverter with Hot Swap at Input *OPTIONAL DISCHARGING COMPONENTS FOR FAST STARTUP .

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Figure 10. High Efficiency 24V to 12V, 10A Voltage Divider with Hot Swap at Input *OPTIONAL DISCHARGING COMPONENTS FOR FAST STARTUP .

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Figure 11. High Efficiency 48V to 12V, 20A Voltage Divider

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7820fc For more information www.linear.com/LTC7820 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC7820#packaging for the most recent package drawings. 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0816 REV C RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev C)

7820fcFor more information www.linear.com/LTC7820 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 06/17 Removed TG/BG from EC tables 3S B 07/17 Changed the # of Switching Cycles in Voltage Divider section Modified INTVCC pin description Changed hysteresis voltage in Power Good Section C 10/17 Corrected hot swap part number call-out. 23, 24

Figure 12. High Efficiency 24V to 12V, 15A Voltage Divider with Disconnect FET at Output

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Summary

Fixed Ratio High Power Inductorless (Charge Pump) DC/DC Controller

Description