LTM4633

LTM4633_15 LINER | Alldatasheet

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Technical content

For more information www.linear .com/L TM4633 Typical applicaTion FeaTures DescripTion Triple 10A Step-Down DC/DC µModule Regulator The LT M®4633 µModule® (micromodule) regulator com- bines three complete 10A switching mode DC/DC con - verters into one small package. Included in the package are the switching controllers, power FETs, inductors, and most support components. The L TM4633’s three regula- tors operate from 4.7V to 16V input rail(s) or 2.375V to 16V with an external 5V bias. The V OUT1 and VOUT2 output range is 0.8V to 1.8V , while the VOUT3 output range is 0.8V to 5.5V . Each output is set by one external resistor . High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase parallel operation of V OUT1 and VOUT2, soft-start and output voltage tracking for supply rail sequencing. Fault protection features include overvoltage protection, overcurrent protection and temperature monitoring. The power module is offered in a space saving, thermally enhanced 15mm × 15mm × 5.01mm BGA package. The L TM4633 is RoHS compliant with Pb-free finish. 12V Input to 1.0V , 1.5V and 3.3V Output Regulator Efficiency vs Load Current

applicaTions

n Three Independent 10A DC Output Current Regulator Channels n Input Voltage Range: 4.7V to 16V n 2.375V to 16V with External 5V Bias n VOUT1,2 Voltage Range: 0.8V to 1.8V n VOUT3 Voltage Range: 0.8V to 5.5V n ±1.5% Maximum Total DC Output Error n Current Mode Control/Fast T ransient Response n Frequency Synchronization n Output Overvoltage and Overcurrent Protection n Multiphase Operation with Current Sharing on V OUT1 and VOUT2 n General Purpose Temperature Monitors n Soft-Start/Voltage T racking n Power Good Monitors n 15mm × 15mm × 5.01mm BGA Package n Telecom, Networking and Industrial Equipment n High Density Point of Load Regulation L, L T , L TC, L TM, µModule, PolyPhase, Burst Mode, Linear Technology and the Linear logo are registered trademarks and PowerPath and L TpowerCAD are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258 and 8163643. Other patents pending. 242k 1.0V 10A 69.8k 1.5V 10A 19.1k 3.3V 10A 10k 13.3k 10k 4.7µF 6.3V CNTL_PWR RUN1 RUN2 RUN3 TK/SS1 TK/SS2 TK/SS3 PGOOD12 PGOOD3 V OUT1 VFB1 VOUT2 VFB2 VOUT3 VFB3

4633 TA01a

LOAD CURRENT (A) EFFICIENCY (%)

4633 TA01b

12VIN, 3.3V OUTPUT 12VIN, 1.5V OUTPUT 12VIN, 1V OUTPUT

For more information www.linear .com/L TM4633 pin conFiguraTionabsoluTe MaxiMuM raTings 1V to 18V MODE/PLLIN, TK/SS1, TK/SS2, TK/SS3, RUN1, RUN2, RUN3, INTVCC, EXTVCC, 0.3V to 6V 0.3V to 0.8V Operating Junction Temperature Range (Note 2) 55°C to 125°C 55°C to 125°C (Note 1) A B C D E F SW3 TEMP2 G H J K L M GND TKSS2 TK/SS1 TK/SS3 V FB3 VFB2 VFB1 FREQ/PLLLPF SGND VIN1 SW1 SW2 VIN2VIN3 VOUT3 TOP VIEW BGA PACKAGE 144 LEAD (15mm × 15mm × 5.01mm) VOUT2 VOUT1 GND GND COMP3 COMP2 COMP1 PGOOD12 PGOOD3 EXTVCC GND GND GND GND GND 2 3 4 5 6 7 8 9 10 11 12 TEMP1 INTVCC CNTL_PWR MODE/PLLIN RUN1 RUN2 RUN3 TJMAX = 125°C, θJA = 7.5°C/W , θJCbottom = 4°C/W , θJCtop = 5°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4-LAYER, WEIGHT = 3.3g θ VALUES DETERMINED PER JESD 51-12 orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2) L TM4633EY#PBF L TM4633EY#PBF L TM4633Y 144-Lead (15mm × 15mm × 5.01mm) BGA –40°C to 125°C L TM4633IY#PBF L TM4633IY#PBF L TM4633Y 144-Lead (15mm × 15mm × 5.01mm) BGA –40°C to 125°C L TM4633MPY#PBF L TM4633MPY#PBF L TM4633Y 144-Lead (15mm × 15mm × 5.01mm) BGA –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

For more information www.linear .com/L TM4633 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V , per the typical application for each regulator channel. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage CNTL_PWR Powered from Separate Supply (5V to 16V Range) l 2.375 16 V CNTL_PWR Powered Tied to VIN Supply l 4.7 16 V VOUT(RANGE) Output Voltage Range VOUT1, VOUT2 Output Voltage Range VOUT3 l l 0.8 0.8 1.8 5.5 V V V OUT(DC) Output Voltage, Total Variation with Line and Load, V OUT1, VOUT2, VOUT3 CIN = 22µF × 3, COUT = 100µF Ceramic × 3, RFB = 69k, MODE/PLLIN = 0V , VIN = 4.7V to 16V , IOUT = 0A to 10A (Note 4) l 1.477 1.50 1.523 V Input Specifications VRUN RUN1, RUN 2, RUN 3 Pin ON Threshold V RUN Rising 1.15 1.3 1.4 V VRUN(HYS) RUN Pin Hysteresis 175 mV IQ(VIN) Input Supply Bias Current Each Channel V OUT = 1.5V , Burst Mode Operation VOUT = 1.5V , Pulse-Skipping Mode VOUT = 1.5V , Switching Continuous Shutdown, RUN = 0V 0.5 mA mA mA µA I S(VIN) Input Supply Current Each Channel V OUT = 1.5V , IOUT = 10A 1.5 A Output Specifications IOUT(DC) Output Continuous Current Range Each Channel VOUT = 1.5V (Note 4) 0 10 A ∆VOUT(LINE) VOUT Line Regulation Accuracy per Channel V OUT = 1.5V , VIN from 2.375V to 16V IOUT = 0A, CNTL_PWR = 12V l 0.015 0.02 %/V ∆VOUT(LOAD) VOUT Load Regulation Accuracy per Channel V OUT = 1.5V , IOUT = 0A to 10A (Note 4) l 0.3 0.5 % VOUT(AC) Output Ripple Voltage per Channel IOUT = 0A, COUT = 100µF Ceramic × 3, VOUT = 1.5V 15 mV ∆VOUT(START) Turn-On Overshoot per Channel COUT = 100µF Ceramic × 3, VOUT = 1.5V , IOUT = 0A 20 mV tSTART Turn-On Time per Channel COUT = 100µF Ceramic × 3, No Load, TK/SS = 0.01µF 6 ms VOUTLS Peak Deviation for Dynamic Load per Channel Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 3, VOUT = 1.5V Typical Bench Data 100 mV tSETTLE Settling Time for Dynamic Load Step per Channel Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 3, VOUT = 1.5V Typical Bench Data 40 µs IOUT(PK) Output Current Limit per Channel V OUT = 1.5V 13 A Control Specifications VFB Voltage at VFB Pin per Channel IOUT = 0A, VOUT = 1.5V IOUT = 0A, VOUT = 1.5V l 0.792 0.794 0.80 0.80 0.808 0.806 V V I FB Current at VFB Pin per Channel (Note 3) –10 –50 nA VOVL Feedback Overvoltage Lockout per Channel l 0.84 0.86 0.88 V ITK/SS T rack Pin Soft-Start Pull-Up Current per Channel TK/SS = 0V 1.1 1.5 1.9 µA t ON(MIN) Minimum On-Time (Note 3) 90 ns Max DC Maximum Duty Cycle 2.375V to 2V at 10A, 5.5V to 5V at 0A (Note 6) 100 %

For more information www.linear .com/L TM4633 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V , per the typical application for each regulator channel. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RFBHI Resistor Between VOUT and VFB Pins 60 60.4 60.8 kΩ VPGOOD PGOOD T rip Level PGOOD12 PGOOD3 V FB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –7.5 7.5 V PGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Internal VCC Voltage Float MODE/PLLIN 6V < VIN < 16V 4.8 5 5.2 V VINTVCC Load Reg INTVCC Load Regulation ICC = 0mA to 50mA 0.5 % VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l 4.5 4.7 V VLDO EXT EXTV CC Voltage Drop ICC = 20mA, VEXTVCC = 5V 30 75 mV VLDOHYS EXTV CC Hysteresis 200 mV Oscillator and Phase-Locked Loop fSYNC SYNC Capture Range Clock Input Duty Cycle = 50% 600 750 kHz fS Switching Frequency VFREQ/PLLLPF = INTVCC 700 750 800 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ VIH(MODE/PLLIN) Clock Input Level High 2.0 V VIL(MODE/PLLIN) Clock Input Level Low 0.8 V Clock Phase V OUT2 to VOUT1 Phase VOUT3 to VOUT2 Phase VOUT1 to VOUT3 Phase VFREQ/PLLLPF = 1.2V (Note 3) 120 120 120 Deg Deg Deg V TEMP1,2 Temperature Diode Forward Voltage I TEMP = 100µA at 25°C 0.598 V TC VTEMP Temperature Coefficient –2.0 mV/°C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4633 is tested under pulsed load conditions such that T J ≈ TA. The L TM4633E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4633I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. The L TM4633MP is guaranteed and tested to meet specifications over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level. Note 4: See output current derating curves for different V IN, VOUT and TA. Note 5: Guaranteed by design. Note 6: High duty designs need to be validated based on maximum temperature rise and derating in ambient conditions.

For more information www.linear .com/L TM4633 Typical perForMance characTerisTics 12V to 1V Load Step ResponseLight Load Efficiency 12V to 1.8V Load Step Response 12V to 1.2V Load Step Response 12V to 2.5V Load Step Response12V to 1.5V Load Step Response 5V Input Efficiency 8V Input Efficiency 12V Input Efficiency 5VIN TO 1.5V (700kHz) 5VIN TO 1.2V (700kHz) 5VIN TO 1V (700kHz)

4633 G01

5VIN TO 3.3V (700kHz) 5VIN TO 2.5V (700kHz) 5VIN TO 1.8V (700kHz) LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4 5 6 7 9 10 8VIN TO 1.5V (700kHz) 8VIN TO 1.2V (700kHz) 8VIN TO 1V (700kHz)

4633 G02

8VIN TO 5V (700kHz) 8VIN TO 3.3V (700kHz) 8VIN TO 2.5V (700kHz) 8VIN TO 1.8V (700kHz) LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4 5 6 7 9 10 12VIN TO 1.5V (700kHz) 12VIN TO 1.2V (700kHz) 12VIN TO 1V (700kHz)

4633 G03

12VIN TO 5V (700kHz) 12VIN TO 3.3V (700kHz) 12VIN TO 2.5V (700kHz) 12VIN TO 1.8V (700kHz) LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4 5 6 7 9 10 VOUT 50mV/DIV IOUT 2A/DIV 40µs/DIV CFF = 220pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G04

40µs/DIV CFF = 220pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G05

40µs/DIV CFF = 220pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G06

40µs/DIV CFF = 220pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G07

50µs/DIV CFF = 100pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC

4633 G08

LOAD CURRENT (A) EFFICIENCY (%) 3 3.5 4 4.5

4633 G17

0.5 1 1.5 2 2.5 5 12V TO 1.5V CONT MODE 12V TO 1.5V PULSE SKIP 12V TO 1.5V Burst Mode OPERATION

For more information www.linear .com/L TM4633 Typical perForMance characTerisTics 12V to 5V Load Step Response 12V to 1.5V No-Load Start-Up 12V to 1.5V No-Load Short Circuit 12V to 1.5V , 10A Load Short Circuit Start Into Pre-Bias Output 12V to 1.5V Full-Load Start-Up 3.3V to 1V Load Step Response 3.3V to 1.8V Load Step Response VOUT 100mV/DIV IOUT 2A/DIV 50µs/DIV CFF = 100pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC

4633 G10

100µs/DIV CFF = NONE, 0A TO 5A LOAD STEP AT 5A/µs COUT = 4 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G11

100µs/DIV CFF = NONE, 0A TO 5A LOAD STEP AT 5A/µs COUT = 4 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G12

TK/SS CAPACITOR = 0.1µF COUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G13

TK/SS CAPACITOR = 0.1µF C OUT = 2 × 100µF CERAMIC, 1 × 470µF POSCAP

4633 G14

12V to 3.3V Load Step Response VOUT 100mV/DIV IOUT 2A/DIV 50µs/DIV CFF = 100pF , 0A TO 5A LOAD STEP AT 5A/µs COUT = 2 × 100µF CERAMIC

4633 G09

0.5V/DIV 50ms/DIVVIN = 12V VOUT = 1V PRE-BIASED AT 500mV

4633 G18

For more information www.linear .com/L TM4633 pin FuncTions GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4, G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7, J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, M1, M6-M8, M12): Ground Pins for Both Input and Output Returns. All ground pins need to connect with large copper areas underneath the unit. V OUT1, VOUT2, VOUT3 (A10-A12, B9-B12, and C10-C12); (A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4): Power Output Pins. Apply output load between these pins and the GND pins. Recommend placing output decoupling capacitance directly between these pins and the GND pins. See Table 5. TEMP1 AND TEMP2 (C9, C5): T wo Onboard Temperature Diodes for Monitoring the VBE Junction Voltage Change with Temperature. Each of these two temperature diode connected PNP transistors is placed in the middle of channel 1 and channel 2, and in the middle of channel 2 and channel 3. See the Applications Information section and an example in Figure 19. V IN1,VIN2,VIN3 (F9-F10,G9-G10,H9-H10);(F5-F6,G5- G6,H5-H6);(F1-F2,G1-G2,H1-H2): Power Input Pins. Apply input voltage between these pins and the GND pins. Recommend placing input decoupling capacitance directly between the V IN pins and the GND pins. The V IN paths can be all combined from one power source, or powered from independent power sources. The V IN paths can operate down to 2.375V when the CNTL_PWR is biased separately from a supply in the range of 4.7V to 16V . See the Applications Information section. SW1 (F11), SW2 (F7), SW3 (F3): The internal switch node for each of the regulator channels for monitoring the switching waveform. An R-C snubber circuit can be placed on these pins to ground to eliminate switch node ringing noise. CNTL_PWR (J6): Input Supply to an Internal Bias LDO to Power the Internal Controller and MOSFET Drivers. This pin is connected to an input supply voltage range of 4.7V to 16V . If the voltage at CNTL_PWR is ≤5.5V , the INTV CC pin should be tied to CNTL_PWR for optimum efficiency. If the voltage at CNTL_PWR is >5.5V , leave INTV CC floating with the recommended decoupling capacitor . When using multiple input supplies, choose the lowest input supply between 4.7V to 16V to supply the CNTL_PWR pin. This will lower the internal power loss and improve efficiency. INTV CC (J8): Output of the Internal Bias LDO for Powering Internal Control Circuitry. Connect a 4.7µF ceramic capaci- tor to ground for decoupling. If the voltage at CNTL_PWR is ≤5.5V, tie the INT VCC pin to CNTL_PWR for optimum efficiency. If the voltage at CNTL_PWR is >5.5V , leave INTV CC floating. See the Applications Information section. SGND (K6-K7, L6-L7): Signal Ground Connections. The signal ground connection in the module is separated from normal power ground (GND) by an internal 2.2Ω resistor . This allows the designer to connect the signal ground pin close to GND near the external output capacitors on the regulator channel’s outputs. The entire internal small-signal feedback circuitry is referenced to SGND, thus allowing for better output regulation. See the recommended layout in the Applications Information section. EXTV CC (L3): External Bias Power Input. The internal bias LDO is bypassed whenever the voltage at EXTVCC is above 4.7V . Never exceed 6V at this pin and ensure CNTL_PWR > EXTVCC at all times to avoid reverse polarity on the internal bias LDO. Connect a 1µF capacitor to ground when used otherwise leave floating. When generating a 5V output on channel 3, connect the 5V output to this pin to improve efficiency. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

For more information www.linear .com/L TM4633 pin FuncTions FREQ/PLLLPF (L8): Frequency Set and PLL Lowpass Filter Pin. This pin is driven with a DC voltage to set the operating frequency. Generally the pin is just connected to INTV CC to set the typical 750kHz operating frequency. Applying a DC voltage of 1.4V to this pin will set the frequency to 600kHz and 1.6V will set it to 700kHz. When an external clock is used, then the FREQ/PLLLPF pin must not be connected to any DC voltage. The pin must be floating and will have the proper internal compensation for the internal loop filter . For V OUT1,2,3 ≤ 1.5V use 600kHz, and for V OUT1,2,3 ≥ 1.5V use ≥700kHz. These frequecny settings optimize efficiency and eliminate minimum on-time issues for less than 1V output. See the Applications Information section. MODE/PLLIN (L9): Force Continuous Mode, Burst Mode, or Pulse-Skipping Mode Selection Pin and External Syn- chronization Input to Phase Detector Pin. Connect this pin to SGND to force all channels into the continuous mode of operation. Connect to INT VCC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator . RUN1, RUN2, RUN3 (L10, L11, K11): Run Control Inputs. A voltage above 1.3V on any RUN pin turns on that particular channel. However , forcing any of these RUN pins below 1.2V causes that channel to shut down. Each of the RUN pins has an internal 10k resistor to ground. This resistor can be used with an external pull-up resistor to the input voltage to set a UVLO for that channel, or simply to turn on the channel. The RUN pins have a maximum voltage of 6V . See the Applications Information section. PGOOD12, PGOOD3 (M2, M3): Output voltage power good indicator for V OUT1 and VOUT2 are combined, and VOUT3 separate. The open-drain logic output is pulled to ground when the output voltage is not within ±7.5% of the regulation point. COMP1, COMP2, COMP3 (M4, L4, K4): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The L TM4633 regulator channels are all internally compensated for proper stability. COMP1 and COMP2 can be tied together for PolyPhase ® 20A parallel operation. See the Applications Information section. VFB1, VFB2, VFB3 (M5, L5, K5): The Negative Input of the Error Amplifier for Each of the Three Channels. Internally, each of these pins is connected to their respective output with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between each individual V FB pin and ground. In PolyPhase operation, tying the VFB1 and VFB2 pins together allows for parallel operation up to 20A. See the Applications Information section for details. TK/SS1, TK/SS2, TK/SS3 (M9, M10, M11): Output Voltage T racking and Soft-Start Inputs. When one particular channel is configured to be the master , a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the V FB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.5μA are charging the soft-start capacitors. In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to be shorted externally.

4633 F01

Figure 1. Simplified L TM4633 Block Diagram

For more information www.linear .com/L TM4633 operaTion Power Module Description The L TM4633 µModule regulator is a high performance triple output nonisolated switching mode DC/DC power supply. It can provide 10A per output with a few exter - nal input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.8V DC to 1.8V DC (V OUT1 and VOUT2), and 0.8V DC to 5.5V DC (V OUT3) over a 2.375V to 16V input range with control bias on the CNTL_PWR pin, or 4.7V to 16V with control bias tied to V IN. When applying control bias in the range from 4.7V to 5.5V , then connect the bias to CNTL_PWR and INVT CC, otherwise if >5.5V only bias the CNTL_PWR pin. The typical applica- tion schematic is shown in Figure 16. The LTM4633 has three integrated constant-frequency current mode regulators, power MOSFET s, power induc- tors, and other supporting discrete components. The typical switching frequency is 750kHz. For switching noise-sensitive applications, it can be externally syn - chronized from 600kHz to 750kHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the L TM4633 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an over current condition. An internal over volt- age monitor protects the output voltages in the event of an overvoltage >7.5%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output overvoltage is cleared. There are two temperature moni- tors in the L TM4633. TEMP1 monitors the close relative temperature of channels 1 and 2, and TEMP2 monitors the close relative temperature of channels 2 and 3. The two diode connected PNP transistors are grounded in the module and can be used as general purpose temperature monitors using a device that is designed to monitor the single-ended connection. Pulling any of the RUN pins below 1.3V forces the cor - responding regulator channel into a shutdown state. The TK/SS pins are used for programming the output voltage ramp and voltage tracking during start-up for each of the channels. See the Applications Information section. The LTM4633 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating conditions. The L TpowerCAD™ software tool is provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. Each of the channels, operate with a 120° phase shift for multiphase operation. VOUT1 and VOUT2 can be combined to provide a single 20A output. The two channels will not be operating 180° phase shift, but 120° phase when combined for a 20A design. So the input RMS current will be higher than a 180° phase shifted design. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE/PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load op- eration in the Typical Performance Characteristics section.

mined by the maximum load current and output voltage. for particular applications. ment section and temperature derating curves. Table 1. VFB Resistor Table vs Various Output Voltages TK/SS1 and TK/SS2, and RUN1 and RUN2. inductive leads, traces or not enough source capacitance.

For more information www.linear .com/L TM4633 applicaTions inForMaTion above formula. This will give the maximum RMS capacitor current requirement. Increasing the output current drawn from the other channels will actually decrease the input RMS ripple current from its maximum value. The out-of- phase technique typically reduces the input capacitor’s RMS ripple current by a factor of 50% when compared to a single phase power supply solution. If the three channels are powered from independent input sources, then each of the input RMS current ratings will need to be calculated specific to that channel. Output Capacitors The L TM4633 is designed for low output voltage ripple noise. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient require - ments. C OUT can be a low ESR tantalum capacitor , low ESR Polymer capacitor or ceramic capacitor . The typical output capacitance range is from 200µF to 470µF . Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and L TpowerCAD is available for free to conduct stability analysis. L TpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. Burst Mode Operation The L TM4633 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For ap- plications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. T o enable Burst Mode operation, simply float the MODE/PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V , the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise, the internal sleep line goes low, and the L TM4633 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation I n applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the L TM4633 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE/PLLIN pin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE/PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the L TM4633 output voltage is in regulation.

For more information www.linear .com/L TM4633 applicaTions inForMaTion start capacitor charging current is always flowing, produc- ing a small offset error . To minimize this error , select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the L TM4633 is forced into continuous mode of operation as soon as V FB is below the undervoltage threshold of 0.74V regard- less of the setting of the MODE/PLLIN pin. However , the LTM4633 should always be set in for ce continuous mode tracking down when there is no load. After TK/SS drops below 0.1V , its channel will operate in discontinuous mode. The master’s TK/SS pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: RTB = MR SR    •60.4k where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal the 60.4k. RTA is derived from equation: RTA = 0.8V VFB 60.4k + VFB RFB – VTRACK RTB where VFB is the feedback voltage reference of the regula- tor , and VTRACK is 0.8V . Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 2. In ratiometric tracking, a different slew rate maybe desired for the slave regulator . R TB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. Power Good The PGOOD12 pin is an open-drain pin that can be used to monitor valid output voltage regulation for V OUT1 and VOUT2, and PGOOD3 for monitoring V OUT3. These pins monitor a ±7.5% window around the 0.8V feedback volt- age on either V FB1,2,3 from the output regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Any of the PGOOD pins are pulled low when the RUN pin of the cor- responding channel is pulled low. Overcurrent and Overvoltage Protection Each of the regulator channels senses the peak inductor current on a cycle-by-cycle basis as current mode opera- tion. When current limit is reached the output voltage will begin to fall and the internal current limit threshold will begin fold back as the output voltage falls below 50% of its value. Foldback current limit is disabled during start-up or track-up. Under a short-circuit condition at low duty cycle operation, each of the regulator channels will begin to skip cycles to limit the short-circuit current. Overvoltage protection is implemented by monitoring each one of the regulator’s V FB pins. When the VFB voltage exceeds ~7.5% above the 0.8V reference value, then an internal comparator monitor will turn off the top power switch, and turn on the bottom power switch to protect the load. If the top power switch faults as a short, then a fuse or circuit breaker would be recommended to protect the system. This is due to the top switch being shorted while the bottom switch is turning on to protect the output from over voltage. High currents will flow and could damage the bottom switch.

For more information www.linear .com/L TM4633 applicaTions inForMaTion Stability Compensation The L TM4633 has already been internally compensated for all output voltages. Table 5 is provided for most applica- tion requirements with verified stability. L TpowerCAD is available for other control loop optimization. Run Enable The RUN 1, 2, 3 pins have an enable threshold of 1.4V maximum, typically 1.3V with 175mV of hysteresis. They control the turn-on of their respective channel. There is a 10k resistor on each pin to ground. The RUN pins can be pulled up to V IN for 5V operation, or a resistor can be placed on the pins and connected to VIN for higher than 5V input. This resistor can be set along with the onboard 10k resistor such that an undervoltage lockout (UVLO) level can be programmed to shut down a particular regulator channel if V IN falls below a set value. Use the equation: R = 10k UVLO–1.3V( ) 1.3V where R is the resistor from the RUN pin to VIN to set the UVLO trip point. For example, if the UVLO point is to be 6.25V while operating at 12V input: 1.3V ≈ 38.3k See the Typical Application circuits in Figure 17. The RUN pins must not go above 6V maximum voltage. The RUN pins have to be pulled up to enable the regulators. SW Pins The SW pins are generally used for testing purposes by monitoring the pin of interest. The SW pins can also be used to dampen out switch node ringing caused by LC parasitics in the switched current path. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the PowerPath™ board inductance in combination with the MOSFET inter- connect inductance. First, the SW pin can be monitored using a wide band - width scope with a high frequency scope probe. The ring frequency can be measured for its value. The impedance, Z, can be calculated: Z(L) = 2π • f • L where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is then chosen so that its impedance is equal to the resistor at the ring frequency: Z(C) = 1 2π • f •C These values are a good place to start with. Modification to these components should be made to attenuate the ring- ing without lowering the regulator’s conversion efficiency. INTV CC and EXTVCC The L TM4633 has an onboard linear regulator fed by CNTL_PWR which delivers a roughly 5V output at INTVCC to power the internal controller and MOSFET drivers for all three regulator channels. CNTL_PWR requires a voltage between 4.7V to 16V . Apply a 4.7µF ceramic capacitor between INTV CC and ground for decoupling. If the volt - age supplied to CNTL_PWR is ≤ 5.5V , connect INTVCC to CNTL_PWR. Otherwise, INTVCC should be left floating. To eliminate power loss in the onboard linear regulator and improve efficiency connect a supply from 4.7V to 6V at EXTV CC. Biasing EXTVCC will reduce the power loss in the internal LDO by (VCNTL_PWR – 5V) • 70mA. If EXTVCC is used add a 1µF ceramic capacitor to ground at EXTVCC and

For more information www.linear .com/L TM4633 applicaTions inForMaTion ensure the voltage at CNTL_PWR is always greater than the voltage at EXTVCC at all times including during start-up and shutdown. Connecting VOUT3 to EXTVCC may present a convenient way to meet the sequencing requirement if V OUT3 is a 5V output. Otherwise float EXTVCC if not used. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configura - tion section of the data sheet are consistent with those parameters defined by JESD 51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per- formed on a µModule package mounted to a hardware test board defined by JESD 51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers in lieu or to compliment any FEA activities may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regula- tor’s thermal performance in their application at various electrical and environmental operating conditions. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section provides values based on four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased: θJA: The thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom: The thermal resistance from the junction to the bottom of the product case, is determined with all of the internal power dissipation flowing through the bottom of the package. In a typical µModule regulator , the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop: The thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJB: The thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured at a specified distance from the package, using a 2-sided, 2-layer board. This board is described in JESD 51-9.

resistances are external to the µModule package. airflow, a majority of the heat flow is into the board. provided in other sections of this data sheet.

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Figure 3. Graphical Representations of JESD51-12 Thermal Coefficients

For more information www.linear .com/L TM4633 applicaTions inForMaTion defined chamber . This θJB + θBA value should accurately equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambi- ent with no air-flow or top mounted heat sink. LTM4633 Thermal Considerations and Output Current Derating The power loss cur ves at 5V input, 8V input, and 12V input are in Figures 7 to 9. These power loss curves can be used in coordination with the load current derating curves in Figures 10 to 15 for calculating an approximate θ JA thermal resistance for the L TM4633 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a multiplicative factor of 1.4 at 125°C junction. This factor comes from the fact that the power loss of the regulator increases about 50% from 25°C to 150°C, thus a 50% spread over 125°C delta equates to ~0.4%/°C power loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multiplied by 0.4%/°C equals a 40% power loss increase at the 125°C junction, thus the 1.4 multiplier . The derating curves are plotted with the output current starting at 30A and the ambient temperature at 40°C. The 30A come from each of the three channels operating at 10A each. This simplifies the loading for this thermal testing. The output voltages are 1.0V and 1.8V when all three channels are loaded together in parallel. Channel 1 and Channel 2 are designed to operate with outputs up to 1.8V . T wo additional derating curves are shown with Channel 1 and Channel 2 operating at 1.8V at 10A each for a total of 20A while Channel 3 is at 5V with 10A load current derated over ambient temperature. This is done to look at some of the different output power conditions to correlate thermal resistance numbers that can be used for derating the L TM4633 power module with different output power requirements. The power loss curve values at a particular output voltage and output current for each output are taken and multiplied by 1.4 for increased power loss at 125°C junction. Thermal models are derived from several temperature measurements in a controlled tem - perature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow . The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 125°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 125°C minus the ambi- ent operating temperature specifies how much temperature rise can be allowed. For example, in Figure 11, the 1V load current is derated to ~20A at ~85°C with no air and with heat sink. In Figure 9, the 12V to 1.0V power loss at 6.66A per channel is 1.4W . The total power loss would be 3 times 1.4W or 4.2W . The 4.2W is then multiplied by the 1.4 multiplier for 125°C junction. This 5.88W value is used with the total temperature rise of 125°C minus the 85°C ambient to calculate θ JA thermal resistance. If the 85°C ambient temperature is subtracted from the 125°C junction temperature, then the difference of 40°C divided by 5.88W equals a 6.8°C/W θ JA thermal resistance. Table 2 specifies a 6°C/W value which is very close. Tables 2 to 4 provide equivalent thermal resistances for 1.0V , 1.8V , and combination 1.8V and 5V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 2 and 4 for the various conditions can be multiplied by the calculated power loss as a function of the 125°C maximum junction temperature to determine if the tem - perature rise plus ambient is below the 125°C maximum junction temperature. Thermal or infrared imaging should be per formed to validate the calculated results. Room temperature power loss can be derived from the power

value with increased temperature. Figure 4. TEMP Pin Diode Voltage vs Temperature Figure 5. Thermal Plot for 12V Input to 1.8V at 10A Output 1,

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For more information www.linear .com/L TM4633 applicaTions inForMaTion If we take this equation an differentiate it with respect temperature T , then: dVD dt = – VGO – VD T This dVD/dT change as a function of temperature is the typical ~–2.0mV/°C. This equation is simplified for the first order derivation. Solving for T , T = –(V G0 – VD)/dVD provide the temperature. 1st Example: Figure 4 for 27°C, or 300°C Kelvin the diode voltage is 0.598V , thus, 300°C = –(1200mV – 598mV)/ –2.0 mV/°C) 2nd Example: Figure 4 for 75°C, or 350°C Kelvin the diode voltage is 0.50V , thus, 350°C = –(1200mV – 500mV)/ –2.0mV /°C) Converting the Kelvin scale to Celsius is simply taking the Kelvin temp and subtracting –273°C Kelvin from it. A typical forward voltage is measured and placed in the electrical characteristics section of the data sheet, and Figure 4 is the plot of this for ward voltage. Measure this forward voltage at 27°C to establish a reference point. Then use the above expression while measuring the forward voltage over temperature will provide a general temperature monitor . The diode connected PNP transistor at the TEMP pins can be used to monitor the internal temperature of the L TM4633. A general temperature monitor can be implemented by connecting a resistor between TEMP and V IN to set the current to 100µA, and then monitoring the diode voltage drop with temperature. See Figure 19 for an example. Safety Considerations The L TM4633 module does not provide galvanic isolation from V IN to any of the three V OUTs. There is no internal fuse. If required, a slow blow fuse with a rating higher than the maximum input current can be used to protect the unit in case of a catastrophic failure. An inline circuit breaker function can also be used instead of a fuse. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bot- tom MOSFET . This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondar y fault protector in this situation. Layout Checklist/Example The high integration of L TM4633 makes the PCB board layout very simple and easy. However , to optimize its electri- cal and thermal performance, some layout considerations are still necessary Use large PCB copper areas for high current paths, in - cluding VIN, GND, V OUT1, VOUT2, and V OUT3. It helps to minimize the PCB conduction loss and thermal stress. Place high frequency ceramic input and output capacitors next to the V IN, GND and the VOUT pins to minimize high frequency noise. Place a dedicated power ground layer underneath the unit. To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection be- tween top layer and other power layers. Do not put vias directly on the pads, unless they are capped or plated over. Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. Bring out test points on the signal pins for monitoring. Figure 6 gives a good example of the recommended layout.

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Figure 6. Recommended PCB Layout

Figure 10. 12VIN, 1VOUT, No Heat Figure 13. 12VIN, 1.8VOUT, With Heat Figure 11. 12VIN, 1VOUT, With Heat Figure 14. 12VIN, 1.8VOUT at 20A, Figure 15. 12VIN, 1.8VOUT at 20A, Figure 12. 12VIN, 1.8VOUT, No Heat Figure 7. 5V Input Power Loss Figure 8. 8V Input Power Loss Figure 9. 12V Input Power Loss

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Table 2. 1.0V Output Table 3. 1.8V Output Table 4. 5V Output, 1.8V Output at 20A on Ch1 and Ch2

Table 5. Output Voltage Response Versus Component Matrix (Refer to Figure 16) 0 to 5A Load Step Typical Measured Values *Bulk capacitance is optional if VIN has very low input impedance.

Figure 16. L TM4633 Typical 12V Input to 1.5V at 10A, 1.2V at 10A, 3.3V at 10A

Figure 17. L TM4633 T riple Input and T riple Output (1.0V , 1.2V and 5V) at 10A

Figure 18. 3.3V Input to 1V at 20A, and 2.5V to 1.2V at 10A

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Figure 19. 5V Input, 1V , 1.8V and 2.5V at 10A with T racking

For more information www.linear .com/L TM4633 L TM4633 Component BGA Pinout package DescripTion PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT3 B1 V OUT3 C1 V OUT3 D1 GND E1 GND F1 V IN3 A2 V OUT3 B2 V OUT3 C2 V OUT3 D2 GND E2 GND F2 V IN3 A3 V OUT3 B3 V OUT3 C3 V OUT3 D3 GND E3 GND F3 SW3 A4 GND B4 V OUT3 C4 V OUT3 D4 GND E4 GND F4 GND A5 V OUT2 B5 V OUT2 C5 TEMP2 D5 GND E5 GND F5 V IN2 A6 V OUT2 B6 V OUT2 C6 V OUT2 D6 GND E6 GND F6 V IN2 A7 V OUT2 B7 V OUT2 C7 V OUT2 D7 GND E7 GND F7 SW2 A8 GND B8 V OUT2 C8 V OUT2 D8 GND E8 GND F8 GND A9 GND B9 V OUT1 C9 TEMP1 D9 GND E9 GND F9 V IN1 A10 V OUT1 B10 V OUT1 C10 V OUT1 D10 GND E10 GND F10 V IN1 A11 V OUT1 B11 V OUT1 C11 V OUT1 D11 GND E11 GND F11 SW1 A12 V OUT1 B12 V OUT1 C12 V OUT1 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 V IN3 H1 V IN3 J1 GND K1 GND L1 GND M1 GND G2 V IN3 H2 V IN3 J2 GND K2 GND L2 GND M2 PGOOD12 G3 GND H3 GND J3 GND K3 GND L3 EXTV CC M3 PGOOD3 G4 GND H4 GND J4 GND K4 COMP3 L4 COMP2 M4 COMP1 G5 V IN2 H5 V IN2 J5 GND K5 V FB3 L5 V FB2 M5 V FB1 G6 V IN2 H6 V IN2 J6 CNTL_PWR K6 SGND L6 SGND M6 GND G7 GND H7 GND J7 GND K7 SGND L7 SGND M7 GND G8 GND H8 GND J8 INTV CC K8 GND L8 FREQ/PLLLPF M8 GND G9 V IN1 H9 V IN1 J9 GND K9 GND L9 MODE/PLLIN M9 TK/SS1 G10 V IN1 H10 V IN1 J10 GND K10 GND L10 RUN1 M10 TK/SS2 G11 GND H11 GND J11 GND K11 RUN3 L11 RUN2 M11 TK/SS3 G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND package phoTo

For more information www.linear .com/L TM4633 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z SUGGESTED PCB LAYOUT TOP VIEW BGA 144 0613 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 0.0000 0.0000 D A DETAIL B PACKAGE SIDE VIEW Z 0.630 ±0.025 Ø 144x E 144-Lead (15mm × 15mm × 5.01mm) (Reference LTC DWG # 05-08-1908 Rev Ø) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z 0.0 PACKAGE BOTTOM VIEW PIN 1 DETAIL A Øb (144 PLACES) M X Y Z ddd M Z eee e F NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A SEE NOTES L K J H G F E D C B M A 1 2 3 4 5 6 7 810 911 12 e G

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES b b

For more information www.linear .com/L TM4633  LINEAR TECHNOLOGY CORPORATION 2013 LT 1013 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4633 Typical applicaTion relaTeD parTs RFB3 121k RFB2 243k RFB1 487k COUT3* COUT6 470µF COUT8 470µF COUT2 100µF 220pF 0.9V VFB1 VFB2 1.0V 1.2V COUT5 100µF 220pF VFB3 100pF COUT1 100µF COUT4 100µF 100µF COUT7 100µF VFB2 VFB3 FOR COUT, RFB, COMP AND CFF SEE TABLE 5 0.1µF 1.2V 13.3k 24.3k48.7k 6.04k 6.04k CIN3 22µF 16V CIN2 22µF 16V CIN1 22µF 16V CIN4 22µF 16V 10k 10k FREQ = 500kHz 30k 10kCNTL_PWR MODE/PLLIN RUN1 RUN2 RUN3 TK/SS2 TK/SS3 FREQ/PLLLPF COMP1 COMP2 COMP3 PGOOD12 PGOOD3 TEMP1 TEMP2 V OUT1 VFB1 VFB1 VOUT2 VFB2 VOUT3 VFB3 4633 F20 GND SGND VIN1 SW1 V IN2 12V INPUT SW2 V IN3 L TM4633 SW3 4.7µF 6.3V INTVCC EXTVCC TK/SS1 *1000µF , 2.5V POSCAP (2R5TPE1000MF) Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability TechClip Videos Quick videos detailing how to bench test electrical and thermal per formance of µModule products. PART NUMBER DESCRIPTION COMMENTS L TM4630 Dual 15VIN, 18A or Single 36A Step-Down µModule Regulator with VOUT Up to 1.8V 4.5V ≤ VIN ≤ 15V , 0.6V ≤ VOUT ≤ 1.8V , PLL Input, Remote Sense Amplifier , VOUT T racking, PGOOD, CLKOUT , Internal Temperature Monitor , 16mm × 16mm × 4.41mm LGA LTM4624 14VIN, 4A Step-Down µModule Regulator in Tiny 6.25mm × 6.25mm × 5.01mm BGA 4V ≤ VIN ≤ 14V , 0.6V ≤ VOUT ≤ 5.5V , VOUT T racking, PGOOD, Light Load Mode, Complete Solution in 1cm2 (Single-Sided PCB) L TM8028 36VIN, UltraFast™, Low Output Noise 5A µModule Regulator 6V ≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 1.8V Set Via 3-Pin Three-State Interface, <1mV VOUT Ripple, 10% Accurate Current Limit, PGOOD, 15mm × 15mm × 4.9mm BGA LTM4637 20VIN, 20A DC/DC µModule Step-Down Regulator 4.5V ≤ V IN ≤ 20V , 0.6V ≤ VOUT ≤ 5.5V , PLL Input, VOUT T racking, Remote Sense Amplifier , PGOOD, 15mm × 15mm × 4.32mm LGA