LTM4634 LINER | Alldatasheet
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Technical content
For more information www.linear .com/L TM4634 Typical applicaTion FeaTures DescripTion Triple Output 5A/5A/4A Step-Down DC/DC µModule® Regulator The LT M®4634 integrates three complete 5A/5A/4A high efficiency switching mode DC/DC converters into one small package. Switching controllers, power FETs, inductors, and most support components are included. Operating over an input voltage range of 4.75V to 28V , the L TM4634 provides three independent output voltages. V OUT1 and VOUT2 are adjustable from 0.8V to 5.5V , while VOUT3 is adjustable from 0.8V to 13.5V . Each output voltage is set by a single external resistor . High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase parallel opera - tion, soft-start and output voltage tracking for supply rail sequencing. Fault protection features include over voltage protection, over current protection and temperature monitoring. The power module is offered in a space saving, thermally enhanced 15mm × 15mm × 5.01mm BGA package. The L TM4634 is available with SnPb (BGA) or RoHS compliant terminal finish. 24V Input to 3.3V , 5V and 12V Output Regulator 24V Input Efficiency
applicaTions
n Three Independent High Efficiency Regulator Channels n IOUT1,2 = 5A, IOUT3 = 4A n Input Voltage Range: 4.75V to 28V n Independent VIN for Each Channel n VOUT1,2 Voltage Range: 0.8V to 5.5V n VOUT3 Voltage Range: 0.8V to 13.5V n ±1.5% Maximum Total DC Output Error n Current Mode Control/Fast T ransient Response n Frequency Synchronization n Output Overvoltage and Overcurrent Protection n PolyPhase® Operation with Current Sharing n General Purpose Temperature Monitors n Soft-Start/Voltage T racking n Power Good Monitors n SnPb or RoHS Compliant Finish n 15mm × 15mm × 5.01mm BGA Package n Telecom, Networking and Industrial Equipment n High Density Point of Load Voltage Regulation L, L T , L TC, L TM, µModule, PolyPhase, Burst Mode, Linear Technology and the Linear logo are registered trademarks and PowerPath, L TpowerCAD and UltraFast are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258 and 8163643. Other patents pending.19.1k 3.3V 11.5k 4.32k 12V 10k40k 2/uni03A9 1µF 10k 4.7µF 6.3V CNTL_PWR RUN1 RUN2 RUN3 TK/SS1 TK/SS2 TK/SS3 PGOOD12 PGOOD3 V OUT1 VFB1 VOUT2 VFB2 VOUT3 VFB3
4634 TA01a
LOAD CURRENT (A) EFFICIENCY (%) 4.5 4.0
4634 TA01b
24V to 3.3V EFF (750kHz) CH1 24V to 5V EFF (750kHz) CH2 24V to 12V EFF (750kHz) CH3 VEXTVCC = 5V
For more information www.linear .com/L TM4634 pin conFiguraTionabsoluTe MaxiMuM raTings 1V to 30V MODE/PLLIN, TK/SS1, TK/SS2, TK/SS3, 0.3V to INTVCC COMP1, COMP2, COMP3, VFB1, VFB2, VFB3 0.3V to INTVCC RUN1, RUN2, RUN3, INTVCC, EXTVCC, 0.3V to 6V 0.3V to 0.8V Operating Junction Temperature Range (Note 2) 40°C to 125°C 55°C to 125°C (Note 1) A B C D E F SW3 TEMP2 G H J K L M GND TKSS2 TK/SS1 TK/SS3 V FB3 VFB2 VFB1 FREQ/PLLLPF SGND VIN1 SW1 SW2 VIN2VIN3 VOUT3 TOP VIEW BGA PACKAGE 144 LEAD (15mm × 15mm × 5.01mm) VOUT2 VOUT1 GND GND COMP3 COMP2 COMP1 PGOOD12 PGOOD3 EXTVCC GND GND GND GND GND 2 3 4 5 6 7 8 9 10 11 12 TEMP1 INTVCC CNTL_PWR MODE/PLLIN RUN1 RUN2 RUN3 TJMAX = 125°C, θJA = 7.5°C/W , θJCbottom = 4°C/W , θJCtop = 5°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4-LAYER, WEIGHT = 3.2g θ VALUES DETERMINED PER JESD51-12 orDer inForMaTion PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (See Note 2)DEVICE FINISH CODE L TM4634EY#PBF SAC305 (RoHS) L TM4634Y e1 BGA 4 –40°C to 125°C L TM4634IY#PBF SAC305 (RoHS) L TM4634Y e1 BGA 4 –40°C to 125°C L TM4634IY SnPb (63/37) L TM4634Y e0 BGA 4 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.
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For more information www.linear .com/L TM4634 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 24V , per the typical application for each regulator channel. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage CNTL_PWR Powered Tied to Input Supply l 4.75 28 V VOUT(RANGE) Output Voltage Range VOUT1, VOUT2 Output Voltage Range VOUT3 l l 0.8 0.8 5.5 13.5 V V V OUT(DC) Output Voltage, Total Variation with Line and Load, V OUT1, VOUT2, VOUT3 CIN = 22µF × 3, COUT = 100µF Ceramic × 3, RFB = 11.5k, MODE/PLLIN = 0V , VIN = 5.5V to 28V , IOUT1,2 = 0A to 5A, IOUT3 = 0A to 4A (Note 4) l 4.925 5.0 5.075 V Input Specifications VRUN RUN1, RUN2, RUN3 Pin ON Threshold V RUN Rising 1.15 1.3 1.4 V VRUN(HYS) RUN Pin Hysteresis 175 mV IQ(VIN) Input Supply Bias Current Each Channel V OUT = 5V , Burst Mode Operation, IOUT = 0A VOUT = 5V , Pulse-Skipping Mode, IOUT = 0A VOUT = 5V , Switching Continuous, IOUT = 0A Shutdown, RUN = 0V , VIN = 24V 0.5 1.6 mA mA mA µA I S(VIN) Input Supply Current Each Channel V IN = 12V , EXTVCC = 5VOUT VOUT1,2 = 5V , VOUT3 = 5V IOUT1,2 = 5A 2.21 A IOUT3 = 4A 1.76 A Output Specifications (Note 4) IOUT(DC) Output Continuous Current Range Each Channel VOUT1,2 = 5V VOUT3 = 5V A A OUT(LINE) VOUT Line Regulation Accuracy per Channel V OUT1 = VIN from 5.5V to 28V IOUT = 0A, CNTL_PWR Tie to VIN l 0.015 0.02 %/V ∆VOUT(LOAD) VOUT Load Regulation Accuracy per Channel V OUT = 5V , IOUT1,2 = 0A to 5A Ch1, Ch2, IOUT3 = 0A to 4A l 0.3 0.5 % VOUT(AC) Output Ripple Voltage per Channel IOUT = 0A, COUT = 100µF Ceramic × 3, VIN = 24V , VOUT = 5V 75 mV ∆VOUT(START) Turn-On Overshoot per Channel COUT = 100µF Ceramic × 3, VOUT = 5V , IOUT = 0A, TK/SS = 0.01µF 50 mV tSTART Turn-On Time per Channel COUT = 100µF Ceramic × 3, VOUT = 5V , IOUT = 0A, TK/SS = 0.01µF 6 ms VOUTLS Peak Deviation for Dynamic Load per Channel Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 3, VOUT = 5V Typical Bench Data 200 mV tSETTLE Settling Time for Dynamic Load Step per Channel Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic × 3, VOUT = 5V Typical Bench Data 50 µs IOUT(PK) Output Current Limit per Channel V OUT = 5V 8 A Control Specifications VFB Voltage at VFB Pin per Channel IOUT = 0A, VOUT = 5V l 0.794 0.792 0.80 0.80 0.806 0.808 V V I FB Current at VFB Pin per Channel (Note 3) –10 –50 nA VOVL Feedback Overvoltage Lockout per Channel l 0.84 0.86 0.88 V ITK/SS T rack Pin Soft-Start Pull-Up Current per Channel TK/SS = 0V 1.1 1.5 1.9 µA t ON(MIN) Minimum On-Time (Note 3) 90 ns Max DC Maximum Duty Cycle 5.5V to 5V at 5A (Note 5) 95 % RFBHI Resistor Between VOUT and VFB Pins 60.0 60.4 60.8 kΩ
For more information www.linear .com/L TM4634 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 24V , per the typical application for each regulator channel. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VPGOOD PGOOD T rip Level PGOOD12 PGOOD3 V FB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –7.5 7.5 V PGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Internal VCC Voltage Float MODE/PLLIN 6V < VIN < 28V , ICC = 0mA 4.8 5 5.2 V VLDOINT INTVCC Load Regulation ICC = 0mA to 100mA 1 % VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l 4.5 4.7 V VLDOEXT EXTV CC Voltage Drop ICC = 20mA, VEXTVCC = 5V 30 75 mV VLDOHYS EXTV CC Hysteresis 200 mV Oscillator and Phase-Locked Loop fSYNC SYNC Capture Range Clock Input Duty Cycle = 50% 250 750 kHz fS Switching Frequency VFREQ/PLLLPF = INTVCC 700 750 825 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ VIH(MODE/PLLIN) Clock Input Level High 2.0 V VIL(MODE/PLLIN) Clock Input Level Low 0.8 V Clock Phase V OUT2 to VOUT1 Phase VOUT3 to VOUT2 Phase VOUT1 to VOUT3 Phase VFREQ/PLLLPF = 1.2V (Note 3) 120 120 120 Deg Deg Deg V TEMP1,2 Temperature Diode Forward Voltage I TEMP = 100µA 0.598 V TC VTEMP Temperature Coefficient –2.0 mV/°C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4634 is tested under pulsed load conditions such that T J ≈ TA. The L TM4634E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4634I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level. Note 4: See output current derating curves for different V IN, VOUT and TA. Note 5: High duty designs need to be validated based on maximum temperature rise and derating in ambient conditions.
For more information www.linear .com/L TM4634 Typical perForMance characTerisTics 24V Input Efficiency (Ch1 and Ch2)12V Input Efficiency (Ch3) 24V Input Efficiency (Ch3) 24V Input Continuous, Pulse- Skipping and Burst Mode Operation 5V Input Efficiency (Ch1 and Ch2) 5V Input Efficiency (Ch3) 12V Input Efficiency (Ch1 and Ch2) LOAD CURRENT (A) EFFICIENCY (%) 100 4.0
4634 G07
5.0VOUT (750kHz) BURST 5.0VOUT (750kHz) PULSE 5.0VOUT (750kHz) CONT 24V to 5V Load Step Response24V to 3.3V Load Step Response OUTPUT 100mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G08 0A TO 2.5A, 2.5A/µs LOAD STEP COUT = 2 × 100µF CERAMIC CAPACITOR OUTPUT 100mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G09 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR LOAD CURRENT (A) EFFICIENCY (%) 100 4.0
4634 G01
5V TO 1.0V EFF (250kHz) 5V TO 1.2V EFF (250kHz) 5V TO 1.5V EFF (250kHz) 5V TO 1.8V EFF (250kHz) 5V TO 2.5V EFF (250kHz) 5V TO 3.3V EFF (250kHz) LOAD CURRENT (A) EFFICIENCY (%) 4.0
4634 G02
5V TO 1.OV EFF (250kHz) 5V TO 1.2V EFF (250kHz) 5V TO 1.5V EFF (250kHz) 5V TO 1.8V EFF (250kHz) 5V TO 2.5V EFF (250kHz) 5V TO 3.3V EFF (250kHz) LOAD CURRENT (A) EFFICIENCY (%) 100 4.0
4634 G03
VEXTVCC = 5V 12V TO 1.0V EFF (250kHz) 12V TO 1.2V EFF (250kHz) 12V TO 1.5V EFF (250kHz) 12V TO 1.8V EFF (250kHz) 12V TO 2.5V EFF (250kHz) 12V TO 3.3V EFF (250kHz) 12V TO 5.0V EFF (250kHz) LOAD CURRENT (A) EFFICIENCY (%) 4.0
4634 G04
VEXTVCC = 5V 12V TO 1.0V EFF (250kHz) 12V TO 1.2V EFF (250kHz) 12V TO 1.5V EFF (250kHz) 12V TO 1.8V EFF (250kHz) 12V TO 2.5V EFF (250kHz) 12V TO 3.3V EFF (250kHz) 12V TO 5.0V EFF (250kHz) LOAD CURRENT (A) EFFICIENCY (%) 100 4.0
4634 G05
VEXTVCC = 5V 24V TO 1.0V EFF (250kHz) 24V TO 1.2V EFF (250kHz) 24V TO 1.5V EFF (300kHz) 24V TO 1.8V EFF (350kHz) 24V TO 2.5V EFF (350kHz) 24V TO 3.3V EFF (600kHz) 24V TO 5.0V EFF (750kHz) LOAD CURRENT (A) EFFICIENCY (%) 4.0
4634 G06
VEXTVCC = 5V 24 TO 1.0V EFF (250kHz) 24 TO 1.2V EFF (250kHz) 24 TO 1.5V EFF (250kHz) 24 TO 1.8V EFF (300kHz) 24 TO 2.5V EFF (300kHz) 24 TO 3.3V EFF (350kHz) 24 TO 5.0V EFF (500kHz)
24 TO 12V EFF (750kHz)
For more information www.linear .com/L TM4634 Typical perForMance characTerisTics 24V to 5V No Load Short 12V to 1.2V Load Step Response 12V to 1.8V Load Step Response 12V to 2.5V Load Step Response 24V to 5V No Load Start-Up 12V to 1.5V Load Step Response 24V to 12V Load Step Response 12V to 1V Load Step Response 24V to 5V Full Load Start-Up OUTPUT 100mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G10 0A TO 2A, 2A/µs LOAD STEP COUT = 2 × 100µF CERAMIC CAPACITOR AND 100µF 16V 16TQC100MYF POS CAPACITOR OUTPUT 50mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G11 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR AND 470µF 2V 2TPE470MAJB POS CAPACITOR OUTPUT 50mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G12 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR AND 470µF 2V 2TPE470MAJB POS CAPACITOR OUTPUT 50mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G13 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR AND 470µF 2V 2TPE470MAJB POS CAPACITOR OUTPUT 50mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G14 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR OUTPUT 50mV/DIV LOAD STEP 1A/DIV 100µs/DIV 4634 G15 0A TO 2.5A, 2.5A/µs LOAD STEP C OUT = 2 × 100µF CERAMIC CAPACITOR VOUT 1V/DIV IOUT 1A/DIV 20ms/DIV 4634 G16VIN = 24V VOUT = 5V IOUT = 0A COUT = 2 × 100µF X5R 1210 VOUT 1V/DIV IOUT 1A/DIV 20ms/DIV 4634 G17VIN = 24V VOUT = 5V IOUT = 5A COUT = 2 × 100µF X5R 1210 VOUT 2V/DIV IIN 1A/DIV 20µs/DIV 4634 G18VIN = 24V VOUT = 5V IOUT = 0A COUT = 2 × 100µF X5R 1210
For more information www.linear .com/L TM4634 Typical perForMance characTerisTics 24V to 5V Full Load Short Start-Up into Pre-Bias Steady-State Output Ripple pin FuncTions GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4, G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7, J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, M1, M6-M8, M12): Ground Pins for Both Input and Output Returns. All ground pins need to connect with large copper areas underneath the unit. V OUT1, VOUT2, VOUT3 (A10-A12, B9-B12, and C10-C12); (A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4): Power Output Pins. Apply output load between these pins and the GND pins. Recommend placing output decoupling capacitance directly between these pins and the GND pins. See Table 4. TEMP1 AND TEMP2 (C9, C5): T wo Onboard Temperature Diodes for Monitoring the VBE Junction Voltage Change with Temperature. Each of these two temperature diode connected PNP transistors is placed in the middle of channel 1 and channel 2, and in the middle of channel 2 and channel 3. See the Applications Information section and an example in Figure 25. Leave floating if not used. V IN1,VIN2,VIN3 (F9-F10,G9-G10,H9-H10);(F5-F6,G5- G6,H5-H6);(F1-F2,G1-G2,H1-H2): Power Input Pins. Apply input voltage between these pins and the GND pins. Recommend placing input decoupling capacitance directly between the V IN pins and the GND pins. The V IN paths can be all combined from one power source, or powered from independent power sources. See the Applications Information section. SW1 (F11), SW2 (F7), SW3 (F3): The internal switch node for each of the regulator channels for monitoring the switching waveform. An R-C snubber circuit can be placed on these pins to ground to eliminate switch node ringing noise. CNTL_PWR (J6): Input Supply to an Internal Bias LDO to Power the Internal Controller and MOSFET Drivers. The operating voltage range is 4.75V to 28V under all condi- tions. If the voltage at CNTL_PWR is ≤5.8V , the INTV CC pin should be tied to CNTL_PWR for optimum efficiency. If the voltage at CNTL_PWR is >5.8V , leave INTV CC float- ing with the recommended decoupling capacitor . To eliminate power loss in the onboard linear regulator and improve efficiency connect a 5V supply at EXTV CC. Ensure CNTL_PWR > EXTVCC at all times to avoid reverse polarity on the internal bias LDO. VOUT 2V/DIV IIN 1A/DIV 20µs/DIV 4634 G19VIN = 24V VOUT = 5V IOUT = 5A COUT = 2 × 100µF X5R 1210 PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . RUN 5V/DIV VOUT1 1V/DIV SW 10V/DIV 20ms/DIV 4634 G20 PREBIAS 1.5V OUTPUT STARTING AT 0.5V BIAS 12V INPUT VOUT RIPPLE 10mV/DIV SW NODE 5V/DIV 2µs/DIV 4634 G21 12V TO 3.3V AT 5A LOAD
For more information www.linear .com/L TM4634 pin FuncTions INTVCC (J8): Output of the Internal Bias LDO for Powering Internal Control Circuitry. Connect a 4.7µF ceramic capaci- tor to ground for decoupling. If the voltage at CNTL_PWR is ≤5.8V, tie the INT VCC pin to CNTL_PWR for optimum efficiency. If the voltage at CNTL_PWR is >5.8V , leave INTV CC floating. See the Applications Information section. SGND (K6-K7, L6-L7): Signal Ground Connections. The signal ground connection in the module is separated from normal power ground (GND) by an internal 2.2Ω resistor . This allows the designer to connect the signal ground pin close to GND near the external output capacitors on the regulator channel’s outputs. The entire internal small-signal feedback circuitry is referenced to SGND, thus allowing for better output regulation. See the recommended layout in the Applications Information section. EXTV CC (L3): External Bias Power Input. The internal bias LDO is bypassed whenever the voltage at EXTVCC is above 4.7V . Never exceed 6V at this pin and ensure CNTL_PWR > EXTVCC at all times to avoid reverse polarity on the internal bias LDO. Connect a 1µF capacitor to ground when used otherwise leave floating. Use a 5V bias or 5V output to power this pin to improve efficiency. FREQ/PLLLPF (L8): Frequency Set and PLL Lowpass Filter Pin. This pin is driven with a DC voltage to set the oper - ating frequency. The recommended operating frequency will be supplied in the efficiency graphs for optimal per - formance. A specific frequency can be chosen as long as the minimum on-time is not violated, and inductor ripple current is optimized. When an external clock is used, then the FREQ/PLLLPF pin must not be connected to any DC voltage. The pin must be floating and will have the proper internal compensation for the internal loop filter . See the Applications Information section. MODE/PLLIN (L9): Forced Continuous Mode, Burst Mode, or Pulse-Skipping Mode Selection Pin and External Syn- chronization Input to Phase Detector Pin. Connect this pin to SGND to force all channels into the continuous mode of operation. Connect to INT VCC to enable pulse-skipping mode of operation. Leave floating to enable Burst Mode operation. A clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator . See the Applications Information section. RUN1, RUN2, RUN3 (L10, L11, K11): Run Control Inputs. A voltage above 1.3V on any RUN pin turns on that par - ticular channel. However , forcing any of these RUN pins below 1.15V causes that channel to shut down. Each of the RUN pins has an internal 10k resistor to ground. This resistor can be used with an external pull-up resistor to the input voltage to set a UVLO for that channel, or simply to turn on the channel. The RUN pins have a maximum voltage of 6V . See the Applications Information section. PGOOD12, PGOOD3 (M2, M3): Output Voltage Power Good Indicator for V OUT1 and VOUT2 Combined, and VOUT3 Separate. The open-drain logic output is pulled to ground when the output voltage is not within ±7.5% of the regula- tion point. COMP1, COMP2, COMP3 (M4, L4, K4): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The L TM4634 regulator channels are all internally compensated for proper stability. COMP1 and COMP2 can be tied together for PolyPhase 10A parallel operation. See the Applications Information section. V FB1, VFB2, VFB3 (M5, L5, K5): The Negative Input of the Error Amplifier for Each of the Three Channels. Internally, each of these pins is connected to their respective output with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between each individual V FB pin and ground. In PolyPhase operation, tying the VFB1 and VFB2 pins together allows for parallel operation up to 10A. See the Applications Information section for details. TK/SS1, TK/SS2, TK/SS3 (M9, M10, M11): Output Voltage T racking and Soft-Start Inputs. When one particular channel is configured to be the master , a capacitor to ground at this pin sets the ramp rate for the master channel’s output voltage. When the channel is configured to be the slave, the V FB voltage of the master channel is reproduced by a resistor divider and applied to this pin. Internal soft-start currents of 1.5μA are charging the soft-start capacitors. In dual output (2 + 1) mode, TK/SS1 and TK/SS2 need to be shorted externally.
Figure 1. Simplified L TM4634 Block Diagram
4634 F01
For more information www.linear .com/L TM4634 operaTion Power Module Description The L TM4634 µModule regulator is a high performance triple output nonisolated switching mode DC/DC power supply. It can provide 5A/5A/4A outputs with a few ex - ternal input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.8V DC to 5.5V DC (V OUT1 and VOUT2), and 0.8V DC to 13.5V DC (V OUT3). When apply- ing control bias in the range from 4.75V to 5.8V , then connect the bias to CNTL_P WR and INT VCC, otherwise if >5.8V only the CNTL_PWR pin needs to be biased. The typical application schematic is shown in Figure 22. The LTM4634 has three integrated constant-frequency cur- rent mode regulators, power MOSFET s, power inductors, and other supporting discrete components. The typical switching frequency is 750kHz. For switching noise- sensitive applications, it can be externally synchronized from 250kHz to 750kHz. Operating frequency range will be dependent upon specific V IN and VOUT requirements as they pertain to minimum on-time and inductor ripple current of less than 60% of the load current. See the Ap- plications Information section. With current mode control and internal feedback loop compensation, the L TM4634 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltages in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output overvoltage is cleared. There are two temperatures monitors in the L TM4634. TEMP1 monitors the close relative tempera - ture of channels 1 and 2, and TEMP2 monitors the close relative temperature of channels 2 and 3. The two diode connected PNP transistors are grounded in the module and can be used as general purpose temperature monitors using a device that is designed to monitor the single-ended connection. Pulling any of the RUN pins below 1.15V forces that regulator channel into a shutdown state. The TK/SS pins are used for programming the output voltage ramp and voltage tracking during start-up for each of the channels. See the Applications Information section. The L TM4634 is internally compensated to be stable over all operating conditions. Table 4 provides a guideline for input and output capacitances for several operating conditions. The L TpowerCAD™ software tool is provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. Each of the channels, operate 120° phase shift for mul - tiphase operation. VOUT1 and VOUT2 can be combined to provide a single 10A output. The two channels will not be operating 180° phase shift, but 120° phase when combined for a 10A design. So the input RMS current may be higher than a 180° phase shifted design. See the Applications Information section for details. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE/PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load op- eration in the Typical Performance Characteristics section.
mined by the maximum load current and output voltage. for particular applications. ment section and temperature derating curves. Table 1. VFB Resistor Table vs Various Output Voltages TK/SS1 and TK/SS2, and RUN1 and RUN2. inductive leads, traces or not enough source capacitance.
For more information www.linear .com/L TM4634 applicaTions inForMaTion of the input RMS current ratings will need to be calculated specific to that channel. Output Capacitors The L TM4634 is designed for low output voltage ripple noise. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient require - ments. C OUT can be a low ESR tantalum capacitor , low ESR Polymer capacitor or ceramic capacitor . The typical output capacitance range is from 200µF to 470µF . Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and L TpowerCAD is available for stability analysis. L TpowerCAD can calculate the output ripple reduction as the number of implemented phases increases by N times. Burst Mode Operation The L TM4634 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For ap- plications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. T o enable Burst Mode operation, simply float the MODE/PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V , the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise, the internal sleep line goes low, and the L TM4634 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation I n applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the L TM4634 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE/PLLINpin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE/PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the L TM4634 output voltage is in regulation. Frequency Synchronization The L TM4634 device operates up to 750kHz. It can also be synchronized with an input clock that has a high level above 2V and a low level below 0.8V at the MODE/PLLIN pin. The FREQ/PLLLPF pin must be floating when synchronized to an incoming clock. Once the L TM4634 is synchronized to an external clock frequency, it will always be running in forced continuous operation. The synchronizing range is from 250kHz to 750kHz. For V OUT1,2,3 ≤ 1.5V use 250kHz to 300kHz, 1.5V ≤ V OUT1,2,3 ≤ 2.5V use 400kHz, 2.5V ≤ VOUT1,2,3 ≤ 5V use 600kHz. If V OUT3 is greater than 5V up to 12V set the operating frequency to 750kHz. These
ripple currents over the input and output voltage ranges. is not an issue at low output voltages.
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Figure 2. Relationship Between Oscillator Frequency 10A equates to duty cycle D = 0.1. capacitors rated at 2ARMS each. and the gate charge required to turn on the top MOSFET .
For more information www.linear .com/L TM4634 applicaTions inForMaTion reference voltage and then proceed up to INTVCC. After the 0.8V ramp, the TK/SS pin will no longer be in control, and the internal voltage reference will control output regula - tion from the feedback divider . Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TK/SS pins are pulled low when the RUN pin is below 1.15V or INTV CC drops below 3.5V . The total soft-start time can be calculated as: tSS = 0.8V •CSS 1.5µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator channels will always start in pulse-skipping mode up to TK/SS = 0.64V . Between TK/SS = 0.64V and 0.74V , it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.74V . The output ripple is minimized during the 100mV forced continuous mode window ensuring a clean PGOOD signal. When the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. Note that the small soft- start capacitor charging current is always flowing, produc- ing a small offset error . To minimize this error , select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the L TM4634 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.74V regardless of the setting of the MODE/PLLIN pin. However , the L TM4634 should always be set in forced continuous mode tracking down when there is no load. After TK/SS drops below 0.1V , its channel will operate in discontinuous mode. The master’s TK/SS pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: RTB = MR SR •60.4k where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal the 60.4k. RTA is derived from equation: RTA = 0.8V VFB 60.4k + VFB RFB – VTRACK RTB where VFB is the feedback voltage reference of the regula- tor , and VTRACK is 0.8V . Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 3. In ratiometric tracking, a different slew rate maybe desired for the slave regulator . R TB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. Power Good The PGOOD12 pin is an open-drain pin that can be used to monitor valid output voltage regulation for V OUT1 and VOUT2, and PGOOD3 for monitoring V OUT3. These pins monitor a ±7.5% window around the 0.8V feedback volt- age on either V FB1,2,3 from the output regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Any of the PGOOD pins are pulled low when the RUN pin of the cor- responding channel is pulled low. Overcurrent and Overvoltage Protection Each of the regulator channels senses the peak inductor current on a cycle-by-cycle basis in current mode opera- tion. When current limit is reached the output voltage will begin to fall and the internal current limit threshold will begin fold back as the output voltage falls below 50% of its value. Foldback current limit is disabled during start- up or track-up. Under short-circuit condition at low duty cycle operation, each of the regulator channels will begin to skip cycles to limit the short-circuit current. Overvoltage protection is implemented by monitoring each one of the regulator’s V FB pins. When the V FB volt- age exceeds ~7.5% of the 0.8V reference value, then an
For more information www.linear .com/L TM4634 applicaTions inForMaTion internal comparator monitor will turn off the top power switch, and turn on the bottom power switch to protect the load. If the top power switch faults as a short, then a fuse or circuit breaker would be recommended to protect the system. This is due to the top switch being shorted while the bottom switch is turning on to protect the output from over voltage. High currents will flow and could damage the bottom switch. Stability Compensation The module has already been internally compensated for all output voltages. Table 4 is provided for most applica- tion requirements with verified stability. L TpowerCAD is available for other control loop optimization. Run Enable The RUN 1, 2, 3 pins have an enable threshold of 1.4V maximum, typically 1.3V with 175mV of hysteresis. They control the turn-on of their respective channel. There is a 10k resistor on each pin to ground. The RUN pins can be pulled up to V IN for 5V operation, or a resistor can be placed on the pins and connected to VIN for higher than 5V input. This resistor can be set along with the onboard 10k resistor such that an undervoltage lockout (UVLO) level can be programmed to shut down a particular regulator channel if V IN falls below a set value. Use the equation: R = 10k UVLO–1.3V( ) 1.3V where R is the resistor from the RUN pin to VIN to set the UVLO trip point. For example, if the UVLO point is to be 6.25V while operating at 12V input: 1.3V ≈ 38k See the Block Diagram in Figure 1. The RUN pins must never exceed 6V maximum voltage. The RUN pins have to be pulled up to enable the regulators. SW Pins The SW pins are generally for testing purposes by moni- toring the pin. The SW pin can also be used to dampen out switch node ringing caused by LC parasitics in the switched current path. Usually a series R-C combination is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the PowerPath™ board inductance in combination with the MOSFET inter- connect inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance, Z, can be calculated: Z(L) = 2π • f • L where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1 2π • f •C these values are a good place to start with. Modification to these components should be made to attenuate the ring- ing without lowering the regulator’s conversion efficiency. INTV CC and EXTVCC The L TM4634 has an onboard linear regulator fed by CNTL_PWR which delivers a roughly 5V output at INTVCC to power the internal controller and MOSFET drivers for all three regulator channels. Apply a 4.7µF ceramic capacitor between INTV CC and ground for decoupling. CNTL_PWR requires a voltage between 4.75V to 28V . If the voltage supplied to CNTL_PWR is ≤ 5.8V , connect INTV CC to CNTL_PWR. Otherwise, INTV CC should be left floating. To eliminate power loss in the onboard linear regulator and improve efficiency connect a supply from 4.7V to 6V at EXTV CC. Biasing EXTVCC at 5V will reduce the power loss in the internal LDO by (V CNTL_PWR – 5V) • 90mA and is recommended for V CNTRL_POWER ≥ 12V when all three channels are operating. If EXTVCC is used add a 1µF
For more information www.linear .com/L TM4634 applicaTions inForMaTion ceramic capacitor to ground at EXTV CC and ensure the voltage at CNTL_PWR is always greater than the voltage at EXTV CC at all times during start-up and shutdown. Connecting VOUT3 to EXTVCC may present a convenient way to meet the sequencing requirement. Otherwise float EXTV CC if not used. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per formed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are, in and of themselves, not relevant to providing guidance of thermal per formance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi- cients explicitly defined in JESD51-12. These coefficients are quoted or paraphrased as follows: θJA: The thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with four layers. 2. θJCbottom: The thermal resistance from the junction to the bottom of the product case, is determined with all of the internal power dissipation flowing through the bottom of the package. In a typical µModule regulator , the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop: The thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJB: The thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured at a specified distance from the package. A graphical representation of the aforementioned ther - mal resistances is given in Figure 4; blue resistances are contained within the μModule regulator , whereas green resistances are external to the µModule package. As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal oper- ating conditions of a μModule regulator . For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally con - duct exclusively through the top or exclusively through
airflow; a majority of the heat flow is into the board. ent with no air-flow or top mounted heat sink. multiplicative factor of 1.4 at 120°C junction.
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Figure 4. Graphical Representations of JESD51-12 Thermal Coefficients
For more information www.linear .com/L TM4634 applicaTions inForMaTion The derating curves are plotted with the output current starting at 15A (5A/CH) and the ambient temperature at ~40°C. The 15A comes from each of the three channels operating at 5A each. This simplifies the loading for this thermal testing. The output voltages are 3.3V , and 5V when all three channels are loaded together in parallel. Channel 1 and Channel 2 are designed to operate with outputs up to 5V , and Channel 3 is designed for 12V . The power loss curve values at a particular output voltage and output current for each output are taken and multiplied by 1.4 for increased power loss at 120°C junction. Thermal models are derived from several temperature measure - ments in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient tempera - ture is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example, in Figure 17 the 5.0V load current is derated to ~12.6A at ~71°C with no air and with no heat sink. In Figure 10, the 12V to 5.0V power loss at 4.2A per chan - nel is 1.25W . The total loss would be 3 times 1.25W for 3.75W total power loss. The 3.75W is then multiplied by the 1.4 multiplier for 120°C junction. This 5.25W value is used with the total temperature rise of 120°C minus the 71°C ambient to calculate θ JA thermal resistance. If the 71°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 49°C divided 5.25W equals a 9.3°C/W θ JA thermal resistance. Table 2 specifies a 9.0°C/W value which is very close. Tables 2 and 3 provide equivalent thermal resistances for 3.3V and 5V outputs with and without air flow and heat sinking. The derived thermal resistances in Tables 2 and 3 for the various conditions can be multiplied by the calculated power loss as a function of the 120°C maximum junction tempera - ture to determine if the temperature rise plus ambient is below the 120°C maximum junction temperature. Thermal measurements or infrared analysis should be performed to validate the values. Ambient temperature power loss can be derived from the power loss cur ves in Figures 8 to 13 and adjusted with the 1.4 multiplier . The printed circuit board is a 1.6mm thick four-layer board with two ounce copper for the two outer layers and 1 ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed in Table 3. Temperature Monitoring (TEMP1 and TEMP2) Diode connected PNP transistors are used for the TEMP1, TEMP2 monitoring function since the diode forward voltage varies with temperature. The temperature dependence of the diodes can be understood in the equation: VD = nVT ln ID IS where VT is the thermal voltage (kT/q), and n, the ideality factor , is 1 for the two diode connected PNPs being used in the L TM4634. IS is expressed by the typical empirical equation: IS = I0 exp –VG0 VT where I0 is a process and geometry-dependent current (I0 is typically around 20 orders of magnitude larger than IS at room temperature), and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero or –273°C. If we take the IS equation and substitute into the VD equa- tion, then we get: VD = VG0 – kT q ln I0 ID , VT = kT q The expression shows that the diode voltage decreases (linearly if I0 were constant) with increasing temperature and constant diode current. Figure 5 shows a plot of V D vs Temperature over the operating temperature range of the L TM4634.
Kelvin temp and subtracting 273 from it. temperature will provide a general temperature monitor . the currents to 100µA each. See Figure 25 for an example. breaker function can also be used instead of a fuse. y fault protector in this situation. Figure 5. Diode Voltage VD vs Temperature T(°C) Figure 6. Thermal Plot 24V to 3.3V at 5A, 5V at 5A, and 12V
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minimize the PCB conduction loss and thermal stress. Place a dedicated power ground layer underneath the unit. tween top layer and other power layers. example of the recommended layout.
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Figure 7. Recommended PCB Layout
Figure 11. 12V Power Loss (Ch3) Figure 12. 24V Power Loss Figure 13. 24V Power Loss (Ch3) Figure 8. 5V Input Power Loss Figure 9. 5V Input Power Loss (Ch3) Figure 10. 12V Input Power Loss
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Figure 14. 12VIN, 3.3VOUT, with Heat Figure 17. 12VIN, 5V , without Heat Figure 15. 12VIN, 3.3VOUT, without Figure 18. 24VIN, 3.3V , with Heat Figure 20. 24VIN, 5V , with Heat Figure 16. 12VIN, 5V , with Heat Figure 19. 24VIN, 3.3V , without Figure 21. 24VIN, 5V , without Heat
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0 LFM AIR FLOW
200 LFM AIR FLOW
400 LFM AIR FLOW
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Table 2. 3.3V Output Table 3. 5V Output
Table 4. Output Voltage Response Versus Component Matrix
Figure 22. L TM4634 Typical 24V Input to 3.3V at 5A, 5V at 5A, 12V at 4A
Figure 23. L TM4634 T riple Input and T riple Output (2.5V , 1.5V and 3.3V) at 5A, 5A and 4A
Figure 24. 24V to 12V at 2.8A, Then 12V to 1V at 10A
Figure 25. 7V to 28V Input, 1.5V , 1.8V and 3.3V at 5A,5A, 4A with T racking
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For more information www.linear .com/L TM4634 L TM4634 Component BGA Pinout package DescripTion PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT3 B1 V OUT3 C1 V OUT3 D1 GND E1 GND F1 V IN3 A2 V OUT3 B2 V OUT3 C2 V OUT3 D2 GND E2 GND F2 V IN3 A3 V OUT3 B3 V OUT3 C3 V OUT3 D3 GND E3 GND F3 SW3 A4 GND B4 V OUT3 C4 V OUT3 D4 GND E4 GND F4 GND A5 V OUT2 B5 V OUT2 C5 TEMP2 D5 GND E5 GND F5 V IN2 A6 V OUT2 B6 V OUT2 C6 V OUT2 D6 GND E6 GND F6 V IN2 A7 V OUT2 B7 V OUT2 C7 V OUT2 D7 GND E7 GND F7 SW2 A8 GND B8 V OUT2 C8 V OUT2 D8 GND E8 GND F8 GND A9 GND B9 V OUT1 C9 TEMP1 D9 GND E9 GND F9 V IN1 A10 V OUT1 B10 V OUT1 C10 V OUT1 D10 GND E10 GND F10 V IN1 A11 V OUT1 B11 V OUT1 C11 V OUT1 D11 GND E11 GND F11 SW1 A12 V OUT1 B12 V OUT1 C12 V OUT1 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 V IN3 H1 V IN3 J1 GND K1 GND L1 GND M1 GND G2 V IN3 H2 V IN3 J2 GND K2 GND L2 GND M2 PGOOD12 G3 GND H3 GND J3 GND K3 GND L3 EXTV CC M3 PGOOD3 G4 GND H4 GND J4 GND K4 COMP3 L4 COMP2 M4 COMP1 G5 V IN2 H5 V IN2 J5 GND K5 V FB3 L5 V FB2 M5 V FB1 G6 V IN2 H6 V IN2 J6 CNTL_PWR K6 SGND L6 SGND M6 GND G7 GND H7 GND J7 GND K7 SGND L7 SGND M7 GND G8 GND H8 GND J8 INTV CC K8 GND L8 FREQ/PLLLPF M8 GND G9 V IN1 H9 V IN1 J9 GND K9 GND L9 MODE/PLLIN M9 TK/SS1 G10 V IN1 H10 V IN1 J10 GND K10 GND L10 RUN1 M10 TK/SS2 G11 GND H11 GND J11 GND K11 RUN3 L11 RUN2 M11 TK/SS3 G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND package phoTo
For more information www.linear .com/L TM4634 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z SUGGESTED PCB LAYOUT TOP VIEW BGA 144 0613 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 0.0000 0.0000 D A DETAIL B PACKAGE SIDE VIEW Z 0.630 ±0.025 Ø 144x E 144-Lead (15mm × 15mm × 5.01mm) (Reference LTC DWG # 05-08-1908 Rev Ø) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z 0.0 PACKAGE BOTTOM VIEW PIN 1 DETAIL A Øb (144 PLACES) M X Y Z ddd M Z eee e F NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A SEE NOTES L K J H G F E D C B M A 1 2 3 4 5 6 7 810 911 12 e G
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES b b
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Figure 26. 24V to 5V at 1A, Then 5V Output to 1.2V at 10A