LTM4632 LINER | Alldatasheet

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4632fcFor more information www.linear .com/L TM4632 TYPICAL APPLICATION FEATURES DESCRIPTION Ultrathin, Triple Output, Step-Down µModule Regulator for DDR-QDR4 Memory The LT M®4632 is an ultrathin triple output step-down µModule® (power module) regulator to provide complete power solution for DDR-QDR4 SRAM. Operating from a 3.6V to 15V input voltage, the LTM4632 supports two ±3A output rails, both sink and source capable, for VDDQ and VTT , plus a 10mA low noise reference VTTR output. Both VTT and VTTR track and are equal to VDDQ/2. Housed in a 6.25mm × 6.25mm × 1.82mm LGA and 6.25mm × 6.25mm × 2.42mm BGA packages, the LTM4632 includes the switching controller , power FETs, inductors and sup- port components. Alternatively, the power module can also be configured as a two phase single ± 6A output VTT . Only a few ceramic input and output capacitors are needed to complete the design. The LTM4632 supports selectable Burst Mode operation (CH1 only) and output voltage tracking for supply rail sequencing. Its high switching frequency and current mode control enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage input, over- current and overtemperature protection. The LTM4632 is available with SnPb (BGA) or RoHS com- pliant terminal finish QDR4 Memory Power µModule Regulator Output Efficiency vs Load Current n Complete DDR-QDR4 SRAM Power Solution Including VDDQ, VTT , VTTR (or VREF) n Solution in 0.5cm2 (Dual-Sided PCB) n Wide Input Voltage Range: 3.6V to 15V n 3.3V Input Compatible with VIN Tied to INTVCC n 0.6V to 2.5V Output Voltage Range n Dual ±3A DC Output Current with Sink and Source Capability n ±1.5%, ±10mA Buffered VTTR = VDDQ/2 Output n 3A VDDQ + 3A VTT or Dual Phase Single 6A VTT n ±1.5% Maximum Total Output Voltage Regulation Error Over Load, Line and Temperature n Current Mode Control, Fast T ransient Response n External Frequency Synchronization n Multiphase Parallelable with Current Sharing n Selectable Burst Mode® Operation n Overvoltage Input and Overtemperature Protection n Power Good Indicator n Ultrathin 6.25mm × 6.25mm × 1.82mm LGA and 6.25mm × 6.25mm × 2.42mm BGA Packages L, L T , L TC, L TM, µModule, Burst Mode, Linear Technology and the Linear logo are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. 52.3k VDDQ

4632 TA01a

10µF 25V VIN 3.6V TO 15V VDDQ 1.3V , 3A 22µF 22µF VOUT1 VTT 0.65V , ±3A VTTR 0.65V , 10mA VOUT2 COMP1 VTTR FB1 GND L TM4632 PGOOD1 PGOOD2 VIN RUN1 RUN2 INTVCC SYNC/MODE TRACK/SS1 V DDQIN COMP2 LOAD CURRENT (A) EFFICIENCY (%) 2 31

4632 TA01b

APPLICATIONS

n General Purpose Point-of-Load Conversion n Telecom, Networking and Industrial Equipment

4632fc For more information www.linear .com/L TM4632 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS MODE/SYNC, COMP1, COMP2, Operating Internal Temperature Range (Note 1) LGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 1.82mm) BGA PACKAGE 25-LEAD (6.25mm × 6.25mm × 2.42mm) TOP VIEW COMP2 SYNC/ MODE GND VOUT1 FB1 PGOOD1 TRACK/SS1 A PGOOD2 V DDQIN VTTR INTVCC RUN2 B C D E COMP1GND GND RUN1 GND VIN VIN VIN VIN VOUT2 TJMAX = 125°C, θJCtop = 17°C/W , θJCbottom = 11°C/ W, θJB +θBA = 22°C/W , θJA = 20°C/W WEIGHT = 0.21g (See Pin Functions, Pin Configuration Table) PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4632EV#PBF Au (RoHS) LTM4632V e4 LGA 3 –40°C to 125°C LTM4632IV#PBF Au (RoHS) LTM4632V e4 LGA 3 –40°C to 125°C LTM4632EY#PBF SAC305 (RoHS) LTM4632Y e1 BGA 3 –40°C to 125°C LTM4632IY#PBF SAC305 (RoHS) LTM4632Y e1 BGA 3 –40°C to 125°C LTM4632IY SnPb (63/37) LTM4632Y e0 BGA 3 –40°C to 125°C

  • Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.
  • Terminal Finish Part Marking: www.linear .com/leadfree
  • Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear .com/umodule/pcbassembly
  • LGA and BGA Package and T ray Drawings: www.linear .com/packaging ORDER INFORMATIONhttp://www.linear .com/product/LTM4632#orderinfo

4632fcFor more information www.linear .com/L TM4632

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 3.6 15 V VOUT1(RANGE) VOUT2(RANGE) Output Voltage Range VIN = 3.6V to 15V l l 0.6 2.5 1.8 V V Output Specification (Channel 1) VOUT1(DC) CH1 Output Voltage, Total Variation with Line and Load CIN = 22µF, COUT = 100µF Ceramic RFB1 = 51.7k, MODE = GND, IOUT = –3A to 3A l 1.28 1.30 1.32 V IOUT1(DC) CH1 Output Continuous Current Range V IN = 12V, VOUT1 = 1.3V (Note 3) –3 3 A IQ1(VIN) CH1 Input Supply Bias Current VIN = 12V, VOUT1 = 1.3V, MODE = GND VIN = 12V, VOUT1 = 1.3V, MODE = INTVCC Shutdown, RUN1 = GND 400 mA µA µA IS1(VIN) CH1 Input Supply Current VIN = 12V, VOUT1 = 1.3V, IOUT = 3A 0.4 A ΔVOUT1(Line)/VOUT1 CH1 Line Regulation Accuracy VOUT1 = 1.3V, VIN = 3.6V to 15V, IOUT1 = 0A l 0.01 0.05 %/V ΔVOUT1(Load)/VOUT1 CH1 Load Regulation Accuracy VOUT1 = 1.3V, IOUT = –3A to 3A l 0.2 1.0 % VOUT1(AC) CH1 Output Ripple Voltage IOUT = 0A, COUT = 47µF Ceramic VIN = 12V, VOUT1 = 1.3V 30 mV ΔVOUT1(START) CH1 Turn-On Overshoot IOUT = 0A, COUT = 47µF Ceramic, TRACK/SS1 = –0.1µF, VIN = 12V, VOUT1 = 1.3V 30 mV tSTART Turn-On Time COUT = 100µF Ceramic, TRACK/SS1 = 0.01µF No Load, VIN = 12V, VOUT1 = 1.3V 1.2 ms ΔVOUTLS1 CH1 Peak Deviation for Dynamic Load Load: 0% to 25% to 0% of Full Load COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V 85 mV tSETTLE1 CH1 Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V 20 µs IOUTPK1 CH1 Output Current Limit VIN = 12V, VOUT1 = 1.3V 4.5 A Output Specification (Channel 2) VOUT2(DC) CH2 Output Voltage, Total Variation with Line and Load CIN = 22µF, COUT = 100µF Ceramic VDDQIN= 1.3V, MODE = GND, IOUT = –3A to 3A l 637 650 663 mV IOUT2(DC) CH2 Output Continuous Current Range V IN = 12V, VDDQIN = 1.3V (Note 3) –3 3 A IQ2(VIN) CH2 Input Supply Bias Current VIN = 12V, VDDQIN = 1.3V, MODE = GND Shutdown, RUN2 = 0 mA µA IS2(VIN) CH2 Input Supply Current VIN = 12V, VDDQIN = 1.3V, IOUT = 3A 0.25 A ΔVOUT2(Line)/VOUT2 CH2 Line Regulation Accuracy VDDQIN = 1.3V, VIN = 3.6V to 15V, IOUT2 = 0A l 0.01 0.05 %/V ΔVOUT2(Load)/VOUT2 CH2 Load Regulation Accuracy VDDQIN = 1.3V, IOUT = –3A to 3A l 0.2 1.0 % VOUT2(AC) CH2 Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic VIN = 12V, VDDQIN = 1.3V 30 mV ΔVOUTLS2 CH2 Peak Deviation for Dynamic Load Load: 0% to 25% to 0% of Full Load COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V 85 mV tSETTLE2 CH2 Settling Time for Dynamic Load Step Load: 0% to 25% to 0% of Full Load COUT = 47µF Ceramic, VIN = 12V, VOUT1 = 1.3V 20 µs IOUTPK2 CH2 Output Current Limit 4.5 A The l denotes the specifications that apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C (Note 2), VIN = 12V, unless otherwise noted, per the typical application in Figure 19

4632fc For more information www.linear .com/L TM4632 Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. The LTM4632 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4632E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4632I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. ELECTRICAL CHARACTERISTICS The l denotes the specifications that apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel at TA = 25°C (Note 2), VIN = 12V, unless otherwise noted, per the typical application in Figure 19 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section VFB1 Voltage at VFB1 Pin IOUT = 0A, VOUT1 = 1.3V l 0.593 0.600 0.607 V IFB1 Current at VFB1 Pin (Note 4) ±30 nA RFBHI1 Resistor Between VOUT1 and VFB1 Pins 60.00 60.40 60.80 kΩ VTTR VTTR Voltage Reference VDDQIN = 1.3V, IVTTR = ±10mA, CVTTR < 10nF l 0.492x VDDQIN 0.50x VDDQIN 0.508x VDDQIN V VRUN1, VRUN2 RUN Pin On Threshold RUN Threshold Rising RUN Threshold Falling 1.18 0.95 1.28 1.01 1.39 1.05 V V IRUN1, IRUN2 RUN Pin Leakage Current 0 ±1 µA ITRACK/SS1 TRACK/SS1 Pin Soft-Start Pull-Up Current TRACK/SS1 = 0V 1.2 µA tON(MIN) Minimum On-Time (Note 4) 20 ns tOFF(MIN) Minimum Off-Time (Note 4) 45 ns VPGOOD PGOOD Trip Level VFB With Respect to 0.6V VOUT2 With Respect to VDDQIN/2 (Note 4) Ramping Negative Ramping Positive –14 RPGOOD PGOOD Pull-Down Resistance 1mA Load 15 Ω VINTVCC Internal VCC Voltage VIN = 3.6V to 15V 3.1 3.3 3.5 V VINTVCC Load Reg INTVCC Load Regulation ICC = 0 to 50mA 1.3 % fOSC Oscillator Frequency 1 MHz SYNC SYNC Threshold Voltage 0.95 V ISYNC/MODE MODE Input Current SYNC/MODE = INTVCC –1.5 µA Note 3. See output current derating curves for different VIN, VOUT and TA. Note 4. 100% tested at wafer level. Note 5. This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.

4632fcFor more information www.linear .com/L TM4632 TYPICAL PERFORMANCE CHARACTERISTICS 1V Output T ransient Response 1.2V Output T ransient Response 1.5V Output T ransient Response 1.8V Output T ransient Response 2.5V Output T ransient Response Start-Up with No Load Current Applied Efficiency vs Load Current at 3.6V IN Efficiency vs Load Current at 5VIN Efficiency vs Load Current at 12V IN LOAD CURRENT (A) EFFICIENCY (%) 100 1.00.5 2.0

4632 G01

3.01.5 2.5 1VOUT 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT LOAD CURRENT (A) EFFICIENCY (%) 100 1.00.5 2.0

4632 G02

3.01.5 2.5 1VOUT 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT LOAD CURRENT (A) EFFICIENCY (%) 100 1.00.5 2.0

4632 G03

3.01.5 2.5 1VOUT 1.2VOUT 1.5VOUT 1.8VOUT 2.5VOUT VIN = 12V VOUT = 1V fS = 1MHz OUTPUT CAPACITOR = 1 × 47µF CERAMIC LOAD STEP = 2.25A TO 3A LOAD STEP 1A/DIV VOUT AC-COUPLED 50mV/DIV

4632 G04

20µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz OUTPUT CAPACITOR = 1 × 47µF CERAMIC LOAD STEP = 2.25A TO 3A LOAD STEP 1A/DIV VOUT AC-COUPLED 50mV/DIV

4632 G07

20µs/DIV VIN = 12V VOUT = 1.2V fS = 1MHz OUTPUT CAPACITOR = 1 × 47µF CERAMIC LOAD STEP = 2.25A TO 3A LOAD STEP 1A/DIV VOUT AC-COUPLED 50mV/DIV

4632 G05

20µs/DIV VIN = 12V VOUT = 2.5V fS = 1MHz OUTPUT CAPACITOR = 1 × 47µF CERAMIC LOAD STEP = 2.25A TO 3A LOAD STEP 1A/DIV VOUT AC-COUPLED 50mV/DIV

4632 G08

20µs/DIV VIN = 12V VOUT = 1.5V fS = 1MHz OUTPUT CAPACITOR = 1 × 47µF CERAMIC LOAD STEP = 2.25A TO 3A LOAD STEP 1A/DIV VOUT AC-COUPLED 50mV/DIV

4632 G06

20µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 0A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC SOFT-START CAPACITOR = 0.1µF VOUT 1A/DIV IIN 0.5A/DIV SW 10V/DIV

4632 G09

20µs/DIV

4632fc For more information www.linear .com/L TM4632 VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 3A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC SOFT-START CAPACITOR = 0.1µF VOUT 1V/DIV IIN 0.5A/DIV SW 10V/DIV

4632 G10

VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 0A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC VOUT 1V/DIV IIN 2A/DIV SW 10V/DIV

4632 G13

20µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 0A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC VOUT 1V/DIV IIN 2A/DIV SW 10V/DIV

4632 G11

20µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 0A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC VOUT AC-COUPLED 50mV/DIV SW 5V/DIV

4632 G14

1µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 3A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC VOUT 1V/DIV IIN 2A/DIV SW 10V/DIV

4632 G12

20µs/DIV VIN = 12V VOUT = 1.8V fS = 1MHz IOUT = 0A INPUT CAPACITOR = 1 × 22µF CERAMIC OUTPUT CAPACITOR = 1 × 47µF CERAMIC VOUT 1V/DIV RUN 10V/DIV SW 5V/DIV

4632 G15

TYPICAL PERFORMANCE CHARACTERISTICS Recover from Short-Circuit with No Load Current Applied Steady-State Output Voltage Ripple Start-Up Into Pre-Biased Output Start-Up with 3A Load Current Applied Short-Circuit with No Load Current Applied Short-Circuit with 3A Load Current Applied

4632fcFor more information www.linear .com/L TM4632 PIN FUNCTIONS VIN ( A2, B3, D3, E2): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. VOUT1 (D1, E1), VOUT2 (A1, B1): Power Output Pins of each Switching Mode Regulator . Apply output load be- tween these pins and GND pins. Recommend placing out- put decoupling capacitance directly between these pins and GND pins. GND (C1-C2, C4, B5, D5): Power Ground Pins for Both Input and Output Returns. PGOOD1 (D4): Output Power Good with Open-Drain Logic of the Channel 1 Switching Mode Regulator . PGOOD1 is pulled to ground when the voltage on the FB1 pin is not within ±8% (typical) of the internal 0.6V reference. This threshold has 15mV of hysteresis. PGOOD2 (B4): Output Power Good with Open-Drain Logic of the Channel 2 Switching Mode Regulator . PGOOD2 is pulled to ground when the voltage on the V OUT2 pin is not within ± 8% (typical) of the V DDQIN/2 voltage. This threshold has 15mV of hysteresis. SYNC/MODE (C5) : Mode Select and External Synchronization Input. Tie this pin to ground to force continuous synchronous operation at all output loads. Floating this pin or tying it to INTV CC enables high effi - ciency Burst Mode operation at light loads. Drive this pin with a clock to synchronize the LTM4632 switching frequency. An internal phase-locked loop will force the bottom power NMOS’s turn on signal to be synchronized with the rising edge of the clock signal. When this pin is driven with a clock, forced continuous mode is automati- cally selected. INTVCC ( C3): Internal 3.3V Regulator Output of the Switching Mode Regulator Channel. The internal power drivers and control circuits are powered from this volt - age. This pin is internally decoupled to GND with a 2.2µF low ESR ceramic capacitor . No more external decoupling capacitor needed. RUN1 ( D2), RUN2 ( B2): Run Control Input of Each Switching Mode Regulator Channel. Enables chip opera- tion by tying RUN above 1.28V. Tying this pin below 1V shuts down the specific regulator channel. Do not float this pin. COMP1 (E5), COMP2 (A5): Current Control Threshold and Error Amplifier Compensation Point of Each Switching Mode Regulator Channel. The current comparator’s trip threshold is linearly proportional to this voltage, whose normal range is from 0.3V to 1.8V. The device is inter nal compensated. Tie COMP pins together in Dual Phase Single Output VTT Configuration. See the Applications Information section for details. FB1 (E4): The Negative Input of the Error Amplifier for the Channel 1 Switching Mode Regulator . Internally, this pin is connected to V OUT1 with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between FB1 and GND pins. Connect this pin to INTV CC in Dual Phase Single Output VTT Configuration. See the Applications Information sec- tion for details. TRACK/SS1 (E3): Output T racking and Soft-Start Pin of the Channel 1 Switching Mode Regulator . It allows the user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier , instead it servos the FB pin to the TRACK/SS voltage. Above 0.6V, the tracking function stops and the internal reference resumes control of the error amplifier . There’s an internal 1.2µA pull-up current from INTVCC on this pin, so putting a capacitor here provides a soft-start function. VTTR (A3): Reference Output. This output is used to sup- ply the VREF voltage for DDR memory. An on-chip buffer amplifier outputs a low noise reference voltage equal to VDDQIN/2. This output is capable of supplying 10mA. VTTR has internal 0.01µF capacitor . Additional R-C filter can be used to further reduce the ripple on VTTR. The error amplifier for channel 2 uses this voltage as its reference voltage. V DDQIN (A4): External Reference Input for Channel 2. An internal resistor divider sets the VTTR pin voltage to be equal to half the voltage applied to this input. Channel 2 uses the VTTR pin voltage as its error amplifier reference.

4632fc For more information www.linear .com/L TM4632 BLOCK DIAGRAM DECOUPLING REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 3.6V to 15V, VOUT = 1.5V) IOUT = 3A 4.7 10 µF COUT External Output Capacitor Requirement (VIN = 3.6V to 15V, VOUT = 1.5V) IOUT = 3A 10 22 µF POWER CONTROL VTTR 2.2µF 0.01µF 0.22µF 10µF INTVCC VDDQIN VDDQ 0.1µF TRACK/SS1 RUN1 RUN2 SYNC/MODE COMP1 1µF VOUT1 VIN 10kPGOOD1 VDDQ 1.3V V IN 3.6V TO 15V INTVCC GND 0.82µH 4632 BD FREQ SGND 312k INTERNAL COMP COMP2 FB1 60.4k 51.7k VOUT1 VOUT2 10kPGOOD2 INTVCC 22µF 0.22µF 1µF VOUT2 VTT 0.65V ±3A GND 0.82µH 22µF INTERNAL COMP BUFFER

which equal to one half of VDDQIN voltage. by current mode control loop. tied to VIN, this module is able to operate from 3.3V input. set frequency. See the Applications Information section. for power supply tracking and soft-start programming. See the Applications Information section. Figure 19. External component selection is primarily deter- nal capacitor requirements for a particular application. and Output Current Derating section in this data sheet.

Table 1. VFB Resistor Table (1%) vs Various Output Voltages lytic aluminum capacitor and polymer capacitor . where η% is the estimated efficiency of the power module. output voltage ripple and very good transient response. of phases implemented increases by N times. above the zero current level to initiate another cycle.

output voltage is in regulation. cations, no additional frequency adjusting is required. the regulator , the phase-locked loop function is disabled. capable of souring and sinking higher current.

4632 F02

Figure 2. Example of Clock Phasing for 4-Phase LTM4632 are internally set to operate 180° out of phase. module into two phase single VTT output operation mode. in multiple LTM4632s paralleling application. ply operation and pin connection. rent sharing. This will balance the thermals on the design.

an external multiphase oscillator like LTC6902.

4632 F03

Figure 3. Example of Clock Phasing for 2-Phase

4632 F04

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

phases. Figure 4 shows this graph. where C SS is the capacitance on the TRACK/SS pin. slew rate is proportional to the master’s. isfy the following equation during the start-up. the slave regulator , as shown in Figure 6. is a good combination for the Ratiometric tracking.

4632 F05

Figure 5. Output Ratiometric T racking Waveform offset to a negligible value. slew rate (SR), as waveform shown in Figure 7.

resistor divider is always the same as its feedback divider . 1.5V and VOUT(SL) = 1.2V application.

4632 F06

Figure 6. Example Schematic of Ratiometric Output Voltage Tracking

4632 F07

Figure 7. Output Coincident T racking Waveform

4632fcFor more information www.linear .com/L TM4632 APPLICATIONS INFORMATION Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a ±8% window around the regulation point. A resistor can be pulled up to a particular supply voltage for monitoring. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4632’s PGOOD falling edge includes a blanking delay of approximately 40μs. Stability Compensation The LTM4632 module internal compensation loop is de-signed and optimized for low ESR ceramic output capacitors only application. Table 5 is provided for most application requirements. The L TpowerCAD Design Tool is available to download for control loop analysis for further optimization. RUN Enable Pulling the RUN pin to ground forces the LTM4632 into its shutdown state, turning off both power MOSFETs and most of its internal control circuitry. Tying the RUN pin voltage above 1.28V will turn on the entire chip. Low Input Application The LTM4632 is capable to run from 3.3V input when the VIN pin is tied to INTV CC pin. See Figure 21 for the application circuit. Please note the INTV CC pin has 3.6V ABS max voltage rating. Pre-Biased Output Start-Up (Channel 1) There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging that output pre-bias. The LTM4632 channel 1 can safely power up into a pre-biased output without discharging it. The LTM4632 accomplishes this by forcing discontinuous mode (DCM) operation until the TRACK/SS1 pin voltage reaches 80% of the 0.6V reference voltage for channel 1. This will prevent the BG from turning on during the pre- biased output start-up which would discharge the out - put. Do not pre-bias LTM4632 with a voltage higher than INTV CC (3.3V) voltage. Overtemperature Protection The internal overtemperature protection monitors the junction temperature of the module. If the junction temperature reaches approximately 170° C, both power switches will be turned off until the temperature drops about 10°C cooler . Input Overvoltage Protection In order to protect the internal power MOSFET devices against transient voltage spikes, the LTM4632 constantly monitors each VIN pin for an overvoltage condition. When VIN rises above 17.5V, the regulator suspends operation by shutting off both power MOSFETs on the correspond- ing channel. Once V IN drops below 16.5V, the regulator immediately resumes normal operation. The regulator executes its soft-start function when exiting an overvolt- age condition. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per-formed on a µModule package mounted to a hardware test board— also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements” ). The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance per- taining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application.

4632fc For more information www.linear .com/L TM4632 The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coef- ficients are quoted or paraphrased below: 1. θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air ther- mal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operat- ing condition. 2. θJCbottom, the thermal resistance from junction to ambient, is the natural convection junction-to-ambi- ent air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 3. θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. APPLICATIONS INFORMATION A graphical representation of the aforementioned ther - mal resistances is given in Figure 8; blue resistances are contained within the μModule regulator , whereas green resistances are external to the µModule package. As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a μModule. For example, in nor - mal board-mounted applications, never does 100% of the device’ s total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the µModule package as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package–granted, in the absence of a heat sink and air - flow, a majority of the heat flow is into the board. Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power , with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing model- ing simplicity–but also, not ignoring practical realities–an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and tempera- ture readings at different interfaces that enable the cal - culation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simu - lated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-envi - ronment chamber while operating the device at the same

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients fies how much module temperature rise can be allowed. PCB dimensions are 95mm × 76mm.

4638 F08

Figure 12. 5V to 1.0V Derating Figure 13. 12V to 1.0V Derating Figure 14. 5V to 1.5V Derating Figure 15. 12V to 1.5V Derating Figure 16. 5V to 2.5V Derating Figure 17. 12V to 2.5V Derating

4632 F09

4632 F12

4632 F15

4632 F13

4632 F16

4632 F14

4632 F17

4632 F10

4632 F11

Table 2. 1.0V Output Table 3. 1.5V Output Table 4. 2.5V Output

Table 5. Output Voltage Response for Each Regulator Channel vs Component Matrix (Refer to Figure 19)

4632 F19

4632 F20

Figure 19. 3.6V to 15V Input, 1.3V/3A VDDQ, 0.65V/±3A VTT and 10mA VTTR Design Figure 20. 4V to 15V Input, Two Phase Single Output ±6A VTT Termination Design with LTM4630 36A VDDQ Supply

4632 F21

4632 F22

Figure 21. 3.3V Input, 1.5V/3A VDDQ, 0.75V/±3A VTT and 10mA VTTR Design Figure 22. Two Module in Parallel, 3.6V to 15V Input, 1.2V/6A VDDQ, 0.6V/±6A VTT and 10mA VTTR Design

4632fc For more information www.linear .com/L TM4632 LTM4632 Component LGA and BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT2 A2 VIN A3 VTTR A4 VDDQIN A5 COMP2 B1 VOUT2 B2 RUN2 B3 VIN B4 PGOOD2 B5 GND C1 GND C2 GND C3 INTVCC C4 SGND C5 SYNC/MODE D1 VOUT1 D2 RUN1 D3 VIN D4 PGOOD1 D5 GND E1 VOUT1 E2 VIN E3 TRACK/SS1 E4 FB1 E5 COMP1 PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . PACKAGE DESCRIPTION

4632fcFor more information www.linear .com/L TM4632 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4632#packaging for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z DETAIL A PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 1.270 1.270 2.540 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 E D C B A 12345 PIN 1 Øb (25 PLACES) D E e b F G DETAIL A 0.3175 0.3175 LGA 25 0613 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 25-Lead (6.25mm × 6.25mm × 1.82mm) (Reference LTC DWG # 05-08-1949 Rev Ø) SEE NOTES NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 25 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A SYMBOL A b D E e F G aaa bbb eee MIN 1.72 0.60 0.27 1.45 NOM 1.82 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 MAX 1.92 0.66 0.37 1.55 0.15 0.10 0.15 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 25 S YXZØ eee

4632fc For more information www.linear .com/L TM4632 PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4632#packaging for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z DETAIL A PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW 0.000 2.540 1.270 1.270 2.540 0.630 ±0.025 2.540 1.270 2.540 1.270 0.3175 0.3175 0.000 E D C B A 12345 PIN 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE Øb (25 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X YZddd M Zeee D E e b F G DETAIL A 0.3175 0.3175 BGA 25 0515 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 25-Lead (6.25mm × 6.25mm × 2.42mm) (Reference LTC DWG # 05-08-1502 Rev Ø) DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.22 0.50 1.72 0.60 0.60 0.27 1.45 NOM 2.42 0.60 1.82 0.75 0.63 6.25 6.25 1.27 5.08 5.08 0.32 1.50 MAX 2.62 0.70 1.92 0.90 0.66 0.37 1.55 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 25 // bbb Z Z AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

4632fcFor more information www.linear .com/L TM4632 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 05/16 Added BGA package 1, 2, 26 B 09/16 Corrected equations of tracking start-up time from RTR(TOP)/[RTR(TOP) + RTR(BOT)] to RTR(BOT)/[RTR(TOP) + RTR(BOT)] 13, 14 C 05/17 Changed VDDQ to 1.3V/3A and VTT to 0.65V 22

4632fc For more information www.linear .com/L TM4632  LINEAR TECHNOLOGY CORPORATION 2016 LT 0517 REV C • PRINTED IN USA www.linear .com/L TM4632 RELATED PARTS PACKAGE PHOTO DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

  • Selector Guides
  • Demo Boards and Gerber Files
  • Free Simulation Tools Manufacturing:
  • Quick Start Guide
  • PCB Design, Assembly and Manufacturing Guidelines
  • Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS LTM4622 Ultrathin, Dual 2.5A or Single 5A Step-Down µModule Regulator Package, 6.25mm × 6.25mm × 2.42 BGA Package 6.25mm × 6.25mm × 2.42 BGA Package LTM4644 Quad 4A Step-Down µModule Regulator 4V < VIN < 14V, 0.6V < VOUT < 5.5V, 9mm × 15mm × 5.01mm BGA Package LTM4630 µModule Regulator for Higher Power VDDQ Supply 4.5V < VIN < 15V, 0.6V <VOUT <1.8V, Single 36A or Dual 18A, 16mm × 16mm × 5.01mm BGA Package, 16mm × 16mm × 4.41mm LGA Package LTM4650 µModule Regulator for High Power FPGA/ASIC Core Supply 4.5V < VIN < 15V, 0.6V <VOUT <1.8V, Single 50A or Dual 25A, 16mm × 16mm × 5.01mm BGA Package LTM4639 Low Input Voltage, Single 20A Step-Down µModule Regulator 2.375V < V IN < 7V, 0.6V < VOUT < 5.5V, 15mm × 15mm × 4.92mm BGA Package LTM4675 µModule Regulator with PSM for High Power , High Accuracy FPGA/ASIC Core Supply DC/DC µModule with Digital Power System Management, 4.5V < V IN < 17V, 0.5V < VOUT < 5.5V with ±0.5% Accuracy, Single 18A or Dual 9A LTM4677 µModule Regulator with PSM for High Power , High Accuracy FPGA/ASIC Core Supply DC/DC µModule with Digital Power System Management, 4.5V < VIN < 16V, 0.5V < VOUT < 1.8V with ±0.5% Accuracy, Single 36A or Dual 18A LTC3717 Step-Down Controller for VTT for DDR Memory Termination 4V < V IN < 36V, IOUT = ±20A, Requires External Inductor and MOSFET LTC6902 Multiphase Oscillator for Multiphase Operation 2-, 3- or 4-Phase, 5kHz to 20MHz Frequency Range