Power Management

LTM4631

Linear Technology

Ultrathin Dual 10A or Single 20A DC/DC 關Module Regulator

Manufacturer: Linear Technology

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4631fbFor more information www.linear .com/L TM4631 Typical applicaTion

DescripTion

Ultrathin Dual 10A or Single 20A DC/DC µModule Regulator The LT M®4631 is a dual 10A or single 20A output switch- ing mode step-down DC/DC µModule ® (power module) regulator . Included in the package are the switching con- troller , power FETs, inductors and all supporting compo- nents. Operating from an input voltage range of 4.5V to 15V, the LTM4631 supports two outputs each with an output voltage range of 0.6V to 1.8V, each set by a single external resistor . Its high efficiency design delivers up to 10A continuous current for each output. Only a few input and output capacitors are needed. The device supports frequency synchronization, multi - phase operation, Burst Mode operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architec - ture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcurrent protection. The LTM4631 is offered in an ultrathin 16mm × 16mm × 1.91mm LGA and 16mm × 16mm × 2.51mm BGA packages. The LTM4631 is avail- able with SnPb (BGA) or ROHS compliant terminal finish.

FeaTures

applicaTions

n Dual 10A or Single 20A Output n Input Voltage Range: 4.5V to 15V n Output Voltage Range: 0.6V to 1.8V n ±1.5% Maximum Total DC Output Error Over Line, Load and T emperature n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Adjustable Switching Frequency n Overcurrent Foldback Protection n Multiphase Parallel Current Sharing with Multiple L TM4631s n Frequency Synchronization n Internal Temperature Monitor n Selectable Burst Mode® Operation n Soft-Start/Voltage T racking n Output Overvoltage Protection n Ultrathin 16mm × 16mm × 1.91mm LGA and 16mm × 16mm × 2.51mm BGA Packages n Telecom and Networking Equipment n Storage and ATCA Cards n Industrial Equipment L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. 20A, 1.2V Output Ultrathin µModule Regulator

4631 TA01a

470µF 6.3V 60.4k 100µF 6.3V PHASMD V OUT1 VOUTS1 VFB1 VFB2 VOUT2 PGOOD2 PGOOD MODE_PLLIN PINS NOT USED IN THIS CIRCUIT : CLKOUT EXTV CC SW1 SW2 V OUTS2 INTVCC PGOOD1 PGOOD 10k SGND GND DIFFP DIFFN DIFFOUT 470µF 6.3V 100µF 6.3V 147k 120k 0.1µF 22µF 25V 4.7µF INTV CC VOUT 1.2V 20A V IN 4.5V TO 15V 1.2V Output Efficiency vs Load Current LOAD CURRENT (A) EFFICIENCY (%) 6 8 102 4

3060 TA01b

4631fb For more information www.linear .com/L TM4631 pin conFiguraTion absoluTe MaxiMuM raTings PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, 3V to INTVCC (Note 1) LGA PACKAGE 144-LEAD (16mm × 16mm × 1.91mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VOUT2VOUT1 GND GND SGND GND TJMAX = 125°C, θJA = 7°C/W , θJCbottom = 1.5°C/W , θJCtop = 3.7°C/W , θJB + θJBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 1.35g BGA PACKAGE 144-LEAD (16mm × 16mm × 2.51mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VOUT2VOUT1 GND GND SGND GND TJMAX = 125°C, θJA = 7°C/W , θJCbottom = 1.5°C/W , θJCtop = 3.7°C/W , θJB + θJBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 1.54g Internal Operating Temperature Range C to 125°C 5°C

4631fbFor more information www.linear .com/L TM4631 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 15 V VOUT Output Voltage l 0.6 1.8 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 1 Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V, IOUT = 0A to 10A l 1.477 1.5 1.523 V Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 22µF ×3, CSS = 0.01µF, COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V 200 mA IQ(VIN) Input Supply Bias Current V IN = 12V, VOUT = 1.5V, Burst Mode Operation VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA µA I S(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 10A VIN = 12V, VOUT = 1.5V, IOUT = 10A 2.7 1.2 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Note 6) 0 10 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 15V IOUT = 0A for Each Output, l 0.01 0.025 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, V OUT = 1.5V, 0A to 10A VIN = 12V (Note 6) l 0.2 0.75 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/ X7R/Ceramic, 470µF POSCAP , VIN = 12V, VOUT = 1.5V, Frequency = 750kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V, VOUT = 1.5V, fSET = INTVCC (Note 4) 750 kHz fSYNC (Each Channel) SYNC Capture Range 500 780 kHz PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE LTM4631EV#PBF Au (RoHS) LTM4631V e4 LGA 3 –40°C to 125°C LTM4631IV#PBF Au (RoHS) LTM4631V e4 LGA 3 –40°C to 125°C LTM4631EY#PBF SAC305 (RoHS) LTM4631Y e1 BGA 3 –40°C to 125°C LTM4631IY#PBF SAC305 (RoHS) LTM4631Y e1 BGA 3 –40°C to 125°C LTM4631IY SnPb (63/37) LTM4631Y e0 BGA 3 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

Terminal Finish Part Marking: www.linear .com/leadfree
Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www .linear .com/umodule/pcbassembly
LGA and BGA Package and T ray Drawings: www.linear .com/packaging orDer inForMaTion http://www.linear .com/product/LTM4631#orderinfo

4631fb For more information www.linear .com/L TM4631 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP , VOUT = 1.5V, IOUT = 0A VIN = 12V 10 mV tSTART (Each Channel) Turn-On T ime COUT = 100µF/X5R/Ceramic, 470µF POSCAP , No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load : 0% to 50% to 0% of Full Load COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V IN = 12V, COUT = 100µF, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 13 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.606 V IFB (Note 5) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V TRACK1 (I), TRACK2 (I) Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.3 1.5 µA UVLO Undervoltage Lockout (Falling) 3.3 V UVLO Hysteresis 0.6 V tON(MIN) Minimum On-Time (Note 5) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 15V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 220 mV Oscillator and Phase-Locked Loop Oscillator Frequency Medium Frequency Lowest Frequency Highest Frequency fSET = 1.2V fSET = 0V (Note 4) fSET > 2.4V , Up to INTVCC 450 210 700 500 250 780 550 290 860 kHz kHz kHz f SET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTV CC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output V oltage 0.8 V V

4631fbFor more information www.linear .com/L TM4631 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4631 is tested under pulsed load conditions such that T J ≈ TA. The LTM4631E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4631I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: Although the switching frequency is programmable from 250kHz to 750kHz, the LTM4631 device is designed to operate from 500kHz to 750kHz for optimized inductor current ripple and efficiency. See the Applications Information section. Note 5: These parameters are tested at wafer sort. Note 6: See output current derating curves for different V IN, VOUT and TA. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Differential Amplifier AV Differential Amplifier Gain 1 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA 3 mV PSRR Differential Amplifier Power Supply Rejection Ratio 5V < V IN < 15V 90 dB ICL Maximum Output Current 3 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l –2.2 mV/C

4631fb For more information www.linear .com/L TM4631 Typical perForMance characTerisTics Burst Mode and Pulse-Skip Mode Efficiency VIN=12V, VOUT = 1.2V, 650kHz 1V Output Single Phase Load Transient Response 1.2V Output Single Phase Load Transient Response 1.5V Output Single Phase Load Transient Response 1.8V Output Single Phase Load Transient Response Single Phase Start-Up with No Load Applied Efficiency vs Output Current, V IN = 5V Efficiency vs Output Current, V IN = 12V Dual Phase Single Output Efficiency vs Output Current, V IN = 12V, LOAD CURRENT (A) EFFICIENCY (%) 2 4 6 8

4631 G01

1.8VOUT, 750kHz 1.5VOUT, 750kHz 1.2VOUT, 650kHz 1.0VOUT, 650kHz LOAD CURRENT (A) EFFICIENCY (%) 2 4 6 8

4631 G02

1.8VOUT, 750kHz 1.5VOUT, 750kHz 1.2VOUT, 650kHz 1.0VOUT, 650kHz LOAD CURRENT (A) EFFICIENCY (%) 4 2 6 8 10 12 14 16 18

4631 G03

1.8VOUT, 750kHz 1.5VOUT, 750kHz 1.2VOUT, 650kHz 1.0VOUT, 650kHz 50µs/DIV VOUT(AC) 50mV/DIV LOAD STEP 4A/DIV

4631 G06

12VIN, 1.0VOUT, 650kHz, 5A-10A Load Step 10A/µs STEP-UP and STEP-DOWN COUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC 50µs/DIV VOUT(AC) 50mV/DIV LOAD STEP 4A/DIV 12VIN, 1.2VOUT, 650kHz, 5A-10A Load Step 10A/µs STEP-UP and STEP-DOWN C OUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC 50µs/DIV VOUT(AC) 50mV/DIV LOAD STEP 4A/DIV

4631 G07

12VIN, 1.5VOUT, 750kHz, 5A-10A Load Step 10A/µs STEP-UP and STEP-DOWN C OUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC 50µs/DIV VOUT(AC) 50mV/DIV LOAD STEP 4A/DIV

4631 G08

12VIN, 1.8VOUT, 750kHz, 5A-10A Load Step 10A/µs STEP-UP and STEP-DOWN C OUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC 50ms/DIV VOUT 500mV/DIV SW 10V/DIV RUN 2V/DIV

4631 G09

12VIN, 1VOUT, 650kHz, No Load COUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC CSS = 0.1µF LOAD CURRENT (A) 0.01 EFFICIENCY (%) 100 1 100.1

4631 G04

4631fbFor more information www.linear .com/L TM4631 Typical perForMance characTerisTics Single Phase Short Circuit Protection with 10A Single Phase Start-up with 10A Applied Single Phase Short Circuit Protection with No load 50ms/DIV VOUT 500mV/DIV SW 10V/DIV RUN 2V/DIV

4631 G10

12VIN, 1VOUT, 650kHz, 10A Load COUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC CSS = 0.1µF 50µs/DIV VOUT 500mV/DIV SW 10V/DIV IIN

4631 G11

12VIN, 1.8VOUT, 750kHz, No Load CIN = 2 × 22µF CERAMIC COUT= 1 × 470µF POSCAP + 1 × 47µF CERAMIC 50µs/DIV VOUT 500mV/DIV SW 10V/DIV IIN

4631 G12

12VIN, 1.8VOUT, 750kHz, No Load CIN = 2 × 22µF CERAMIC COUT = 1 × 470µF POSCAP + 1 × 47µF CERAMIC

4631fb For more information www.linear .com/L TM4631 pin FuncTions VOUT1 ( A1-A5, B1- B5, C1- C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. VOUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the VOUTS pins is con- nected to the DIFFOUT pin in remote sensing or directly to V OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. fSET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 12. VFB1, V FB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is con- nected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor . Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave out- put’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier . This pin is connected to the remote sense point of the output voltage. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier . This pin is connected to the remote sense point of the output GND. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

4631fbFor more information www.linear .com/L TM4631 pin FuncTions RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan- nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation con- nect one of the VOUTS pin to DIFFOUT for remote sensing. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4 ): Connect this pin to SGND, INTV CC, or floating this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 (G9, G8): Output Voltage Power Good Indicator . Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regula- tion point. INTV CC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTV CC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Onboard General Purpose Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to V IN when operating VIN on 5V. An efficiency increase will occur that is a function of the (V IN – INTVCC) multiplied by power MOSFET driver current. Typical current require- ment is 30mA. VIN must be applied before EXTV CC, and EXTVCC must be removed before VIN. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. (Recommended to Use Test Points to Monitor Signal Pin Connections.)

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4631 Block Diagram

4631fbFor more information www.linear .com/L TM4631 operaTion Power Module Description The LTM4631 is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 10A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 1.8VDC over 4.5V to 15V input voltages. The typical application schematic is shown in Figure 23. The LTM4631 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 550kHz to 750kHz. For switching-noise sen- sitive applications, it can be externally synchronized from 500kHz to 780kHz. A resistor can be used to program a free run frequency on the FSET pin. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4631 module has sufficient sta- bility margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condi- tion. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regu- lation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator . See the Applications Information section. The LTM4631 is internally compensated to be stable over all operating conditions. Table 4 provides a guide line for input and output capacitances for several operating con- ditions. The Linear Technology µModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to different levels. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping opera- tion using the MODE_PLLIN pin. These light load fea - tures will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. A general purpose temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. The switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details.

Figure 23. External component selection is primarily requirements for particular applications. down ratio that can be achieved for a given input voltage. capability related to high duty cycle on the top side switch. where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. Table 1. VFB Resistor Table vs Various Output Voltages back setting resistor can be used for the parallel design. one programming resistor as shown in Figure 2. Figure 2. 4-Phase Parallel Configurations

4631 F02

4 PARALLELED OUTPUTS

4631fbFor more information www.linear .com/L TM4631 applicaTions inForMaTion Input Capacitors The LTM4631 module should be connected to a low ac- impedance DC source. For the regulator input one 10µF to 22µF input ceramic capacitor is used for RMS ripple current for each phase. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capaci- tance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: D = VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D • 1−D( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , Polymer capacitor . Output Capacitors The LTM4631 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , the low ESR polymer capaci - tor or ceramic capacitor . The typical output capacitance range for each output is 300µF. Additional output filter - ing may be required by the system designer , if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A transient at 10A/µs speed. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and the Linear Technology L TpowerCAD Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the num - ber of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The LTM4631 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermit- tently based on load demand, thus saving quiescent cur- rent. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’ s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, caus- ing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4631 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation.

4631fb For more information www.linear .com/L TM4631 applicaTions inForMaTion Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4631 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current compara - tor may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequen - cies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the low - est output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start- up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4631’s output voltage is in regulation. Either regulator can be configured for force continuous mode. Multiphase Operation For output loads that demand more than 10A of current, two outputs in LTM4631 or even multiple LTM4631s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the LTM4631 to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked-loop allows the LTM4631 to lock onto incoming clock phase as well. The CLKOUT sig- nal can be connected to the MODE_PLLIN pin of the fol- lowing stage to line up both the frequency and the phase of the entire system. T ying the PHASMD pin to INT VCC, SGND, or (floating) generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4631 chan- nel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the out- put voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The LTM4631 device is an inherently current mode con- trolled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 26 shows an example of parallel operation and pin connection. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of mul- tiphase operation. The input RMS ripple current cancella- tion mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. PLL, Frequency Adjustment and Synchronization The LTM4631 switching frequency is set by a resistor (RfSET) from the fSET pin to signal ground. A 10µA current (IFREQ) flowing out of the fSET pin through RfSET develops a volt- age on fSET. RfSET can be calculated as: RfSET = FREQ 500kHz / V+0.2V ⎣⎢ ⎦⎥ 1 10µA

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

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Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table

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180 PHASE0 PHASE

90 DEGREE

270 PHASE90 PHASE

60 DEGREE 60 DEGREE

240 PHASE60 PHASE

300 PHASE120 PHASE

ciency graphs for optimal frequency set point. set resistor for free run operation. and the gate charge required turning on the top MOSFET . good rule of thumb is to keep on-time longer than 90ns. VTRACK is the track ramp applied to the slave’s track pin. in Figure 6 will be equal to the RFB for coincident tracking. Figure 7 shows the coincident tracking waveforms. Figure 5. Operating Frequency vs fSET Pin Voltage

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Figure 7. Output Coincident T racking Waveform Figure 6. Example of Output T racking Application Circuit

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will control output regulation from the feedback divider . setting on the MODE_PLLIN pin.

4631fb For more information www.linear .com/L TM4631 applicaTions inForMaTion where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal the 60.4k. RTA is derived from equation: RTA = 0.6V VFB 60.4k + VFB RFB − VTRACK RTB where VFB is the feedback voltage reference of the regula- tor , and VTRACK is 0.6V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator . RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R TB = 76.8k. Solve for RTA to equal to 49.9k. Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The module has already been internally compensated for all output voltages. Table 4 is provided for most appli - cation requirements. The Linear Technology µModule Power Design Tool will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Application circuits in Figure 23. INTVCC and EXTVCC The LTM4631 module has an internal 5V low dropout regulator that is derived from the input voltage. This regu- lator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTVCC allows an external 5V supply to power the LTM4631 and reduce power dissipation from the internal low dropout 5V regulator . The power loss savings can be calculated by: (VIN – 5V) • 30mA = PLOSS EXTVCC has a threshold of 4.7V for activation, and a maxi- mum rating of 6V. When using a 5V input, connect this 5V input to EXTV CC also to maintain a 5V gate drive level. EXTVCC must sequence on after V IN, and EXTV CC must sequence off before VIN. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either V OUTS1 or V OUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 24 and review Figure 2.

its impedance is equal to the resistor at the ring frequency. composite diode voltage slope. Figure 8. Diode Voltage VD vs Temperature T(K)

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4631fb For more information www.linear .com/L TM4631 applicaTions inForMaTion To obtain a linear voltage proportional to temperature we cancel the I S variable in the natural logarithm term to remove the I S dependency from the equation 1. This is accomplished by measuring the diode voltage at two cur- rents I1, and I2, where I1 = 10 • I2) and subtracting we get: ΔVD = T(KELVIN)•KD •IN I1 IS – T(KELVIN)•KD •INI2 IS Combining like terms, then simplifying the natural log terms yields: ΔVD = T(KELVIN) • KD • lN(10) and redefining constant K'D =KD •IN(10) = 198µV K yields ΔVD = K’D • T(KELVIN) Solving for temperature: T(KELVIN)= ΔVD K'D (°CELSIUS)= T(KELVIN)– 273.15 where 300°K = 27°C means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. The diode connected PNP transistor between the TEMP pin and the SGND pin can be used to monitor the internal temperature of the LTM4631. See Figure 24 for an example. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board—also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their appli- cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance per- taining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coef- ficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the pack - age. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCTOP, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the

don’t generally match the user’s application.

θJB, the thermal resistance from junction to the

board is described in JESD 51-9. resistances are external to the µModule. a majority of the heat flow is into the board. Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

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Figure 12. Recommended PCB Layout

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Table 2. 1.0V Output Table 3. 1.5V Output

Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 5A Load Step Typical Measured Values Figure 13. 1.0V Output Power Figure 14. 1.5V Output Power Figure 15. 12V to 1V Derating

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Figure 16. 5V to 1V Derating Figure 17. 12V to 1V Derating Figure 18. 5V to 1V Derating Figure 19. 12V to 1.5V Derating Figure 20. 5V to 1.5V Derating Figure 21. 12V to 1.5V Derating Figure 22. 5V to 1.5V Derating

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Figure 23. Typical 4.5VIN to 15VIN, 1.0V and 1.2V at 10A Outputs

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Figure 24. LTM4631 2-Phase, 1.5V at 20A Design with Temperature Monitoring

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Figure 25. LTM4631 1.2V and 1V Output with T racking Function

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Figure 26. LTM4631 4-Phase, 1.2V at 40A Output

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4631fb For more information www.linear .com/L TM4631 LTM4631 LGA and BGA Pinouts package DescripTion PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 f SET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2 A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN G4 PHASEMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND

4631fbFor more information www.linear .com/L TM4631 package DescripTion Please refer to http://www.linear .com/product/LTM4631#packaging for the most recent package drawings. 144-Lead (16mm × 16mm × 1.91mm) (Reference L TC DWG # 05-08-1504 Rev A) DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G LGA 144 1015 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” SYMBOL A b D E e F G aaa bbb eee MIN 1.81 0.60 0.36 1.45 NOM 1.91 0.63 16.0 16.0 1.27 13.97 13.97 0.41 1.50 MAX 2.01 0.66 0.46 1.55 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 144 DETAIL A DIA 0.630 PAD 1 L K J H G F E D C BM A SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 SEE NOTES

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y L TMXXXXXX µModule DETAIL A Øb (144 PLACES) M X Y Z ddd M Z eee 0.630 ±0.025 Ø 144x

4631fb For more information www.linear .com/L TM4631 package DescripTion Please refer to http://www.linear .com/product/LTM4631#packaging for the most recent package drawings. 144-Lead (16mm × 16mm × 2.51mm) (Reference L TC DWG # 05-08-1503 Rev B) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 0517 REV B TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 A B C D E F G HK JL M SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SEE NOTES SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.31 0.50 1.81 0.60 0.60 0.36 1.45 NOM 2.51 0.60 1.91 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 1.50 MAX 2.71 0.70 2.01 0.90 0.66 0.46 1.55 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 144 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y aaa Z

4631fbFor more information www.linear .com/L TM4631 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 7/17 Corrected title of vertical axis on Figure 13 and Figure 14 from Efficiency to Power Loss 24 B 8/17 Added BGA package 1, 2, 3, 32

4631fb For more information www.linear .com/L TM4631  LINEAR TECHNOLOGY CORPORATION 2016 LT 0817 REV B • PRINTED IN USA www.linear .com/L TM4631 relaTeD parTs Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS 6.25mm × 6.25mm × 2.42mm BGA 6.25mm × 6.25mm × 2.42mm BGA LTM4632 Ultrathin, T riple Output µModule Regulator for DDR- QDR4 Memory. Dual ±3A for VDDQ and VTT , and V REF . 6.25mm × 6.25mm × 2.42mm BGA LTM4644 Quad 4A µModule Regulator 4V ≤ VIN ≤14V, 0.6V ≤ VOUT ≤ 5.5V. 9mm × 15mm × 5.01mm BGA 15mm × 15mm × 4.32 LGA, 16mm × 16mm × 4.92mm BGA × 15mm × 4.41 LGA, 16mm × 16mm × 5.01mm BGA LTM4630 LTM4650 Dual 18A or Single 36A µModule Regulator Dual 25A or Single 50A µModule Regulator Pin Compatible with LTM4631. 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V. 16mm × 16mm × 5.01 BGA, 16mm × 16mm × 4.41mm LGA (LTM4630 Only). LTM4630-1 LTM4650-1 LTM4630 with 0.8% DC and 3% T ransient Accuracy LTM4650 with 3% T ransient Accuracy LTM4677 Dual 18A or Single 36A µModule Regulator with Digital Power System Management 4.5V ≤ V Power Management Solution for FPGAs Reference Design for Altera and Xilinx FPGAs www.linear .com/FPGA package phoTo

Product Information

LTM4631 specifications and overview.

Summary

Ultrathin Dual 10A or Single 20A DC/DC 關Module Regulator

Description

Ultrathin Dual 10A or Single 20A DC/DC 關Module Regulator

Source title LTM4631 Datasheet(PDF) - Linear Technology

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