LTM4630A

LTM4650-1 LINER | Alldatasheet

Document overview

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Technical content

46501fcFor more information www.linear .com/L TM4650-1 Typical applicaTion

DescripTion

µModule Regulator with 0.8% DC and 3% Transient Accuracy The LT M®4650-1A/LTM4650-1B is dual 25A or single 50A output step-down µModule ® (power module) regulator with ±0.8% (LTM4650-1A) and ±1.5% (LTM4650-1B) total DC output error with ±3% transient output error. Included in the package are the switching controller, power FETs, inductors, and all supporting components. External compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs, and processors. With synchronized multiphase parallel current sharing, six LTM4650-1 devices can de - liver up to 300A. The LTM4650-1 is offered in a 16mm × 16mm ×

5.01 BGA package, with SnPb (BGA) or RoHS

compliant terminal finish.

FeaTures

applicaTions

n ±0.8% Maximum Total DC Output Error Over Line and Load (L TM4650-1A) n ±3% T ransient Output Error with Minimum Output Capacitance n Dual 25A or Single 50A Output n 4.5V to 15V Input, 0.6V to 1.8V Output Voltage Range n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Current Sharing Up to 300A n 16mm × 16mm × 5.01mm BGA Package n FPGA, ASIC, µProcessor Core Voltage Regulation n Information, Communication Systems L, LT, LT C, LT M, Linear Technology, the Linear logo, µModule, Burst Mode, L TpowerCAD and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. 50A, 1.0V Output DC/DC µModule Regulator 1.0V Output Efficiency, fSW = 500kHz 25% Load Step T ransient Response, ±3% Output Regulation Window. 12VIN, 1.0VOUT, 50A with 6x 220μF Ceramic Cap

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VIN 220µF CERAMIC 68pF V OUT1 VFB1 VFB2 VOUTS2 COMP2 VOUT2 1.0V 50A MODE_PLLINSGNDPHASMD GND COMP1 V OUT2 DIFFP DIFFN DIFFOUT 90.9k 121k VIN 4.5V TO 15V 120k 0.1µF 22µF 25V 4.7µF TEMP RUN1 RUN2 TRACK1 TRACK2 INTV CC PGOOD1 PGOOD2 fSET PINS NOT USED IN THIS CIRCUIT : CLKOUT EXTV CC SW1 SW2 V OUTS1 10k 10nF 3.24k LOAD CURRENT (A) EFFICIENCY (%)

46501 TA01b

VIN = 5V VIN = 12V VOUT 20mV/DIV AC-COUPLED LOAD STEP 10A/DIV 50µs/DIV

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12.5A STEP *SEE DEMO CIRCUIT DC2479A-B

46501fc For more information www.linear .com/L TM4650-1 pin conFiguraTionabsoluTe MaxiMuM raTings (Note 1) orDer inForMaTion PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, 3V to INTVCC to INTVCC Internal Operating Temperature Range 5°C to 125°C 5°C BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VIN VOUT2GND GND VOUT1 SGND GND TJMAX = 125°C, θJA = 7°C/W, θJCbottom = 1.5°C/W, θJCtop = 3.7°C/W, θJB + θJBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.5g PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TOTAL DC ACCURACY TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE LTM4650EY-1A#PBF SAC305 (RoHS) LTM4650Y- 1 e1 BGA 3 ±0.8% –40°C to 125°C LTM4650IY-1A#PBF SAC305 (RoHS) LTM4650Y- 1 e1 BGA 3 ±0.8% –40°C to 125°C LTM4650EY-1B#PBF SAC305 (RoHS) LTM4650Y- 1 e1 BGA 3 ±1.5% –40°C to 125°C LTM4650IY-1B#PBF SAC305 (RoHS) LTM4650Y- 1 e1 BGA 3 ±1.5% –40°C to 125°C LTM4650IY-1A SnPb (63/37) LTM4650Y-1 e0 BGA 3 ±0.8% –40°C to 125°C LTM4650IY-1B SnPb (63/37) LTM4650Y-1 e0 BGA 3 ±1.5% –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609.

Terminal Finish Part Marking: www.linear.com/leadfree
Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly
BGA Package and T ray Drawings: www.linear.com/packaging http://www.linear.com/product/LTM4650-1#orderinfo

46501fcFor more information www.linear .com/L TM4650-1 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 15 V VOUT Output DC Voltage l 0.6 1.8 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 2 Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.2V, IOUT = 0A to 25A A-Grade (0.8%) B-Grade (1.5%) l l 1.190 1.182 1.210 1.218 V V Input Specifications V RUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 22µF × 3, CSS = 0.01µF, COUT = 100µF × 3, VOUT = 1.2V 1 A IQ(VIN) Input Supply Bias Current (Both Channel Running VIN = 12V, VOUT = 1.2V, Burst Mode Operation VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.2V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 4.5 240 mA mA mA µA I S(VIN) Input Supply Current VIN = 4.5V, VOUT = 1.2V, IOUT = 25A VIN = 12V, VOUT = 1.2V, IOUT = 25A 8.4 3.2 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.2V (Note 6) 0 25 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.2V, VIN from 4.5V to 15V IOUT = 0A for Each Output, l 0.01 0.1 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, V OUT = 1.2V, 0A to 25A VIN = 12V (Note 6) A-Grade B-Grade l l 0.1 0.2 0.4 0.75 V OUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF × 3 Ceramic, 470µF POSCAP, VIN = 12V, VOUT = 1.2V, Frequency = 500kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V, VOUT = 1.2V, fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range 400 780 kHz ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF Ceramic, 470µF POSCAP, VOUT = 1.2V, IOUT = 0A VIN = 12V 10 mV tSTART (Each Channel) Turn-On T ime COUT = 100µF Ceramic, 470µF POSCAP, No Load, TRACK/SS with 0.01µF to GND, V IN = 12V 5 ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load : 0% to 50% to 0% of Full Load COUT = 22µF × 3 Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.2V 30 mV

46501fc For more information www.linear .com/L TM4650-1 elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 12V, COUT = 100µF, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.2V 35 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.2V A-Grade B-Grade l l 0.596 0.594 0.600 0.600 0.604 0.606 V V I FB (Note 5) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V TRACK1 (I), TRACK2 (I) Track Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.3 1.5 µA UVLO Undervoltage Lockout (Falling) 3.3 V UVLO Hysteresis 0.6 V tON(MIN) Minimum On-Time (Note 5) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 INTV CC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 15V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA 0.75 2 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 220 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz Frequency Low Lowest Frequency fSET = 0.93V 400 kHz Frequency High Highest Frequency fSET > 2.4V , Up to INTVCC 780 kHz fSET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTV CC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output V oltage 0.2 V V

46501fcFor more information www.linear .com/L TM4650-1

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4650-1 is tested under pulsed load conditions such that T J ≈ TA. The LTM4650-1E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4650-1I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: LTM4650-1 device is designed to operate from 400kHz to 750kHz. Note 5: These parameters are tested at wafer sort. Note 6: See output current derating curves for different V IN, VOUT and TA. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Differential Amplifier AV Differential Amplifier Gain 1 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.2V, IDIFFOUT = 100µA 3 mV PSRR Differential Amplifier Power Supply Rejection Ratio 5V < V IN < 15V 90 dB ICL Maximum Output Current 3 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l –2.2 mV/C The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 24. Typical perForMance characTerisTics Efficiency vs Output Current, VIN = 5V Efficiency vs Output Current, V IN = 12V Dual Phase Single Output Efficiency vs Output Current, V IN = 12V, fS = 500kHz LOAD CURRENT (A) EFFICIENCY (%)

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1.5VOUT, 600kHz 1.8VOUT, 600kHz 1.2VOUT, 500kHz 1.0VOUT, 500kHz 0.8VOUT, 400kHz LOAD CURRENT (A) EFFICIENCY (%)

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1.5VOUT, 600kHz 1.8VOUT, 600kHz 1.2VOUT, 500kHz 1.0VOUT, 500kHz 0.8VOUT, 400kHz LOAD CURRENT (A) EFFICIENCY (%) 20 30 40 5010

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1.5VOUT, 600kHz 1.8VOUT, 600kHz 1.2VOUT, 500kHz 1.0VOUT, 500kHz 0.8VOUT, 400kHz

46501fc For more information www.linear .com/L TM4650-1 Typical perForMance characTerisTics Single Phase Short Circuit Protection with 25ASingle Phase Start-up with 25A Single Phase Short Circuit Protection with No load 1.5V Dual Phase Single Output Load Transient Response 1.8V Dual Phase Single Output Load Transient Response Single Phase Start-Up with No load 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 0.2A/Div

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12VIN, 1.2VOUT, 500kHz COUT = 1× 470µF POSCAP + 2× 100µF CERAMIC, CSS = 0.1µF 50/uni03BCs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div

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12VIN, 1.2VOUT, 500kHz COUT = 1× 470µF POSCAP + 2× 100µF CERAMIC, CSS = 0.1µF 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div

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12VIN, 1.2VOUT, 500kHz COUT = 1× 470µF POSCAP + 2× 100µF CERAMIC, CSS = 0.1/uni03BCF 50µs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 2A/Div

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12VIN, 1.2VOUT, 500kHz COUT = 1× 470µF POSCAP + 2× 100µF CERAMIC Burst Mode and Pulse-Skip Mode Efficiency V IN=12V, VOUT = 1.2V, fS = 500kHz 1V Dual Phase Single Output Load Transient Response 1.2V Dual Phase Single Output Load Transient Response LOAD CURRENT (A) 0.01 30EFFICIENCY (%) 100 1 100.1

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50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV

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12VIN, 1VOUT, 500kHz, 12.5A LOAD STEP, 10A/µs STEP-UP AND STEP-DOWN COUT = 6× 220µF CERAMIC CFF = 68pF 50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV

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12VIN, 1.2VOUT, 500kHz, 12.5A LOAD STEP, 10A/µs STEP-UP AND STEP-DOWN C OUT = 6× 220µF CERAMIC CFF = 68pF 50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV

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12VIN, 1.5VOUT, 600kHz, 12.5A LOAD STEP, 10A/µs STEP-UP AND STEP-DOWN C OUT = 6× 220µF CERAMIC CFF = 68pF 50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV

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12VIN, 1.8VOUT, 600kHz, 12.5A LOAD STEP, 10A/µs STEP-UP AND STEP-DOWN C OUT = 6× 220µF CERAMIC CFF = 68pF

46501fcFor more information www.linear .com/L TM4650-1 pin FuncTions VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. V OUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Rec- ommend placing output decoupling capacitance directly between these pins and GND pins. Review T able 4. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the V OUTS pins is connected to the DIFFOUT pin in remote sensing or directly to V OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. f SET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the ap- plication. See layout guidelines in Figure 13. V FB1, V FB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is con - nected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between V FB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave out- put’s track pin. This voltage divider is equal to the slave output’ s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. COMP pin internal has 10pF filter cap to SGND. An external RC filter circuit is required for control loop compensation. See Applications Information section. Tie the COMP pins together for parallel operation. Do not drive this pin. DIFFP (E8): Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. See the Applications Information section. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

46501fc For more information www.linear .com/L TM4650-1 pin FuncTions MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan- nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2 V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation con - nect one of the VOUTS pin to DIFFOUT for remote sensing. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTV CC, or float- ing this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 (G 9, G 8): Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. INTV CC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Temperature Monitor. An internal diode con- nected NPN transistor between this pin and SGND with 10nF filtering capacitor . See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. VIN must be applied before EXTVCC, and EXTVCC must be removed before VIN. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. (Recommended to Use Test Points to Monitor Signal Pin Connections.)

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4650-1 Block Diagram

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46501fc For more information www.linear .com/L TM4650-1 operaTion Power Module Description The LTM4650-1 is a dual-output standalone nonisolated switching mode DC/DC power supply with ±0.8% (A-Grade) total DC output error over line, load and temperature varia- tion. It can provide two 25A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 1.8VDC over 4.5V to 15V input voltages. The typical application schematic is shown in Figure 24. The LTM4650-1 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is from 400kHz to 600kHz depending on output voltage. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 780kHz. A resistor can be used to program a free run frequency on the FSET pin. See the Applications Information section. With current mode control, the LTM4650-1 module has sufficient stability margins and good transient perfor - mance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an over current condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator. See the Applications Information section. The LTM4650-1 has a built-in 10pF high frequency filter cap from COMP to SGND for each output. An external RC filtering circuit is required to achieve fast Type II control loop compensation. Table 4 provides a guide line for input, output capacitances and RC comp values for several oper- ating conditions. The Linear Technology µModule Power Design T ool (L TpowerCAD®) will be provided for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sens- ing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin to different levels. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping opera- tion using the MODE_PLLIN pin. These light load features will accommodate battery operation . Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. See the Applications Information section for details. A general purpose temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. The switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details.

Figure 24. External component selection is primarily requirements for particular applications. load step transient must fall within this allowed window. DC accuracy by using 100µF ceramic output capacitors. Figure 2. Typical Load Step T ransient Response with DC Voltage

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Figure 3. Overall Output Capacitor vs Total DC Accuracy down ratio that can be achieved for a given input voltage. where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. The PWM controller has an internal 0.6V reference voltage. to their respective outputs for proper feedback regulation.

Table 1. VFB Resistor Table vs Various Output Voltages back setting resistor can be used for the parallel design. one programming resistor as shown in Figure 4. bulk capacitor is not needed. rated electrolytic aluminum capacitor, Polymer capacitor. Figure 4. 4-Phase Parallel Configurations

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4 PARALLELED OUTPUTS

46501fcFor more information www.linear .com/L TM4650-1 applicaTions inForMaTion Output Capacitors The LTM4650-1 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 400µF to 600µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 12.5A (25%) and 25A (50%) load step transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and the Linear Technology L Tpower- CAD Design Tool will be provided for stability analysis. In multi LTM4650-1 paralleling applications, Table 4 RC compensation value is still valid in terms of having one set of RC filters on each of the paralleling modules while connecting all the COMP, FB and V OUT pins together. See Figure 29 and Multiphase Operation section. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology L TpowerCAD Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from V OUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from V OUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The LTM4650-1 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate in - termittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, caus- ing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4650-1 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high effi - ciency at intermediate currents are desired, pulse-skipping mode should be used . Pulse-skipping operation allows the LTM4650-1 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode.

Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table

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180 PHASE0 PHASE

90 DEGREE

270 PHASE90 PHASE

60 DEGREE 60 DEGREE

240 PHASE60 PHASE

300 PHASE120 PHASE

for clock phasing with the PHASMD table.

46501fcFor more information www.linear .com/L TM4650-1 A multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. In multi LTM4650-1s parallel applications, C TH and RTH values in Table 4 are still valid to achieve a ±3% transient response in a 25% load step. Connect one set of RC (RTH and CTH) network to the COMP pin of each paralleling module like a dual phase single output setup. Then connect the COMP pins, FB pins, TRACK/SS pin and V OUT pins from different modules together. See Figure 29 for an example of parallel operation. L TpowerCAD Power Design Tool can also be used to optimize loop compensation and transient performance if only one set of RC (R TH and CTH) network is to be added to the common COMP pins. The LTM4650-1 device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 29 shows an example of parallel operation and pin connection. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancel- lation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 6 shows this graph. applicaTions inForMaTion Frequency Selection and Phase-Lock Loop (MODE_PLLIN and f SET Pins) The LTM4650-1 device is operated over a range of fre - quencies to improve power conversion efficiency. It is recommended to operate the module at 400kHz for output voltage below 1.0V, 500kHz for output voltage between 1.0V to 1.5V and 600kHz for output voltage above 1.5V, for the best efficiency and inductor current ripple. The LTM4650-1 switching frequency can be set with an external resistor from the f SET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be applied. Figure 7 shows a graph of frequency setting verses programming voltage. An external clock can be applied to the MODE_PLLIN pin from 0V to INTVCC over a frequency range of 400kHz to 780kHz. The clock input high threshold is 1.6V and the clock input low threshold is 1V. The LTM4650-1 has the PLL loop filter components on board. The frequency setting resistor should always be present to set the initial switching frequency before locking to an external clock. Both regulators will operate in continuous mode while being externally clock. The output of the PLL phase detector has a pair of comple- mentary current sources that charge and discharge the internal filter network. When the external clock is applied then the f SET frequency resistor is disconnected with an internal switch, and the current sources control the frequency adjustment to lock to the incoming external clock. When no external clock is applied, then the internal switch is on, thus connecting the external f SET frequency set resistor for free run operation.

Figure 6. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

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Figure 7. Operating Frequency vs fSET Pin Voltage

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Figure 8. Example of Output T racking Application Circuit and the gate charge required turning on the top MOSFET. good rule of thumb is to keep on-time longer than 110ns. VTRACK is the track ramp applied to the slave’s track pin.

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Figure 9. Output Coincident T racking Waveform

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in Figure 8 will be equal to the RFB for coincident tracking. Figure 9 shows the coincident tracking waveforms. voltage will reach it final value before the master output. TB = 76.8k. Solve for RTA to equal to 49.9k. offset to a negligible value. will control output regulation from the feedback divider.

46501fcFor more information www.linear .com/L TM4650-1 applicaTions inForMaTion Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The LTM4650-1 has a built-in 10pF high frequency filter capacitor from COMP to SGND on each output channel. An external RC filtering circuit is required to add from COMP to SGND to achieve fast Type II control loop compensation. Table 4 is provided for most application requirements. The Linear Technology µModule Power Design Tool (L Tpower- CAD) will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4 V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Applica- tion circuits in Figure 24. INTVCC and EXTVCC The LTM4650-1 module has an internal 5V low dropout regulator that is derived from the input voltage. This regu- lator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTV CC allows an external 5 V supply to power the LTM4650-1 and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: VIN – 5V) • 30mA = PLOSS EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after V IN, and EXTV CC must sequence off before VIN. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either V OUTS1 or V OUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the V OUTS pins. Review the parallel schematics in Figure 25 and review Figure 4. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths . Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: ZL = 2πfL, where f is the resonant frequency of the ring , and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that

composite diode voltage slope. its impedance is equal to the resistor at the ring frequency. Figure 10. Diode Voltage VD vs Temperature T(°C)

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46501fcFor more information www.linear .com/L TM4650-1 applicaTions inForMaTion To obtain a linear voltage proportional to temperature we cancel the IS variable in the natural logarithm term to remove the I S dependency from the equation 1. This is accomplished by measuring the diode voltage at two cur- rents I1, and I2, where I1 = 10 • I2) and subtracting we get: ΔVD = T(KELVIN)•KD •IN I1 IS – T(KELVIN)•KD •INI2 IS Combining like terms, then simplifying the natural log terms yields: Δ VD = T(KELVIN) • KD • lN(10) and redefining constant K'D =KD •IN(10) = 198µV K yields Δ VD = K'D • T(KELVIN) Solving for temperature: T(KELVIN)= ΔVD K'D (°CELSIUS)= T(KELVIN)– 273.15 where 300° K = 27°C means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198μV per Kelvin of the junction with a zero intercept at 0 Kelvin. The diode connected PNP transistor at the TEMP pin can be used to monitor the internal temperature of the LTM4650-1. See Figure 25 for an example. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board—also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coef- ficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application.

Figure 11. Graphical Representation of JESD51-12 Thermal Coefficients

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θJCTOP, the thermal resistance from junction to top of

the heat flows from the junction to the top of the part. generally match the user’s application. two layer board. This board is described in JESD 51-9. resistances are external to the µModule.

Figure 13. Recommended PCB Layout

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erations are still necessary.

Use large PCB copper areas for high current paths , including V IN, GND, VOUT1 and VOUT2. It helps to mini- mize the PCB conduction loss and thermal stress.
Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
Place a dedicated power ground layer underneath the unit.
To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. applicaTions inForMaTion
Do not put via directly on the pad, unless they are capped or plated over.
Use a separated SGND ground copper area for com - ponents connected to signal pins. Connect the SGND to GND underneath the unit.
For parallel modules , tie the VOUT, VFB, and COMP pins together. Use an internal layer to closely connect these pins together. The TRACK pin can be tied a common capacitor for regulator soft-start.
Bring out test points on the signal pins for monitoring. Figure 13 gives a good example of the recommended layout. LGA and BGA PCB layouts are identical with the exception of circle pads for BGA (see Package Description).

Table 2. 0.9V Output Table 3. 1.5V Output Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 23) Load Step Typical Measured Values

46501fcFor more information www.linear .com/L TM4650-1 applicaTions inForMaTion 25% Load Step (0A to 12.5A) Ceramic Output Capacitor Only Solutions PEAK-PEAK DEVIATION PERCENTAGE V IN VOUT CIN* (BULK) CIN (CERAMIC) COUT (BULK) COUT (CERAMIC) COMP PIN PARALLEL CAPACITOR (CTHP) COMP PIN RESISTOR (RTH) COMP PIN CAPACITOR (CTH) FEED- FORWARD CAPACITOR (CFF) PEAK- PEAK DEVIATION (VPK-PK) SETTLING TIME (tSETTLE) CTRL LOOP BAND- WIDTH (BW) CTRL LOOP PHASE MARGIN (PM) LOAD STEP (A) LOAD STEP SLEW RATE RFB (kΩ) FREQ (kHz) ±3% (<60mV) 12V 1V 150µF 22µF x 2 None 220µF x 6 33pF 3.24kΩ 10nF 68pF 53mV 80µs 88kHz 47 Deg 12.5 10A/µs 90.9 500 ±3% (<72mV) 12V 1.2V 150µF 22µF x 2 None 220µF x 5 33pF 3.24kΩ 10nF 68pF 56mV 80µs 89kHz 49 Deg 12.5 10A/µs 60.4 500 ±3% (<90mV) 12V 1.5V 150µF 22µF x 2 None 220µF x 4 33pF 3.24kΩ 10nF 68pF 58mV 80µs 91kHz 58 Deg 12.5 10A/µs 40.2 600 ±3% (<108mV) 12V 1.8V 150µF 22µF x 2 None 220µF x 4 33pF 3.24kΩ 10nF 68pF 64mV 90µs 98kHz 65 Deg 12.5 10A/µs 30.2 600 25% Load Step (0A to 9A) Bulk + Ceramic Output Capacitor Solutions PEAK-PEAK DEVIATION PERCENTAGE V IN VOUT CIN* (BULK) CIN (CERAMIC) COUT (BULK) COUT (CERAMIC) COMP PIN PARALLEL CAPACITOR (CTHP) COMP PIN RESISTOR (RTH) COMP PIN CAPACITOR (CTH) FEED- FORWARD CAPACITOR (CFF) PEAK- PEAK DEVIATION (VPK-PK) SETTLING TIME (tSETTLE) CTRL LOOP BAND- WIDTH (BW) CTRL LOOP PHASE MARGIN (PM) LOAD STEP (A) LOAD STEP SLEW RATE RFB (kΩ) FREQ (kHz) ±3% (<60mV) 12 V 1V 150µF 22µF × 2 470µF × 2 100µF × 4 33pF 3.16kΩ 3300pF 68pF 55mV 30µs 82kHz 68 Deg 12.5 10A/µs 90.9 500 ±3% (<72mV) 12V 1.2V 150µF 22µF × 2 470µF × 2 100µF × 4 33pF 3.16kΩ 3300pF 68pF 55mV 30µs 82kHz 73 Deg 12.5 10A/µs 60.4 500 ±3% (<90mV) 12V 1.5V 150µF 22µF × 2 470µF × 2 100µF × 4 82pF 4.12kΩ 3300pF None 64mV 30µs 59kHz 53 Deg 12.5 10A/µs 40.2 600 ±3% (<108mV) 12V 1.8V 150µF 22µF × 2 470µF × 2 100µF × 4 82pF 4.12kΩ 3300pF None 75mV 30µs 51kHz 58 Deg 12.5 10A/µs 30.2 600 50% Load Step (0A to 25A) Ceramic Output Capacitor Only Solutions PEAK-PEAK DEVIATION PERCENTAGE V IN VOUT CIN* (BULK) CIN (CERAMIC) COUT (BULK) COUT (CERAMIC) COMP PIN PARALLEL CAPACITOR (CTHP) COMP PIN RESISTOR (RTH) COMP PIN CAPACITOR (CTH) FEED- FORWARD CAPACITOR (CFF) PEAK- PEAK DEVIATION (VPK-PK) SETTLING TIME (tSETTLE) CTRL LOOP BAND- WIDTH (BW) CTRL LOOP PHASE MARGIN (PM) LOAD STEP (A) LOAD STEP SLEW RATE RFB (kΩ) FREQ (kHz) ±3% (<60mV) 12V 1V 150µF 22µF × 2 None 220µF × 12 33pF 6.81kΩ 4.7nF 100pF 58mV 80µs 76kHz 45 Deg 25 10A/µs 90.9 500 ±3% (<72mV) 12V 1.2V 150µF 22µF × 2 None 220µF × 12 33pF 6.81kΩ 4.7nF 100pF 61mV 80µs 77kHz 50 Deg 25 10A/µs 60.4 500 ±3% (<90mV) 12V 1.5V 150µF 22µF × 2 None 220µF × 14 33pF 5.90kΩ 4.7nF None 90mV 80µs 47kHz 45 Deg 25 10A/µs 40.2 600 ±3% (<108mV) 12V 1.8V 150µF 22µF × 2 None 220µF × 14 33pF 5.90kΩ 4.7nF None 105mV 90µs 43kHz 50 Deg 25 10A/µs 30.2 600 50% Load Step (0A to 25A) Bulk + Ceramic Output Capacitor Solutions PEAK-PEAK DEVIATION PERCENTAGE V IN VOUT CIN* (BULK) CIN (CERAMIC) COUT (BULK) COUT (CERAMIC) COMP PIN PARALLEL CAPACITOR (CTHP) COMP PIN RESISTOR (RTH) COMP PIN CAPACITOR (CTH) FEED- FORWARD CAPACITOR (CFF) PEAK- PEAK DEVIATION (VPK-PK) SETTLING TIME (tSETTLE) CTRL LOOP BAND- WIDTH (BW) CTRL LOOP PHASE MARGIN (PM) LOAD STEP (A) LOAD STEP SLEW RATE RFB (kΩ) FREQ (kHz) ±3% (<60mV) 12V 1V 150µF 22µF × 2 470µF × 6 100µF × 4 33pF 12.0kΩ 3300pF 47pF 47mV 30µs 70kHz 57 Deg 25 10A/µs 90.9 500 ±3% (<72mV) 12V 1.2V 150µF 22µF × 2 470µF × 6 100µF × 4 33pF 12.0kΩ 3300pF 47pF 48mV 30µs 67kHz 65 Deg 25 10A/µs 60.4 500 ±3% (<90mV) 12V 1.5V 150µF 22µF × 2 470µF × 6 100µF × 4 68pF 10.2kΩ 3300pF None 56mV 40µs 50kHz 49 Deg 25 10A/µs 40.2 600 ±3% (<108mV) 12V 1.8V 150µF 22µF × 2 470µF × 6 100µF × 4 82pF 14.5kΩ 3300pF None 58mV 50µs 51kHz 46 Deg 25 10A/µs 30.2 600 *Bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads.

Figure 14. 0.9V Output Power Figure 15. 1.5V Output Power Figure 16. 5V to 0.9V

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Figure 17. 12V to 0.9V Figure 18. 5V to 0.9V Derating Figure 19. 12V to 0.9V Derating

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Figure 20. 5V to 1.5V Derating Figure 21. 12V to 1.5V

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Figure 22. 5V to 1.5V Derating Figure 23. 12V to 1.5V

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Figure 24. Typical 4.5VIN to 15VIN, 1.5V and 1.2V at 25A Outputs

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Figure 25. LTM4650-1 2-Phase, 1V at 50A Design Figure 26. 25%, 12.5A Load Step T ransient Figure 27. Bode Plot of Figure 23 Circuit

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Figure 28. LTM4650-1 1.2V and 1V Output T racking

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Figure 29. LTM4650-1 4-Phase, 1.2V at 100A

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46501fcFor more information www.linear .com/L TM4650-1 LTM4650-1 Component BGA Pinout package DescripTion PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT1 B1 V OUT1 C1 V OUT1 D1 GND E1 GND F1 GND A2 V OUT1 B2 V OUT1 C2 V OUT1 D2 GND E2 GND F2 GND A3 V OUT1 B3 V OUT1 C3 V OUT1 D3 GND E3 GND F3 GND A4 V OUT1 B4 V OUT1 C4 V OUT1 D4 GND E4 GND F4 MODE_PLLIN A5 V OUT1 B5 V OUT1 C5 V OUT1S D5 V FB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 f SET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 V FB2 E7 COMP2 F7 SGND A8 V OUT2 B8 V OUT2 C8 V OUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 V OUT2 B9 V OUT2 C9 V OUT2 D9 GND E9 DIFFN F9 RUN2 A10 V OUT2 B10 V OUT2 C10 V OUT2 D10 GND E10 GND F10 GND A11 V OUT2 B11 V OUT2 C11 V OUT2 D11 GND E11 GND F11 GND A12 V OUT2 B12 V OUT2 C12 V OUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 V IN K2 V IN L2 V IN M2 V IN G3 GND H3 GND J3 V IN K3 V IN L3 V IN M3 V IN G4 PHASEMD H4 GND J4 V IN K4 V IN L4 V IN M4 V IN G5 CLKOUT H5 GND J5 GND K5 GND L5 V IN M5 V IN G6 SGND H6 GND J6 TEMP K6 GND L6 V IN M6 V IN G7 SGND H7 GND J7 EXTV CC K7 GND L7 V IN M7 V IN G8 PGOOD2 H8 INTV CC J8 GND K8 GND L8 V IN M8 V IN G9 PGOOD1 H9 GND J9 V IN K9 V IN L9 V IN M9 V IN G10 GND H10 GND J10 V IN K10 V IN L10 V IN M10 V IN G11 SW2 H11 GND J11 V IN K11 V IN L11 V IN M11 V IN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND

46501fc For more information www.linear .com/L TM4650-1 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion Please refer to http://www.linear.com/product/LTM4650-1#packaging for the most recent package drawings. 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1523 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 1215 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 L K J H G F E D C BM A SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

46501fcFor more information www.linear .com/L TM4650-1

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 05/16 Added SnPb Ball Finish 1, 2 B 07/16 Added LTM4650-1A Connected COMP pin of Master and Slave devices 1, 2, 3, 4, 10 C 12/16 Corrected Part Marking and Finished Code 2

46501fc For more information www.linear .com/L TM4650-1  LINEAR TECHNOLOGY CORPORATION 2016 LT 1216 REV C • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4650-1 relaTeD parTs package phoTo Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. BGA PART NUMBER DESCRIPTION COMMENTS LTM4650 LTM4650-1 with Internal Compensation 4.5V ≤ VIN ≤ 15V, Dual 25A or Single 50A LTM4630 Lower Current than LTM4650; Dual 18A or Single 36A Pin Compatible with LTM4650; 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 15mm × 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages LTM4630A Lower Current and Higher VOUT than LTM4650; Up to 5.3VOUT, Dual 18A or Single 26A Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm LGA Package LTM4630-1 Lower Current than LTM4650 with External Compensation and ±0.8% (–1A) or ±1.5% (–1B) VOUT Accuracy Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 15mm × 15mm × 5.01mm BGA Package LTM4620 Lower Current than LTM4650; Dual 13A or Single 26A. Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V, 15mm 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages LTM4620A Lower Current and Higher VOUT than LTM4650; Up to 5.3VOUT, Dual 13A or Single 26A. Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V, 15mm 15mm × 4.41mm LGA and 15mm × 15mm × 5.01mm BGA Packages LTM4628 Lower Current, Higher VIN and VOUT than LTM4650; Dual 8A or Single 16A Pin Compatible with LTM4650; 4.5V ≤ VIN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V, 15mm 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA Packages

Summary

Dual 25A or Single 50A 關Module Regulator with 0.8% DC and 3% Transient Accuracy

Description

Dual 25A or Single 50A 關Module Regulator with 0.8% DC and 3% Transient Accuracy

Source title LTM4630A Datasheet(PDF) - Linear Technology

Read LTM4630A online.

LTM4650-1 LINER | Alldatasheet

Document overview

Technical content

DescripTion

5.01 BGA package, with SnPb (BGA) or RoHS

FeaTures

applicaTions

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elecTrical characTerisTics

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4 PARALLELED OUTPUTS

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7 PACKAGE ROW AND COLUMN LABELING MAY VARY

revision hisTory

LTM4630A specifications and overview.

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