LTM4630 LINER | Alldatasheet
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Technical content
For more information www.linear .com/L TM4630 TYPICAL APPLICATION
DESCRIPTION
DC/DC µModule Regulator The LT M®4630 is a dual 18A or single 36A output switching mode step-down DC/DC µModule® (micromodule) regula- tor . Included in the package are the switching controllers, power FETs, inductors, and all supporting components. Operating from an input voltage range of 4.5V to 15V , the L TM4630 supports two outputs each with an output voltage range of 0.6V to 1.8V , each set by a single external resistor . Its high efficiency design delivers up to 18A continuous current for each output. Only a few input and output ca - pacitors are needed. The L TM4630 is pin compatible with the LTM4620 and L TM4620A (dual 13A, single 26A) and the L TM4628 (dual 8A, single 16A). The device supports frequency synchronization, multi - phase operation, Burst Mode operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode ar chitecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcurrent protection. The L TM4630 is offered in 16mm × 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm BGA packages. The L TM4630 is ROHS compliant.
FEATURES
APPLICATIONS
n Dual 18A or Single 36A Output n Wide Input Voltage Range: 4.5V to 15V n Output Voltage Range: 0.6V to 1.8V n ±1.5% Maximum Total DC Output Error Over Line, Load and T emperature n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Adjustable Switching Frequency n Overcurrent Foldback Protection n Multiphase Parallel Current Sharing with Multiple L TM4630s Up to 144A n Frequency Synchronization n Internal Temperature Monitor n Pin Compatible with the L TM4620 and L TM4620A (Dual 13A, Single 26A) and L TM4628 (Dual 8A, Single 16A) n Selectable Burst Mode® Operation n Soft-Start/Voltage T racking n Output Overvoltage Protection n 16mm × 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm BGA Packages n Telecom and Networking Equipment n Storage and ATCA Cards n Industrial Equipment L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. 36A, 1.2V Output DC/DC µModule Regulator
4630 TA01a
f SET 470µF 6.3V 60.4k 100µF 6.3V PHASMD V OUT1 VOUTS1 SW1 VFB1 VFB2 COMP1 COMP2 VOUTS2 VOUT2 SW2 PGOOD2 PGOOD MODE_PLLIN CLKOUT INTV CC EXTVCC PGOOD1 PGOOD 10k SGND GND DIFFP DIFFN DIFFOUT 470µF 6.3V 100µF 6.3V 121k 10k 5.1V 120k 0.1µF 22µF 25V 4.7µF INTVCC VOUT 1.2V 36A V IN 4.5V TO 15V 1.2VOUT Efficiency vs IOUT OUTPUT CURRENT (A) EFFICIENCY (%) 10 12 14 16 182 4 6
4630 TA01b
VIN = 5V VIN = 12V
For more information www.linear .com/L TM4630 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, 0.3V to INTVCC (Note 1) LGA PACKAGE 144-LEAD (16mm × 16mm × 4.41mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VIN VOUT2GND GND VOUT1 SGND GND TJMAX = 125°C, ΘJA = 7°C/W , ΘJCbottom = 1.5°C/W , ΘJCtop = 3.7°C/W , ΘJB + ΘJBA ≅ 7°C/W Θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.2g BGA PACKAGE 144-LEAD (16mm × 16mm × 4.41mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VOUT2GND GND SGND GND TJMAX = 125°C, ΘJA = 7°C/W , ΘJCbottom = 1.5°C/W , ΘJCtop = 3.7°C/W , ΘJB + ΘJBA ≅ 7°C/W Θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.2g INT Internal Operating Temperature Range Storage T 55°C to 125°C PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE L TM4630EV#PBF Au (RoHS) L TM4630V e4 LGA 3 –40°C to 125°C L TM4630IV#PBF Au (RoHS) L TM4630V e4 LGA 3 –40°C to 125°C L TM4630EY#PBF SAC305 (RoHS) L TM4630Y e1 BGA 3 –40°C to 125°C L TM4630IY#PBF SAC305 (RoHS) L TM4630Y e1 BGA 3 –40°C to 125°C L TM4630IY SnPb (63/37) L TM4630Y e0 BGA 3 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.
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For more information www.linear .com/L TM4630 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 15 V VOUT Output Voltage l 0.6 1.8 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 1 Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V , IOUT = 0A to 18A l 1.477 1.5 1.523 V Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 22µF ×3, CSS = 0.01µF , COUT = 100µF ×3, VOUT1 = 1.5V , VOUT2 = 1.5V , VIN = 12V 1 A IQ(VIN) Input Supply Bias Current V IN = 12V , VOUT = 1.5V , Burst Mode Operation VIN = 12V , VOUT = 1.5V , Pulse-Skipping Mode VIN = 12V , VOUT= 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA µA I S(VIN) Input Supply Current VIN = 5V , VOUT = 1.5V , IOUT = 18A VIN = 12V , VOUT = 1.5V , IOUT = 18A 2.6 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 7) 0 18 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V , VIN from 4.5V to 15V IOUT = 0A for Each Output, l 0.01 0.025 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, V OUT = 1.5V , 0A to 18A VIN = 12V (Note 7) l 0.5 0.75 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/ X7R/Ceramic, 470µF POSCAP , VIN = 12V , VOUT = 1.5V , Frequency = 450kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V , VOUT = 1.5V , fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range 400 780 kHz ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP , VOUT = 1.5V , IOUT = 0A VIN = 12V 10 mV tSTART (Each Channel) Turn-On T ime COUT = 100µF/X5R/Ceramic, 470µF POSCAP , No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP VIN = 12V , VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V IN = 12V , COUT = 100µF , 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V , VOUT = 1.5V 30 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.606 V IFB (Note 6) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V TRACK1 (I), TRACK2 (I) T rack Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.25 1.5 µA
For more information www.linear .com/L TM4630 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 23. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS UVLO Undervoltage Lockout (Falling) 3.3 V UVLO Hysteresis 0.6 V tON(MIN) Minimum On-Time (Note 6) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 15V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 220 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz Frequency Low Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz Frequency High Highest Frequency fSET > 2.4V , Up to INTVCC 700 780 860 kHz fSET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTV CC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output V oltage 0.2 V V Differential Amplifier A V Differential Amplifier Gain 1 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V , IDIFFOUT = 100µA 3 mV PSRR Differential Amplifier Power Supply Rejection Ratio 5V < V IN < 15V 90 dB ICL Maximum Output Current 3 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l –2.2 mV/C
For more information www.linear .com/L TM4630
ELECTRICAL CHARACTERISTICS
TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode and Pulse-Skip Mode Efficiency VIN=12V , VOUT = 1.2V , fS = 450kHz 1V Single Phase Output Load Transient Response 1.2V Single Phase Output Load Transient Response Efficiency vs Output Current, V IN = 5V , fS = 450kHz Efficiency vs Output Current, V IN = 12V , fS = 450kHz Dual Phase Single Output Efficiency vs Output Current, V IN = 12V , fS = 450kHz LOAD CURRENT (A) EFFICIENCY (%) 100 10 12 14 16 182 4 6
4630 G01
VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1V LOAD CURRENT (A) EFFICIENCY (%) 10 12 14 16 182 4 6
4630 G02
VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1V LOAD CURRENT (A) EFFICIENCY (%) 20 25 30 35 405 10
4630 G03
VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 1V LOAD CURRENT (A) 0.01 EFFICIENCY (%) 100 1 100.1
4630 G04
20µs/DIV VOUT(AC) 50mV/Div LOAD STEP 2A/DIV
4630 G05
12VIN, 1VOUT, 450kHz, 4.5A LOAD STEP, 4.5A/µs STEP-UP AND STEP-DOWN COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC 20µs/DIV VOUT(AC) 50mV/Div LOAD STEP 2A/DIV
4630 G06
12VIN, 1.2VOUT, 450kHz, 4.5A LOAD STEP, 4.5A/µs STEP-UP AND STEP-DOWN C OUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4630 is tested under pulsed load conditions such that T J ≈ TA. The L TM4630E is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4630I is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 400kHz to 750kHz. Note 5: L TM4630 device is designed to operate from 400kHz to 750kHz Note 6: These parameters are tested at wafer sort. Note 7: See output current derating curves for different V IN, VOUT and TA.
For more information www.linear .com/L TM4630 TYPICAL PERFORMANCE CHARACTERISTICS Single Phase Short Circuit Protection with 18ASingle Phase Start-up with 18A Single Phase Short Circuit Protection with No load 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div
4630 G10
12VIN, 1.2VOUT, 450kHz COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC, CSS = 0.1µF 50µs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div
4630 G11
12VIN, 1.2VOUT, 450kHz COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC 50µs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div
4630 G12
12VIN, 1.2VOUT, 450kHz COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC 1.5V Single Phase Output Load Transient Response 1.8V Single Phase Output Load Transient Response Single Phase Start-Up with No load 20µs/DIV VOUT(AC) 50mV/Div LOAD STEP 2A/DIV
4630 G07
12VIN, 1.5VOUT, 450kHz, 4.5A LOAD STEP, 4.5A/µs STEP-UP AND STEP-DOWN COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC 20µs/DIV VOUT(AC) 50mV/Div LOAD STEP 2A/DIV
4630 G08
12VIN, 1.8VOUT, 450kHz, 4.5A LOAD STEP, 4.5A/µs STEP-UP AND STEP-DOWN C OUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 0.2A/Div
4630 G09
12VIN, 1.2VOUT, 450kHz COUT = 1 470µF 4V POSCAP + 1 100µF 6.3V CERAMIC, CSS = 0.1µF
For more information www.linear .com/L TM4630 PIN FUNCTIONS VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 4. See Note 8 in the Electrical Characteristics section for output current guideline. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. V OUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance di - rectly between these pins and GND pins. Review Table 4. See Note 8 in the Electrical Characteristics section for output current guideline. V OUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the V OUTS pins is connected to the DIFFOUT pin in remote sensing or directly to V OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. f SET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the ap- plication. See layout guidelines in Figure 22. V FB1, V FB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is con - nected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor . Different output voltages can be programmed with an additional resistor between V FB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier . This pin is connected to the remote sense point of the output voltage. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier . This pin is connected to the remote sense point of the output GND. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .
For more information www.linear .com/L TM4630 PIN FUNCTIONS RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan- nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation connect one of the V OUTS pin to DIFFOUT for remote sensing. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTV CC, or float- ing this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 (G9, G8): Output Voltage Power Good Indicator . Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. INTV CC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTV CC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Onboard General Purpose Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTV CC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V . Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V . An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. V IN must be applied before EXTVCC, and EXTVCC must be removed before VIN. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. (Recommended to Use Test Points to Monitor Signal Pin Connections.)
TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified L TM4630 Block Diagram
For more information www.linear .com/L TM4630 OPERATION Power Module Description The L TM4630 is a dual-output standalone nonisolated switching mode DC/DC power supply. It can provide two 18A outputs with few external input and output capacitors and setup components. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 1.8VDC over 4.5V to 15V input voltages. The typical application schematic is shown in Figure 23. The L TM4630 has dual integrated constant-frequency cur- rent mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 500kHz. For switching-noise sensitive applications, it can be externally synchronized from 400kHz to 780kHz. A resistor can be used to program a free run frequency on the FSET pin. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4630 module has sufficient stabil- ity margins and good transient per formance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator . See the Applications Information section. The L TM4630 is internally compensated to be stable over all operating conditions. Table 4 provides a guide line for input and output capacitances for several operating conditions. The Linear Technology µModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. Multiphase operation can be easily employed with the MODE_PLLIN, PHASMD, and CLKOUT pins. Up to 12 phases can be cascaded to run simultaneously with re - spect to each other by programming the PHASMD pin to different levels. See the Applications Information section. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping opera- tion using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the T ypical Performance Characteristics section. See the Applications Information section for details. A general purpose temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. The switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details.
mined by the maximum load current and output voltage. for particular applications. down ratio that can be achieved for a given input voltage. capability related to high duty cycle on the top side switch. where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. The PWM controller has an internal 0.6V reference voltage. to their respective outputs for proper feedback regulation. Table 1. VFB Resistor Table vs Various Output Voltages back setting resistor can be used for the parallel design. one programming resistor as shown in Figure 2. Figure 2. 4-Phase Parallel Configurations
4630 F02
4 PARALLELED OUTPUTS
For more information www.linear .com/L TM4630 APPLICATIONS INFORMATION Input Capacitors The L TM4630 module should be connected to a low ac- impedance DC source. For the regulator input four 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: D = VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D • 1 − D( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , Polymer capacitor . Output Capacitors The L TM4630 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , the low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 200µF to 470µF . Additional output filtering may be required by the system designer , if further reduction of output ripples or dynamic transient spikes is required. Table 4 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4.5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 4 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduc- tion as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from V OUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from V OUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The L TM4630 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate intermit- tently based on load demand, thus saving quiescent cur- rent. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’ s average current is greater than the load requirement. As the COMP voltage drops below 0.5V , the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, caus- ing COMP to rise above 0.5V , the internal sleep line goes low, and the L TM4630 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation.
For more information www.linear .com/L TM4630 APPLICATIONS INFORMATION Pulse-Skipping Mode Operation In applications where low output ripple and high effi - ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4630 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. T ying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the L TM4630’s output voltage is in regulation. Either regulator can be configured for force continuous mode. Multiphase Operation For output loads that demand more than 18A of current, two outputs in L TM4630 or even multiple L TM4630s can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the L TM4630 to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked-loop allows the L TM4630 to lock onto incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTV CC, SGND, or (floating) generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively . A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each L TM4630 chan- nel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. The RMS input ripple current is reduced by , and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The L TM4630 device is an inherently current mode con - trolled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 26 shows an example of parallel operation and pin connection. Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancel- lation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 4 shows this graph. Frequency Selection and Phase-Lock Loop (MODE_PLLIN and fSET Pins) The L TM4630 device is operated over a range of frequencies to improve power conversion efficiency. It is recommended to operate the module at 500kHz over the output range for the best efficiency and inductor current ripple The L TM4630 switching frequency can be set with an external resistor from the f SET pin to SGND. An accurate 10µA current source into the resistor will set a voltage that programs the frequency or a DC voltage can be
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
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Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
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180 PHASE0 PHASE
90 DEGREE
270 PHASE90 PHASE
60 DEGREE 60 DEGREE
240 PHASE60 PHASE
300 PHASE120 PHASE
in continuous mode while being externally clock. set resistor for free run operation. good rule of thumb is to keep on-time longer than 110ns. VTRACK is the track ramp applied to the slave’s track pin. in Figure 6 will be equal to the RFB for coincident tracking. Figure 7 shows the coincident tracking waveforms. Figure 5. Operating Frequency vs fSET Pin Voltage
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and the gate charge required turning on the top MOSFET .
Figure 7. Output Coincident T racking Waveform Figure 6. Example of Output T racking Application Circuit
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- PULL-UP RESISTOR AND ZENER ARE OPTIONAL.
will control output regulation from the feedback divider .
For more information www.linear .com/L TM4630 APPLICATIONS INFORMATION SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: ZL = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Temperature Monitoring A diode connected PNP transistor is used for the TEMP monitor function by monitoring its voltage over tempera- ture. The temperature dependence of this diode voltage can be understood in the equation: VD = nVT ln ID IS where VT is the thermal voltage (kT/q), and n, the ideality factor , is 1 for the diode connected PNP transistor be- ing used in the L TM4630. IS is expressed by the typical empirical equation: IS = I0 exp –VG0 VT where I0 is a process and geometry dependent current, (I0 is typically around 20k orders of magnitude larger than IS at room temperature) and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero or –273°C. If we take the IS equation and substitute into the VD equa- tion, then we get: VD = VG0 – kT q ln I0 ID , VT = kT q The expression shows that the diode voltage decreases (linearly if I0 were constant) with increasing temperature and constant diode current. Figure 6 shows a plot of V D vs Temperature over the operating temperature range of the L TM4630. If we take this equation and differentiate it with respect to temperature T , then: dVD dT = – VG0 – VD T This dVD/dT term is the temperature coefficient equal to about –2mV/K or –2mV/°C. The equation is simplified for the first order derivation. Solving for T , T = –(V G0 – V D)/(dVD/dT) provides the temperature. 1st Example: Figure 8 for 27°C, or 300K the diode voltage is 0.598V , thus, 300K = –(1200mV – 598mV)/ –2.0 mV/K) 2nd Example: Figure 8 for 75°C, or 350K the diode voltage is 0.50V , thus, 350K = –(1200mV – 500mV)/ –2.0mV/K)
Kelvin temp and subtracting 273 from it. temperature will provide a general temperature monitor . rent to 100µA. See Figure 24 for an example. thermal performance to one’s own application. air” although natural convection causes the air to move. an actual application or viable operating condition.
- θJCbottom, the thermal resistance from junction to the
dissipation flowing through the bottom of the package. the heat flows from the junction to the top of the part. generally match the user’s application. Figure 8. Diode Voltage VD vs Temperature T(K)
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Package Thermal Information”).
- θJB, the thermal resistance from junction to the printed
two layer board. This board is described in JESD 51-9. resistances are external to the µModule. Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
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Figure 12. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads)
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Table 2. 1.0V Output Table 3. 1.5V Output
Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values
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Figure 16. 5V to 1V Derating Figure 17. 12V to 1V Derating Figure 18. 5V to 1V Derating Figure 19. 12V to 1.5V Derating Figure 20. 5V to 1.5V Derating Figure 21. 12V to 1.5V Derating Figure 22. 5V to 1.5V Derating
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Figure 23. Typical 4.5VIN to 15VIN, 1.5V and 1.2V at 18A Outputs
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Figure 24. L TM4630 2-Phase, 1.5V at 36A Design
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Figure 25. L TM4630 1.2V and 1V Output T racking
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Figure 26. L TM4630 4-Phase, 1.2V at 70A
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For more information www.linear .com/L TM4630 L TM4630 Component LGA and BGA Pinout PACKAGE DESCRIPTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 f SET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2 A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN G4 PHASEMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND
For more information www.linear .com/L TM4630 PACKAGE DESCRIPTION Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. 144-Lead (16mm × 16mm × 4.41mm) (Reference L TC DWG # 05-08-1901 Rev B) DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G LGA 144 0213 REV B TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” SYMBOL A b D E e F G aaa bbb eee MIN 4.31 0.60 0.36 3.95 NOM 4.41 0.63 16.0 16.0 1.27 13.97 13.97 0.41 4.00 MAX 4.51 0.66 0.46 4.05 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 144 DETAIL A DIA 0.630 PAD 1 L K J H G F E D C BM A SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 SQ. 143x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A 0.630 ±0.025 SQ. 143x S Y XZ Ø eee 3x, C (0.22 x45°) SEE NOTES
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y L TMXXXXXX µModule
For more information www.linear .com/L TM4630 PACKAGE DESCRIPTION Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1969 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 0114 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 A B C D E F G HK JL M SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES
For more information www.linear .com/L TM4630 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 03/14 Added BGA package 1, 2, 32
For more information www.linear .com/L TM4630 LINEAR TECHNOLOGY CORPORATION 2013 LT 0314 REV A • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4630 RELATED PARTS PACKAGE PHOTO DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
- Selector Guides
- Demo Boards and Gerber Files
- Free Simulation Tools Manufacturing:
- Quick Start Guide
- PCB Design, Assembly and Manufacturing Guidelines
- Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS L TM4620 Dual 13A Single 26A µModule Regulator Pin Compatible with L TM4630; 4.5V ≤ VIN ≤ 16V , 0.6V ≤ VOUT ≤ 2.5V , 15mm × 15mm × 4.32mm LTM4628 Dual 8A, Single 16A µModule Regulator Pin Compatible with L TM4630; 4.5V ≤ VIN ≤ 26.5V , 0.6V ≤ VOUT ≤ 5.5V , 15mm × 15mm × 4.32mm LTM4627 15A µModule Regulator 4.5V ≤ VIN ≤ 20V , 0.6V ≤ VOUT ≤ 5.5V , 15mm × 15mm × 4.32mm L TM4611 Ultralow VIN, 15A µModule Regulator 1.5V ≤ VIN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 15mm × 15mm × 4.32mm L TM4619 Dual 26VIN, 4A DC/DC µModule Regulator 4.5V ≤ V IN ≤ 26.5V; 0.8V ≤ VOUT ≤ 5V L TM4615 T riple Low VIN, 4A DC/DC µModule Regulator 2.375 ≤ V IN ≤ 5.5V; T wo 4A and One 1.5A Output L TM4616 Dual 8A, Low VIN, DC/DC µModule Regulator 2.7V ≤ V IN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V L TM8062/ L TM8062A 32V IN, 2A µModule Battery Charger with Maximum Peak Power T racking (MPPT) Adjustable VBATT Up to 14.4V (18.8V for the L TM8062A), C/10 or Timer Termination, 9mm × 15mm × 4.32mm LGA Package L TM8027 60VIN, 4A DC/DC Step-Down µModule Regulator 4.5V ≤ V IN ≤ 60V , 2.5V ≤ VOUT ≤ 24V , 15mm × 15mm × 4.32mm LGA Package L TM4613 EN55022B Compliant 36VIN, 8A Step-Down µModule Regulator 5V ≤ VIN ≤ 36V , 3.3V ≤ VOUT ≤ 15V , Synchronizable, Parallelable, 15mm × 15mm × 4.32mm LGA Package LGA BGA