LTM4618 LINER | Alldatasheet
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Technical content
DESCRIPTION
6A DC/DC µModule Regulator with Tracking and Frequency Synchronization The L TM®4618 is a complete 6A output switching mode DC/DC power supply in a 9mm × 15mm × 4.32mm LGA package. Included in the package are the switching con- troller , power FETs, inductor and all support components. Operating over an input voltage range of 4.5V to 26.5V , the L TM4618 supports an output voltage range of 0.8V to 5V set by a single external resistor . Its high effi ciency design delivers 6A continuous current (8A peak). Only a few input and output capacitors are needed. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrifi cing stability. The device supports frequency synchronization and output voltage tracking for supply rail sequencing. Burst Mode operation or pulse- skipping mode can be selected for light load operations. Fault protection features include overvoltage protection, overcurrent protection and foldback current limit for short-circuit protection. The L TM4618 is Pb-free and RoHS compliant. L, L T , L TC, L TM, Linear Technology, the Linear logo, Burst Mode and μModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2.5V/6A DC/DC Power μModule® with 6V to 26.5V Input
FEATURES
APPLICATIONS
n Complete Standalone Power Supply n Wide Input Voltage Range: 4.5V to 26.5V n 6A DC Typical, 8A Peak Output Current n 0.8V to 5V Output n Output Voltage T racking n ±1.75% Maximum Total DC Error n Current Mode Control/Fast T ransient Response n Phase-Lockable Fixed Frequency 250kHz to 780kHz n On-Board Frequency Synchronization n Selectable Burst Mode ® Operation n Power Good Voltage Indicator n Output Overvoltage Protection n Output Current Foldback Limiting n 9mm × 15mm × 4.32mm LGA Package n Telecom and Networking Equipment n Servers n Storage Cards n ATCA Cards n Industrial Equipment n Point of Load Regulation n Medical Systems Effi ciency and Power Loss vs Load Current LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 3.0 2.5 1.5 2.0 1.0 0.5
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12VIN TO 2.5VOUT 24VIN TO 2.5VOUT
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28.7k COUT VOUT 2.5V/6A 0.1μF CIN VIN 6V to 26.5V
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS MODE/PLLIN, TK/SS, CC Operating Junction Temperature Range (Note 1) BCDEFGHJKLA TK/SS COMP PGOODVFB INTVCC M LGA PACKAGE 84-LEAD (15mm s 9mm s 4.32mm) TOP VIEW VIN VOUT PGND SW EXTVCC FREQ RUN MODE/ PLLIN SGND/PGND ΘJA = 16°C/W , ΘJCtop = 15°C/W , ΘJCbottom = 4°C/W , WEIGHT = 2.3g, θJB + θBA = 16°C/W , θBA = BOARD-TO-AMBIENT RESISTANCE, θ VALUES DEFINED PER JESD51-12 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage (Note 5) l 4.5 26.5 V VOUT(DC) Output Voltage Total Variation with Line and Load CIN = 10μF ×2, RFB = 28.0kΩ COUT = 100μF ×3 X7R Ceramic MODE/PLLIN = 0V , V FREQ = 2.4V V IN = 6V to 26.5V , IOUT = 0A to 6A (Note 4) l 2.476 2.52 2.557 V Input Specifi cations VIN(UVLO) Undervoltage Lockout Thresholds V INTVCC Rising VINTVCC Falling 2.00 1.85 2.20 2.00 2.35 2.15 V V IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 10μF ×2, COUT = 100μF ×3 V OUT = 2.5V V IN = 12V V IN = 26.5V 0.3 0.2 A A LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4618EV#PBF L TM4618V 84-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C L TM4618IV#PBF L TM4618V 84-Lead (15mm × 9mm × 4.32mm) LGA –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ ORDER INFORMATION ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C (Note 2), VIN = 12V , per typical application in Figure 21.
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C (Note 2), VIN = 12V , per typical application in Figure 21. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current V IN = 12V, VOUT = 2.5V, IOUT = 0A VIN = 26.5V, VOUT = 2.5V, IOUT = 0A Shutdown, RUN = 0, VIN = 26.5V mA mA μA I S(VIN) Input Supply Current V IN = 12V, VOUT = 2.5V, IOUT = 6A VIN = 26.5V, VOUT = 2.5V, IOUT = 6A 1.430 0.675 A A INTVCC Internal VCC Voltage V IN = 12V, VRUN > 2V, No Load 4.8 5 5.2 V VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive l 4.5 4.7 V VLDO External EXTV CC Voltage Drop INTV CC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC Hysteresis EXTV CC Hysteresis 200 mV Output Specifi cations I OUT(DC) Output Continuous Current Range V IN = 12V, VOUT = 2.5V (Note 4) 0 6 A ΔVOUT(LINE) VOUT Line Regulation Accuracy V OUT = 2.5V, VIN from 6V to 26.5V IOUT = 0A l 0.02 0.04 %/V ΔVOUT(LOAD) VOUT Load Regulation Accuracy V IN = 12V, VOUT = 2.5V, 0 to 6A (Note 4) l 0.3 0.6 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100μF ×3 X5R Ceramic V IN = 12V, VOUT = 2.5V V IN = 26.5V, VOUT = 2.5V mV mV fS Output Ripple Voltage Frequency I OUT = 2A, VIN = 12V , VOUT = 2.5V , VFREQ = INTVCC 780 kHz ΔVOUT(START) Turn-On Overshoot COUT = 100μF ×3 X5R Ceramic VOUT = 2.5V, IOUT = 0A V IN = 12V V IN = 26.5V mV mV tSTART Turn-On Time COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V, IOUT = 0A, TK/SS Capacitor = 0.01μF V IN = 12V V IN = 26.5V 0.75 0.70 ms ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% of Full Load COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V V IN = 12V 15 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% of Full Load COUT = 100μF ×3 X5R Ceramic, VOUT = 2.5V V IN = 12V 10 μs IOUT(PK) Output Current Limit COUT = 100μF ×3 X5R Ceramic V IN = 6V, VOUT = 2.5V V IN = 26.5V, VOUT = 2.5V A A Control Section VFB Error Amplifi er Feedback Voltage I OUT = 0A, VOUT = 2.5V l 0.792 0.788 0.8 0.8 0.808 0.808 V V IFB Error Amplifi er Feedback Current (Note 3) –10 –50 nA VOVL Feedback Voltage Lockout Measured at V FB 0.84 0.86 0.88 V ITK/SS Soft-Start Charge Current V TK/SS = 0V 0.9 1.3 1.7 μA DFMAX Maximum Duty Factor In Dropout (Note 3) 97 % tON(MIN) Minimum On-Time (Note 3) 90 ns fNOM Nominal Frequency V FREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency V FREQ = 0V 210 250 290 kHz
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fHIGH Highest Frequency V FREQ ≥ 2.4V , INTVCC 700 780 860 kHz VIH(MODE/PLLIN) Synchronous Clock High Level 2.0 V VIL(MODE/PLLIN) Synchronous Clock Low Level 0.8 V RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ IFREQ FREQ Pin Sinking Current Sourcing Current f MODE/PLLIN > fOSC fMODE/PLLIN < fOSC –13 μA μA VRUN RUN Pin On Threshold RUN Rising 1.1 1.22 1.35 V VRUN Hysteresis RUN Pin Hysteresis 120 mV RFBHI Resistor Between VOUT and VFB Pins 60.1 60.4 60.7 kΩ PGOOD Output V PGL PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current V PGOOD = 5V ±2 μA VPG PGOOD T rip Level V FB with Respect to Set Regulated Voltage V FB Ramping Negative V FB Ramping Positive –7.5 7.5 –10 The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C (Note 2), VIN = 12V , per typical application in Figure 21. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4618 is tested under pulsed load conditions such that T J ≈ TA. The L TM4618E is guaranteed to meet performance specifi cations over the 0°C to 125°C operating junction temperature range. Specifi cations over the full –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4618I is guaranteed to meet specifi cations over the full operating junction temperature range. Note that the maximum ambient temperature consistent with these specifi cations is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at wafer level only. Note 4: See Output Current Derating curves for different V IN, VOUT and TA. Note 5: For input voltages less than 6V , tie the VIN, INTVCC and EXTVCC together . The L TM4618 will operate from 5V inputs, but VIN, INTVCC and EXTVCC need to be tied together .
TYPICAL PERFORMANCE CHARACTERISTICS 2.5V T ransient Response 3.3V T ransient Response 5V T ransient Response Effi ciency vs Load Current with Different Mode Settings (12V to 3.3V) 1.2V T ransient Response 1.5V T ransient Response Effi ciency vs Load Current with IN (CCM) Effi ciency vs Load Current with 12VIN (CCM) Effi ciency vs Load Current with 24VIN (CCM) LOAD CURRENT (A) EFFICIENCY (%) 100
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5V TO 0.8VOUT 5V TO 1.2VOUT 5V TO 1.5VOUT 5V TO 2.5VOUT 5V TO 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 100
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12V TO 1.2VOUT 12V TO 1.5VOUT 12V TO 2.5VOUT 12V TO 3.3VOUT 12V TO 5VOUT LOAD CURRENT (A) EFFICIENCY (%)
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24V TO 2.5VOUT 24V TO 3.3VOUT 24V TO 5VOUT LOAD CURRENT (A) 0.01 EFFICIENCY (%) 100
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10.1 BURST PULSE SKIP CCM VIN = 12V VOUT = 3.3V IOUT 1A/DIV VOUT 50mV/DIV
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50μs/DIV VIN = 12V AND VOUT = 1.2V AT 3A/μs LOAD STEP COUT = 2s 22μF 6.3V CERAMIC CAPACITOR 1s 100μF 6.3V CERAMIC CAPACITOR 1s 220μF SANYO POSCAP VOUT 50mV/DIV IOUT 1A/DIV
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50μs/DIV VIN = 12V AND VOUT = 1.5V AT 3A/μs LOAD STEP COUT = 2s 22μF 6.3V CERAMIC CAPACITOR 1s 100μF 6.3V CERAMIC CAPACITOR 1s 220μF SANYO POSCAP VOUT 50mV/DIV IOUT 1A/DIV
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50μs/DIV VIN = 12V AND VOUT = 2.5V AT 3A/μs LOAD STEP COUT = 2s 22μF 6.3V CERAMIC CAPACITOR 1s 100μF 6.3V CERAMIC CAPACITOR 1s 220μF SANYO POSCAP VOUT 50mV/DIV IOUT 1A/DIV
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50μs/DIV VIN = 12V AND VOUT = 3.3V AT 3A/μs LOAD STEP COUT = 2s 22μF 6.3V CERAMIC CAPACITOR 1s 100μF 6.3V CERAMIC CAPACITOR 1s 220μF SANYO POSCAP VOUT 100mV/DIV IOUT 1A/DIV
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50μs/DIV VIN = 12V AND VOUT = 5V AT 3A/μs LOAD STEP COUT = 2s 22μF 6.3V CERAMIC CAPACITOR 1s 100μF 6.3V CERAMIC CAPACITOR 1s 220μF SANYO POSCAP
Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 6A VOUT 1V/DIV IIN 1A/DIV
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100μs/DIV VIN = 12V AND VOUT = 2.5V COUT = 2s 22μF 6.3V CERAMIC, 1s 100μF 6.3V CERAMIC AND 1s 220μF SANYO POSCAP VOUT 1V/DIV IIN 1A/DIV
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100μs/DIV VIN = 12V AND VOUT = 2.5V COUT = 2s 22μF 6.3V CERAMIC, 1s 100μF 6.3V CERAMIC AND 1s 220μF SANYO POSCAP TYPICAL PERFORMANCE CHARACTERISTICS Start-Up, IOUT = 0A Start-Up, I OUT = 6A VOUT 1V/DIV IIN 0.2A/DIV
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VIN = 12V AND VOUT = 2.5V COUT = 2s 22μF 6.3V CERAMIC, 1s 100μF 6.3V CERAMIC AND 1s 220μF SANYO POSCAP CSOFT-START = 0.1μF VOUT 1V/DIV IIN 0.5A/DIV
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VIN = 12V AND VOUT = 2.5V COUT = 2s 22μF 6.3V CERAMIC, 1s 100μF 6.3V CERAMIC AND 1s 220μF SANYO POSCAP CSOFT-START = 0.1μF
NC (A1): No Connect. Leave fl oating. FREQ (A2): Frequency Selection Pin. An internal low pass fi lter is tied to this pin. The frequency can be selected from 250kHz to 780kHz by setting a voltage from this pin to SGND. A programming resistor divider can be used to set the operating frequency. See the Applications Information section. MODE/PLLIN (A3): Mode Selection or External Synchroni- zation Pin. Tying this pin to INTV CC enables pulse-skipping operation. Tying this pin low enables forced continuous mode operation. Burst Mode operation is enabled by fl oat- ing the pin. A clock on the pin will force the controller into forced continuous mode of operation and synchronize to the internal oscillator . The programming DC voltage has to be removed for clock synchronization. PGND (BANK 2: A4, B4, D4-D7, E1-E7, F1-F7, G1-G7, H1-H7, J5-J7, K5, K7, L5-L7, M5-M7): Power ground pins for both input and output returns. V IN (BANK 1: A5-A7, B5-B7, C5-C7): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. TK/SS (B1): Output Voltage T racking and Soft-Start Pin. An internal soft-start current of 1.3μA charges the soft-start capacitor . See the Applications Information section. RUN (B2): Run Control Pin. A voltage above 1.35V on this pin turns on the module. Forcing this pin below 1.1V will shut down the output. The RUN pin has a 1μA pull- up current source that increases to 10μA as the RUN pin voltage reaches 1.5V and up to compliance. Therefore the pin can be left fl oating for normal operation. A maximum of 6V can be applied to the pin. A voltage divider can be used for a UVLO function. See the Applications Informa- tion section. SGND (B3, C2 and C3): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to PGND. See applications for details. COMP (C1): Current control threshold and error ampli- fi er compensation point. The module has been internally compensated for most I/O ranges. EXTV CC (C4): External Voltage Input. Bypasses the internal INTVCC LDO and powers the internal circuitry and MOSFET drivers. If a 5V source is available, the internal LDO is disabled, and the power dissipation is lower , especially at higher input voltages. See the Applications Information section. V FB (D1): The negative input of the error amplifi er . Inter- nally, this pin is connected to VOUT with a 60.4kΩ precision resistor . Different output voltages can be programmed with an additional resistor between V FB and SGND pins. See applications for details. PGOOD (D2): Output Voltage Power Good Indicator . Open- drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. INTV CC (D3): Internal 5V Regulator Output. This pin is for additional decoupling of the 5V internal regulator . VOUT (BANK 3: J1-J4, K1-K4, L1-L4, M1-M4): Power Out- put Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. SW (K6): Switching Node of the Circuit. This pin is used to check the switching frequency. Leave pin fl oating. A resistor-capacitor snubber can be placed from SW to PGND to eliminate high frequency switch node ringing. See the Applications Information section. PIN FUNCTIONS BCDEFGHJKLAM BANK 1 VIN SGND/PGND CNTRL BANK 3 SW BANK 2 PGND VOUT
Figure 1. Simplifi ed L TM4618 Block Diagram
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TA = 25°C. Use Figure 1 confi guration.
The L TM4618 is a standalone non-isolated switching mode DC/DC power supply. It can deliver up to 6A (DC current) output with few external input and output capacitors. This module provides precisely regulated output voltages pro- grammable via external resistors from 0.8VDC to 5.0VDC over 4.5V to 26.5V input voltages. The typical application schematic is shown in Figure 21. For ≤6V inputs, connect V IN, INTVCC and EXTVCC together . The L TM4618 has an integrated constant frequency current mode regulator and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 750kHz. With current mode control and internal feedback loop compensation, the L TM4618 module has suffi cient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. Pull- ing the RUN pin below 1.1V forces the controller into its shutdown state, by turning off both MOSFETs. The TK/SS pin can be used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The L TM4618 is internally compensated to be stable over all operating conditions. The Linear Technology μModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. Multiphase operation can be easily employed with the synchronization control. High effi ciency at light loads can be accomplished with selectable Burst Mode or pulse-skipping mode operations using the MODE/PLLIN pin. Effi ciency graphs are provided for light load operation in the Typical Performance Char- acteristics section.
Figure 21. External component selection is primarily down ratio that can be achieved for a given input voltage. sections in this data sheet for the current restrictions. ON(MIN) is approximately 90ns, guardband to 110ns. The PWM controller has an internal 0.8V reference voltage. Table 1. VFB Resistor Table vs Various Output Voltages ductive leads, traces or not enough source capacitance. plication Note 77 explains the details.
meet the output voltage ripple and transient requirements. of implemented phases increases by N times. as shown in Figure 21. The typical frequency is 750kHz. respondingly larger ripple current and voltage ripple.
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Figure 3. Relationship Between Switching before the regulator’s inductor ripple current peaks.
Typical Applications section for synchronization examples. The L TM4618 minimum on-time is limited to about 90ns. slave’s feedback divider to implement coincident tracking. values for coincident or ratio tracking. Figure 4. Output Voltage Coincident T racking
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Figure 5. Coincident T racking Characteristics
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The module has already been internally compensated for all output voltages. The Linear Technology μModule Power Design Tool will be provided for other control loop optimization. RUN Pin The RUN pin has a 1μA pull-up current source that will enable the device in a fl oat condition. A voltage divider can be used to enable a UVLO function using the RUN pin. See Figure 21. Fault Conditions: Current Limit and Overcurrent Foldback The L TM4618 has a current mode controller , which inher- ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. To further limit current in the event of an overload condi- tion, the L TM4618 provides foldback current limiting. If the output voltage falls by more than 40%, then the maximum output current is progressively lowered to about 25% of its full current limit value. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Confi guration section of the data sheet are consistent with those param- eters defi ned by JESD51-9 and are intended for use with fi nite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a μModule package mounted to a hardware test board—also defi ned by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coeffi cients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the μModule regulator’s thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- fi guration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Confi guration section shows four thermal coef- fi cients explicitly defi ned in JESD 51-12; these coeffi cients are quoted or paraphrased below:
- θ JA, the thermal resistance from junction to ambi- ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defi ned test board, which does not refl ect an actual application or viable operating condition.
- θ JCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation fl owing through the bottom of the pack- age. In the typical μModule, the bulk of the heat fl ows out the bottom of the package, but there is always heat fl ow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application.
- θ JCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation fl owing through the top of the package. As the electrical connections of the typical μModule are on the bottom of the pack- age, it is rare for an application to operate such that most of the heat fl ows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test condi- tions don’t generally match the user’s application.
- θ JB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat fl ows through the bottom of the μModule and into the board, and
the package, using a two sided, two layer board. This board is described in JESD 51-9.
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Figure 6. Graphical Representation of JESD51-12 Thermal Coeffi cients
Figure 7. Power Loss at 1.5VOUT Figure 8. Power Loss at 3.3VOUT
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current or power with increasing ambient temperature. provided to protect each unit from catastrophic failure.
Figure 13. 12VIN to 3.3VOUT without Figure 14. 12VIN to 3.3VOUT with
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Figure 15. 24VIN to 3.3VOUT Figure 16. 24VIN to 3.3VOUT with
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Figure 11. 12VIN to 1.5VOUT Figure 12. 12VIN to 1.5VOUT with
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Figure 10. 5VIN to 1.5VOUT with
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Table 2. 1.5V Output Table 3. 3.3V Output Table 4. Output Voltage Response vs Component Matrix (Refer to Figure 21) 0A to 3A Load Step
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Figure 18. VIN 26.5V , VOUT 3.3V , IOUT 5A,
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Figure 19. VIN 26.5V , VOUT 3.3V , IOUT 5A,
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Figure 17. 6V to 26.5V Input, 3.3V at 6A Design,
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Figure 20. Recommended PCB Layout Example
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rupting the noise sensitive circuitry on the system board.
- Use large PCB copper areas for high current path, including V IN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
- Test points can be placed on signal pin for monitor- ing during testing.
- Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the unit.
- To minimize the via conduction loss and reduce mod- ule thermal stress, use multiple vias for interconnec- tion between top layer and other power layers.
- Do not put vias directly on the pad, unless they are capped.
- Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Figure 20 gives a good example of the recommended layout.
Figure 21. Typical 6V to 26.5V Input, 2.5V at 6A Design, 500kHz Operation
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Figure 22. T wo L TM4618 Parallel, 2.5V at 12A Design
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Figure 23. 4-Phase, Four Outputs (5V , 3.3V , 2.5V and 1.8V) with T racking
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(Arranged by Pin Function) PIN NAME PIN NAME PIN NAME PIN NAME N/C FREQ MODE/PLLIN PGND V IN VIN VIN V FB PGOOD INTVCC PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND V OUT VOUT VOUT VOUT PGND SW PGND TK/SS RUN SGND PGND V IN VIN VIN PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND V OUT VOUT VOUT VOUT PGND PGND PGND COMP SGND SGND EXTV CC VIN VIN VIN PGND PGND PGND PGND PGND PGND PGND V OUT VOUT VOUT VOUT PGND PGND PGND V OUT VOUT VOUT VOUT PGND PGND PGND PACKAGE DESCRIPTION PACKAGE PHOTOGRAPH
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 84-Lead (15mm × 9mm × 4.32mm) (Reference L TC DWG # 05-08-1842 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 84 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4.22 – 4.42 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 3.95 – 4.05 Z PACKAGE TOP VIEW 9.00 BSC 15.00 BSC PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW LGA 84 0409 REV Ø L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A 7.620 BSC 1.27 BSC 12.70 BSC 675 1 234 H B A D C E F G M J K L 0.000 1.270 1.270 2.540 2.540 3.810 3.810 6.985 6.985 4.445 4.445 5.715 5.715 3.175 3.175 1.905 1.905 0.635 0.635 0.000 SYMBOL aaa bbb eee TOLERANCE 0.15 0.10 0.05 0.315 0.315 DIA (0.630) PAD 1 3s CHAMFER 0.22 s 45° DETAIL A 0.630 ±0.025 SQ. 83x S YXeee bbb Z
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2010 LT 0710 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TM4603 6A DC/DC μModule Regulator with PLL and Output T racking/Margining 4.5V to 20V Input, 0.6V to 5V Output, 15mm × 15mm × 2.8mm LGA Package L TM4604A 4A DC/DC μModule Regulator 2.375V to 5.5V Input, 0.8V to 5V Output, T racking L TM4608A 8A DC/DC μModule Regulator 2.7V to 5.5V Input, 0.6V to 5V Output, PLL, T racking L TM4612 36V IN DC/DC μModule Regulator 4.5V to 36V Input, 3.3V to 15V Output, PLL, T racking, Margining L TM4619 Dual 4A DC/DC μModule Regulator 4.5V to 26.5V Input, Dual 0.8V to 5V Output, PLL, T racking L TM8025 36V IN, 3A DC/DC μModule Regulator 3.6V ≤ VIN ≤ 36V; 0.8V ≤ VOUT ≤ 24V; 9mm × 15mm × 4.32mm LGA Package TYPICAL APPLICATION
4618 TA02
V OUT VFB PGOOD MODE/PLLININTVCC EXTVCC L TM4618 SGND PGND 10k 28.7k 31.6k COUT 100μF 47pF VOUT 2.5V/6A 0.1μF CIN 10μF VIN 4.5V ≤ VIN ≤ 6V R2UVLO FUNCTION VIN VIN • R2 ¶µ r1.22V 5V Input, 2.5V at 6A Design, 500kHz Operation