LTM4611

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Technical content

4639fFor more information www.linear .com/L TM4639 Low VIN 20A DC/DC µModule Step-Down Regulator TYPICAL APPLICATION

DESCRIPTION

The LT M®4639 is a complete 20A output high efficiency switch mode step-down DC/DC µModule (micromodule) regulator. Included in the package are the switching controller, power FETs, inductor and compensation components. Operating over an input voltage range from 2.375V to 7V, the LTM4639 supports an output voltage range of 0.6V to 5.5V, set by a single external resistor. Only a few input and output capacitors are needed. Current mode operation allows precision current sharing of up to four LTM4639 regulators to obtain up to 80A output. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase/ current sharing, Burst Mode operation and output voltage tracking for supply rail sequencing. A diode-connected PNP transistor is included for use as an internal temperature monitor. For up to 20V input operation, please see the LTM4637. The LTM4639 is offered in a 15mm × 15mm × 4.92mm BGA package. The LTM4639 is RoHS compliant. L, LT, LT C, LT M, PolyPhase, Burst Mode, µModule, Linear Technology, the Linear logo are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210, 8163643. 3.3VIN, 1.5VOUT, 20A DC/DC µModule® Regulator

FEATURES

APPLICATIONS

n Complete 20A Switch Mode Power Supply n 2.375V to 7V Input Voltage Range (VIN < 4.5V, Need CPWR Bias) n 0.6V to 5.5V Output Voltage Range n ±1.5% Maximum Total DC Output Voltage Error (–40°C to 125°C) n Differential Remote Sense Amplifier for Precision Regulation (V OUT ≤ 3.3V) n Current Mode Control/Fast T ransient Response n Parallel Multiphase Current Sharing (Up to 80A) n Frequency Synchronization n Selectable Pulse-Skipping or Burst Mode® Operation n Soft-Start/Voltage T racking n Up to 88% Efficiency (3.3VIN, 1.5VOUT) n Overcurrent Foldback Protection n Output Overvoltage Protection n Internal Temperature Monitor n Overtemperature Protection n 15mm × 15mm × 4.92mm BGA Package n Telecom Servers and Networking Equipment n Industrial Equipment n Medical Systems n High Ambient Temperature Systems n 3.3V Input Systems 3.3V to 1.5V Efficiency and Power Loss PGOOD VOUT VOUT_LCL DIFF_OUT VOSNS+ VOSNS– VFB L TM4639 RFB** 40.2k 100k 22µF 6.3V V IN 3.3V 0.1µF

4639 TA01a

f SET MODE_PLLIN TEMP– TEMP+ INTVCCEXTVCC SGND GND OT_TEST CPWR * SEE TABLE 5 ** SEE TABLE 1 2.2µF1µF +5V BIAS CCOMPA 180pF 100µF* 6.3V 680µF* 2.5V V OUT 1.5V 20A +CFF* 180pF CBOT* 22pF OUTPUT CURRENT (A) EFFICIENCY (%) POWER LOSS 100

4639 TA01b

1.0 1.5 2.0 2.5 3.0 3.5 4.5 0.5 4.0 18 2014 12 166 10 82 4 EFFICIENCY POWER LOSS CPWR = 5V FREQ = 400kHz

4639f For more information www.linear .com/L TM4639 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS MODE_PLLIN, fSET, TRACK/SS, 3V to 5V Internal Operating Temperature Range 40°C to 125°C 55°C to 125°C 5°C (Note 1)

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Range Input DC Voltage Range VIN < 4.5V, CPWR Bias l 2.375 7 V CPWR Voltage 4.5 5 6 V VOUT Range Output DC Voltage Range l 0.6 5.5 V VOUT(DC) Output Voltage, Total Variation with Line and Load C IN = 22µF × 3, CPWR = 5V COUT = 100µF Ceramic, 470µF POSCAP RFB = 40.2k, MODE_PLLIN = GND VIN = 2.375V to 7V, IOUT = 0A to 20A (Note 4) l 1.477 1.50 1.523 V The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in Figure 22. ORDER INFORMATION BGA PACKAGE 133-LEAD (15mm × 15mm × 4.92mm) VIN 1 2 3 4 5 6 7 8 10 9 11 12 B C D E F G H J K L A M INTVCC fSET COMPATRACK/SS MODE_PLLIN INTVCC TOP VIEW SGND VOUT VIN GND TEMP+ TEMP– EXTVCC VFB PGOOD PGOOD CPWR OT_TEST RUN VOSNS+ DIFF_OUT VOUT_LCL VOSNS– COMPB TJ(MAX) = 125°C, θJA = 9.5°C/W, θJCbottom = 4°C/W, θJCtop = 6.7°C/W, θJB = 4.5°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.8g θ VALUES DETERMINED PER JESD51-12 PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RA TING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4639EY#PBF SAC305 (RoHS) LTM4639Y e1 BGA 4 –40°C to 125°C LTM4639IY#PBF LTM4639Y LTM4639IY SnPb (63/37) LTM4639Y e0 BGA 4 –40°C to 125°C

• Consult Marketing for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly
• LGA and BGA Package and T ray Drawings: www.linear.com/packaging

4639fFor more information www.linear .com/L TM4639 The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in Figure 22. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Specifications VRUN RUN Pin On Threshold V RUN Rising 1.1 1.25 1.4 V VRUNHYS RUN Pin On Hysteresis 130 mV IQ(VIN) Input Supply Bias Current VIN = 7V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A VIN = 7V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A VIN = 7V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A Shutdown, RUN = 0, VIN = CPWR = 7V mA mA mA µA I S(VIN) Input Supply Current VIN = 3.3V, VOUT = 1.5V, IOUT = 20A, CPWR = 5V VIN = 7V, VOUT = 1.5V, IOUT = 20A, CPWR = 5V 10.35 4.93 A A I PWR(IN) Control Power Current 3.3V IN to 1.5VOUT at 0A Load, CPWR = 5V 28 mA Output Specifications IOUT(DC) Output Continuous Current Range VIN = 3.3V, VOUT = 1.5V (Note 4) 0 20 A ∆VOUT (Line) VOUT Line Regulation Accuracy V OUT = 1.5V, VIN from 2.375V to 7V, CPWR = 5V, IOUT = 0A l 0.02 0.04 %/V ∆VOUT (Load) VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 20A, VIN = 3.3V, CPWR = 5V (Note 4) l 0.1 0.3 % VOUT(AC) Output Ripple Voltage I OUT = 0A, COUT = 100µF Ceramic, 470µF POSCAP VIN = 3.3V, VOUT = 1.5V, CPWR = 5V 20 mVP-P ∆VOUT(START) Turn-On Overshoot COUT = 100µF Ceramic, 470µF POSCAP, VOUT = 1.5V, IOUT = 0A, VIN = 3.3V, CPWR = 5V 15 mV tSTART Turn-On Time COUT = 100µF Ceramic, 470µF POSCAP, No Load, TRACK/SS = 0.001µF, VIN = 3.3V, CPWR = 5V 0.6 ms ∆VOUTLS Peak Deviation for Dynamic Load Load: 5A to 12.5A Load Step, 1µs Rise Time C OUT = 100µF × 2 Ceramic, COUT × 2 POSCAP, VIN = 3.3V, VOUT = 1.5V, CPWR = 5V 30 mV tSETTLE Settling Time for Dynamic Load Step Load: 5A to 12.5A Load Step, 3.3V, V IN = 5V, VOUT = 1.5V COUT = 100µF × 2 Ceramic, 680µF POSCAP 30 µs IOUTPK Output Current Limit V IN = 3.3V, VOUT = 1.5V VIN = 7V, VOUT = 1.5V A A Control Section V FB Voltage at VFB Pin I OUT = 0A, VOUT = 1.5V l 0.594 0.60 0.606 V IFB Current at VFB Pin (Note 7) –12 –25 nA VOVL Feedback Overvoltage Lockout l 0.65 0.67 0.69 V ITRACK/SS T rack Pin Soft-Start Pull- Up Current TRACK/SS = 0V 1.0 1.2 1.4 µA t ON(MIN) Minimum On-Time (Note 3) 100 ns RFBHI Resistor Between VOUT_LCL and VFB Pins 60.05 60.40 60.75 kΩ Remote Sense Amplifier VOSNS+, VOSNS– CM RANGE Common Mode Input Range VIN = 3.3V, Run > 1.4V, CPWR = 5V 0 3.6 V VDIFF_OUT(MAX) Maximum DIFF_OUT Voltage I DIFF_OUT = 300µA INTVCC – 1.4 V VOS Input Offset Voltage V OSNS+ = VDIFF_OUT = 1.5V, IDIFF_OUT = 100µA 2.5 mV

4639f For more information www.linear .com/L TM4639 The l denotes the specifications which apply over the specified internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 3.3V, CPWR = 5V, per the typical application in Figure 22. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AV Differential Gain (Note 7) 1 V/V SR Slew Rate (Note 6) 2 V/µs GBP Gain Bandwidth Product (Note 6) 3 MHz CMRR Common Mode Rejection (Note 7) 60 dB IDIFF_OUT DIFF_OUT Current Sourcing 2 mA PSRR Power Supply Rejection Ratio 5V < VIN < 7V (Note 7) CPWR T racking VIN 100 dB RIN Input Resistance V OSNS+ to GND 80 kΩ PGOOD Output VPGOOD PGOOD T rip Level V FB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –10 V PGL PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Source Output 5V < V IN < 7V, CPWR T racking VIN 4.8 5 5.2 V VLDOINT INTVCC Load Regulation I CC = 0 to 40mA, CPWR = 5.5V 2 % VEXTVCC External VCC Switchover EXTV CC Ramping Positive, CPWR = 5.5V, INTVCC Output 5V l 4.5 4.7 V VLDOEXT EXTVCC Voltage Drop I CC = 25mA, VEXTVCC = 5V, CPWR = 5.5V 75 220 mV Oscillator and Phase-Locked Loop fSYNC Frequency Sync Capture Range MODE_PLLIN Clock Duty Cycle = 50% 250 800 kHz fNOM Nominal Frequency V fSET = 1.2V 450 500 550 kHz fLOW Lowest Frequency V fSET = 0V 210 250 290 kHz fHIGH Highest Frequency V fSET ≥ 2.4V 700 770 850 kHz IFREQ Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ V IH_MODE_PLLIN Clock Input Level High 2.0 V VIL_MODE_PLLIN Clock Input Level Low 0.8 V Temperature Diode VTEMP TEMP Diode Voltage I TEMP = 100µA 0.6 V TC VTEMP Temperature Coefficient l –2 mV/°C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4639 is tested under pulsed load conditions such that T J ≈ TA. The LTM4639E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4639I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of I MAX Load. (See the Applications Information section) Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: Limit current into the RUN pin to less than 2mA. Note 6: Guaranteed by design. Note 7: 100% tested at wafer level.

4639fFor more information www.linear .com/L TM4639 TYPICAL PERFORMANCE CHARACTERISTICS 7V Efficiency Graph 2.5V to 1V with 7.5A/µs Load Step, CPWR = 5V 2.5V to 1.2V with 7.5A/µs Load Step, C PWR = 5V 2.5V to 1.5V with 7.5A/µs Load Step, C PWR = 5V 3.3V to 1V with 7.5A/µs Load Step, C PWR = 5V 3.3V to 1.2V with 7.5A/µs Load Step, C PWR = 5V 2.5V Input Efficiency Graph 3.3V Efficiency Graph 5V Efficiency Graph OUTPUT CURRENT (A) EFFICIENCY (%)80 100 2 10 14

4637 G01

2.5V TO 1.8V 2.5V TO 1.5V 2.5V TO 1.2V 2.5V TO 1V CPWR = 5V FREQ = 350kHz OUTPUT CURRENT (A) EFFICIENCY (%)80 100 2 10 14

4639 G02

3.3V TO 2.5V 3.3V TO 1.8V 3.3V TO 1.5V 3.3V TO 1.2V 3.3V TO 1V CPWR = 5V FREQ = 400kHz OUTPUT CURRENT (A) EFFICIENCY (%)80 100 2 10 14

4639 G03

5V TO 3.3V 5V TO 2.5V 5V TO 1.8V 5V TO 1.5V 5V TO 1.2V 5V TO 1V CPWR = VIN FREQ = 500kHz OUTPUT CURRENT (A) EFFICIENCY (%)80 100 2 10 14 7V TO 3.3V 7V TO 2.5V 7V TO 1.8V 7V TO 1.5V 7V TO 1.2V 7V TO 1V CPWR = VIN FREQ = 550kHz 50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 LOAD STEP 0A TO 7.5A VOUT VP-P = 80mV

4639 G05

50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G06

0A TO 7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G07

7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G08

0A TO 7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G09

0A TO 7.5A

4639f For more information www.linear .com/L TM4639 TYPICAL PERFORMANCE CHARACTERISTICS 3.3V to 1.5V with 7.5A/µs Load Step, CPWR = 5V 5V to 1.8V with 7.5A/µs Load Step, C PWR = 5V 5V to 3.3V with 7.5A/µs Load Step, C PWR = 5V 7V to 5V with 7.5A/µs Load Step, C PWR = 5V 50µs/DIV COMPA CONNECTED TO COMPB CFF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G10

7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = 180pF, CBOT = 22pF, CCOMPA = 180pF COUT = 100µF CER ×2, 680µF 2.5V 6m/uni03A9 POSCAP ×2 VOUT VP-P = 80mV

4639 G11

0A TO 7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = NONE, CBOT = 22pF, CCOMPA = 180pF COUT = 47µF CER ×1, 220µF 6.3V 15m/uni03A9 POSCAP ×2 VOUT VP-P = 250mV

4639 G12

0A TO 7.5A 50µs/DIV COMPA CONNECTED TO COMPB C FF = NONE, CBOT = 22pF, CCOMPA = 180pF COUT = 22µF CER ×1, 150µF 6.3V 15m/uni03A9 POSCAP ×2 VOUT VP-P = 400mV

4639 G13

7.5A Turn-On No Load Start-Up Pre-Biased Load Recycling VIN (On-Off-On) Output Short-Circuit Output Ripple Noise 20ms/DIV RUN 1V/DIV VOUT 0.5V/DIV VIN = 5V VOUT = 1V IOUT = 20A SW

4639 G14

0.5V/DIV VIN = 5V VOUT = 1V, VOUT = 0.5V BIAS IOUT = 20A SW

4639 G15

0.5V/DIV VIN = 5V VOUT = 1V SW

4639 G16

500µs/DIV VOUT 0.5V/DIV IIN 200mA/DIV VIN = 5V VOUT = 1V SW

4639 G17

1µs/DIV VIN = 3.3V VOUT = 1V IOUT = 20A

4639 G18

VP-P = 8mV

4639fFor more information www.linear .com/L TM4639 PIN FUNCTIONS VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply input voltage between these and GND pins. Recommend placing input decoupling capacitance directly between VIN and GND pins. VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output Pins. Apply output load between these and GND pins. Recommend placing output decoupling capacitance between these pins and GND pins. Review Table 5. Output range 0.6V to 5.5V. GND (C7, C9, D1-D6, D8, E1-E5, E7, E9, F1-F5, F7-F9, G1-G9, H1-H9): Power Ground Pins for Both Input and Output. PGOOD (F11, G12): Output Voltage Power Good Indicator. Open-drain logic output is pulled to ground when the output voltage exceeds a ±10% regulation window. Both pins are tied together internally. SGND ( G11, H11, H12): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND. See layout guidelines in Figure 21. TEMP + (F6): Temperature Monitor. See Applications In- formation section. TEMP – (E6): Kelvin Return of the Internal Temperature Monitor. MODE_PLLIN ( A8): Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to enable pulse-skipping mode. Connect to ground to enable forced continuous mode. Floating this pin will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section. CPWR (B7): Control Bias Input. Required to operate the LTM4639 regulator below 4.5V input. For VIN ≥4.5V up to 7V connect CPWR to VIN. To maintain soft-start function, sequence VIN before C PWR, then enable the RUN pin. If the RUN pin has a pull-up resistor to VIN, then sequence CPWR after VIN. OT_TEST (B9): Used for Test Purposes. Float this pin, or tie to VIN to disable overtemperature protection. fSET (B12): A resistor can be applied from this pin to ground to set the operating frequency, or a DC voltage can be applied to set the frequency. See the Applications Information section. TRACK/SS (A9): Output Voltage T racking Pin and Soft- Start Inputs. The pin has a 1.2µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. See the Applications Information section. VFB (F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to V OUT_LCL with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between V FB and ground pins. In PolyPhase ® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section. COMPA ( A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMP pins together for parallel operation. This pin can be compensated externally for optimized loop response or connected to the COMPB pin. See the Applications Information section. COMPB ( A12): Default Compensation Network Corresponding to Table 5. Tie this pin to COMPA to use default compensation. See the Applications Information section. RUN (A10): Run Control Pin. A voltage above 1.4V will turn on the module. A 5.1V Zener diode to ground is internal to the module for limiting the voltage on the RUN pin to 5V and allowing the use of a pull-up resistor to V IN for enabling the device. Limit current into the RUN pin to ≤ 2mA. INTVCC (A7, D9): Internal 5V LDO for Driving the Control Circuitry and the Power MOSFET Drivers. Both pins are internally connected. The 5V LDO has a 100mA current limit. INTV CC is controlled and enabled when RUN is activated high. See Applications Section. This pin is an output, do not drive this pin. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

4639f For more information www.linear .com/L TM4639 PIN FUNCTIONS EXTVCC (E12): External power input to an internal control switch allows an external source greater than 4.7V, but less than 6V to supply IC power and bypass the internal INTVCC LDO. EXTVCC must be less than VIN at all times during power-on and power-off sequences. See the Applications Information section. 5V output application can connect the 5V output to this pin to improve efficiency. The 5V output is connected to EXTVCC in the 5V derating curves. VOUT_LCL (L12): This pin connects to VOUT through a 1M resistor, and to VFB with a 60.4k resistor. The remote sense amplifier output DIFF_OUT is connected to VOUT_LCL, and drives the 60.4k top feedback resistor in remote sensing applications. When the remote sense amplifier is used, DIFF_OUT effectively eliminates the 1MΩ from V OUT to VOUT_LCL. When the remote sense amplifier is not used, then connect VOUT_LCL to VOUT directly. VOSNS+ (J12): (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier can be used for V OUT ≤ 3.3V. Connect to ground when not used. VOSNS– (M12): (–) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier can be used for V OUT ≤ 3.3V. Connect to ground when not used. DIFF_OUT (K12): Output of the Remote Sense Amplifier. This pin connects to the V OUT_LCL pin for remote sense applications. Otherwise float when not used. The remote sense amplifier can be used for VOUT ≤ 3.3V. MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7, (A12, B11, C10, C11, C12, D10, D11, D12): Extra mounting pads used for increased solder integrity strength. Leave floating.

Figure 1. Simplified LTM4639 Block Diagram

4639 F01

4639f For more information www.linear .com/L TM4639 DECOUPLING REQUIREMENTS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 2.375V to 7V, VOUT = 1.5V), CPWR ≥ 4.5V IOUT = 20A, 4× 22µF Ceramic X7R Capacitors (See Table 5) 88 µF COUT External Output Capacitor Requirement (VIN = 2.375V to 7V, VOUT = 1.5V), CPWR ≥ 4.5V IOUT = 20A (See Table 5) 400 µF TA = 25°C. Use Figure 1 configuration . Power Module Description The LTM4639 is a low input voltage,high performance single output standalone nonisolated switching mode DC/ DC power supply. It can provide a 20A output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 5.5VDC over a 2.375V to 7V input range. The typical application schematic is shown in Figure 22. The LTM4639 has an integrated constant-frequency current mode regulator, power MOSFETs, 0.3µH inductor, and other supporting discrete components. The switching frequency range is from 250kHz to 770kHz, and the typical operating frequency is shown in Table 5 for each VOUT. For switching noise-sensitive applications, it can be externally synchronized from 250kHz to 800kHz, subject to minimum on-time limitations. A single resistor is used to program the frequency. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4639 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Overtemperature protection will turn off the regulator’s RUN pin at ~130°C to 137°C. See Applications Information. OPERATION Pulling the RUN pin below 1.1V forces the regulator into a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Application Information section. The LTM4639 is internally compensated to be stable over all operating conditions with COMPA tied to COMPB. Table 5 provides a guideline for input and output capacitances for several operating conditions. L TpowerCAD™ is available for transient and stability analysis. Custom compensation can be used with the COMPA pin using the L TpowerCAD and an external compensation network. The V FB pin is used to program the output voltage with a single external resistor to ground. A remote sense amplifier is provided for accurately sensing output voltages ≤3.3V at the load point. Multiphase operation can be easily employed with the synchronization inputs using an external clock source. See application examples. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. A TEMP + and TEMP– pin is provided to allow the internal device temperature to be monitored using an onboard diode connected PNP transistor. This diode connected PNP transistor can be used with TEMP monitor devices like the LTC2990, LTC2997, LTC2974 and LTC2978.

requirements for particular applications. at very low input voltage and high duty cycle applications. temperature derating curves. Table 1. VFB Resistor Table vs Various Output Voltages COMP pins must be tied together also. good choice with RMS ripple current ratings of ~ 2A each. capacitor can be used for more input bulk capacitance. planes are used, then this bulk capacitor is not needed. where η% is the estimated efficiency of the power module. electrolytic capacitor or a Polymer capacitor. typical output capacitance range is from 200µF to 800µF. bulk capacitance to optimize the transient performance.

4639f For more information www.linear .com/L TM4639 Stability criteria are considered in the Table 5 matrix, and L TpowerCAD is available for stability analysis and custom compensation for loop optimization using the COMPA pin. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. L TpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increase by N times. Burst Mode Operation The LTM4639 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply float the MODE_PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMPA pin indicates a lower value. The voltage at the COMPA pin drops when the inductor’s average current is greater than the load requirement. As the COMP A voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMPA to rise, the internal sleep line goes low, and the LTM4639 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high effi- ciency at intermediate currents are desired, pulse- skipping mode should be used. Pulse-skipping operation allows the LTM4639 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMPA voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4639’s output voltage is in regulation. Multiphase Operation For outputs that demand more than 20A of load current, multiple LTM4639 devices can be paralleled to provide more output current without increasing input and output ripple voltage. The MODE_PLLIN pin allows the LTM4639 to be synchronized to an external clock and the internal phase-locked loop allows the LTM4639 to lock onto input clock phase as well. The fSET resistor is selected for normal frequency, then the incoming clock can synchronize the device over the specified range. See Figure 24 for a synchronizing example circuit. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. See Application Note 77. The LTM4639 device is an inherently current mode controlled device, so parallel modules will have good current sharing. This will balance the thermals in the design. Tie the COMPA and V FB pins of each LTM4639 APPLICATIONS INFORMATION

schematic of the parallel design. Figure 3. Relationship Between Switching Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases)

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1 PHASE

2 PHASE

3 PHASE

4 PHASE

6 PHASE

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minimum on-time is limited to approximately 100ns. resistor. Figure 4 shows an example of coincident tracking. Figure 4. Dual Outputs (1.5V and 1.2V) with Tracking

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Figure 5. Output Voltage Coincident T racking Characteristics

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VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 4. voltage will reach its final value before the master output. = 75k. Solve for RTA to equal 51.1k. limiting is disabled during soft-start or tracking start-up. VTRACK is the track ramp applied to the slave’s track pin.

relationship (Figure 6), which is at odds with the equation. composite diode voltage slope. Figure 6. Diode Voltage VD vs Temperature T(°C)

4639 F06TEMPERATURE (°C)

4639fFor more information www.linear .com/L TM4639 To obtain a linear voltage proportional to temperature, we cancel the IS variable in the natural logarithm term to remove the IS dependency from the following equation. This is accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2 Subtracting we get: ∆VD = T(KELVIN) •KD •In I1 IS − T(KELVIN) •KD •In IS Combining like terms, then simplifying the natural log terms yields: VD = T(KELVIN) • KD • In(10) and redefining constant K’D = KD • In(10) = 198µV/k yields VD = K’D • T(KELVIN) Solving for temperature: T(KELVIN)= ∆VD K'D T(KELVIN)=[°C]+ 273.15, [°C]= T(KELVIN)− 273.15 means that is we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198µV per Kelvin of the junction with a zero intercept at 0 Kelvin. The diode connected PNP transistor at the TEMP+, TEMP– pins can be used to monitor the internal temperature of the LTM4639. A general temperature monitor can be implemented by connecting a resistor between TEMP + and VIN to set the current to 100µA, grounding the TEMP– pin, and then monitoring the diode voltage drop with temperature. A more accurate temperature monitor can be achieved with a circuit injecting two currents that are at a 10:1 ratio. See Figure 22 for an example. Overtemperature Protection The internal overtemperature protection monitors the internal temperature of the module and shuts off the regulator at ~130°C to 137°C. Once the regulator cools down the regulator will restart. Run Enable The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.25V, and the pin has an internal 5.1V Zener to protect the pin. The RUN pin can be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = ((R1+R2)/R2) • 1.25V See Figure 1, Simplified Block Diagram. INTVCC Regulator The LTM4639 has an internal low dropout regulator from VIN called INTV CC. This regulator output has a 2.2µF ceramic capacitor internal. An additional 2.2µF ceramic capacitor is needed on this pin to ground. This regulator powers the internal controller and MOSFET drivers. The gate driver current is ~20mA for 750kHz operation. The regulator loss can be calculated as: VIN – 5V) • 20mA = PLOSS EXTVCC external voltage source ≥ 4.7V can be applied to this pin to eliminate the internal INTVCC LDO power loss and increase regulator efficiency. A 5V supply can be applied to run the internal circuitry and power MOSFET driver. If unused, leave pin floating. EXTV CC must be less than VIN at all times during power-on and power-off sequences. Stability Compensation The LTM4639 has already been internally compensated for all output voltages. Table 5 is provided for most application requirements. L TpowerCAD is available for other control loop optimization. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). APPLICATIONS INFORMATION

4639f For more information www.linear .com/L TM4639 APPLICATIONS INFORMATION Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambient, is the natural convection junction- to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with four layers. θJCbottom, the thermal resistance from junction to the bottom of the product case , is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4 θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned thermal resistances is given in Figure 7; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θ JCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4639, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4639 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software- defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the

ambient temperature is increased with and without airflow. Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients

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Figure 8. 3.3V Input Power Loss Curves Figure 9. 5V Input Power Loss Curves Figure 10. 7V Input Power Loss Curves 95mm × 76mm. The BGA heat sinks are listed in Table 6.

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0 LFM

200 LFM

400 LFM

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Figure 14. 7VIN to 1.0VOUT with Heat Sink Figure 15. 5V IN to 2.5VOUT No Heat Sink Figure 16. 5VIN to 2.5VOUT with Heat Sink Figure 17. 7VIN to 2.5VOUT No Heat Sink Figure 18. 7VIN to 2.5VOUT with Heat Sink

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Figure 19. 7VIN to 5VOUT No Heat Sink, Figure 20. 7VIN to 5VOUT with Heat Sink,

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Table 2. 1V Output Table 3. 2.5V Output Table 4. 5V Output (5V Output Connected to EXTV CC Pin)

4639fFor more information www.linear .com/L TM4639 APPLICATIONS INFORMATION COUT1 AND COUT2 CERAMIC VENDORS VALUE PA RT NUMBER TDK 22µF, 6.3V C3216X7S0J226M Murata 22µF, 10V GRM31CR61C226KE15L Murata 47µF, 10V GRM31CR61A476KE15L TDK 100µF, 6.3V C4532X5R0J107MZ Murata 100µF, 6.3V GRM32ER60J107M AVX 100µF, 6.3V 18126D107MAT COUT1 AND COUT2 BULK VENDORS VALUE PART NUMBER Sanyo POSCAP 680µF, 2.5V 2R5TPF680M6L Panasonic 220µF, 4V EEFCXOG221ER Sanyo POSCAP 150µF, 10V 10TBF150M CIN BULK VENDOR VALUE PART NUMBER Sanyo 100µF, 16V 16SVP100M Table 5* . Output Voltage Response vs Component Matrix (Refer to Figure 22). Typical Measured Values Standard Internal Compensation COMPA and COMPB Tied Together VOUT (V) CIN (CERAMIC) CIN (BULK)* COUT1 (CERAMIC) COUT2 (CERAMIC AND BULK) CFF (pF) CBOT (pF) CCOMPA (pF) VIN (V) DROOP (mV) PEAK-TO- PEAK DEVIATION (mV) RECOVER Y TIME (µs) LOAD STEP (A/µs) RFB (kΩ) FREQ (kHz) TRACK VIN 2.5V, 3.3V,5V,7V 1 22µF × 4 100µF 100µF × 2 680µF × 2 180 22 180 2.5, 3.3, 5, 7 34 72 34 7.5 90.9 350, 400, 500, 500 1.2 22µ F × 4 100µF 100µF × 2 680µF × 2 180 22 180 2.5, 3.3, 5, 7 37 72 34 7.5 60.4 350, 400, 500, 500 1.5 22µ F × 4 100µF 100µF × 2 680µF × 2 180 22 180 2.5, 3.3, 5, 7 37 80 34 7.5 40.2 350, 400, 500, 500 1.8 22µ F × 4 100µF 100µF × 2 680µF × 2 180 22 180 2.5, 3.3, 5, 7 38 80 34 7.5 30.1 350, 400, 500, 500 2.5 22µ F × 4 100µF 47µF 220µF - 22 180 3.3, 5, 7 111 225 24 7.5 19.1 400, 500, 550 3.3 22µ F × 4 100µF 22µF 150µF - 22 180 5,7 150 300 24 7.5 13.3 500, 550 5 22µF × 4 100µF 22µF 150µF - 22 180 7 187 370 24 7.5 8.25 550 *Bulk capacitance is optional if VIN has very low input impedance. Additional Bulk Capacitance may be required for ≤ 3.3V input Depends on Source Impedance

Table 7. Recommended Heat Sinks *Bulk capacitance is optional if VIN has very low input impedance.

to be provided to protect each unit from catastrophic failure. protection and overtemperature protection. siderations are still necessary.

• Use l arge PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
• Plac e high frequency ceramic input and output capacitors next to the V IN, GND and V OUT pins to minimize high frequency noise.
• Plac e a dedicated power ground layer underneath the unit.
• To mini mize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not pu t vias directly on the pad, unless they are capped or plated over.
• Place test points on signal pins for testing.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit.
• For p arallel modules, tie the COMP and V FB pins together. Use an internal layer to closely connect these pins together. Figure 21 gives a good example of the recommended layout. APPLICATIONS INFORMATION

Figure 21. Recommended PCB Layout

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Figure 22. 2.375V to 7VIN, 1.5V at 20A Design

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Figure 23. 1V at 40A, Two Parallel Outputs with 2-Phase Operation, 350kHz

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Figure 24. 1.2V, 80A, Current Sharing with 4-Phase Operation

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4639fFor more information www.linear .com/L TM4639 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V IN B1 V IN C1 V IN D1 GND E1 GND F1 GND A2 V IN B2 V IN C2 V IN D2 GND E2 GND F2 GND A3 V IN B3 V IN C3 V IN D3 GND E3 GND F3 GND A4 V IN B4 V IN C4 V IN D4 GND E4 GND F4 GND A5 V IN B5 V IN C5 V IN D5 GND E5 GND F5 GND A6 V IN B6 V IN C6 V IN D6 GND E6 TEMP – F6 TEMP + A7 INTV CC B7 C PWR C7 GND D7 – E7 GND F7 GND A8 MODE_PLLIN B8 – C8 – D8 GND E8 – F8 GND A9 TRACK/SS B9 OT_TEST C9 GND D9 INTV CC E9 GND F9 GND A10 RUN B10 – C10 MTP2 D10 MTP5 E10 – F10 – A11 COMPA B11 MTP1 C11 MTP3 D11 MTP6 E11 – F11 PGOOD A12 COMPB B12 f SET C12 MTP4 D12 MTP7 E12 EXTV CC F12 V FB PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 V OUT K1 V OUT L1 V OUT M1 V OUT G2 GND H2 GND J2 V OUT K2 V OUT L2 V OUT M2 V OUT G3 GND H3 GND J3 V OUT K3 V OUT L3 V OUT M3 V OUT G4 GND H4 GND J4 V OUT K4 V OUT L4 V OUT M4 V OUT G5 GND H5 GND J5 V OUT K5 V OUT L5 V OUT M5 V OUT G6 GND H6 GND J6 V OUT K6 V OUT L6 V OUT M6 V OUT G7 GND H7 GND J7 V OUT K7 V OUT L7 V OUT M7 V OUT G8 GND H8 GND J8 V OUT K8 V OUT L8 V OUT M8 V OUT G9 GND H9 GND J9 V OUT K9 V OUT L9 V OUT M9 V OUT G10 – H10 – J10 V OUT K10 V OUT L10 V OUT M10 V OUT G11 SGND H11 SGND J11 – K11 V OUT L11 V OUT M11 V OUT G12 PGOOD H12 SGND J12 V OSNS+ K12 DIFF_OUT L12 V OUT_LCL M12 V OSNS– PACKAGE DESCRIPTION Pin Assignment Table (Arranged by Pin Number) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.

Figure 25. 7VIN, 5V at 20A Design

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4639fFor more information www.linear .com/L TM4639 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PIN 1 SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 133 1113 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A 0.0000 0.0000 DETAIL A Øb (133 PLACES) DETAIL B SUBSTRATE 0.27 – 0.37 3.95 – 4.05 // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 133x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.72 0.50 4.22 0.60 0.60 NOM 4.92 0.60 4.32 0.75 0.63 15.0 15.0 1.27 13.97 13.97 MAX 5.12 0.70 4.42 0.90 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 133 E b e e b F G 133-Lead (15mm × 15mm × 4.92mm) (Reference LTC DWG # 05-08-1962 Rev Ø) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 F G HM L J K E A B C D 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES 133-Lead (15mm × 15mm × 4.92mm) (Reference L TC DWG # 05-08-1962 Rev Ø)

4639f For more information www.linear .com/L TM4639  LINEAR TECHNOLOGY CORPORATION 2014 LT 0914 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4639 RELATED PARTS DESIGN RESOURCES TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTM4637 Higher VIN Range Than the LTM4639 4.5V ≤ VIN ≤ 20V, 20A LTM4611 Lower VIN Range Than the LTM4639 1.5V ≤ VIN ≤ 5.5V,15A, Auxiliary VBIAS Not Required LTM4644 Quad Output, 4A Each 2.375V ≤ VIN ≤ 14V, Low VIN Required Auxiliary VBIAS, Current Share to 16A LTM4615 T riple Output, 4A, 4A, 1.5A 2.375V ≤ VIN ≤ 5.5V, Auxiliary VBIAS Not Required LTM4616 Dual Output, 8A Each 2.7V ≤ VIN ≤ 5.5V, Current Share to 16A, Auxiliary VBIAS Not Required LTM4608A Lower IOUT and Smaller Package Than the LTM4639 2.7V ≤ V IN ≤ 5.5V, 8A, 9mm × 15mm × 2.8mm 1.8V at 20A Design with Input Current and Temperature Monitoring PGOOD VOUT VOUT_LCL DIFF_OUT VOSNS+ VOSNS– VFB L TM4639 RFB 30.1k 125k 470pF MEASURE TEMP CIN 22µF 25V 0.1µF C4 220µF 6.3V X5R V OUT 1.8V AT 20A CONTINUOUS MODE 4639 TA02 10m/uni03A9 CFF 68pF CBOT 22pF CP 100pF VIN COMPA COMPB TRACK/SS RUN f SET MODE_PLLIN TEMP– TEMP+ INTVCCEXTVCC SGND GND OT_TEST CPWR +5V INPUT L TC2990 GND VCC SDA SCL ADR0 V4ADR1 V2 V1 0.1µF 2-WIRE I2C INTERFACE MEASURE IIN CS 1200pF RS 20k SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.