LTM4611 LINER | Alldatasheet
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Technical content
DescripTion
Ultralow VIN, 15A DC/DC µModule Regulator The LTM4611 is a high density 15A output, switch mode DC/DC buck converter power supply capable of operating from very low voltage input supplies. Included in the pack- age are the buck switching controller, power FETs, induc- tor and loop-compensation components. The LTM4611 delivers up to 15A continuous current at high efficiency from an input voltage of 1.5V IN up to 5.5VIN. The output voltage is set between 0.8V and 5V by a resistor. Only a few input and output capacitors are needed. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase/current sharing operation, Burst Mode operation and output voltage tracking for supply rail sequencing. The LTM4611 is available in a thermally enhanced 15mm × 15mm × 4.32mm LGA package. The LTM4611 is PB-free and RoHS compliant. 1.5VIN to 5.5VIN, 15A Step-Down DC/DC µModule ® Regulator
FeaTures
applicaTions
n Complete Switch Mode Power Supply n Input Voltage Range: 1.5V to 5.5V n 15A DC Output n Output Voltage Range: 0.8V to 5V n ±1.5% Total DC Output Error n Differential Remote Sensing for Precision Regulation n Current Mode Control/ Fast T ransient Response n Overcurrent Foldback Protection n Parallel Multiple L TM®4611s for Current Sharing n Frequency Synchronization n Selectable Pulse-Skipping or Burst Mode® Operation n Soft-Start/Voltage T racking n Up to 94% Efficiency n Output Overvoltage Protection n Small 15mm × 15mm × 4.32mm LGA Package n Telecom Servers and Networking Equipment n Storage and ATCA Cards n General Purpose Point of Load Regulation Efficiency vs Load Current L, L T , L TC, L TM, Linear Technology, the Linear logo, Burst Mode, PolyPhase and µModule are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210. TRACK/SS RUN MODE_PLLIN PGOOD VOUT VFB VOUT_LCL DIFFVOUT VOSNS+ VOSNS– L TM4611 VIN RFB** CFF* 22µF s3 CSS 0.1µF 100µF* V OUT STEP-DOWN 15A *SEE TABLE 5 **SEE TABLE 1
4611 TA01
1.5V TO 5.5V SGND GND CP* LOAD CURRENT (A) EFFICIENCY (%)
4611 TA01b
5VIN, 3.3VOUT 3.3VIN, 2.5VOUT 2.5VIN, 1.5VOUT 2.5VIN, 1.2VOUT 3.3VIN, 1VOUT 1.5VIN, 0.9VOUT 5VIN, 1VOUT
pin conFiguraTionabsoluTe MaxiMuM raTings Terminal Voltages VOUT with VOUT without MODE_PLLIN, PLLFL TR/fSET, TRACK/SS, VOSNS–, VOSNS+, Terminal Currents DIFFV Temperatures Operating Junction Temperature Range (Note 2) Storage Temperature Range Peak Solder Reflow Body Temperature (Note 3) (Note 1) orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM4611EV#PBF LTM4611EV#PBF LTM4611V 133-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C LTM4611IV#PBF LTM4611IV#PBF LTM4611V 133-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ LGA PACKAGE 133-LEAD (15mm s 15mm s 4.32mm) VIN 1 2 3 4 5 6 7 8 10 9 11 12 B C D E F G H J K L A M VOSNS+ VOSNS– DIFFVOUT VOUT_LCL MTP1-9 INTVCC VFB PLLFL TR/fSET INTVCC TRACK/SS MODE_PLLIN RUN COMP TOP VIEW SGND PGOOD VOUT VIN GND TJ(MAX) = 125°C θJCtop = 26°C/W, θJCbottom = 2.3°C/W, θJB = 10°C/W, θJA = 14°C/W θ VALUES DETERMINED PER JESD51-12 WEIGHT = 2.6 GRAMS
elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.3V , per the typical application in Figure 21. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Specifications VIN Input DC Voltage l 1.5 5.5 V VRUN RUN Pin On Threshold VRUN Rising l 1.1 1.22 1.35 V VRUNHYS RUN Pin On Hysteresis 80 mV VRUN(FLOAT) RUN Pin Voltage when Floating 3.4 3.65 4 V IRUN(UP,1V) RUN Pin Pull-Up Current (RUN = 1V) 1.1 µA IRUN(UP,1.5V) RUN Pin Pull-Up Current (RUN = 1.5V) 10 µA I RUN(DOWN,5V) RUN Pin Pull-Down Current (RUN = 5V) 1 nA I Q Input Supply Bias Current V OUT = 1.5V, Burst Mode Operation, I OUT = 0.1A VOUT = 1.5V, Pulse-Skipping Mode, I OUT = 0.1A VOUT = 1.5V, Switching Continuous, I OUT = 0.1A Shutdown, RUN = 0V 140 145 1.1 mA mA mA mA I S(VIN) Input Supply Current VIN = 2.5V, VOUT = 1.5V, IOUT = 15A VIN = 3.3V, VOUT = 1.5V, IOUT = 15A VIN = 5V, VOUT = 1.5V, IOUT = 15A VIN = 1.5V, VOUT = 0.8V, IOUT = 15A 10.4 7.9 5.3 10.2 A A A A Output Specifications V OUT(DC) Output Voltage, Total Variation with Line and Load Utilizing DIFF_AMP, RFB = Not Used, VIN = 1.5V to 5.5V, IOUT = 0A to 15A (Note 4), RFB Electrically Floating, MODE_PLLIN = GND l 0.785 0.781 0.797 0.797 0.809 0.813 V V V OUT(RANGE) Utilizing DIFF_AMP (Example See Figure 21) 3.7 V Not Utilizing DIFF_AMP (Example See Figure 20) 5.4 V IOUT(DC) Output Continuous Current Range V OUT = VFB (Note 4) 0 15 A ∆VOUT (Line) VOUT Line Regulation Accuracy V OUT = VFB, VIN from 1.5V to 5.5V, IOUT = 0A l 0.3 % ∆VOUT (Load) VOUT Load Regulation Accuracy V OUT = 1.5V, IOUT = 0A to 15A, VIN = 3.3V (Note 4) l 0.2 0.5 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF ×4 X5R Ceramic, VIN = 3.3V, VOUT = 1.5V 8 mVP-P ∆VOUT(START) Turn-On Overshoot COUT = 100µF ×4 X5R Ceramic, VOUT = 1.5V, IOUT = 0A, VIN = 3.3V, CSS = 1nF 5 mV tSTART Turn-On Time COUT = 100µF ×4 X5R Ceramic, No Load, CSS = 1nF, VIN = 3.3V, VOUT = 1.5V 500 µs ∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load V IN = 3.3V, VOUT = 1.5V, COUT = 100µF ×4 X5R Ceramic, CFF = 100pF 60 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load V IN = 3.3V, VOUT = 1.5V, COUT = 100µF ×4 X5R Ceramic, CFF = 100pF 40 µs IOUT(PK) Output Current Limit VIN = 5V, VOUT = 1.5V VIN = 3.3V, VOUT = 1.5V A A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section VFB Voltage at V FB Pin IOUT = 0A, VOUT = VFB l 0.783 0.797 0.811 V IFB –10 nA VOVL Feedback Overvoltage Lockout l 0.84 0.87 0.89 V ITRACK/SS Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V 0.9 1.4 1.9 µA tON(MIN) Minimum On-Time (Note 5) 90 ns RFBHI Resistor Between V OUT_LCL and VFB Pins 60.05 60.40 60.75 kΩ VOSNS+, VOSNS– CM RANGE Common Mode Input Range V IN = 3.3V, Run > 1.5V 0 INTVCC – 1 V DIFFVOUT Range DIFF_AMP Output Voltage Range V IN = 3.3V, DIFFVOUT Load = 100k 0 INTVCC V VOS DIFF_AMP Input Offset Voltage Magnitude l 1.25 mV mV A V DIFF_AMP Differential Gain 1 V/V VPGOOD PGOOD Trip Level VFB with Respect to Set Output VFB Ramping Positive, PGOOD Transitioning VFB Ramping Positive, PGOOD Transitioning VFB Ramping Negative, PGOOD Transitioning VFB Ramping Negative, PGOOD Transitioning –10 –10 –7.5 7.5 7.5 –7.5 SR DIFF_AMP Slew Rate 2 V/µs GBP DIFF_AMP Gain-Bandwidth Product
3 MHz
CMRR DIFF_AMP Common Mode Rejection 100 dB R IN DIFF_AMP Input Resistance V OSNS+ to GND 19.9 20.0 20.1 kΩ INTVCC Linear Regulator VINTVCC Internal VCC Voltage 1.5V < VIN < 5.5V 4.8 5 5.2 V VINTVCC Load Reg INTV CC Load Regulation ICC = 0 to 50mA 0.5 % Oscillator and Phase-Locked Loop fS Output Ripple Voltage Frequency V IN = 3.3V, VOUT = 1.5V, 0.85V ≤ PLLFLTR/f SET ≤ 2.0V 280 835 kHz fSYNC SYNC Capture Range 360 710 kHz elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.3V , per the typical application in Figure 21.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4611 is tested under pulsed load conditions such that T J ≈ TA. The L TM4611E is guaranteed to meet performance specifications over the 0°C to 125°C operating junction temperature (TJ) range. Specifications over the full –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4611I is guaranteed to meet specifications over the full –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: Consistent with Pb-free 260°C peak IR reflow soldering profiles. See Application Note 100. Note 4: See output current derating curves for different V IN, VOUT and TA. Note 5: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of IMAX Load. (See the Typical Applications section) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PLLFL TR/fSET(FLOAT) PLLFLTR/f SET Open-Circuit Voltage PLLFLTR/f SET Pin Voltage When Floating 1.23 V Frequency Nominal Nominal Frequency PLLFLTR/f SET Floating 500 kHz Frequency Low Lowest Frequency PLLFLTR/f SET = 0.85V 330 kHz Frequency High Highest Frequency PLLFLTR/f SET = 2.0V 780 kHz IPLLFL TR PLLFL TR Sourcing Capability Sinking Capability Mode_PLLIN Frequency > f OSC Mode_PLLIN Frequency < fOSC –13 µA µA R MODE(PLLIN) Mode_PLLIN Input Resistance 250 kΩ VIH Clock Input Level High 2.0 V VIL Clock Input Level Low 0.6 V Mode_PLLIN Clock Clock Input Duty Cycle Range 40 50 60 % elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating junction temperature range, otherwise specifications are at TA = 25°C, VIN = 3.3V , per the typical application in Figure 21.
Typical perForMance characTerisTics 1V Transient Response, 5V IN Efficiency vs Load Current at 1.5VIN, Forced Continuous Mode Efficiency vs Load Current at 1.8V IN, Forced Continuous Mode OUTPUT CURRENT (A) EFFICIENCY (%)
4611 G01
1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT OUTPUT CURRENT (A) EFFICIENCY (%)
4611 G02
1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT Efficiency vs Load Current at 2.5V IN, Forced Continuous Mode OUTPUT CURRENT (A) EFFICIENCY (%)
4611 G03
1.0VOUT 0.9VOUT 0.8VOUT 1.8VOUT 1.5VOUT 1.2VOUT Efficiency vs Load Current at 3.3V IN, Forced Continuous Mode Efficiency vs Load Current at IN, Forced Continuous Mode 1V Transient Response, 3.3V IN OUTPUT CURRENT (A) EFFICIENCY (%)
4611 G04
1.0VOUT 0.9VOUT 0.8VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT OUTPUT CURRENT (A) EFFICIENCY (%)
4611 G05
1.2VOUT 1.0VOUT 0.9VOUT 0.8VOUT 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT ILOAD 5A/DIV 20µs/DIV VIN = 3.3V , VOUT = 1V , USING DIFF AMP 4 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 47pF , CP = NONE 7.5A LOAD STEP AT 7.5A/µs
4611 G06
OUTPUT CURRENT (A) 0.1 EFFICIENCY (%) 1 10
4611 G14
3.3VIN TO 1.5VOUT 5VIN TO 1VOUT Pulse-Skipping Mode Efficiency OUTPUT CURRENT (A) 0.1 EFFICIENCY (%) 1 10
4611 G15
3.3VIN TO 1.5VOUT 5VIN TO 1VOUT ILOAD 5A/DIV 20µs/DIV 4611 G07 VOUT 50mV/DIV AC-COUPLED VIN = 5V , VOUT = 1V , USING DIFF AMP 4 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 47pF , CP = NONE 7.5A LOAD STEP AT 7.5A/µs
3.3V Transient Response, 5V IN Typical perForMance characTerisTics Start-Up, No Load Short-Circuit, 15A Short-Circuit, No Load Start-Up, 15A Load Start-Up, Pre-Bias ILOAD 5A/DIV 20µs/DIV 4611 G08 VOUT 50mV/DIV AC-COUPLED VIN = 5V , VOUT = 3.3V , USING DIFF AMP 2 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 10pF , CP = NONE 7.5A LOAD STEP AT 7.5A/µs VOUT 500mV/DIV IIN 1A/DIV 1ms/DIV 4611 G09 VIN 1V/DIV VIN = 3.3V , VOUT = 1.5V , NO LOAD 3 s 22µF CERAMIC INPUT CAPACITORS CSS = 10nF 4 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 33pF , CP = 10pF IIN 5A/DIV ILOAD 5A/DIV VOUT 500mV/DIV 1ms/DIV 4611 G12 VIN 1V/DIV VIN = 3.3V , VOUT = 1.5V , 100m/uni03A9 LOAD 3 s 22µF CERAMIC INPUT CAPACITORS CSS = 10nF 4 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 33pF , CP = 10pF RUN 5V/DIV IIN 1A/DIV ILOAD 2mA/DIV 2ms/DIV 4611 G13 VOUT 500mV/DIV VIN = 3.3V , VOUT = 1.5V , 0.75V PRE-BIAS LOAD 3 s 22µF CERAMIC INPUT CAPACITORS CSS = 10nF 4 s 100µF CERAMIC OUTPUT CAPACITORS CFF = 33pF , CP = 10pF IIN 2A/DIV 20µs/DIV 4611 G10 VOUT 500mV/DIV VIN = 3.3V , VOUT = 1.5V 15A LOAD PRIOR TO SHORT IIN 1A/DIV 20µs/DIV 4611 G11 VOUT 500mV/DIV VIN = 3.3V , VOUT = 1.5V NO LOAD PRIOR TO SHORT pin FuncTions VIN: (A1-A6, B1-B6, C1-C6) Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. VOUT: (J1-J10, K1-K11, L1-L11, M1-M11) Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 5. GND: (B7 , B9, C7 , C9, D1-D6, D8, E1-E7 , E9, F1-F9, G1-G9, H1-H9) Power Ground Pins for Both Input and Output Returns. PGOOD: (F11, G12) Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage exceeds a ±5% regulation window. Both pins are tied together internally. SGND: (G11, H11, H12) Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See the layout guidelines in Figure 17. MODE_PLLIN: (A8) Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to GND to force continuous mode operation. Connect to INTV CC to enable pulse-skip- ping mode operation. Leaving the pin floating will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section.
PLLFLTR/fSET: (B12) Phase-Locked Loop Lowpass Filter for the Internal Phase Detector. LTM4611’s default switch- ing frequency is 500kHz. Its switching frequency can be increased by connecting a resistor from this pin to INTV CC, or decreased by connecting a resistor from this pin to SGND. See the Applications Information section. V FB: (F12) The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL with a 60.4k precision resistor. Different output voltages can be pro- grammed with an additional resistor between the VFB and GND pins. In PolyPhase ® operation, tying the V FB pins together allows for parallel operation. See the Applications Information section for details. TRACK/SS: (A9) Output Voltage Tracking Pin and Soft- Start Inputs. The pin has a 1.4µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The different voltage is applied to a voltage divider then the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. Tie all TRACK/SS pins together for parallel operation. See the Applications In- formation section. COMP: (A11) Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMP pins together for parallel operation. The device is internally compensated. RUN: (A10) Run Control Pin. A voltage above 1.35V will turn on in the module. The V IN undervoltage lockout (UVLO) of the LTM4611 must be set with resistor networks from V IN to RUN and optionally from RUN to GND. Tie all RUN pins together for parallel operation. pin FuncTions INTVCC: (A7, D9) Internal 5V LDO for Driving the Control Circuitry and the Power MOSFET Drivers. Both pins are internally connected. V OUT_LCL: (L12) This pin connects to VOUT through a 1M resistor and to VFB with a 60.4k resistor. The remote sense amplifier output DIFFVOUT is connected to VOUT_LCL, and drives the 60.4k top feedback resistor in remote sensing applications. When the remote sense amplifier is used, the DIFF_V OUT effectively eliminates the 1MΩ from VOUT to VOUT_LCL. When the remote sense amplifier is not used, then connect VOUT_LCL to VOUT directly. VOSNS+: (J12) (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier is used for V OUT ≤ 3.7V. For VOUT > 3.7V, tie VOSNS+ to GND to rail the output of the remote sense amplifier. VOSNS–: (M12) (–) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier is used for VOUT ≤ 3.7 V. For VOUT > 3.7V, tie VOSNS– to INTVCC to rail the output of the remote sense amplifier. DIFFVOUT : (K12) Output of the Remote Sense Amplifier. This pin connects to the V OUT_LCL pin for remote sense applications. Otherwise float when not used. MTP1:A12, MTP2:B11, MTP3:C10, MTP4:C11, MTP5: C12, MTP6:D10, MTP7:D11, MTP8:D12, MTP9:E12: Extra mounting pads used for increased solder integrity strength. Leave electrically open circuit.
TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4611 Block Diagram
4611 F01
The LTM4611 is a high performance single output stand- alone nonisolated switching mode DC/DC power supply. It can provide a 15A output with few external input and output capacitors. This module provides precisely regu- lated output voltages programmable via external resistors from 0.8V DC to 5VDC over a 1.5V to 5.5V input range. The typical application schematic is shown in Figure 21. The LTM4611 has an integrated constant-frequency cur- rent mode regulator, power MOSFETs, 0.2µH inductor and other supporting discrete components. The nominal switching frequency range is from 330kHz to 780kHz, and the default operating frequency is 500kHz. For switching noise-sensitive applications, it can be externally syn- chronized from 360kHz to 710kHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4611 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltage in the event of an overvoltage >7.5%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUN pin below 1.1V forces the regulator into a shutdown state. The TRACK/SS pin is used for program- ming the output voltage ramp and voltage tracking during start-up. See the Application Information section. The LTM4611 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating con- ditions. The Linear Technology µModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. A remote sense amplifier is provided for accurately sensing output voltages ≤3.7V at the load point. Multiphase operation can be easily employed with the synchronization inputs using an external clock source. See the Typical Applications. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light-load features will accommodate battery operation. Efficiency graphs are provided for light-load operation in the Typical Performance Characteristics section. operaTion
Figure 21. External component selection is primarily requirements for particular applications. should be taken into consideration in such applications. in truly achieving ultralow dropout at high output current. combination with a sluggish source supply. tion and temperature derating curves. is used, then DIFFVOUT is connected to the VOUT_LCL pin. Table 1. VFB Resistor Table vs Various Output Voltages tied together as shown in Figures 18 and 19. and value CFF from VOUT to VFB, local to each µModule. N • CFF from VOUT to the bussed VFB signal, can suffice. inductive leads, traces or not enough source capacitance.
For a buck converter, the switching duty cycle can be estimated as: D= VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D•(1–D) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor or a Polymer capacitor. Output Capacitors The LTM4611 is designed for low output voltage ripple noise. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient require- ments. C OUT can be the low ESR tantalum capacitor, the low ESR Polymer capacitor or ceramic capacitors. The typical output capacitance range is from 200µF to 800µF. Additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of dif- ferent output voltages and output capacitors to minimize the voltage droop and overshoot during a 7A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stabil- ity criteria are considered in the Table 5 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the num- ber of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phase’s increases by N times. Burst Mode Operation The LTM4611 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply leave the MODE_PLLIN pin floating. During Burst Mode operation, the peak current of the inductor is set to approximately 33% of the maximum peak current value in normal operation even though the voltage at the I TH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the ITH voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In this sleep mode, the internal circuitry is partially turned off, reducing the LTM4611’s quiescent current while the load current is supplied by the output capacitors. When the output voltage drops–causing I TH to rise–the internal sleep line goes low and the LTM4611 resumes normal operation. The next oscillator cycle turns on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high effi- ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4611 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be applicaTions inForMaTion
Figures 18 and 19 for a synchronizing example circuit. than the number of phases used times the output voltage). of phases used. See Application Note 77. sharing. This will balance the thermals on the design. devices operating in parallel. Figure 2. Normalized Input RMS Ripple Current vs Duty Factor for One to Six µModules (Phases)
1 PHASE
2 PHASE
3 PHASE
4 PHASE
6 PHASE
associated with that operating condition. See Figure 3. ripple and noise characteristics.
- VOUT VIN Output Voltage T racking and Soft-Start Functions Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4611 uses an accurate 60.4k resistor internally for the top feedback resis- tor. Figure 4 shows an example of coincident tracking. VOUT _ SLAVE = 1+ 60.4k RFB2 • VTRACK VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.8V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point. Volt- age tracking is disabled when V TRACK is more than 0.8V. RTA in Figure 4 will be equal to the R FB2 for coincident tracking. The TRACK/SS pin of the master can be controlled by an external ramp or the soft-start function of that regulator can be used to develop that master ramp. The LTM4611 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. A 1.4µA current source is used to charge the soft-start capacitor. The following equation can be used: tSOFTSTART = 0.8V • CSS 1.4µA applicaTions inForMaTion VALUE OF RESISTOR ON PLLFL TR/fSET PIN (M/uni03A9) 0.1 0.96PLLFL TR/fSET PIN VOL TAGE (V) SWITCHING FREQUENCY (kHz) 1.23 1.50 1 10 100
4611 F03
Figure 3. Relationship Between Oscillator Frequency,
Figure 4. Dual Outputs (1.5V and 1.2V) With Tracking Figure 5. Output Voltage Coincident Tracking
4611 F04
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steady-state value (1.23V by default).
Decreasing the PLLFLTR/f SET RC time constant can be accomplished, for example, by driving the PLLFLTR/fSET pin with an external, lower impedance resistor divider network from INTVCC and GND to PLLFLTR/fSET—in the simplest of implementations, by shorting PLLFLTR/f SET to INTVCC (thereby programming the switching frequency to 780kHz, nominal), or by driving the PLLFLTR/fSET pin from a low impedance voltage source. When, in addition to needing faster turn-on time, one is also synchronizing to an external clock signal, one need bear in mind: the PLL ’s sink and source current is recommended for not more than ±8µA loading, and the PLL will need to successfully drive any external PLLFLTR/f SET network impedance to achieve phase lock; and lastly, some phase shift in clock synchronization will occur as external loading on PLLFLTR/f SET becomes heavier. To be clear, using a CSS value of 10nF (or higher) eliminates the need for any of the above special considerations or provisions. Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0V to 0.8V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in volts/time. The equation: MR SR • 60.4k= RTB where MR is the master’s output slew rate and SR is the slave’s output slew rate in volts/time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal to 60.4k. RTA is derived from equation: RTA = 0.8V VFB 60.4k + VFB RFB2 – VTRACK RTB where VFB is the feedback voltage reference of the regula- tor, and VTRACK is 0.8V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TA is equal to RFB2 with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 121k in Figure 4. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R TB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then R TB = 75k. Solve for RTA to equal to 87k. Beware that without any kind of soft-start ramp up, it is important to provide thorough input filter capacitance to handle input surge currents at start-up, so as to avoid excessive input line sag and power supply motor boating. Leaving provision for at least a soft-start capacitor in one’s application is strongly recommended. Overcurrent and Overvoltage Protection The LTM4611 has overcurrent protection (OCP) in a short circuit. The internal current comparator threshold folds back during a short to reduce the output current. An overvoltage condition (OVP) above 7.5% of the regu- lated output voltage will force the top MOSFET off and the bottom MOSFET on until the condition is cleared. An input electronic circuit breaker or fuse can be sized to be tripped or cleared when the bottom MOSFET is turned on to protect against the overvoltage. Foldback current limiting is disabled during soft-start or tracking start-up. Run Enable The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.22V. The RUN pin must be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: R2= R1 VUVLO 1.22V – 1 To achieve the lowest possible UVLO, 1.22V, leave R2 unpopulated. R1 can be 10k, or if R2 is unpopulated, R1 may be replaced with a hardwired connection from V IN to RUN.
See the Block Diagram for the example of use. When RUN is below its threshold, TRACK/SS is pulled low by internal circuity. INTV CC Regulator The LTM4611 has an internally regulated bias supply called INTVCC. This regulator output has a 4.7µF ceramic capaci- tor internal. This regulator powers the internal controller and MOSFET drivers. The gate driver current is ~13mA for 500kHz operation and ~20mA for 780kHz operation; the regulator loss is ~40mW and ~60mW, respectively. Stability Compensation The module has already been internally compensated for all output voltages. Table 5 is provided for most ap- plication requirements. The Linear Technology µModule Power Design Tool will be provided for other control loop optimization. Thermal Considerations and Output Current Derating The LTM4611 output current may need to be derated if it is required to operate in a high ambient temperature or deliver a large amount of continuous power. Some factors that influence derating are input voltage, output power, ambient temperature, airflow, and elevation (air density). The power loss curves in Figures 7 to 9 and current de- rating curves in Figures 10 to 16 can be used as a guide. These curves were generated by an LTM4611 mounted to a 95mm × 76mm 4-layer FR4 printed circuit board (PCB) 1.6mm thick with two ounce copper for the outer layers and one ounce copper for the two inner layers. Boards of other sizes and layer count can exhibit different thermal behavior, so it is ultimately incumbent upon the user to verify proper operation over the intended system’s line, load and environmental operating conditions. The thermal resistance numbers listed in the Pin Configura- tion section of the data sheet are based on modeling the µModule package mounted on a test board specified per JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The thermal coef- ficients provided are based on JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). For increased accuracy and fidelity to the actual applica- tion, many designers use finite element analysis (FEA) to predict thermal performance. To that end, the Pin Configuration section of the data sheet typically gives four thermal coefficients: θJA: thermal resistance from junction to ambient. 2. θJCbottom: thermal resistance from junction to the bot- tom of the product case. θJCtop: thermal resistance from junction to top of the product case. θJB: thermal resistance from junction to the printed circuit board. While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid confusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased in the following: θJA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not necessarily reflect an actual application or viable operating condition. θJCbottom is the junction-to-board thermal resistance with all of the component power dissipation flow- ing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCtop is determined with nearly all of the component power dissipation flowing through the top of the pack- age. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an ap- plication to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application.
- θJB is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a por- tion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. Given these definitions, it should now be apparent that none of these thermal coefficients reflects an actual physical operating condition of a µModule. Thus, none of them can be individually used to accurately predict the thermal performance of the product. Likewise, it would be inappropriate to attempt to use any one coefficient to correlate to the junction temperature versus load graphs given in the product’s data sheet. The only appropriate way to use the coefficients is to run a detailed thermal analysis, such as FEA, which considers all of the thermal resistances simultaneously. A graphical representation of these thermal resistances is given in Figure 5. The blue resistances are contained within the µModule, and the green are outside. The die temperature of the LTM4611 must be lower than the maximum rating of 125°C, so care should be taken in the layout of the circuit to ensure good heat sinking of the LTM4611. The bulk of the heat flow out of the LTM4611 is through the bottom of the module and the LGA pads into the printed circuit board. Consequently, a poor printed circuit board design can cause excessive heating, result- ing in impaired performance or reliability. Please refer to the PCB Layout section for printed circuit board design suggestions The 1.2V, 2.5V and 3.3V power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 16 for calculating an approximate θ JA thermal resistance for the LTM4611 with various heat sinking and air flow conditions, as evaluated on the aforementioned 4-layer FR4 PCB. The power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. These approximate factors are: 1 up to 50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for 90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C. The derating curves are plotted with the output current starting at 15A and the ambient temperature at 55°C. The output voltages are 1.2V, 2.5V and 3.3V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal mod- eling analysis. The junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. The BGA heat sinks evaluated in Table 5 yield very comparable performance in laminar airflow despite being visibly different in con- struction and form factor. The power loss increase with
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JUNCTION-TO-CASE (TOP) RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD) CASE (TOP)-TO-AMBIENT RESISTANCE BOARD-TO-AMBIENT RESISTANCE JUNCTION-TO-CASE (BOTTOM) RESISTANCE JUNCTION At CASE (BOTTOM)-TO-BOARD RESISTANCE Figure 6
Figure 7. 1.2VOUT Power Loss
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Table 2. 1.2V Output Table 4. 3.3V Output
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Table 3. 2.5V Output
Table 5. Output Voltage Response Versus Component Matrix, 0A to 7.5A Load Step ent temperature multiplicative factors.
HEAT SINK MANUFACTURER PART NUMBER WEBSITE Wakefield Engineering LTN20069 www.wakefield.com AAVID Thermalloy 375424B00034G www.aavidthermalloy.com *The quantity and quality of bulk input bypass capacitance needed, particularly for low dropout scenarios (VIN – VOUT < 600mV) is mainly dependent on the output impedance and dynamic response of the power source feeding the LTM4611(s). Consider, in the extreme: for a heavy load step, the full transient on LTM4611’s output is directly referred to its input, and the LTM4611 can only deliver to its output whatever the source supply and local input caps can provide. Sluggish source supplies will call for more bulk capacitance placed locally to the LTM4611’s input, to assist the source supply in riding through severe transient load steps. VOUT (V) VIN (V) CIN* (CERAMIC) CIN* (BULK) COUT2 (CERAMIC) COUT1 (BULK) C FF CP USING DIFF AMP FIGURE TRANSIENT DROOP, 0A TO 7.5A LOAD STEP (mV) TRANSIENT PEAK-TO-PEAK, 0A TO 7.5A TO 0A (mVP-P) RECOVERY TIME (µs) LOAD STEP SLEW RATE (A/µs) RSET (kΩ) 1.2 3.3 2 × 47µF 150µF 4 x 100µF None 33pF 10pF Y 21 60 116 30 7.5 121 1.2 3.3 2 × 47µF 150µF 7 × 22µF 330µF 10pF 10pF Y 21 63 117 20 7.5 121 1.2 5 2 × 47µF 150µF 4 × 100µF None 47pF None Y 21 47 105 30 7.5 121 1.2 5 2 × 47µF 150µF 6 × 22µF 330µF 10pF 10pF Y 21 64 123 25 7.5 121 1.5 1.8 2 × 47µF 1000µF 6 × 100µF None 220pF None Y 21 83 147 25 7.5 69 1.5 1.8 2 × 47µF 1000µF 2 × 22µF 470µF 47pF None Y 21 71 135 40 7.5 69 1.5 2.5 2 × 47µF 220µF 4 × 100µF None 220pF None Y 21 64 122 40 7.5 69 1.5 2.5 2 × 47µF 220µF 5 × 22µF 330µF 22pF 10pF Y 21 68 133 30 7.5 69 1.5 3.3 2 × 47µF 150µF 4 × 100µF None 33pF 10pF Y 21 66 123 30 7.5 69 1.5 3.3 2 × 47µF 150µF 4 × 22µF 330µF 22pF None Y 21 67 124 30 7.5 69 1.5 5 2 × 47µF 150µF 4 × 100µF None 33pF 10pF Y 21 59 122 30 7.5 69 1.5 5 2 × 47µF 150µF 6 × 22µF 330µF None 10pF Y 21 67 131 30 7.5 69 1.8 2.5 2 × 47µF 330µF 4 × 100µF None 220pF None Y 21 73 137 45 7.5 48.1 1.8 2.5 2 × 47µF 330µF 5 × 22µF 330µF 22pF None Y 21 76 145 35 7.5 48.1 1.8 3.3 2 × 47µF 150µF 4 × 100µF None 47pF 10pF Y 21 57 118 40 7.5 48.1 1.8 3.3 2 × 47µF 150µF 4 × 22µF 330µF 22pF None Y 21 69 137 30 7.5 48.1 1.8 5 2 × 47µF 150µF 4 × 100µF None 33pF 10pF Y 21 64 127 40 7.5 48.1 1.8 5 2 × 47µF 150µF 6 × 22µF 330µF None 10pF Y 21 69 133 30 7.5 48.1 2.5 3.3 2 × 47µF 330µF 3 × 100µF None 100pF None Y 21 71 143 45 7.5 28.4 2.5 3.3 2 × 47µF 330µF 4 × 100µF None 100pF None Y 21 66 123 40 7.5 28.4 2.5 3.3 2 × 47µF 330µF 3 × 22µF 330µF 47pF None Y 21 67 128 50 7.5 28.4 2.5 5 2 × 47µF 150µF 3 × 100µF None 100pF None Y 21 60 134 45 7.5 28.4 2.5 5 2 × 47µF 150µF 4 × 100µF None 100pF None Y 21 54 115 50 7.5 28.4 2.5 5 2 × 47µF 150µF 5 × 22µF 330µF 22pF None Y 21 81 160 40 7.5 28.4 3.3 5 2 × 47µF 150µF 2 × 100µF None 22pF None Y 21 137 274 40 7.5 19.3 3.3 5 2 × 47µF 150µF 3 × 100µF None 47pF None Y 21 67 143 50 7.5 19.3 3.3 5 2 × 47µF 150µF 4 × 100µF None 100pF None Y 21 56 119 60 7.5 19.3 3.3 5 2 × 47µF 150µF 5 × 22µF 330µF 22pF None Y 21 95 193 45 7.5 19.3 5 5.5 2 × 47µF 680µF 1 × 100µF None 10pF None N 20 264 511 30 7.5 11.5 5 5.5 2 × 47µF 680µF 7 × 22µF None None None N 20 218 431 40 7.5 11.5 applicaTions inForMaTion THERMALLY CONDUCTIVE ADHESIVE TAPE MANUFACTURER PART NUMBER WEBSITE Chromerics T411 www.chromerics.com
protection and overcurrent protection. erations are still necessary.
- U se large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
- Pl ace high frequency ceramic input and output capaci- tors next to the V IN, GND and V OUT pins to minimize high frequency noise.
- Pl ace a dedicated power ground layer underneath the unit.
- T o minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
- D o not put vias directly on the pad, unless they are capped or plated over.
- U se a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to GND underneath the unit.
- F or parallel modules, tie the respective COMP , V FB, VOUT_LCL, TRACK/SS and RUN pins together. Use an internal layer to closely connect these pins together. Figure 17 gives a good example of the recommended lay out. Figures 18 and 19 show schematics of the LTM4611 devices operating in parallel.
- T o facilitate stuffing verification, test and debug activi- ties, consider routing control signals of the LTM4611 with short traces to localized test points, test pads or test vias–as PCB layout space permits. Both in-house and contract manufacturers enjoy gaining electrical access to all non low impedance (>10Ω) pins of an IC or µModule device to improve in-circuit test (ICT) coverage.
Figure 17. Recommended PCB Layouts
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Figure 18. 1.2V, 60A, Current Sharing with 4-Phase Operation
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Figure 19. 1V at 30A LTM4611 Two Parallel Outputs with 2-Phase Operation
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Figure 20. 3.3V at 15A Design, Example of Not Using Differential Remote Sense
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PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME VIN B1 VIN C1 VIN D1 GND E1 GND F1 GND A2 VIN B2 VIN C2 VIN D2 GND E2 GND F2 GND A3 VIN B3 VIN C3 VIN D3 GND E3 GND F3 GND A4 VIN B4 VIN C4 VIN D4 GND E4 GND F4 GND A5 VIN B5 VIN C5 VIN D5 GND E5 GND F5 GND A6 VIN B6 VIN C6 VIN D6 GND E6 GND F6 GND A7 INTVCC B7 GND C7 GND D7 - E7 GND F7 GND A8 MODE_PLLIN B8 - C8 - D8 GND E8 - F8 GND A9 TRACK/SS B9 GND C9 GND D9 INTVCC E9 GND F9 GND A10 RUN B10 - C10 MTP3 D10 MTP6 E10 - F10 - A11 COMP B11 MTP2 C11 MTP4 D11 MTP7 E11 - F11 PGOOD A12 MTP1 B12 PLLFLTR/f SET C12 MTP5 D12 MTP8 E12 MTP9 F12 VFB PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME GND H1 GND J1 VOUT K1 VOUT L1 VOUT M1 VOUT G2 GND H2 GND J2 VOUT K2 VOUT L2 VOUT M2 VOUT G3 GND H3 GND J3 VOUT K3 VOUT L3 VOUT M3 VOUT G4 GND H4 GND J4 VOUT K4 VOUT L4 VOUT M4 VOUT G5 GND H5 GND J5 VOUT K5 VOUT L5 VOUT M5 VOUT G6 GND H6 GND J6 VOUT K6 VOUT L6 VOUT M6 VOUT G7 GND H7 GND J7 VOUT K7 VOUT L7 VOUT M7 VOUT G8 GND H8 GND J8 VOUT K8 VOUT L8 VOUT M8 VOUT G9 GND H9 GND J9 VOUT K9 VOUT L9 VOUT M9 VOUT G10 - H10 - J10 VOUT K10 VOUT L10 VOUT M10 VOUT G11 SGND H11 SGND J11 - K11 VOUT L11 VOUT M11 VOUT G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFFVOUT L12 VOUT_LCL M12 VOSNS – Pin Assignment Table (Arranged by Pin Number) package phoTograph
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.15 0.10 0.05 4.22 – 4.42 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 3.95 – 4.05 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 L K J H G F E D C B PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES M A DETAIL A 0.630 ±0.025 SQ. 133x S Y X eee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 1008 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 0.630 0.630 133-Lead (15mm × 15mm × 4.32mm) (Reference L TC DWG # 05-08-1777 Rev Ø)
Figure 21. 1.5V to 5.5VIN, 1V at 15A Design