LTM4609

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Technical content

38V, 10A DC/DC µModule Regulator with Advanced Input and Load Protection The L TM®4641 is a switch mode step-down DC/DC µModule® (micromodule) regulator with advanced input and load protection features. T rip detection thresholds for the following faults are customizable: input undervoltage, overtemperature, input overvoltage and output overvolt- age. Select fault conditions can be set for latchoff or hysteretic restart response—or disabled. Included in the package are the switching controller and housekeeping ICs, power MOSFETs, inductor , overvoltage drivers, biasing circuitry and supporting components. Operating from input voltages of 4V to 38V (4.5V start-up), the device supports output voltages from 0.6V to 6V , set by an external resis- tor network remote sensing the point-of-load’s voltage. The L TM4641’s high efficiency design can deliver up to 10A continuous current with a few input and output ca - pacitors. The regulator’s constant on-time current mode control architecture enables high step-down ratios and fast response to transient line and load changes. The L TM4641 is offered in a 15mm × 15mm × 5.01mm RoHS compliant BGA package with Pb-free finish.

APPLICATIONS

n Wide Operating Input Voltage Range: 4.5V to 38V n 10A DC Typical, 12A Peak Output Current n Output Range: 0.6V to 6V n ±1.5% Maximum Total Output DC Voltage Error n Differential Remote Sense Amplifier for POL Regulation n Internal Temperature, Analog Indicator Output n Overcurrent Foldback and Overtemperature Protection n Current Mode Control/Fast T ransient Response n Parallelable for Higher Output Current n Selectable Pulse-Skipping Operation n Soft-Start/Voltage T racking/Pre-Bias Start-Up n 15mm × 15mm × 5.01mm BGA Package Input Protection n UVLO, Overvoltage Shutdown and Latchoff Thresholds n N-Channel Overvoltage Power-Interrupt MOSFET Driver n Surge Stopper Capable with Few External Components Load Protection n Robust, Resettable Latchoff Overvoltage Protection n N-Channel Overvoltage Crowbar Power MOSFET Driver n Ruggedized Electronics n Avionics and Industrial Equipment L, L T , L TC, L TM, µModule, Burst Mode, Linear Technology and the Linear logo are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6100678, 6304066, 6580258, 6677210. VOUT (200mV/DIV) 4µs/DIV TESTED AT WORST-CASE CONDITION: NO LOAD

4641 TA01b

1.1VOUT PEAK CROWBAR (5V/DIV) VINL, VINH (25V/DIV) 1V Load Protected from M TOP Short-Circuit at 38V IN µModule Regulator with Input Disconnect and Fast Crowbar Output Overvoltage Protection IOVRETRY VING VINGP VINH SW MCB** MBOT MTOP MSP* 2VOUT CROWBAR VOSNS+ VOSNS– GND OVPGM VINL fSET 750k 5.6M

4641 TA01a

SGND CONNECTS TO GND INTERNAL TO µMODULE REGULATOR MSP: (OPTIONAL) SERIES-PASS OVERVOL TAGE POWER INTERRUPT MOSFET , NXP PSMN014-60LS MCB: (OPTIONAL) OUTPUT OVERVOL TAGE CROWBAR MOSFET , NXP PH2625L 5.49k 5.49kL TM4641 10µF 50V UVLO INTV CC DRVCC RUN 10nF TRACK/SS OVLO FCB LATCH SGND 100µF VOUT 10A 100µF 50V V IN 4V TO 38V 4.5V START-UP LOAD

Applications Information—Power Supply Features . 17 Switching Frequency (On Time) Selection and Voltage Dropout Criteria (Achievable VIN-to-VOUT Setting the Output Voltage; the Differential Remote Sense Amplifier Output Capacitors and Loop Stability/Loop Compensation Pulse-Skipping Mode vs Forced Continuous Mode 24 Soft-Start, Rail-Tracking and Start-Up Into Pre-Bias Applications Information—Input Protection

Features

Input Monitoring Pins: UVLO, IOVRETRY, OVLO ....29 Start-Up/Shutdown and Run Enable; Power-On Reset and Timeout Delay Time Applications Information—Load Protection Power Good Indicator and Latching Output Overvoltage Protection Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB) Applications Information—Multimodule Parallel Applications Information—Thermal Considerations and Output Current Derating Thermal Considerations and Output Current Derating Applications Information—Output Capacitance Table Applications Information—Safety and Layout Guidance Appendix A. Functional Block Diagram and Features Quick Reference Guide Appendix C. Switching Frequency Considerations and Usage of R Appendix D. Remote Sensing in Harsh Environments Appendix E. Inspiration For Pulse-Skipping Mode Operation Appendix F. Adjusting the Fast Output Overvoltage Comparator Threshold

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Terminal Voltages INTVCC, DRVCC, RUN, TRACK/SS, PGOOD, OTBH, UVLO, IOVRETRY, OVLO, Terminal Currents INTVCC (Continuous; CROWBAR Internal Operating Temperature Range (Note 2) Peak Package Body Temperature (SMT Reflow) ... 245°C (Note 1) SW BGA PACKAGE 144-LEAD (15mm × 15mm × 5.01mm) TOP VIEW GND GND GND GND 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A OVPGMCROWBARTEMP IOVRETRY 1VREF OVLOHYST UVLO SGND VORB– VORB+ VOSNS– VOSNS+ DRVCC SGND VINL fSET LATCH RUN TMR OTBH COMP PGOOD TRACK/SS VINH VOUT VINGPVINGSGND INTVCC FCB TJMAX = 125°C, θJCtop = 11°C/W , θJCbottom = 2.5°C/W θJB = 3°C/W , θJA = 10.4°C/W θ VALUES DETERMINED PER JESD51-12 WEIGHT = 2.9 GRAMS ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (Note 2) L TM4641EY#PBF L TM4641EY#PBF L TM4641Y 144-Lead (15mm × 15mm × 5.01mm) BGA –40°C to 125°C L TM4641IY#PBF L TM4641IY#PBF L TM4641Y 144-Lead (15mm × 15mm × 5.01mm) BGA –40°C to 125°C L TM4641MPY#PBF L TM4641MPY#PBF L TM4641Y 144-Lead (15mm × 15mm × 5.01mm) BGA –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V , per the typical application shown in Figure 45, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 38 V VOUT Output Voltage Range Use RSET1A = RSET1B ≤ 8.2kΩ. RfSET Values Recommended in Table 1 l 0.6 6 V VOUT(DC) Output Voltage, Total Variation with Line and Load, and Prior to UVLO 4.5V ≤ VIN ≤ 38V , 0A ≤ IOUT ≤ 10A VIN = 4V (Ramped Down from 4.5V), IOUT = 0A l l 1.773 1.773 1.800 1.800 1.827 1.827 V V Input Specifications V RUN(ON,OFF) RUN On/Off Threshold Run Rising, Turn On Run Falling, Turn Off l l 0.8 1.25 1.15 2 V V I RUN(ON) RUN Pull-Up Current VRUN = 0V VRUN = 3.3V l l –580 –220 –520 –165 –460 –110 µA µA I RUN(OFF) RUN Pull-Down Current, Switching Inhibited V RUN = 3.3V , UVLO = 0V (MHYST On) 1 nA VINL(UVLO) VINL Undervoltage Lockout VINL Rising VINL Falling Hysteresis l l l 3.5 300 4.2 3.8 400 4.5 V V mV I INRUSH(VINH) Input Inrush Current Through VINH, at Start-Up CSS = Open 230 mA IQ(VINH) Power Stage Bias Current (IVINH) at No Load IOUT = 0A and: FCB ≥ 0.84V (Pulse-Skipping Mode) FCB ≤ 0.76V (Forced Continuous Mode) Shutdown, RUN = 0 0.2 mA mA mA I Q(VINL) Control Bias Current (IVINL) INTVCC Connected to DRVCC and: VIN = 28V , IOUT = 0A VIN = 28V , IOUT = 10A VIN = 28V , Shutdown, RUN = 0 14.5 15.5 mA mA mA I S(VINH) Power Stage Input Current (IVINH) at Full Load IOUT = 10A and: VIN = 4.5V VIN = 28V VIN = 38V 4.65 790 590 A mA mA Output Specifications I OUT(DC) Output Continuous Current Range (Note 3) l 0 10 A ∆VOUT(LINE)/VOUT Line Regulation Accuracy VIN from 4.5V to 38V , IOUT = 0A l 0.02 0.15 % ∆VOUT(LOAD)/VOUT Load Regulation Accuracy IOUT from 0A to 10A (Note 3) l 0.04 0.15 % VOUT(AC) Output Voltage Ripple Amplitude IOUT = 0A 16 mVP-P fS Output Voltage Ripple Frequency IOUT = 0A IOUT = 10A 290 330 kHz kHz V OUT(START) Turn-On Overshoot IOUT = 0A 10 mV tSTART VIN-to-VOUT Start-Up Time RUN Electrically Open Circuit, Time Between Application of V IN to VOUT Becoming Regulated, OVPGM = 1.5V , CTMR = CSS = Open 3 ms tRUN(ON-DELAY) RUN-to-VOUT Turn-On Response Time VIN Established, (TMR-Set POR Time Expired) Time Between RUN Releasing from GND to PGOOD Going Logic High, C SS = Open, OVPGM = 1.5V 175 400 μs ∆VOUT(LS) Peak Deviation for Dynamic Load Step I OUT from 0A to 5A at 5A/µs IOUT from 5A to 0A at 5A/µs mV mV t SETTLE(LS) Settling Time for Dynamic Load Step IOUT from 0A to 5A at 5A/µs IOUT from 5A to 0A at 5A/µs μs µs

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V , per the typical application shown in Figure 45, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IOUT(PK) Output Current Limit 5.1kΩ Pull-Up from PGOOD to 5V Source, IOUT Ramped Up Until VOUT Below PGOOD Lower Threshold, PGOOD Pulls Logic Low 24 A IVINH(IOUT_SHORT) Power Stage Input Current During Output Short Circuit VOUT Electrically Shorted to GND 45 mA Control Section VFB Differential Feedback Voltage from VOSNS+ to VOSNS– IOUT = 0A l 591 600 609 mV ITRACK/SS TRACK/SS Pull-Up Current VTRACK/SS = 0V –0.45 –1 μA VFCB FCB Threshold 0.76 0.8 0.84 V IFCB FCB Pin Current VFCB = 0.8V 0 ±1 μA tON(MIN) Minimum On-Time (Note 4) 43 75 ns tOFF(MIN) Minimum Off-Time (Note 4) 220 300 ns VOSNS(DM) Remote Sense Pin-Pair Differential Mode Input Range Valid Differential V OSNS+ -to- VOSNS– Range (Use RSET1A = RSET1B ≤ 8.2k) l 0 2.7 V VOSNS(CM) Remote Sense Pin-Pair Common Mode Input Range Valid V OSNS– Common Mode Range Valid VOSNS+ Common Mode Range (Use RSET1A = RSET1B ≤ 8.2k) l l –0.3 V V RIN(VOSNS+) Input Resistance VOSNS+ to GND 16318 16400 16482 Ω INTVCC, DRVCC, 1VREF VINTVCC Internal VCC Voltage 6V ≤ VIN ≤ 38V , INTVCC Not Connected to DRVCC, DRVCC = 5.3V l 5.1 5.3 5.4 V ∆VINTVCC(LOAD) VINTVCC INTVCC Load Regulation RUN = 0V , INTVCC Not Connected to DRVCC, DRVCC = 5.3V and: IINTVCC Varied from 0mA to –20mA IINTVCC Varied from 0mA to –30mA –0.7 V INTVCC(LOWLINE) INTVCC Voltage at Low Line VIN = 4.5V , RSET1A = RSET1B = 0Ω (~0.6VOUT, RfSET Value Recommended in Table 1) l 4.2 4.3 V DRVCC(UVLO) DRVCC Undervoltage Lockout DRVCC Rising DRVCC Falling l l 3.9 3.2 4.05 3.35 4.2 3.5 V V I DRVCC DRVCC Current INTVCC Not Connected to DRVCC, DRVCC = 5.3V , RSET1A, RSET1B and RSET2 Setting VOUT to: 1.8VOUT, RfSET = 2MΩ, 0A ≤ IOUT ≤ 10A 6.0VOUT, RfSET = Open, 0A ≤ IOUT ≤ 10A (Use RSET1A = RSET1B ≤ 8.2k) mA mA V 1VREF(DC) 1VREF DC Voltage Regulation I1VREF = 0mA I1VREF = ±1mA l l 0.985 0.980 1.000 1.000 1.015 1.020 V V PGOOD Output V PGOOD(TH) Power Good Window, Logic State T ransition Thresholds Ramping Differential VOSNS+ – VOSNS– Voltage: Up, PGOOD Goes Logic Low → High Up, PGOOD Goes Logic High → Low Down, PGOOD Goes Logic Low → High Down, PGOOD Goes Logic High → Low 533 645 621 525 556 660 644 540 579 675 667 555 mV mV mV mV V PGOOD(HYST) Hysteresis Differential VOSNS+ – VOSNS– Voltage Returning 8 16 24 mV VPGOOD(VOL) Logic-Low Output Voltage IPGOOD = 5mA l 75 400 mV tPGOOD(DELAY) PGOOD Logic-Low Blanking Time Delay Between Differential VOSNS+ – VOSNS– Voltage Exiting PGOOD Valid Window to PGOOD Going Logic Low (Note 4) 12 μs

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V , per the typical application shown in Figure 45, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power-Interrupt MOSFET Drive VVING Gate Drive Voltage for Power- Interrupt MOSFET , MSP VIN = 4.5V , 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA VIN = 28V , 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA VIN = 38V , 0A ≤ IOUT ≤ 10A, VING Sourcing 1µA VIN = 4V (Ramped Down from 4.5V), IOUT = 0A, VING Sourcing 1µA l l l l 11.5 10.5 13.3 38.4 48.4 11.5 15.5 51.5 14.2 V V V V I VING(UP) VING Pull-Up Current VING Tied to VINGP, and: VIN = 4.5V , VING Pulled to 6.5V VIN = 28V , VING Pulled to 30V l l 350 425 475 550 600 675 µA µA I VING_DOWN(CROWBAR ACTIVE,CROWBAR INACTIVE) VING Pull-Down Current VING Tied to VINGP, Pulled to 33V , and: RUN Pulled to 0V (CROWBAR Inactive) OVPGM Pulled to 0V (CROWBAR Active) l l mA mA t VING(OVP_DELAY) VING OVP Pull-Down Delay OVPGM Driven from 650mV to 550mV , VING Discharge Response Time l 1.3 2.6 µs IVINGP(LEAK) Zener Diode Leakage Current VINGP Driven to (VINH + 10V) 1 nA VINGP(CLAMP) Zener Diode Breakdown Voltage VINGP-to-VINH Differential Voltage; IVINGP = 5mA 15 V Fault Pins and Functions VOVPGM Default Output Overvoltage Program Setting OVPGM Electrically Open Circuit l 650 666 680 mV IOVPGM(UP) OVPGM Pull-Up Current OVPGM = 0V l –2.07 –2 –1.91 μA IOVPGM(DOWN) OVPGM Pull-Down Current OVPGM = 1V l 0.945 1 1.06 μA OVPTH Output Overvoltage Protection Inception Threshold Ramping Up Differential V OSNS+-to-VOSNS– Voltage Until CROWBAR Outputs Logic High l 647 666 683 mV OVPERR Output Overvoltage Protection Inception Error Difference Between OVP TH and VOVPGM (OVPTH-VOVPGM) l –12 0 12 mV tCROWBAR(OVP_DELAY) CROWBAR Response Time OVPGM Driven from 650mV to 550mV l 400 500 ns VCROWBAR(OH) CROWBAR Output, Active High Voltage OVP GM Pulled to 0V and: ICROWBAR = –100μA, IINTVCC = –20mA ICROWBAR = –4mA, IINTVCC = –20mA l l 4.3 4.2 4.65 4.55 4.9 V V V CROWBAR(OL) CROWBAR Output, Passive Low Voltage I CROWBAR = 1μA l 260 500 mV VCROWBAR(OVERSHOOT) CROWBAR Peak Voltage Overshoot at V INL Start-Up and Shutdown VINL Ramped Up from/Down to 0V l 550 900 mV VCROWBAR(TH) CROWBAR Latchoff Threshold CROWBAR Ramped Up Until HYST Goes Logic Low l 1.4 1.5 1.6 V VTEMP TEMP Voltage RUN = 0V , TA = 25°C RUN = 0V , TA = 125°C (See Figure 10 for Reference) 950 980 585 1010 mV mV OT TH(INCEPTION) TEMP Overtemperature Inception Threshold Ramping TEMP Downward Until HYST Outputs Logic Low l 428 438 448 mV OTTH(RECOVER) TEMP Overtemperature Recovery Threshold Ramping TEMP Upward Until HYST Outputs Logic High l 501 514 527 mV UVOVTH UVLO/OVLO/IOVRETRY Undervoltage/Overvoltage Inception Thresholds Ramping UVLO, OVLO or IOVRETRY Positive Until HYST Toggles Its State l 488 500 512 mV

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VINH = VINL = 28V , per the typical application shown in Figure 45, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tUVOVD UVLO/OVLO/IOVRETRY/ TEMP Response Time ±50mV Overdrive (All Pins) ±5mV Overdrive, UVLO/OVLO/IOVRETRY Pins Only (Note 4) l 125 100 500 µs µs I UVOV Input Current of UVLO, OVLO and IOVRETRY UVLO = 0.55V or OVLO = 0.45V or IOVRETRY = 0.45V l ±30 nA VHOUSEKEEPING(UVLO) Housekeeping Circuitry UVLO Voltage on INTVCC, INTVCC Rising (Note 4) Hysteresis, INTVCC Returning (Note 4) 1.9 2.1 V mV VHYST(SWITCHING ON) HYST Voltage (MHYST Off, RUN Logic High) RUN Electrically Open Circuit RUN = 1.8V l l 4.9 1.85 5.1 2.1 5.25 2.35 V V V HYST(SWITCHING OFF , RUN) HYST Voltage (MHYST Off, RUN Logic Low) RUN = 0V l 170 350 480 mV VHYST(SWITCHING OFF , FAUL T) HYST Voltage, Switching Action Inhibited (M HYST On) UVLO < UVOVTH or OVLO > UVOVTH or IOVRETRY > UVOVTH or TEMP < OTTH(INCEPTION) or CROWBAR > VCROWBAR(TH) or DRVCC < DRVCCUVLO(FALLING) (See Figures 62, 63) l 30 65 mV TMRUOTO Timeout and Power-On Reset Period CTMR = 1nF , Time from Fault Clearing to HYST Being Released by Internal Circuitry l 5 9 14 ms VLATCH(IH) LATCH Clear Threshold Input High l 1.2 V VLATCH(IL) LATCH Clear Threshold Input Low l 0.8 V ILATCH LATCH Input Current VLATCH = 7.5V l ±1 μA ITMR(UP) TMR Pull-Up Current VTMR = 0V l –1.2 –2.1 –2.8 μA ITMR(DOWN) TMR Pull-Down Current VTMR = 1.6V l 1.2 2.1 2.8 μA VTMR(DIS) Timer Disable Voltage Referenced to INTVCC l –180 –270 mV OTBHVIL OTBH Low Level Input Voltage l 0.4 V OTBHVZ OTBH Pin Voltage When Left Electrically Open Circuit –10μA ≤ I OTBH ≤ 10μA l 0.6 0.9 1.2 V IOTBH(MAX) Maximum OTBH Current OTBH Electrically Shorted to SGND l 30 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. The L TM4641 SW absolute maximum rating of 40V is verified in ATE by regulating V OUT while at 40VIN, in a controlled manner guaranteed to not affect device reliability or lifetime. Static testing of SW leakage current at 40V IN is performed at control IC wafer level only. Note 2: The L TM4641 is tested under pulsed load conditions such that T J ≈ TA. The L TM4641E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4641I is guaranteed over the –40°C to 125°C operating junction temperature range. The L TM4641MP is tested and guaranteed over the full –55°C to 125°C operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: See output current derating curves for different V IN, VOUT and TA. Note 4: 100% tested at wafer level only.

TYPICAL PERFORMANCE CHARACTERISTICS Pulse-Skipping vs Forced Continuous Mode Efficiency, 28V IN to 3.3VOUT 1V T ransient Response, 38VIN 1V T ransient Response, 4.5VIN 3.3V T ransient Response, 28V IN to 3.3VOUT Output Start-Up, No Load Efficiency vs Load Current at 36VIN Efficiency vs Load Current at 6VIN Efficiency vs Load Current at 24VIN Efficiency vs Load Current at 12VIN (Figure 45 circuit with R fSET per Table 1 and RSET1A , RSET1B and RSET2 per Table 2, unless otherwise noted) OUTPUT CURRENT (A) EFFICIENCY (%) 1 5 7

4641 G01

6.0VOUT 5.0VOUT 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT OUTPUT CURRENT (A) EFFICIENCY (%) 1 5 7

4641 G02

6.0VOUT 5.0VOUT 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT OUTPUT CURRENT (A) EFFICIENCY (%) 1 5 7

4641 G03

6.0VOUT 5.0VOUT 3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT OUTPUT CURRENT (A) EFFICIENCY (%) 1 5 7

4641 G04

3.3VOUT 2.5VOUT 1.8VOUT 1.5VOUT 1.2VOUT 1.0VOUT 0.9VOUT OUTPUT CURRENT (A) 0.001 EFFICIENCY (%)

4641 G05

0.01 0.1 1 FCB = INTVCC (PULSE-SKIPPING) FCB = SGND FORCED CONTINUOUS VOUT 50mV/DIV AC-COUPLED IOUT 2.5A/DIV 20µs/DIV 0A TO 5A LOAD STEPS AT 5A/µs FRONT PAGE CIRCUIT WITH OV PGM = OPEN CIRCUIT

4641 G06

2.5A/DIV 20µs/DIV 4641 G07 0A TO 5A LOAD STEPS AT 5A/µs FRONT PAGE CIRCUIT WITH OV PGM = OPEN CIRCUIT VOUT 50mV/DIV AC-COUPLED IOUT 2.5A/DIV 20µs/DIV 4641 G08 0A TO 5A LOAD STEPS AT 5A/µs FIGURE 46 CIRCUIT VOUT 1V/DIV IIN 200mA/DIV RUN 5V/DIV 800µs/DIV 4641 G09 VIN = 24V CIN(MLCC) = 2 × 10µF X7R

Output Start-Up, 10A Load (Figure 45 circuit with R fSET per Table 1 and RSET1A , RSET1B and RSET2 per Table 2, unless otherwise noted) TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with VINH Shorted to SW Node, 1VOUT(NOM) Start-Up with VINH Shorted to SW Node, 3.3VOUT(NOM) Autonomous Restart with VINH Shorted to SW Node, 3.3VOUT(NOM) Paralleled Modules, Current- Sharing Performance. cf. Figure 66 Circuit. 28V IN Control IC Bandgap and 1VREF Voltages vs Temperature. 28VIN Output Start-Up, Pre-Bias Condition Output Short-Circuit, No Initial Load Output Short-Circuit, 10A Initial Load VOUT 1V/DIV IIN 1A/DIV RUN 5V/DIV 800µs/DIV 4641 G10 VIN = 24V CIN(MLCC) = 2 × 10µF X7R VOUT 1V/DIV IIN 200mA/DIV ILOAD 1mA/DIV RUN 5V/DIV 800µs/DIV 4641 G11 VIN = 24V CIN(MLCC) = 2 × 10µF X7R VOUT 1V/DIV IIN 1A/DIV 20µs/DIV 4641 G12 VIN = 24V CIN(MLCC) = 2 × 10µF X7R VOUT 1V/DIV IIN 1A/DIV 20µs/DIV 4641 G13 VIN = 24V CIN(MLCC) = 2 × 10µF X7R VIN 20V/DIV VINH 2V/DIV CROWBAR 5V/DIV VOUT 200mV/DIV 400µs/DIV 4641 G14 FRONT PAGE CIRCUIT WITH VINH SHORT CIRCUITED TO SW PRIOR TO POWER-UP . APPL YING UP TO 38VIN. NO LOAD VIN 10V/DIV VINH 5V/DIV CROWBAR 5V/DIV VOUT 1V/DIV 800µs/DIV 4641 G15 FIGURE 46 CIRCUIT WITH VINH SHORT CIRCUITED TO SW PRIOR TO POWER-UP . APPL YING UP TO 38V IN. NO LOAD VIN 10V/DIV VINH 10V/DIV CROWBAR 5V/DIV VOUT 1V/DIV 100ms/DIV 4641 G16 FIGURE 46 CIRCUIT , SHORT CIRCUITING VINH TO SW IN SITU, OPERATING AT 38VIN AND NO LOAD. LATCH CONNECTED TO INTVCC AND CTMR = 47nF TOTAL OUTPUT CURRENT (A)

4641 G17

–2 MODULE OUTPUT CURRENT (A) U1 IOUT U2 IOUT JUNCTION TEMPERATURE (°C) –75

0.594 VFB BANDGAP VOLTAGE (V)

1VREF VOLTAGE (V) 0.596 0.600 0.602 0.604 –25 25 50 150

4641 G18

0.598 –50 0 75 100 125 0.606 0.994 0.996 1.000 1.002 1.004 0.998 1.006 V1VREF(DC) VFB

SGND (A1-A3; B1-B3; C1-C4; K1, K3; L3; M1-M3): Signal Ground Pins. This is the return ground path for all analog control and low power circuitry. SGND is tied to GND in- ternal to the µModule regulator in a manner that promotes the best internal signal integrity—therefore, SGND should not be connected to GND in the user’s PCB layout. See the Layout Checklist/Example section of the Applications Information section for more information pertaining to SGND and layout. All SGND pins are electrically connected to each other , internally. HYST (A4): Input Undervoltage Hysteresis Programming Pin. Normally used as an output, but can be used as an input. If the L TM4641’s inherent, default undervoltage lockout (UVLO) settings are satisfactory, 4.5V IN(RISING, MAX) and 4VIN(FALLING, MAX), HYST can be left electrically open circuit. See the Applications Information section to customize the L TM4641’s UVLO thresholds. HYST is a logic-high output with moderate pull-up strength that commands L TM4641’s internal control IC to regulate the module’s output voltage when conditions on the RUN, UVLO, OVLO, IOVRETRY, TEMP , CROWBAR, INTV CC and DRVCC pins permit it (any recent latchoff events notwith- standing, otherwise OTBH and LATCH can also play a role). When a fault condition is detected, internal circuitry (M HYST; see Figure 1) drives HYST logic low and the L TM4641’s output is turned off. HYST can be used as a fault-indicator . See the Applications Information section. HYST is pulled low when the RUN pin is pulled low, via an internal Schottky diode. HYST can be driven low by external open-collector/open-drain circuitry directly—as an alternate to the RUN pin interface. However , external circuitry should never drive HYST high, since doing so (indiscriminately) could cause thermal overstress to M HYST, when MHYST is on. TEMP (A5): Power Stage Temperature Indicator and Overtemperature Detection Pin. When left electrically open circuit, TEMP’s voltage varies according to an internal NTC (negative temperature coefficient) thermistor , residing in close proximity to L TM4641’s power stage. When TEMP falls below 438mV (corresponding to a thermistor and power stage temperature of ~145°C), the L TM4641 pulls HYST low to inhibit regulation of its output voltage. HYST may be deasserted when TEMP subsequently exceeds 514mV (nominally corresponding to a cool-off hysteresis of ~10°C), depending on the OTBH setting. (See OTBH and the Applications Information section.) To disable the µModule regulator’s overtemperature shutdown feature, connect the TEMP and 1V REF pins. The thermal shutdown inception threshold can also be modi- fied, see the Applications Information section. IOVRETRY (A6): Nonlatching Input Overvoltage Threshold Programming Pin. The L TM4641 pulls HYST low to inhibit regulation of its output voltage when IOVRETRY exceeds 0.5V . The L TM4641 can resume switching action when IOVRETRY is below 0.5V . If no nonlatching input overvoltage shutdown behavior is desired, connect this pin to SGND. Do not leave this pin open circuit. GND (A7-A12; B6-B8, B11-B12; C7-C8; D6-D8; E1-E8; F1-F12; G1-G12; H3-H9, H11-H12; J5-J12; K5-K6, K11- K12; L4-L6; M4-M6): Power ground pins for input and output returns. See the Layout Checklist/Example section of the Applications Information section. All GND pins are electrically connected to each other , internally. UVLO (B4): Input Undervoltage Lockout Programming Pin. The L TM4641 pulls HYST low to inhibit regulation of its output voltage whenever UVLO is less than 0.5V . The L TM4641 can resume switching action when UVLO exceeds 0.5V . Do not leave this pin open circuit. If the L TM4641’s default UVLO settings are used, 4.5V IN(RISING, MAX) and 4VIN(FALLING, MAX), then the UVLO pin should be electrically connected to 1VREF or INTVCC. Otherwise, see HYST and the Applications Information section for using a resistor-divider network to implement personalized UVLO rising and UVLO falling settings. OVLO (B5): Input Overvoltage Latchoff Programming Pin. L TM4641 pulls HYST low to inhibit regulation of its output voltage when OVLO exceeds 0.5V . If OVLO subsequently falls below 0.5V , the module’s output remains latched off; the L TM4641 cannot resume regulation of the output voltage until either the LATCH pin is toggled high or V INL is power cycled. If input overvoltage latchoff behavior is not desired, electrically short this pin to SGND. Do not leave this pin open circuit.

with moderate pull-down strength to SGND. crowbar the module’s output voltage (MCB, in Figure 1). leave CROWBAR electrically open circuit. inverting input pin of L TM4641’s fast OOV comparator . components (see the Applications Information section). in the Applications Information section and Appendix F.

• CROWBAR activates (see CROWBAR)
• Input latchoff overvoltage fault (see OVLO)
• Latchoff overtemperature fault (when OTBH is logic low; see TEMP and OTBH) LATCH is a high impedance input and must not be left elec- trically open circuit. LATCH can be driven by a μController in intelligent systems: a reasonable implementation for unlatching the L TM4641 is to pull LATCH logic high for the maximum anticipated timeout delay time—after which, HYST can be observed to indicate whether the L TM4641 has become unlatched. REF (C6): Buffered 1V Reference Output Pin. Minimize capacitance on this pin, to assure the OV PGM and TEMP pins are operational in a timely manner at power-up. 1VREF should never be externally loaded except as explained in the Applications Information section. VOUT (C9-C12; D9-D12; E9-E12): Power Output Pins of the L TM4641 DC/DC Converter Power Stage. All VOUT pins are electrically connected to each other , internally. Apply output load between these pins and the GND pins. It is recommended to place output decoupling capacitance directly between these pins and the GND pins. Review

Table 9. See the Layout Checklist/Example section of the Applications Information section.

the remote-sense connections prior to powering up the L TM4641. VORB+ can also be connected as a redundant feedback connection to VOSNS+ on the user’s motherboard. VORB– (D2): VOSNS– Readback Pin. This pin connects to VOSNS– internal to the µModule regulator . It is recommended to route this pin (differentially with VORB+) to a test point so as to allow the user a way to confirm the integrity of the remote-sense connections prior to powering up the L TM4641. V ORB– can also be connected as a redundant feedback connection to VOSNS– on the user’s motherboard. OTBH (D3): Overtemperature Behavior Programming Pin. When an overtemperature condition is detected (see TEMP), HYST pulls logic low to inhibit switching. If OTBH is connected to SGND, the L TM4641 latches HYST low. If OTBH is left floating, output voltage regulation can resume when the overtemperature event clears. TMR (D4): Timeout Delay Timer and Power-On Reset (POR) Programming Pin. Connect a capacitor (C TMR) from TMR to SGND to program the POR and timeout delay time of the L TM4641; 9ms delay time per nanofarad of capacitance. The minimum delay time is ~90μs, when TMR is left electrically open circuit. Even though they use the same capacitor , the power-on reset and timeout delay timers operate independently of each other . Any nonlatching fault or latching fault will reset the respective timer to the full delay time without impacting the other timer . The timeout delay time programmed by a C TMR capacitor can be negated by pulling TMR to INTVCC. RUN (D5): Run (On/Off) Control Pin. A RUN pin voltage below 0.8V will turn off the module. A voltage above 2V will command the module to turn on, if HYST is not as- serted low by M HYST. The L TM4641 contains a moderate (10k) pull-up resistor from HYST to INTVCC, and a pull-up Schottky diode from RUN to HYST (see Figure 1). When RUN is pulled logic low, HYST is pulled logic low via the internal Schottky diode. RUN is compatible with direct- drive (totem-pole output drive) as well as open-collector/ open-drain interfaces. V OSNS+ (H1): Positive Input to the Remote Sense Differ- ential Amplifier . This pin connects to the positive side of the output voltage remote sense point (VOUT potential) via a resistor (RSET1A). When regulating the output voltage, the L TM4641 control loop drives the differential voltage between V OSNS+ and V OSNS– to the lesser of TRACK/ SS and 0.6V . VOSNS+ is connected to V ORB+ internal to the module (see VORB+). A resistor may be needed from VOSNS+ to VOSNS– for some output voltage settings. (See the Applications Information section: Setting the Output Voltage.) Minimize stray capacitance to this pin to protect the integrity of the output voltage feedback signal. V OSNS– (H2): Negative Input to the Remote Sense Dif - ferential Amplifier . This pin connects to the negative side of the output voltage remote sense point (GND potential) via a resistor (R SET1B). When switching action is on, the L TM4641 control loop drives the differential voltage between V OSNS+ and V OSNS– to the lesser of TRACK/ SS and 0.6V . VOSNS– is connected to V ORB– internal to the module (see VORB–). A resistor may be needed from VOSNS+ to VOSNS– for some output voltage settings. (See the Applications Information section.) Minimize stray ca- pacitance to this pin to protect the integrity of the output voltage feedback signal. SW (H10): Switching Node of the Power Stage. Mainly used for testing purposes, however , one may optionally connect a snubber (series-configured capacitor C SW and resistor RSW) from SW to GND to reduce radiated EMI—in exchange for a minor compromise to power conversion efficiency. (See the Applications Information section.) COMP (J1): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold of L TM4641’s valley current mode control loop—and corre- spondingly, the commanded trough of the power inductor current—increases as this control voltage increases. It can be useful to make COMP available for observation on a PCB via or test pad with an oscilloscope probe. However , stray capacitance and trace lengths to this sensitive analog node should be minimized. f SET (J2): Switching Frequency Setting and Adjustment Pin. This pin interfaces directly to the ION pin of L TM4641’s internal control IC. Current flow into the ION pin programs the on-time of the control loop’s one-shot timer and power control MOSFET , MTOP. Minimize stray capacitance and any tracelengths to this pin. For applications requiring regulated output voltages of 3V or less at any time including during voltage rail tracking,

an on-time adjustment with a resistor to fSET is required. Otherwise, fSET can be left open circuit. See the Applica- tions Information section for details. VINL (J3): Input Voltage Pin, Low Current for Power Control and Logic Bias. Feeds L TM4641’s internal 5.3V LDO (see INTVCC). Apply input voltage bias between this pin and GND. Decouple to GND with a capacitor (0.1µF to 1µF). This pin powers the heart of L TM4641’s DC/DC controller and internal housekeeping ICs. V INL bias cur- rent is within ~5mA of the sum of INTVCC and CROWBAR loading currents. If using the advanced output overvoltage (OOV) protection features of the L TM4641, connect VINL to either the drain of the external power-interrupt power MOSFET , identified on the front page schematic as MSP , or a separate input bias supply. If not making use of the advanced OOV protection features, V INL and VINH can connect directly to the same input power source. LDO losses can be eliminated by connecting VINL, INTVCC, and DRVCC if a low power auxiliary ~5V rail is available to power the resulting node. (See the Applications Informa- tion section, Figure 47 and Figure 49.) DRV CC (J4): Power MOSFET Driver Input Power Pin. DRVCC is normally connected to INTVCC. It must be kept within two diode drops (2 • VBE or ~1.2V at 25°C) of INTVCC. DRVCC powers the internal MOSFET driver that interfaces to the switching MOSFETs (MTOP and MBOT) within L TM4641’s power stage. It is pinned out separately from INTV CC to allow gate-driver current to be observed, and to allow an auxiliary ~5V to 6V bias supply to optionally provide the MOSFET driver bias current. The INTV CC/DRVCC pin pair can be biased from up to 6V (absolute maximum) from an external supply with 50mA peak sourcing capability, to reduce the L TM4641’s INTV CC LDO losses (see Applica - tions Information section and Figure 51). When DRVCC is connected directly to INTV CC, no bypass capacitance is needed except in rare applications where very fast output voltage ramp up is required (e.g., no soft-start capacitor on TRACK/SS, or rail-tracking rails with sub-60µs turn-on rise-time). Otherwise, ~2.2µF to 4.7μF X7R MLCC local bypassing to GND is recommended. Higher impedance sources may require higher bypass capacitance, to mitigate DRV CC sag during VOUT start-up. An undervoltage lockout detector monitors DRVCC. HYST is pulled low and switching action is inhibited if DRVCC is less than 4.2V rising (maximum) and 3.5V falling (maximum). FCB (K2): Forced Continuous/Pulse-Skipping Mode Opera- tion Programming Pin. Connect this pin to SGND to force continuous mode operation of the synchronous power MOSFETs (M TOP and MBOT) at all output load conditions. Connect this pin to INTVCC to enable pulse-skipping mode operation: the freewheeling power switching MOSFET BOT) is turned off of to prevent reverse flow of output current (I OUT) at light loads. See Appendix E for more details. This is a high impedance input and must not be left electrically open circuit. INTV CC (K4): Internal 5.3V LDO Output. LDO operates off of VINL. The INTVCC rail biases low power control and housekeeping circuitry. INTV CC is usually connected to DRVCC to power the MOSFET drivers interfacing to the switching power MOSFETs. No decoupling capacitance is needed on this pin unless it is being used to bias external circuitry (not common); do not apply more than 4.7µF (±20% tolerance) of external decoupling capacitance. The INTV CC/DRVCC pin pair can be overdriven by an external supply, from up to 6V (absolute maximum) with 50mA peak sourcing capability, to eliminate power losses otherwise incurred by the L TM4641’s V INL-to-INTVCC linear regulator (see the Applications Information section and Figure 51). VINH (K7-10; L7-12; M7-8, 11-12): Input Voltage Pin, High Current to the Power Converter Stage of the L TM4641. All VINH pins are electrically connected to each other internally. Devote a large copper plane to connect as many of the V INH pins to each other as is feasible. This will help form a low impedance electrical connection between the input source and the L TM4641’s power stage. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the L TM4641 for a given application. If utilizing the advanced output overvoltage (OOV) protec- tion features of the L TM4641, connect V INH to the source pin(s) of the external power-interrupt MOSFET , identified on the front page schematic as MSP , with a short wide trace, or preferably a small copper plane capable of adequately

handling the input current to L TM4641’s power stage. Do not decouple the VINH pins with any bypass capacitance in this case. Instead, place all decoupling capacitance directly between the drain of MSP to GND. If not utilizing the advanced OOV protection features of the L TM4641, do decouple the V INH pins to GND with local ceramic and bulk decoupling capacitance (see the Applications Information section). PGOOD (L1): Output Voltage Power Good Indicator . This is an open-drain logic output pin that is pulled to ground when the output voltage (and accordingly, the divided-down representation of the output voltage, V FB, as presented to the control loop) is outside ±10% of the nominal target for regulation. TRACK/SS (L2): Output Voltage T racking and Soft-Start Programming Pin. This pin has a 1.0μA pull-up current source, typical. A capacitor can be placed from this pin to SGND to obtain an output voltage soft-start ramp-up rate whose turn-on time is 0.6ms per nanofarad of capacitance. Alternatively, when a voltage is applied to TRACK/SS through a resistor-divider network from another rail, the L TM4641 output is able to track the external voltage to satisfy coincident and ratiometric rail-voltage sequencing requirements. See the Applications Information section. VING (M9): Gate Drive Output Pin. If utilizing the advanced output overvoltage (OOV) protection features of the L TM4641, connect V ING to VINGP and to the gate of the external power-interrupt N-channel MOSFET feeding VINH, identified on the front page schematic as MSP; otherwise, leave this pin electrically open circuit. V INGP (M10): Gate Drive Protection Pin. If utilizing the ad- vanced OOV protection features of the L TM4641, connect VINGP to VING and to the gate of the external power-interrupt N-channel MOSFET feeding VINH, MSP; otherwise, leave this pin electrically open circuit.

Figure 1. Simplified Block Diagram. cf. Functional Block Diagram in Appendix A, Figure 62

4641 F01

Figure 1. For a more detailed look, the Functional Block Diagram is found in Appendix A, Figure 62. and much more. To view the latest report visit http://www. insurance beyond other μModule regulators.

APPLICATIONS INFORMATION—POWER SUPPLY FEATURES The operation of MSP as a power interrupter provides a critical element of robust OOV protection: it removes a means for input power to flow through a damaged power stage to any precious loads on the output voltage rail, even when input power is cycled. For even greater resilience to a short-circuit between V INH and the SW switching node of the power stage, an external logic-level N-channel power MOSFET , MCB, is optionally placed—in a crowbar configuration—on the output of the power module. When an OOV condition is detected, CROWBAR turns on MCB (within 500ns, maximum) to discharge the output capacitors and transform any residual energy in L TM4641’s power stage into a trivial amount of heat—energy which would otherwise have only served to inject charge into (further pump up the voltage on) the output capacitors, where precious loads reside. The control and monitoring circuitry within the L TM4641 power module provide the following:

• Fast, accurate, latching output overvoltage detector (<500ns response time, <±12mv threshold error)
• N-channel output overvoltage crowbar power MOSFET drive
• Accurate (<±2.4%) nonlatching and resettable latching input overvoltage shutdown thresholds
• N-channel overvoltage power-interrupt MOSFET drive
• Accurate (<±2.4%) Input UVLO rising and UVLO falling thresholds
• Built-in and adjustable overtemperature shutdown protection, programmable for resettable latching or nonlatching (hysteretic restart) response
• Analog temperature indicator output pin
• Adjustable power-on reset and timeout delay time
• Latchoff behavior that can be altered to instead provide autonomous restart after timeout delay time expires
• Parallelable for higher output power
• Differential remote sensing of POL voltage
• Internal loop compensation
• Output current foldback protection
• Selectable pulse-skipping mode operation
• Output voltage soft-start and rail tracking
• Power-up into pre-biased conditions without sinking current from the output capacitors
• Adjustable switching frequency
• Power good indicator
• RUN enable pin Novel and simple circuit implementations with L TM4641 and a few external components enable surge ride- through protection and overtemperature detection of a power-interrupt MOSFET . (See Figure 47, for example.) The aforementioned features enabled by L TM4641 are grouped by function and described in the remainder of the Applications Information section. Power (V INH) and Bias (VINL) Input Pins L TM4641’s power stage (VINH) and control bias (V INL) input pins are brought out separately to allow freedom for implementing more sophisticated system configura- tions, such as: fully utilizing L TM4641’s advanced output overvoltage (OOV) protection features to protect the load (e.g., front page schematic or Figure 46); providing rudi- mentary input surge ride-through protection (Figure 47); performing DC/DC down conversion from a power rail below L TM4641’s inherent UVLO thresholds (from a 3.3V bus in Figure 49). If V INH and V INL are powered from separate rails, it is recommended to power up VINL prior to or concurrently with VINH. VINL should have a final value of at minimum 3.5V within 2ms of VINH exceeding 3.5V . The recommen- dation to sequence VINL ahead of or closely with V INH is not related at all to module device reliability but stems rather from a desire to assure that the control section of L TM4641 drives the MOSFETs in L TM4641’s power stage deterministically whenever any appreciable V INH voltage is present. It is always permissible for VINL voltage to be present—regardless of the state of VINH—however , realize that there is no UVLO detection on VINH. To prevent the control section from trying to regulate through a dropout condition or commencing switching activity in the absence of V INH potential, it is recommended

dropout curve in Figure 4 (see also Figure 11). a discharge path for VINL in the event of loss of VIN. L TM4641 in the Figure 45 and Figure 46 circuits. returns to normal (an overcurrent event, notwithstanding). Figure 2. Start-Up and Shutdown Waveforms of Figure

4641 F02

maximum achievable switching frequency of operation. where VINL is in units of volts and RfSET is in units of ohms. equal to 3VOUT, and for rail-tracking applications. cal, but guard banded conservatively to 75ns, maximum. should be designed to be less than 93.3μA. output voltage, in units of volts.

• Why should the switching controller be operated at a higher switching frequency (i.e., programmed for a shorter on-time with R fSET) than that yielded by the internal 1.3MΩ VINL-to-fSET resistor alone… …for nominal output voltages of 3V and less? …in rail-tracking applications?
• When VINL and V INH are operated from separate supplies… … why should RfSET ordinarily connect to the VIN power source rather than VINH (Figure 49)? …when is it okay for R fSET to connect to V INH (Figure 47)? For application circuits of the form found in Figure 45, Figure 46, Figure 47 and Figure 51: see Figure 3 for the maximum recommended value of R fSET as a function of nominal target output voltage, and resulting full-load switching frequency corresponding to those R fSET values. Figure 3 can also be interpreted to provide the lowest recommended switching frequency for a given target output voltage. Table 1 summarizes nominal values of R fSET endorsed for some popular output voltages; use of commonly available ±5% tolerance resistors or better with ±100ppm/°C temperature coefficient or better is recommended.

Figure 3. Maximum Recommended R fSET (Nominal Values) for

4641 F03

Table 1. Endorsed RfSET Resistor Value vs Output Voltage for not more than 750kΩ (nominal) per Figure 3. control loop’s current comparator , and turn off MBOT.

• VOUT is nominal output voltage in volts.
• tOFF(MIN) is the minimum length of time MBOT can be on, after MTOP turns off. For a conservative de- sign, use a value of 300ns, taken from the Electrical Characteristics Table.
• tON is the on-time of the power control MOSFET , MTOP, as programmed by the current flowing into the ION pin of L TM4641’s internal control IC.
• RPS is the series resistance of the module’s power stage, from VINH to VOUT. For VIN ≥ 6V , this is less than 50mΩ, even at extreme temperatures (T J ≈ 125°C). For VIN < 6V , the effective series resistance increases due to drop in INTV CC voltage and cor- responding decreased gate-drive enhancement of M TOP. Printed circuit board (PCB) and/or cable resistance present in the copper planes and/or wires that physically connect the output of the module to the load adds to R PS’s effective value.
• IOUT is the load current on VOUT in amperes. For applications of the form shown in Figure 45, Fig- ure 46 and Figure 47: the minimum allowable V INH voltage of operation to avoid dropout for 3V < V OUT ≤ 6V is shown in Figure 4. The curves are a result of realizing that V IN(DROPOUT) equals V INH (neglecting MSP voltage drop) when dropout actually occurs, and that Equations 1 and 2 yield an expression for t ON as a function of V INH. MTOP will be less fully enhanced during its on-time if DRV CC is less than its nominal value of 5.3V (for example, when VINL< 6V and when DRVCC bias is provided by INTVCC). DRVCC’s effect on RPS at low line is illustrated in Figure 4. III. Maximum Attainable f SW. The maximum attainable switching frequency of operation (in units of Hz) for a given on-time (t ON, in seconds) is governed simply by: fMAX = 1 tON + tOFF(MIN) (8) where a conservative value of 300ns can be used for tOFF(MIN).

Figure 4. Line Dropout Voltage vs Output Voltage at No count by the system designer . over line, load, and temperature is better than ±1.5%. module’s feedback sense pins is shown in Figure 5. Figure 5. Basic Feedback Remote Sense Connections and Techniques; Setting the Output Voltage

4641 F05

TWISTED PAIR IF USING WIRES).

4641 F04

APPLICATIONS INFORMATION—POWER SUPPLY FEATURES The output voltage at the POL is differentially sensed via a symmetrical impedance-divider network. In Figure 1 and Figure 5, it is seen that the control loop regulates the output voltage such that the differential V OSNS+-to-VOSNS– feedback signal voltage is the lesser of the TRACK/SS pin voltage or the regulator’s nominal bandgap voltage of 600mV . The arrangement and values of the resistors in the symmetrical impedance-divider network set the output voltage. The remote sense pins (V OSNS+, VOSNS–) have redundant connections internal to the module to readback pins (VORB+, VORB–). The readback pins provide a means to verify the integrity of the feedback signal connection during moth- erboard ICT (in circuit test). The importance of verifying the integrity of the connection of the feedback signal to the output voltage prior to powering up the input voltage cannot be understated. If one or both feedback pins are left electrically floating due to manufacturing assembly defect, for example, or if the remote-sense pins are short circuited to each other , the control loop and overvoltage- detector circuitry have no awareness of the actual output voltage condition. A compromised feedback connection presents a very real danger of (1) the control loop com - manding on M TOP at the highest possible duty cycle—due to the lack of negative feedback—and (2) the L TM4641’s protection circuitry being unaware of any issue. In a pro- duction environment, modern day ICT can easily catch any such stuffing or assembly errors; in a lab or prototyping environment, an ohmmeter can do the job. For many applications that use a mixture of MLCC and bulk (low ESR tantalum or polymer) output capacitors, the symmetrical impedance-divider network that feeds back the POL ’s voltage to the module need only be constructed with resistors R SET1A and R SET1B, for output voltages of 1.2VOUT and lower . RSET2 must be present for output voltages in excess of 1.2VOUT. RSET1A and RSET1B should always have the same nominal value. Applications with MLCC-only output capacitors (see Output Capacitors and Loop Stability in following pages) will demonstrate improved transient response when feedforward capaci - tors C FFA and CFFB, nominally equal in value, are installed electrically in parallel with RSET1A and RSET1B, respectively. Use of 0.1% tolerance resistors (or better) for R SET1A, RSET1B, and RSET2 are recommended—with temperature coefficients of resistance suitable for one’s operating range of PCB temperature—to assure that output voltage error introduced by resistor value variation is acceptable for the application. SMT resistors with T .C.R.s of ±25ppm/°C and better are readily available in the marketplace. For output voltage settings less than or equal to 1.2V OUT, RSET2 is not needed, and RSET1A and RSET1B are given by: RSET1A = RSET1 B= VOUT 0.6V –1    •8.2kΩ (9) For output voltages above 1.2VOUT, RSET1A (and RSET1B) should be set equal to 8.2kΩ (or less, if 8.2kΩ is not a convenient value for the user), and RSET2 is then given by: RSET2 = 2•RSET1A VOUT 0.6 – RSET1A 8.2kΩ − 1 (10) It is always permissible to select a value for RSET1A (and RSET1B) less than that given by Equation 9—and then calculate a valid value for R SET2 from Equation 10—as long as RSET1A and RSET1B are designed to withstand the higher resulting power dissipation. When VOUT is in regulation, the voltages at V OSNS+ and VOSNS– are given by: VVOSNS+ = 0.6V 8.2kΩ ||RSET1A ||RSET2( ) + ∆ VGND RSET1A

• RSET1A ||16.4kΩ( ) (11) and VVOSNS– = VVOSNS+ – 0.6V (12) respectively. ∆VGND is the voltage drop between ground at the POL and L TM4641’s SGND pins in volts. This voltage drop is usually entirely a result of I • R drop in the output distribution path—largest when maximum load current is being drawn: ∆VGND = VGND(POL) – VSGND(L TM4641) (13)

for popular output voltages are shown in Table 2. Table 2. Recommended RSET1A, RSET1B and RSET2 Values

• What is the rationale for using a symmetrical resistor network?
• What should I do if I cannot shield the differential sense feedback lines with GND? (I anticipate differential mode noise in the feedback signal?)
• What should I do if the module and the load(s) are separated by a significant distance (~50cm or more), or if the load current flows through a cable assembly or power connector? (I anticipate common mode noise in the feedback signal?) Input Capacitors The L TM4641 module should be connected to a low AC impedance, nominally DC output voltage source. MLCC input bypass capacitors must be provided externally, as close in proximity to the module as possible (see Figure 43). If external MOSFET MSP is not used (Figure 45), two 10μF or four 4.7μF ceramic capacitors should be electrically connected directly between the V INH and GND pins. If MSP is used (Figure 46, Figure 47 and Figure 49), then MSP must be placed as close to the L TM4641’s V INH pins as possible, and two 10μF or four 4.7μF ceramic capaci- tors should be electrically connected directly between the drain of MSP and GND (see Figure 44). A 47μF to 100μF surface mount bulk capacitor can be used to supplement input power bypassing, and can share the burden of any local ceramic capacitors in filtering the power stage’s ripple current. If low impedance power planes are used to bring V IN to the vicinity of the module, input source impedance will be low enough that bulk capacitors will not be needed. A localized bulk input capacitor is needed when an underdamped LC-resonant tank is formed by routing long input leads or traces (low ESR inductance) bypassed only with MLCCs (ultralow ESR capacitance). Neglecting the inductor peak-to-peak current ripple, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η • D• 1–D( ) (15) where η is the power conversion efficiency of the L TM4641 module and D is the duty cycle on-time of MTOP. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor or a polymer capacitor . For a buck converter , the switching duty cycle of M TOP can be estimated as: D= VOUT VIN (16) Output Capacitors and Loop Stability/Loop Compensation The current mode constant on-time architecture enables very high step-down input-to-output ratios with compel- ling transient response. It also enables cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. The L TM4641 is internally compensated to yield stability over all operating conditions.

APPLICATIONS INFORMATION—POWER SUPPLY FEATURES The output capacitors C OUT(BULK) and C OUT(MLCC) must be chosen with low enough effective series resistance (ESR) to meet the output voltage ripple requirements and provide localized bypassing for the load. Although the L TM4641 provides fast transient response, the output voltage at the POL is reliant on nearby charge stored in a reservoir of ceramic capacitors C OUT(MLCC) to minimize sag and overshoot in the initial microseconds of a high dI/dt transient load step-up and step-down, respectively. If used, C OUT(BULK) can be comprised of low ESR tantalum or low ESR polymer capacitor(s); these capacitors then serve as a local reservoir to replenish the MLCCs during transient load events. It is also possible to use C OUT(MLCC) only, however , the use of feedforward capacitors, C FF, should then be installed in the remote-sense feedback path, to obtain an optimized transient response (see Figure 5 feedback connections). The C OUT(MLCC) ceramic capacitors should be at least X5R-type material. X5R-type and X7R-type MLCCs are recommended when operating PCB temperatures are not more than 85°C and 125°C, respectively. Both materials are renown in the industry for having a relatively low ca- pacitance change over their respective temperature range of operation (±15%). However , X5R and X7R MLCCs do exhibit significant loss of capacitance with applied DC voltage and are subject to aging effects, and this must be taken into account in any system design. Refer to the capacitor manufacturer’s specifications for details. The typical output capacitance range is between 200μF to 800μF . The system designer should use discretion in determining whether additional output filtering may be needed, if further reduction of output ripple—or output voltage deviation during dynamic load or line transient events—is required. In Table 9, guidelines are provided for output capacitor selection, for various operating conditions. The table optimizes total equivalent ESR and total bulk capacitance for the transient load step performance. Stability criteria is considered. The Linear Technology L TpowerCAD™ de- sign tool is available for transient simulation and stability analysis, if desired. Pulse-Skipping Mode vs Forced Continuous Mode In applications where high DC/DC conversion efficiency at light-load currents is highly desired—when the input voltage source is a battery, for example—pulse-skipping mode operation should be employed. Pulse-skipping mode operation prevents power flow from the output capacitors to the input source. Be aware, however , due to M BOT’s re- sulting asynchronous operation at light load, applications employing pulse-skipping mode may necessitate more output capacitance and/or a higher OV PGM setting than operation in forced continuous mode would. Pulse-skipping mode is activated by connecting FCB to INTVCC. Forced continuous operation is activated by con- necting FCB to SGND. Be aware that in pulse-skipping mode and ultralight loads (say, less than 20mA out), the VING voltage may appear as a sawtooth waveform as a result of being charge-pumped at a slower rate, to conserve energy. See Appendix E for more information on how pulse-skipping mode works. Soft-Start, Rail-T racking and Start-Up Into Pre-Bias The TRACK/SS pin can be used to either soft-start the output of the L TM4641 regulator , or make L TM4641’s output voltage track another rail coincidentally or ratio- metrically. When RUN or HYST is low, the TRACK/SS pin is discharged. When RUN and HYST are released, TRACK/SS sources a microamp of current. When a soft-start capacitor , CSS, is applied to the pin, the current source is responsible for generating an output volt- age turn-on time of 0.6ms per nanofarad of capacitance. The power stage is high impedance (M TOP and M BOT are off) until the TRACK/SS pin voltage exceeds VFB, the remote-sense differential amplifier’s output voltage. This allows power-up into pre-biased output voltage conditions without sinking of current from the output capacitors. When TRACK/SS exceeds the control IC’s 600mV bandgap voltage, V FB is regulated at 600mV and VOUT reaches its nominal output voltage.

TAC/RTBC network are sufficiently small.

4641 F06a

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Figure 6. Two Different Modes of Output Voltage Tracking propriate for the final, “full-scale” (FS) output voltage. ramp down of the output voltage to the desired value. voltage of the L TM4641 generated rail.

Figure 7. Examples of LTM4641 Performing Coincident and Ratiometric Rail-Tracking. cf. Figure 8 Waveforms

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1,U1, U2 AND U3 SGND ( ) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES.

source on TRACK/SS are sufficiently small. on the VOUT_SLAVE_C and VOUT_SLAVE_R outputs. Figure 8. Output Voltage Waveforms of U1, U2 and U3. cf. through a Schottky diode, as shown in the Figure 51 circuit.

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input surge current and output voltage overshoot.

tolerance) of external decoupling capacitance. 25°C, B-value < 5000K)—in the manner shown in Figure 47. REF beyond ±100μA is not recommended. and the resulting impact to OVPGM’s voltage waveform. NTC resistance, and TEMP voltage is found in Figure 10. 438mV , a latchoff overtemperature event is registered. is explained in detail in the Start-Up/Shutdown section. exceeds 125°C when overtemperature protection is active. erating junction temperature may impair device reliability.

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Figure 9. Response of 1V REF to 0μA ⇔ 100μA Load Steps

in detail in the Start-Up/Shutdown section. entering a region of possible dropout operation (Figure 51). INH when VINL is biased from an auxiliary rail (Figure 49). returns to normal temperatures. pins’ functions in greater detail.

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Figure 10. Relationship of NTC Resistance to Junction Figure 11. Setting the LTM4641 Custom UVLO Rising and

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SGND CONNECTS TO GND INTERNAL TO MODULE.

APPLICATIONS INFORMATION—INPUT PROTECTION FEATURES Variables to define up-front are as follows:

• VSU: VIN start-up voltage, in volts. This is the custom- ized UVLO rising voltage.
• VSD: VIN shutdown voltage, in volts. This is the custom- ized UVLO falling voltage.
• VHYST: The value of the voltage on the HYST pin (in volts) when switching action is on and just prior to the input voltage (VIN) falling below VSD.
• RHYST: The hysteresis-setting resistor . If used, RHYST is recommended to take on a value of 1MΩ or higher , so that the HYST voltage is negligibly affected by external loading.
• V OV: The input voltage above which a latchoff input overvoltage event occurs.
• VRT: The input voltage above which a nonlatching input overvoltage event occurs. Then, RTUV and RBUV are given by: RTUV = VSU − VSD VHYST
• RHYST (20) and RBUV = UVOVTH VSU − UVOVTH RTUV – UVOVTH RHYST (21) UVOVTH is nominally 0.5V , from the Electrical Characteris- tics Table. The value of VHYST used in the above equations requires more careful consideration. Review Figure 1 and assess system details of the specific application in which the L TM4641 is being placed. It is known from the Electri- cal Characteristics table that when V INL ≥ 6V that INTVCC = 5.3V; and we see the voltage on the HYST pin, when switching action is on, is V HYST(SWITCHING_ON), 5.1V— nominally. Observe that if the RUN pin were driven high by 3.3V logic, however , that V HYST would be a Schottky diode forward-voltage drop above 3.3V—and V HYST in that instance would be 3.6V . If VSD is targeted below 6VIN, it is necessary to consider that V HYST’s pull-up voltage, INTVCC, is decreasing with V INL. For example, at V INL = 4.5V input, INTVCC is nominally 4.3V (VINTVCC(LOWLINE)), and it is inferred (in that scenario) that V HYST would be closer to 4.1V , when RUN is floating. It is the moderately weak pull-up strength of HYST (10kΩ pull-up to INTV CC), and the desire for any loading of the HYST signal to negligibly alter the HYST logic-high output voltage level (less than ~50mV), that motivates a high impedance (~1MΩ) hysteresis-setting resistor to interface between HYST and UVLO, when custom UVLO settings are desired. The customized UVLO start-up and shutdown input voltage settings can be double-checked with: VSU = UVOVTH • RTUV RBUV ||RHYST + 1 (22) VSD = VSU – VHYST RHYST
• RTUV (23) To set the input overvoltage (latching and nonlatching) thresholds, choose first how much current, IDIV, to continu- ally have drawn by the R TOV/RMOV/RBOV resistor-divider string for this function, at ultrahigh line. 10μA to 20µA is a normal amount to allocate. The total resistance of the divider string is then given by: RTOT = VOV IDIV (24) Then, the resistors in the input overvoltage divider are given by: RBOV = RTOT •UVOVTH VOV (25) RMOV = UVOVTH •RTOT • 1 VRT – 1 VOV , (26) RTOV = RTOT – RM – RB (27) It may be tempting to try rearranging these equations so that RTOV’s value is fixed, first, and to compute RMOV and R BOV subsequently. However , due to large divide- down ratio (usually) of ultrahigh line input voltage down to these pins with ~0.5V thresholds, the rounding off of R MOV and RBOV to nearest EIA standard values after fixing

characteristics shown in Figure 12.

• RUN exceeds 1.25V (nominal; 2V, overtemperature); power-on reset (POR) and timeout delay times do not apply to RUN.
• All nonlatching fault-monitor pins have been in their operationally valid states for the full duration of the POR delay time, set optionally by C TMR (the capacitor on the TMR pin). Explicit pins and operationally valid thresholds follow: a. DRVCC > 4.05V . In the circuits of Figures 45 and 46, this is guaranteed for VINL ≥ 4.5V , minimum. In Figure 49, this requirement is met when the auxiliary bias supply exceeds 4.05V . b. UVLO > 500mV c. IOVRETRY < 500mV d. TEMP > 514mV (when OTBH is electrically open circuit)
• No latchoff fault conditions are present, and the LTM4641 is not in a “latched off” state from any previously detected latchoff fault condition. If a latchoff fault condition oc- curs/occurred, the L TM4641 must be unlatched by a logic high LATCH signal: if all latchoff fault-monitoring pins are in operationally valid states when LATCH transitions from logic low to high, the L TM4641 becomes immediately unlatched; if, instead, any latchoff fault-monitoring pin is outside its operationally valid state when LATCH is logic high, the L TM4641 becomes unlatched if LATCH remains logic high after all latchoff fault-monitoring pins have been in their operationally valid states for the full duration of the timeout delay time (set optionally by C TMR). Explicit pins and operationally valid thresholds follow: a. OVLO < 500mV b. TEMP > 514mV (when OTBH is logic low) c. CROWBAR < 1.5V The POR and timeout delay time is 9ms per nanofarad of C TMR capacitance. If C TMR is not used, the POR and timeout delay time is ~90μs.

Figure 12. Transient Duration vs Comparator Overdrive

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APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES If any nonlatching fault conditions occur , internal circuitry pulls HYST low and switching action is inhibited. The power stage will be high impedance until the aforementioned start- up conditions are met. If any latchoff fault condition occurs, HYST is latched low and switching action is inhibited until the L TM4641 is unlatched (by pulling LATCH logic high) or V INL power is recycled (with INTVCC falling below 2V). The L TM4641 can be configured to restart autonomously after an adjustable timeout delay time—instead of ex- hibiting latchoff behavior—by leaving LATCH logic high (connected to INTV CC, for example) and setting the hiccup retry timeout delay time with C TMR (see Figure 47). Be reminded that use of CTMR also introduces POR behavior , yet the POR and timeout delay timers operate indepen - dently. The effect of CTMR can be negated by pulling the TMR pin to INTVCC. Switching action will be inhibited if any of the following occur:

• RUN is less than 1.15V (nominal; 0.8V, overtemperature). Not a fault; no POR or timeout delay time is imposed.
• Any nonlatching faults occur: a. DRVCC falls below 3.35V . In the Figure 45 and Figure 46 circuits, this happens at VINL < 4V , maximum. b. UVLO falls below 0.5V . c. IOVRETRY exceeds 0.5V . d. TEMP falls below 438mV when OTBH is electrically open circuit.
• Any latchoff faults occur: a. OVLO exceeds 0.5V . b. CROWBAR exceeds 1.5V . c. TEMP falls below 438mV when OTBH is logic low. The L TM4641’s state diagram is provided in Appendix B. Start-up and shutdown mechanisms for any given op - erating scenario are identified in the state diagram. The TEMP and DRV CC pins have built-in hysteresis. The UVLO, IOVRETRY, OVLO, TEMP , CROWBAR and DRVCC pins con- nect to comparators with built-in glitch immunity, with characteristics indicated in Figure 12. Overcurrent Foldback Protection The L TM4641 has overcurrent protection (OCP). In a short circuit from V OUT to GND, the internal current comparator threshold folds back during a short to reduce the output current, progressively down to about one-third of its normal value (down from 24A to 8A, typical). To recover from foldback current limit, the excessive load or low impedance short needs to be removed. Foldback current limiting action is disabled during soft-start and tracking start-up. Power Good Indicator and Latching Output Overvoltage Protection Internal overvoltage and undervoltage comparators assert the open-drain PGOOD output logic low if the output voltage is outside ±10% of nominal, after a 12μs “blanking time”. The blanking time allows the output voltage to experience brief excursions (due to large load-step transients, for example) without nuisance-tripping PGOOD. The PGOOD output is deasserted without any deliberate blanking time when the output voltage returns to (or enters) the power good window, with ~2% to 3% of hysteresis. If the feed- back voltage exceeds the upper PGOOD valid limit, the synchronous power MOSFET , M BOT, turns on (with no blanking time)—to try sinking current from the output to GND, through L TM4641’s power inductor—until the output voltage returns to the PGOOD valid region. If the output voltage exceeds an adjustable threshold set by OV PGM, whose default value corresponds to 11% above nominal, the L TM4641 pulls its CROWBAR output logic high imme- diately (500ns response time, maximum) and latches off its output voltage: the power stage becomes high impedance, with both M TOP and MBOT turning off and staying latched off; furthermore, MSP’s gate is pulled to V INH potential rapidly (<2.6μs response time, maximum), to disconnect the input source voltage from the module’s power stage. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. The behavior of turning on the synchronous MOSFET dur- ing detection of an output overvoltage is a rudimentary and popular kind of output overvoltage protection scheme commonly found in the power supply and semiconductor control IC industry. It can provide mediocre overvoltage

APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES protection during severe load current step-down events, but is not very effective at protecting loads from genuine fault conditions such as a short circuited high side power switching MOSFET . Furthermore, such schemes tend to be implemented with the overvoltage detector’s threshold dependent on the same bandgap voltage that the output is being regulated to. Applications needing superior output overvoltage and load protection require the performance achieved with the output crowbar MOSFET , MCB and power interrupt switch, MSP , and L TM4641’s use of an independent reference voltage(1V REF) to generate an OOV threshold. Power-Interrupt MOSFET (MSP), CROWBAR Pin and Output CROWBAR MOSFET (MCB) Within 500ns (maximum) of the control-loop-referred feedback signal, V FB, exceeding the voltage on OV PGM (plus-or-minus OVPERR), an OOV event is detected, and the CROWBAR output swings high enough to turn on an optional crowbaring device (MCB) residing on V OUT. No more than 2.6µs after OOV detection, VING is discharged and an optional power interrupt switch, MSP , disconnects the L TM4641’s power stage from the input source supply. When MCB and MSP are used in conjunction as shown in the Figure 46 circuit, the L TM4641 is able to provide best- in-class output overvoltage protection against arguably the most despised failure mode high step-down buck convert- ers can theoretically suffer: an electrical short between the input source to the output, via the switching node. Turning on MCB upon detection of OOV helps discharge the output capacitors and prevent any further positive ex- cursion of output voltage by transforming residual energy in L TM4641’s power stage into heat; meanwhile, turning off MSP removes a path for current flow between the in- put power source and the output—preventing hazardous (input) voltage from reaching the precious load. It should be noted that when an OOV event is detected, CROWBAR is not held high (equivalently, MCB is not left turned on) indefinitely. The act of pulling CROWBAR high (above 1.5V nominal), whether due to internal or external circuitry, invokes a latchoff response and strong discharge of V ING; HYST is latched low and switching action is inhibited after CROWBAR overcomes the glitch immunity require- ment (see Figure 12). The fast OOV comparator’s output is fed through a blocking PN diode into a 10nF capacitor on the CROWBAR output; internal circuitry interfacing to CROWBAR presents itself as a ~10kΩ load (see Figure 62 in Appendix A). The use of the PN diode and 10nF capaci- tor creates a way for the CROWBAR output to stay logic high, even if the duration of OOV is very brief, and assures the glitch immunity of the latchoff detection circuitry is overcome. The 10kΩ load and 10nF capacitor provide an upper bound for the duration of time MCB might be on after CROWBAR activates: 400μs, or four time constants. Parasitic capacitance on the gate of MCB may increase this time, slightly. Observe that when HYST is low, the noninverting input to the fast OOV comparator (see Appendix A) is clamped by a Schottky diode. (When RUN is low, the noninverting input to the fast OOV comparator is clamped by two series Schottky diodes.) This differs from when switching ac - tion is engaged, where the noninverting input to the fast OOV comparator is normally the V FB signal. Therefore, be aware that the CROWBAR output is nominally inhibited when switching action is inhibited. Restarting regulation after a latchoff event has occurred is explained in detail in the Start-Up/Shutdown section. MCB should be placed close to the majority of the load(s)’s bulk and MLCC local bypass capacitors. CROWBAR should be connected to the gate of MCB with a generous signal trace width (20mils, or 0.5mm), to support driving the peak current needed to turn on MCB upon OOV detection. At the instant that MCB turns on, it typically draws hundreds of amps from the output capacitors which are mainly located near the load. When MCB turns off, the B-field that may have been built up in the parasitic inductance in the cop- per plane between the output capacitors and MCB cannot vanish instantaneously, and the collapsing of that B-field can induce a negative voltage across the output capacitors and load. Closer proximity of MCB to the majority of the output capacitors minimizes this parasitic inductance and hence the resulting magnitude of the negative voltage spike. MCB must be selected according to the following criteria:

• MCB must be a logic-level N-channel MOSFET
• The drain-to-source rating of MCB must be greater than the maximum output voltage, VOUT(PEAK,OOV_DETECTED)

APPLICATIONS INFORMATION—LOAD PROTECTION FEATURES

• When CROWBAR goes logic high, the peak drain cur- rent in MCB will be given by VOUT(PEAK,OOV_DETECTED)/ RDS(ON). The peak drain current, and its duration, must not exceed the maximum safe operating area of the MOSFET ; consult the MOSFET vendor’s data sheet. An upper bound for MCB’s on-time is 400μs. However , this worst-case conduction time can only happen if the output capacitance on V OUT is extraordinarily large. The length of time that MCB can possibly conduct ultrahigh drain current is also bounded by 4 • RDS(ON) • COUT(TOTAL). In a majority of applications, output capacitance is low enough that MCB does not conduct ultrahigh drain current for longer than a few microseconds, as seen on the front page.
• MCB’s junction temperature must not exceed its specified maximum at any time. Consult the MOSFET vendor’s data sheet for device thermal characteristics for “single shot” thermal transients or “single pulse” power-handling capability. The peak power sustained by MCB is V OUT(PEAK,OOV_DETECTED)2/RDS(ON). If MCB is used and it is expected that LATCH will be toggled high (to unlatch the L TM4641) or held logic high continuously (for automatic L TM4641 restart after fault- off), recognize that peak power sustained by MCB during CROWBAR activity may not be single pulse anymore. Therefore, to prevent MCB thermal overstress in such applications, it is recommended to use C TMR to set a rea- sonable cool-down period for the MOSFET . Additionally, one may opt to implement a circuit that shuts down the L TM4641 when MCB temperature is detected to be too high: a minor modification to Figure 47, RT1 would be located as close in proximity to MCB as possible (instead of MSP), and R1, R2, and R3 would be experimentally determined. Consult the MOSFET vendor’s data sheet for maximum rated junction temperature and device thermal characteristics for repeated pulsed-power transients. When using MSP , connect V ING to VINGP and to the gate of MSP . See the Input Capacitors section (earlier) for informa- tion on the input bypassing technique when MSP is used. MSP must be selected according to the following criteria:
• MSP can be either a standard logic or a logic-level N-channel MOSFET .
• The drain-to-source breakdown voltage of MSP must be greater than the maximum input source voltage. Consult the MOSFET vendor’s data sheet and consider temperature effects.
• In order to support very fast turn-on of output volt- age (e.g., sub 1ms ramp up), MSP should be turned on quickly to bring up V INH quickly. Therefore, a gate input capacitance (CISS) below 4.7nF is preferred (less is better).
• MSP must be able to conduct the maximum input current to the L TM4641’s power stage without getting too hot. Choose a suitable MOSFET package size and R DS(ON) that results in reasonable MOSFET junction temperature rise. Be mindful that I Q(VINH) is highest during low line operation. Blowing a series-pass input fuse with a crowbaring SCR can be an effective overvoltage protection scheme for higher output voltages, e.g., 5V , but a crowbaring MOSFET on the output of the converter is more effective at clamping the output voltage. For the same current, the power MOSFET will have much less voltage drop than the PN-junction voltage drop of an SCR. SCR-based circuits involving the L TM4641 are not presented here. Evaluation of induced or simulated overvoltage events on a demo board (such as DC1543) is recommended to ensure the end result meets the user’s expectations. Fast Output Overvoltage Comparator Threshold O VPGM is nominally biased by internal circuitry to 666mV , according to a 499kΩ and 1MΩ resistor-divider network internal to the L TM4641 driven from the 1VREF. This pin connects directly to the inverting input of the fast OOV comparator—setting the trip threshold that the control-loop-referred feedback voltage, V FB, would have to exceed to result in CROWBAR becoming logic high. Recall that the control-loop pulse frequency modu- lates M TOP such that V FB is driven to the lesser of the TRACK/SS pin or the bandgap reference voltage of 600mV . When TRACK/SS (and hence, the output voltage) has been fully ramped up, the 666mV on OV PGM represents an OOV setting 11% above nominal output voltage. To increase the OOV threshold, a resistor can be connected externally from 1V REF to OV PGM; to decrease the OOV threshold, a resistor can be connected externally from

with an external resistor divider comprised of low T .C.R. MOSFETs in L TM4641’s power stage. cuits. A value between 0.7Ω and 4.2Ω is normal.

1. In the examples shown, the snubber networks reduce

EMI signal amplitude by as much as ~5dB. when a high side MOSFET fault condition is simulated. Figure 13. Radiated Emissions Scan of LTM4641 Producing Figure 14. Radiated Emissions Scan of LTM4641 Producing

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output overvoltage protection. waveform and are contained in the reflected input current. if attenuation of the reflected input currents is desired. so paralleled modules demonstrate good current sharing. differences between paralleled modules.

• V OUT
• GND
• V INH
• VINL
• HYST (to synchronize start-up and shutdown)
• TRACK/SS
• COMP (to accomplish current sharing)
• CROWBAR (to syn chronize out put ove rvoltage response)
• LATCH (to reset all modules after a latchoff event)
• VING, if MSP is used APPLICATIONS INFORMATION—EMI PERFORMANCE FREQUENCY (MHz) –10 SIGNAL AMPLITUDE (dB µV/m)

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Figure 15. Radiated Emissions Scan of LTM4641 Producing Figure 16. Radiated Emissions Scan of LTM4641 Producing

APPLICATIONS INFORMATION—MULTIMODE PARALLEL OPERATION

• VOSNS+, differentially bussed with V OSNS–; use GND shielding
• VOSNS–, differentially bussed with V OSNS+; use GND shielding
• PGOOD, if used Pulling any one module’s RUN pin low will pull all module’s HYST pins low, to cease switching and output voltage regu- lation. When paralleling L TM4641 outputs, each module should have its own R fSET resistor locally (if needed) to set the on time (IION) consistent with the output voltage set- ting (cf. Table 1 and Figure 3). Customized UVLO settings, latching and nonlatching input overvoltage thresholds, and output overvoltage thresholds need only be configured on one L TM4641. INTV CC and DRVCC should be connected to each other , separately on each module (see Figures 56 and 66)—or , if powering DRV CC from an auxiliary bias rail, then by applying the technique of Figure 51 to each module. If MSP is used, only one V INGP need be connected to the gate of MSP . The routing of MSP’s source pins to the VINH of all modules may be difficult to accomplish in layout without introducing significant loop area; it may be necessary then to use one MSP MOSFET on the input to each L TM4641 power stage for practical routing. Also, the connections of V OSNS+ and VOSNS– to multiple modules can be difficult to shield, in practice, so leaving provision for differential-mode filtering of the remote sense signal DM1, CDM2) local to each modules’ remote-sense input pins is advisable. Be aware that the loading of the paralleled remote sense amplifiers on the bussed feedback signal alters the equa- tions for setting output voltage as follows. When paralleling n modules, for VOUT ≤1.2V , select RSET1A not larger than that given by: RSET1A = RSET1 B= VOUT 0.6V –1    • 8.2kΩ n   (32) For VOUT > 1.2V , select RSET1A not larger than that given by: RSET1A = RSET1 B= 8.2kΩ n (33) Then, determine RSET2 by: RSET2 = 2•RSET1A VOUT 0.6 –n •RSET1A 8.2kΩ –1 (34) The output voltage setting can be double-checked by: VOUT = 0.6V 1 + n•RSET1A 8.2kΩ + 2•RSET1A RSET2 (35) The voltage on the V OSNS+ pins of the modules during regulation become: VVOSNS+ = 0.6V 8.2kΩ n ||RSET1A ||RSET2 + ∆ VGND RSET1A
• RSET1A || 16.4kΩ n   (36) In multimodule parallel scenarios, VOSNS– and ∆VGND are still given by Equations 12 and 13, respectively. Lastly, be aware that the total charge current on the TRACK/SS net will be n • 1μA.

APPLICATIONS INFORMATION—THERMAL CONSIDERATIONS AND OUTPUT CURRENT DERATING Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board de- fined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are in-and-of themselves not relevant to providing guidance of thermal performance; instead, the derating curves provided later in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi - cients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 1 θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. 2 θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator , the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3 θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4 θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 17; blue resistances are contained within the µModule regulator , whereas green resistances are external to the µModule package. As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance

airflow, a majority of the heat flow is into the board. Figure 17. Graphical Representation of JESD51-12 Thermal Coefficients in the Pin Configuration section of this data sheet. LTM4641 with various heat sinking and air flow conditions.

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perature. These approximate factors are listed in Table 3. above ambient temperature multiplicative factors. Table 3. Power Loss Multiplicative Factors vs Ambient

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Figure 18. 6VOUT Power Loss, Figure 19. 3.3VOUT Power Loss, Figure 20. 1.5VOUT Power Loss,

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Figure 24. 12VIN to 6VOUT with Heat Figure 25. 24V IN to 6VOUT with Heat Figure 26. 36V IN to 6VOUT with Heat Figure 22. 24V IN to 6VOUT, No Heat Figure 23. 36V IN to 6VOUT, No Heat

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Figure 27. 6VIN to 3.3VOUT No Heat Figure 28. 12VIN to 3.3VOUT No Heat Figure 29. 24V IN to 3.3VOUT No Heat

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Figure 30. 36V IN to 3.3VOUT, No Figure 33. 24V IN to 3.3VOUT with Figure 34. 36V IN to 3.3VOUT with Figure 35. 6V IN to 1.5VOUT No Heat Figure 31. 6VIN to 3.3VOUT, with Figure 32. 12VIN to 3.3VOUT, with

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Figure 39. 6VIN to 1.5VOUT, with Figure 42. 36V IN to 1.5VOUT with Figure 36. 12VIN to 1.5VOUT No Heat Figure 37. 24VIN to 1.5VOUT No Heat Figure 38. 36V IN to 1.5VOUT No Heat Figure 40. 12VIN to 1.5VOUT, with Figure 41. 24VIN to 1.5VOUT, with

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Table 9. T ransient Performance (Typical Values) vs Recommended Output Capacitance. Figure 45 and Figure 46 Circuits *Bulk Capacitance is optional if VIN has very low input impedance.

APPLICATIONS INFORMATION—SAFETY AND LAYOUT GUIDANCE Safety Considerations The L TM4641 modules do not provide galvanic isolation from VIN to V OUT. There is no internal fuse. If fusing is required, a slow blow fuse with a rating twice the maximum input current needs to be provided. The L TM4641 sup- ports overcurrent protection and two kinds of overvoltage protection (see the Power Good Indicator and Latching Output Overvoltage Protection section). Layout Checklist/Example The high integration of L TM4641 makes the PCB board layout very straightforward. To optimize its electrical and thermal performance, some layout considerations are necessary. Figure 43 and Figure 44 show recommended layouts for the circuits shown in Figure 45 and Figure 46, respectively.

• Refer to the following document for device land pattern and stencil design: http://www.linear .com/docs/40146.
• The gerber file for demo board DC1543 can be down- loaded at http://www.linear .com/demo
• Use a solid copper GND plane directly underneath the module. This will help form the return path electrical connections to the input source and output load. It will also provide a thermal path for removing heat from the BGA package and minimize junction temperature rise of the L TM4641 for a given application. For consistent ripple and noise from application to application, connect the output GND plane (the one that conducts load side return current back to the module) and the input GND plane (the one that conducts module return current back to the input source) underneath the module, only.
• Use large PCB copper areas for high current paths, including VINH and VOUT.
• Place high frequency ceramic input and output capaci- tors next to the VINH, GND and VOUT pins to minimize high frequency noise. VINH exception: If MSP is used, (1) place MSP as close to the VINH pins of the L TM4641 as possible and (2) bypass the drain of MSP—and not VINH—to GND pins of the L TM4641. Only one or two high frequency MLCCs (C OUT(MLCC)) need be placed directly next to the VOUT and GND pins of the L TM4641, to minimize high frequency noise close to the source. The majority of COUT(MLCC) should be located close to the load to provide high quality bypassing.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put vias directly under any pads, unless they are capped or plated over .
• Use a separated SGND ground copper area for compo- nents connecting to signal pins. Components connecting to SGND should be placed as close to the module as possible and routed with minimum trace lengths and trace widths, for best noise immunity.
• Note that there are two clusters of SGND pins on the module: one, formed by Pins A1-A3, B1-B3, C1-C4 (A1-quadrant); and a second formed by Pins K1, K3, L3, and M1-M3 (M1-quadrant). It is good PCB design practice to provide a copper plane connecting all A1-quadrant SGND pins together and another plane connecting all M1-quadrant SGND pins together . It is not necessary to connect these two clusters of SGND copper planes to each other in the PCB layout, because all SGND pins are electrically connected to each other internal to the module.
• Do not connect the any SGND pins or SGND plane(s) to the GND plane; the electrical star connection is made internal to the module.
• For parallel module operation, see the Multimodule Parallel Operation section for a list of interconnecting pins across paralleled modules. Circuit Figures 56 and 66 show four and two L TM4641 devices operating in parallel, respectively. Route signal-level (non-power) nets on an internal layer , with GND planes overlapping signal routes to shield them from noise. It is even more effective to surround module-to-module signal connections on the internal layer containing the signal routes with adjacent GND planes or routes, and periodi- cally “punching-through” GND via connections to GND plane shields on adjacent layers. This practice forms the equivalent of a “coaxial cable” structure within the PCB, and is highly effective at shielding sensitive signals from noise sources. Maintain differential routing of the V OSNS+/VOSNS– pin pair .

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Figure 45. 4V IN to 38VIN, LTM4641 Basic Configuration, 1.8V Output at 10A

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Figure 46. LTM4641 Delivering 3.3V Output at 10A, and Providing Robust Output

Figure 47. LTM4641 Generating 1V Output at 10A, Surge Protected up to 80V IN Transients. Figure 48. Oscilloscope Snap-Shot of Figure 47 Circuit Riding Through

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9 Second Intervals When Input

is Turned On to Protect the Load Upon OOV Detection. Ride-Through Protection for L TM4641.

Figure 49. LTM4641 Producing 0.9V OUT at 10A, from 3.3VIN, and Providing Advanced Output Overvoltage Figure 50. Oscilloscope Snap-Shot of Figure 49 Circuit, 2Ω Load on V OUT.

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Figure 51. Over-Driving INTV CC/DRVCC to Reduce VINL-to-INTV CC Linear Regulator Losses (cf. Figures 52 to 54) Figure 52. Thermal Image of U1 from Figure 51 Circuit. Figure 53. Thermal Image of U1 from Figure 51 Circuit. Figure 54. Thermal Image of U1 from Figure 51 Circuit. Figure 55. Thermal Image of U1 from Figure 51 Circuit.

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Figure 56: 1V, 40A Fault-Protected Load Powered by Four Parallel LTM4641—from Up to 38V IN. cf. Figure 57 RfSET1 750k 4.5VIN START-UP OPERATION UP TO 38V AND DOWN TO 4V CMLCC(OUT) 100µF 6.3V ×12 CIN(MLCC) 10µF 50V CIN(BULK) 100µF 50V V OUT 40A LOCAL HIGH FREQUENCY DECOUPLING R SET1A 1.37k CFF1 100pF CFF2 100pF RSET1B 1.37k LOAD VOSNS+ VOUTVINL fSET INTVCC DRVCC IOVRETRY OVLO RUN RUN ENABLE LATCHOFF RESET PULL LATCH NORMALL Y LOW FOR LATCHOFF RESPONSE TO OUTPUT OVERVOL TAGE AND OVER- TEMPERATURE EVENTS. PULL LATCH HIGH TO RESTART 1V OUTPUT AL TERNATIVEL Y, CONNECT LATCH TO INTV CC AND INSTALL CTMR1, CTMR2, CTMR3 AND CTMR4 TO SET 1V OUTPUT FOR TIMED AUTONOMOUS RESTART AFTER FAUL T SHUTDOWN EVENTS MCB: NXP PSMN5R0-30YL MSP: NXP PSMN3R0-60BS FAUL T INDICATOR C SS 22nF CTMR1 N/U VOSNS– VORB+ UVLO HYST FCB GNDSGNDCOMPTMRTRACK/SS V ING VINGP MSP MCB VINH L TM4641 CROWBAR LATCH VORB– TEMP 1VREF OVPGM OTBH PGOOD SW CDM1 10pF RfSET2 750k VOSNS+ VOUTVINL fSET INTVCC DRVCC IOVRETRY OVLO RUN CTMR2 N/U VOSNS– VORB+ UVLO HYST FCB GNDSGNDCOMPTMRTRACK/SS V ING VINGP VINH L TM4641 CROWBAR LATCH VORB– TEMP 1VREF OVPGM OTBH PGOOD SW CDM2 10pF TO SYSTEM µP (OPTIONAL) RfSET3 750k VOSNS+ VOUTVINL fSET INTVCC DRVCC IOVRETRY OVLO RUN CTMR3 N/U VOSNS– VORB+ UVLO HYST FCB GNDSGNDCOMPTMRTRACK/SS V ING VINGP VINH L TM4641 CROWBAR LATCH VORB– TEMP 1VREF OVPGM OTBH PGOOD SW CDM3 10pF RfSET4 750k VOSNS+ VOUTVINL fSET INTVCC DRVCC IOVRETRY OVLO RUN CTMR4 N/U VOSNS– VORB+ UVLO HYST FCB GNDSGNDCOMPTMRTRACK/SS V ING VINGP VINH L TM4641 CROWBAR LATCH VORB– TEMP 1VREF OVPGM OTBH PGOOD

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U1, U2, U3 AND U4 SGND ( 1, 2, 3, 4) CONNECT TO GND INTERNAL TO THEIR RESPECTIVE MODULES. KEEP MODULE SGND ROUTES/PLANES SEPARATE FROM OTHER MODULES AND FROM GND ON MOTHERBOARD

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Figure 59. Pulsed Application of V IN. Figure 58 Circuit with 500Ω Load.

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Figure 60. Fault-Protected Load with Power Supply Management. LTM4641’s Fast Output Overvoltage Latchoff Trip Figure 61. LTM4641’s VOUT Margined High/Low by LTC2978 Via I 2C Commands. Figure 60 Circuit. 12V IN.

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L TM4641 SGND CONNECTS TO GND INTERNAL TO MODULE.

Figure 62. Functional Block Diagram

Figure 63. Start-Up/Shutdown State Diagram

1. CUSTOM UVLO INPUT TOO LOW (V
2. NONLATCHING INPUT OVERVOL TAGE (VIOVRETRY > UVOVTH, ~0.5VTH)
3. DRVCC TOO LOW (VDRVCC < DRVCC(UVLO_RISING), ~3.9VTH)
4. NONLATCHING OVERTEMPERATURE
5. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
6. CUSTOM UVLO INPUT TOO LOW (V
7. NONLATCHING INPUT OVERVOL TAGE (VIOVRETRY > UVOVTH, ~0.5VTH)
8. DRVCC TOO LOW (VDRVCC < DRVCC(UVLO_FALLING), ~3.35VTH)
9. NONLATCHING OVERTEMPERATURE
10. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
11. CUSTOM UVLO INPUT O.K. (V
12. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
13. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)

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1. LATCHOFF INPUT OVERVOL TAGE (V
2. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
3. LATCHOFF INPUT OVERVOL TAGE (V
4. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
5. CUSTOM UVLO INPUT O.K. (V
6. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
7. TEMPERATURE O.K. (VTEMP > OTTH(INCEPTION), ~438mVTH)
8. RUN > VRUN(ON) (2VTH, MAX)
9. CUSTOM UVLO INPUT O.K. (V
10. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
11. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)
12. RUN > VRUN(ON) (2VTH, MAX)
13. CUSTOM UVLO INPUT O.K. (V
14. CROWBAR INACTIVE (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
15. TEMPERATURE O.K. (VTEMP > OTTH(RECOVER), ~514mVTH)
16. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
17. CROWBAR ACTIVE (VCROWBAR > VCROWBAR(TH), ~1.5VTH)
18. CROWBAR O.K. (VCROWBAR < VCROWBAR(TH), ~1.5VTH)
19. TEMPERATURE O.K. (OTBH = LOW AND VTEMP > OTTH(RECOVER), ~514mVTH)

Appendix C. Switching Frequency Considerations and Usage of RfSET There exist many scenarios in which a resistor , R fSET, should be connected externally to L TM4641’s fSET pin—to decrease the on-time of MTOP: most commonly, when the output voltage setting is less than or equal to 3V , and in rail-tracking applications; and less commonly, when V INL and VINH are operating from different source supplies. In the former cases, RfSET is usually applied from fSET to VINL (Figure 45 and front page application circuit); in the latter , R fSET is usually applied from f SET to the voltage source feeding L TM4641’s power stage—upstream of MSP , if a power-interrupt input MOSFET is used (Figure 49). There are several motivations and considerations behind this guidance: (1) Inherent to L TM4641’s constant on-time ar chitec- ture, the switching frequency of L TM4641 decreases as output voltage decreases. In order to maintain a reasonable output capacitor value solution size and output voltage ripple—even at lower output voltages (≤3V OUT)—RfSET should be applied, so that the control- ler’s ION pin current and the resulting nominal switching frequency is higher than the on-time dictated by the internal V INL-to-fSET-connected 1.3MΩ resistor . (2) The PFM control scheme employed by L TM4641 yields a switching frequency at zero load current (“no-load operation”) that is typically 20% to 25% lower than what it is at full load. As a result, inductor ripple cur- rent is proportionally higher at no load than what it is at heavy load. Recall that L TM4641 employs R DS(ON) current sensing; furthermore, realize that it is essential for the controller’s current-sense amplifier to be able to perceive and command sufficiently negative inductor trough current, enough to maintain a maximum average inductor current of 0A, so that output voltage can be properly regulated down to no load. A value of R fSET should be used to assure that switching frequency is high enough (or on-time is small enough) at no load so that the current-sense information representing the trough of choke current is never too large in ampli - tude. Figure 3 provides conservative guidance on the maximum value of R fSET (or equivalently, the minimum ION current) that assures proper no-load operation. (3) In rail-tracking applications, L TM4641’s output voltage must track a reference voltage not only during V OUT ramp up but also during V OUT ramp down; fulfilling the latter requires L TM4641 to sink current from the output capacitors. A value of R fSET should be used that assures the output voltage can be ramped down to one’s minimum desired output voltage of regula- tion—not just the intended nominal output voltage. Figure 3 provides this guidance. (4) In order to maintain a relatively constant switching frequency for a given output voltage (across the full line voltage), the on-time of M TOP should be inversely proportional to the voltage source feeding the V INH power stage—upstream of MSP , if a power-interrupt MOSFET is used (Figure 46). When V INL and VINH are operated from different rails, this goal can be accom- plished satisfactorily by placing R fSET between f SET and the power V IN input source (see Figure 49: the connection is to VIN and not VINL, and usually not VINH, but see a counterexample in Figure 47 and explana - tion in item number 5 of this list). A minor error term to the on-time is introduced by the internal 1.3MΩ V INL-to-fSET-connected resistor in such scenarios, so calculation of IION at all operating input voltage corner cases (power , VINH and control bias, V INL extremes) and the resulting switching frequency range of opera- tion, given by Equation 6, should be considered. (5) When MSP is used, and when V INL and V INH are operated from different rails—here is the reason it is recommended to connect R fSET from f SET to the drain of MSP rather than VINH: prior to start-up, MSP is off, and V INH is discharged. Connecting R fSET to VINH would set the on-time at the instant switching activity commenced to be much lower than intended. The on-time would not reach its final settling value until V ING circuitry had turned on MSP enough for VINH to become pulled up to V IN potential. It should become apparent that a mechanism may exist for dynamic interaction between how rapidly the output voltage ramps up (depending on TRACK/SS pin usage) versus how rapidly MSP might turn on. We know from item number 2 of this list that on-time should not be arbitrarily large. In general, to avoid any undesirable

and hardware evaluation on a case-by-case basis. ground by as much as ±0.6V . Figure 64. Feedback Remote Sense Connections and Techniques for Harshest Operating Environments

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T wisted Pair if Using Wires).

common mode noise in the remote-sense signal pin pair . current ramps downward as energy in its B-field wanes. tent output voltage ripple, regardless of the load current. waveform; inductor current does not go below 0A. age) can be adjusted or tightened from its default value.

• It is not recommended to change the OVPGM voltage dynamically because the fast OOV comparator has no glitch immunity beyond what is provided by OV PGM’s internal 47pF capacitor , and routing of OVPGM can make it vulnerable to electrostatic noise.
• The 15.6μs time constant filter formed by OVPGM’s in- ternal 47pF capacitor and default 499kΩ||1MΩ resistor- divider network should be maintained for practical values of OV PGM voltage: 0.6V < V OVPGM < 0.9V . Capacitive filtering of OVPGM must not be applied indiscriminately. The OVPGM voltage must come up very rapidly with the 1VREF at start-up, to prevent a race condition that would otherwise result in nuisance OOV detection and a faulty latchoff event—so any externally applied capacitance cannot be arbitrarily high. On the other hand, OV PGM must have some filtering from switching noise sources and should be sufficiently insulated from any possible dynamic activity on 1V REF. (See Figure 9.)
• External resistor(s) applied between OVPGM and 1VREF/ SGND should be relatively high impedance, to minimize loading on the 1V REF output. Then, small values of COVPGM achieve a consistent time constant as OVPGM’s resistance-divider network is altered. Figure 65 shows the optional network one can apply to alter or tighten the OV PGM setpoint.

Figure 65. Optional OV PGM Network to Alter or Tighten V OVPGM

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To nudge the OVPGM setpoint downward, to a new OOV inception threshold voltage at OV PGM(NEW)—using an RBOVPGM resistor , only—calculate: RBOVPGM = 1 1V –OVPGM(NEW) OVPGM(NEW) •499kΩ – 1 1MΩ (37) The new OVPGM threshold can then be double-checked by OVPGM(NEW) = 1V• 1 MΩ ||RBOVPGM( ) 499kΩ+ 1 MΩ ||RBOVPGM( ) (38) When lowering the OV PGM setpoint with application of RBOVPGM only, it is not necessary to apply a C OVPGM capacitor , because: for an extreme OVPGM(NEW) setting of 600mV , which is not practical since that is the voltage of V FB during normal regulation, the time-constant of the OVPGM network would have changed by less than 2μs from its default value. To nudge the OVPGM trip threshold upward to set a new OOV inception threshold voltage at OV PGM(NEW)—using an RTOVPGM resistor only—calculate: RTOVPGM = 1 OVPGM(NEW) 1V – OVPGM(NEW)( )•1MΩ – 1 499k Ω (39) The new OVPGM setting can then be double-checked by: OVPGM(NEW) = 1V•1 MΩ 499kΩ ||RTOVPGM + 1 MΩ( ) (40) If RTOVPGM is computed in Equation 39 to be smaller than 10kΩ, connect OV PGM to 1V REF and do not apply any COVPGM capacitor; this will yield an OOV setting of 167% of nominal. Otherwise, use the next smallest standard value of COVPGM available, computed by: COVPGM = 15.6µs 499kΩ ||1 MΩ ||RTOVPGM( ) – 47pF (41) The default V OVPGM setpoint is 665mV ±2.26%, over temperature. To tighten the OV PGM setpoint, begin by choosing RBOVPGM to be a commonly available precision and a T .C.R. of ±25ppm/°C can provide a considerable improvement in accuracy over the default divider network, over temperature. Next, decide the new value of V OVPGM desired—OVPGM(NEW)—within a practical window of 0.6V < OVPGM(NEW) < 0.9V . Then, compute RTOVPGM according to: RTOVPGM = OVPGM(NEW) 1V –OVPGM(NEW)( )• 1 MΩ ||RBOVPGM( ) – 1 499kΩ (42) The new OVPGM setting can be double-checked by: OVPGM(NEW) = 1V• 1 MΩ ||RBOVPGM( ) 499kΩ ||RTOVPGM + 1 MΩ ||RBOVPGM( ) (43) Then, use the next smallest standard value of C OVPGM available, computed by: COVPGM(NEW) = 15.6µs 499kΩ ||1 MΩ ||RTOVPGM ||RBOVPGM( ) – 47pF (44) For example, the OVPGM(NEW) setpoint can be kept at its nominal value of 666mV—but with better accuracy—by using ±0.1% precision resistors with ±25ppm/°C T .C.R. for R BOVPGM = 100k and RTOVPGM = 49.9k, and bypassing OVPGM to SGND with COVPGM = 470pF . The resulting VOVPGM OOV setpoint threshold becomes better than ±1.8%, over temperature. The vast majority of the remaining variation in the threshold setting comes variation of the 1V REF—a ±1.5% reference, over temperature. The extreme values of the OOV setpoint voltage, plus the OVPERR term—which is the offset voltage of the fast comparator (±12mV maximum, over temperature)—gives guidance on what the minimum and maximum voltage V FB can be at which the CROWBAR output would swing logic high and invoke latchoff overvoltage protection. One must take care to set the OV PGM voltage to a practical level and not too aggressively. If OV PGM is set too low, the system will demonstrate nuisance output overvoltage latchoff behavior . The output voltage of any switching

regulator can witnesses transient excursions above its ideal DC voltage operating point routinely, owing to:

• Control IC bandgap reference accuracy
• Output voltage ripple and noise
• Load current step-down transient events—including recovery from a short-circuit condition
• Steep line voltage step-up
• Start-up overshoot (little or no soft-starting of VOUT), or rail-tracking a fast master rail The Linear Technology L TpowerCAD design tool can help quantify some of these dynamic values; L TM4641’s total DC error (including bandgap reference variation) is better than ±1.5%, over temperature. If OV PGM has been decreased to its lowest practical level and output voltage overshoot during high side MOSFET short-circuit testing (shorting V INH to SW on evaluation hardware such as DC1543, for example) does not clamp the output voltage to one’s satisfaction, be aware that increasing output capacitance can reduce the maximum output voltage excursion. The reason follows: the larger the output capacitance, the longer it takes for the output voltage to be ramped up, even in the extreme case of deliberately short circuiting V INH to SW . The capacitance on VOUT is mainly what prevents the output voltage from shooting up to VINH—until CROWBAR turns on MCB. Multimodule parallel applications also have better output voltage overshoot during high side MOSFET short-circuit testing, owing to the fact that the sibling modules whose high side MOSFETs are not short circuited are able to help pull the output voltage down by turning on their low side power MOSFETs. Examples of paralleled L TM4641 power- ing and protecting loads are shown in Figures 56 and 66.

Table 10. L TM4641 Component BGA Pinout

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PIN 1 SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 144 0212 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A 0.0000 0.0000 DETAIL A Øb (144 PLACES) D A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 144x E b e e b F G 144-Lead (15mm × 15mm × 5.01mm) (Reference LTC DWG # 05-08-1914 Rev Ø) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z 0.0 F G H M L J K E A B C D 2 14 35 6 712 8 9 10 11

4641 F66

Figure 66. 1V, 20A Fault-Protected Load Powered by Paralleled LTM4641—from Up to 38VIN. cf. Typical Performance Characteristics