LTM4608V

LTM4608 LINER | Alldatasheet

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FEATURES

APPLICATIONS

DESCRIPTION

Low VIN, 8A DC/DC µModuleTM with Tracking, Margining, and Frequency Synchronization The L TM®4608 is a complete 8A switch mode DC/DC power supply. Included in the package are the switching control- ler , power FETs, inductor and all support components. Operating over an input voltage range of 2.375V to 5.5V , the L TM4608 supports an output voltage range of 0.6V to 5V , set by a single external resistor . This high effi ciency design delivers up to 8A continuous current (10A peak). Only bulk input and output capacitors are needed. The low profi le package (2.8mm) enables utilization of unused space on the back side of PC boards for high density point-of-load regulation. The high switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrifi cing stability. The device supports frequency syn- chronization, programmable multiphase and/or spread spectrum operation, output voltage tracking for supply rail sequencing and voltage margining. Fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. The power module is offered in a compact and thermally enhanced 15mm × 9mm × 2.8mm LGA package. The L TM4608 is Pb-free and RoHS compliant . 3V to 5.5V Input to 1.8V Output DC/DC μModule ■ Complete Standalone Power Supply ■ ± 1.5% Output Voltage Regulation ■ 2.375V to 5.5V Input Voltage Range ■ 8A DC, 10A Peak Output Current ■ 0.6V Up to 5V Output ■ Output Voltage T racking and Margining ■ Power Good T racks Margining ■ Multiphase Operation ■ Parallel Current Sharing ■ Onboard Frequency Synchronization ■ Spread Spectrum Frequency Modulation ■ Overcurrent/Thermal Shutdown Protection ■ Current Mode Control/Fast T ransient Response ■ Selectable Burst Mode ® Operation ■ Up to 95% Effi ciency ■ Output Overvoltage Protection ■ Small Surface Mount Footprint, Low Profi le (15mm × 9mm × 2.8mm) LGA Package ■ Telecom, Networking and Industrial Equipment ■ Storage Systems ■ Point of Load Regulation , L T , L TC, L TM and Burst Mode are registered trademarks of Linear Technology Corporation. μModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. VIN SVIN SW RUN PLLLPF TRACK V OUT FB ITH ITHM PGOOD MGN CLKOUT GND CLKIN CLKIN 4.87k

4608 TA01a

100μF10μF PGOOD VOUT VOUT 1.8V VIN 3V TO 5.5V L TM4608 SGND Effi ciency vs Load Current LOAD CURRENT (A) EFFICIENCY (%) 100 2468

4608 TA01b

VOUT = 1.8V VIN = 5V VIN = 3.3V

PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS PGOOD, PLLLPF , CLKIN, PHMODE, MODE...–0.3V to VIN Operating Temperature Range (Note 2).... –40°C to 85°C (Note 1) GND GND GND SW A BCD LGA PACKAGE 68-PIN (15mm × 9mm × 2.8mm) EFG CNTRL CNTRL V OUT VIN TOP VIEW TJMAX = 125°C, θJA = 25°C/W , θJP = 7°C/W , θJC = 50°C/W , WEIGHT = 1.0g ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage ● 2.375 5.5 V VOUT(DC) Output Voltage CIN = 10μF × 1, COUT = 100μF Ceramic, 100μF POSCAP, RFB = 6.65k V IN = 2.375V to 5.5V , VOUT = 1.5V , IOUT = 0A 1.475 1.468 1.49 1.49 1.505 1.512 V V Input Specifi cations V IN(UVLO) Undervoltage Lockout Threshold SV IN Rising SVIN Falling 2.05 1.85 2.2 2.0 2.35 2.15 V V The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 18. LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2) L TM4608EV#PBF L TM4608V 68-Lead (15mm × 9mm × 2.8mm) LGA –40°C to 85°C L TM4608IV#PBF L TM4608V 68-Lead (15mm × 9mm × 2.8mm) LGA –40°C to 85°C Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 18. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current V IN = 3.3V , VOUT = 1.5V , No Switching, Mode = VIN VIN = 3.3V , VOUT = 1.5V , No Switching, Mode = 0V VIN = 3.3V , VOUT = 1.5V , Switching Continuous 400 1.15 μA mA mA V IN = 5V , VOUT = 1.5V , No Switching, Mode = VIN VIN = 5V , VOUT = 1.5V , No Switching, Mode = 0V VIN = 5V , VOUT = 1.5V , Switching Continuous 450 1.3 μA mA mA Shutdown, RUN = 0, V IN = 5V 1 μA IS(VIN) Input Supply Current V IN = 2.375V , VOUT = 1.5V , IOUT = 5A VIN = 3.3V , VOUT = 1.5V , IOUT = 8A VIN = 5V , VOUT = 1.5V , IOUT = 8A 3.75 4.5 2.93 A A A Output Specifi cations I OUT(DC) Output Continuous Current Range (See Output Current Derating Curves for Different V IN, VOUT and TA) VOUT = 1.5V V IN = 3.3V , 5.5V V IN = 2.375V A A ΔVOUT(LINE) VOUT ΔVOUT(LOAD) VOUT Load Regulation Accuracy V OUT = 1.5V V IN = 3.3V , 5.5V , ILOAD = 0A to 8A V IN = 2.375V , ILOAD = 0A to 5A 0.3 0.3 0.75 0.75 VOUT(AC) Output Ripple Voltage I OUT = 0A, COUT = 100μF/X5R/Ceramic, VIN = 5V , VOUT = 1.5V 10 mV P-P fS Switching Frequency I OUT = 8A, VIN = 5V , VOUT = 1.5V 1.3 1.5 1.7 MHz fSYNC SYNC Capture Range 0.75 2.25 MHz ΔVOUT(START) Turn-On Overshoot C OUT = 100μF , VOUT = 1.5V , IOUT = 0A V IN = 3.3V V IN = 5V mV mV tSTART Turn-On Time C OUT = 100μF , VOUT = 1.5V , IOUT = 1A, Resistive Load, T rack = VIN, VIN = 5V 100 μs ΔVOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 100μF Ceramic, 100μF POSCAP, VIN = 5V , VOUT = 1.5V 15 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 5V , VOUT = 1.5V , COUT = 100μF 10 μs IOUT(PK) Output Current Limit C OUT = 100μF V IN = 2.375V , VOUT = 1.5V V IN = 3.3V , VOUT = 1.5V V IN = 5V , VOUT = 1.5V A A A Control Section V FB Voltage at FB Pin I OUT = 0A, VOUT = 1.5V , VIN = 2.375V to 5.5V 0.592 0.589 0.596 0.596 0.600 0.603 V V SS Delay Internal Soft-Start Delay 90 μs IFB 0.2 μA VRUN RUN Pin On/Off Threshold RUN Rising RUN Falling 1.4 1.3 1.55 1.4 1.7 1.5 V V

ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 18. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRACK T racking Threshold (Rising) T racking Threshold (Falling) T racking Disable Threshold RUN = V IN RUN = 0V 0.57 0.18 VIN – 0.5 V V V R FBHI Resistor Between VOUT and FB Pins 9.95 10 10.05 kΩ ΔVPGOOD PGOOD Range ±10 % %Margining Output Voltage Margining Percentage MGN = VIN, BSEL = 0V MGN = VIN, BSEL = VIN MGN = VIN, BSEL = Float MGN = 0V , BSEL = 0V MGN = 0V , BSEL = V IN MGN = 0V , BSEL = Float –14 –10 –15 –11 –16 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4608E is guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4608I is guaranteed and tested over the –40°C to 85°C temperature range.

VIN (V) VOUT (V) 1.5 2.0 2.5 3 5

4608 G06

1.0 0.5 12 4 3.0 3.5 4.0 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 5A VIN (V) VOUT (V) 1.5 2.0 2.5 3 5

4608 G05

1.0 0.5 12 4 3.0 3.5 4.0 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 8A TYPICAL PERFORMANCE CHARACTERISTICS Effi ciency vs Load Current Burst Mode Effi ciency with 5V Input VIN to VOUT Step-Down Ratio Supply Current vs VIN Load T ransient Response Load T ransient Response Effi ciency vs Load Current Effi ciency vs Load Current LOAD CURRENT EFFICIENCY (%) 100 24 68

4608 G01

5VIN 1.2VOUT 5VIN 1.5VOUT 5VIN 1.8VOUT 5VIN 2.5VOUT 5VIN 3.3VOUT CONTINUOUS MODE LOAD CURRENT EFFICIENCY (%) 100 2468

4608 G02

3.3VIN 1.2VOUT 3.3VIN 1.5VOUT 3.3VIN 1.8VOUT 3.3VIN 2.5VOUT CONTINUOUS MODE LOAD CURRENT (A) EFFICIENCY (%) 100 2 4 5

4608 G03

2.5VIN 1.0VOUT 2.5VIN 1.5VOUT 2.5VIN 1.8VOUT CONTINUOUS MODE VIN to VOUT Step-Down Ratio LOAD CURRENT (A) EFFICIENCY (%)60 100 0.2 0.4 0.6 0.8

4608 G04

VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V INPUT VOL TAGE (V) 2.5 SUPPL Y CURRENT (mA) 4.5 1.6 1.4 1.2 0.8 0.6 0.4 0.2

4608 G07

3.53 54 5.5 VO = 1.2V PULSE-SKIPPING MODE VO = 1.2V BURST MODE 1A/DIV 20mV/DIV 20μs/DIVVIN = 5V VOUT = 3.3V 2A/μs STEP C OUT = 100μF X5R C1 = 100pF , C3 = 22pF FROM FIGURE 18

4608 G08

per Figure 18 Typcial Application 2A/DIV 20mV/DIV 20μs/DIVVIN = 5V VOUT = 2.5V 2.5A/μs STEP C OUT = 100μF X5R C1 = 120pF , C3 = 47pF FROM FIGURE 18

4608 G09

TEMPERATURE (°C) –50 VFB (mV) 592 594 596 25 75

4608 G14

–25 0 50 598 600 602 100 VIN = 5.5V VIN = 3.3V VIN = 2.375V Load T ransient Response Start-Up V FB vs Temperature Load Regulation vs Current 2.5V Output Current Short-Circuit Protection (2.5V Short, No Load) Load T ransient Response Load T ransient Response VOUT 0.5V/DIV VIN 2V/DIV 50μs/DIVVIN = 5V VOUT = 1.5V COUT = 100μF NO LOAD AND 8A LOAD (DEFAUL T 100μs SOFT-START)

4608 G13

LOAD CURRENT (A) –0.5 LOAD REGULATION (%) –0.4 –0.2 –0.1 0.5 0.2 24 5 –0.3 0.3 0.4 0.1 1 3 678

4608 G15

VIN = 3.3V VOUT = 1.8V Short-Circuit Protection (2.5V Short, 4A Load) OUTPUT CURRENT (A) OUTPUT VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 51 01 5 2 0

4608 G16

50μs/DIV

4608 G17

VIN = 5V VOUT = 2.5V 5V/DIV 5V/DIV 5A/DIV 5A/DIV 50μs/DIV

4608 G18

VIN = 5V VOUT = 2.5V TYPICAL PERFORMANCE CHARACTERISTICSper Figure 18 Typcial Application 2A/DIV 20mV/DIV 20μs/DIVVIN = 5V VOUT = 1.8V 2.5A/μs STEP C OUT = 100μF X5R C1 = NONE, C3 = NONE FROM FIGURE 18

4608 G10

20μs/DIVVIN = 5V VOUT = 1.5V 2.5A/μs STEP C OUT = 100μF X5R C1 = NONE, C3 = NONE FROM FIGURE 18

4608 G11

20μs/DIVVIN = 5V VOUT = 1.2V 2.5A/μs STEP C OUT = 2 × 100μF C1 = 100pF , C3 = NONE FROM FIGURE 18

4608 G12

PHMODE (B4): Phase Selector Input. This pin determines the phase relationship between the internal oscillator and CLKOUT . Tie it high for 2-phase operation, tie it low for 3-phase operation, and fl oat or tie it to V IN/2 for 4-phase operation. MGN (B8): Margining Pin. Tie this pin to VOUT to disable margining. For margining, connect a voltage divider from V IN to GND with the center point connected to the MGN pin. Each resistor ≈ 50k. See Applications Information and Figure 18. BSEL (B7): Margining Bit Select Pin. Tying BSEL low selects ±5%, tying it high selects ±10%. Floating it or tying it to V IN/2 selects ±15%. TRACK (E5): Output Voltage T racking Pin. Voltage track- ing is enabled when the TRACK voltage is below 0.57V . If tracking is not desired, then connect the TRACK pin to SV IN. If TRACK is not tied to SVIN, then the TRACK pin’s voltage needs to be below 0.18V before the chip shuts down even though RUN is already low. Do not fl oat this pin. A resistor divider and capacitor can be applied to the TRACK pin to increase the soft-start time of the regulator . See Applications Information. Can tie together for parallel operation and tracking. Load current needs to be present during track down. FB (E7): The Negative Input of the Error Amplifi er . Internally, this pin is connected to V OUT with a 10k precision resistor . Different output voltages can be programmed with an ad- ditional resistor between FB and GND pins. In PolyPhase operation, tie FB pins together for parallel operation. See Applications Information for details. I TH (F6): Current Control Threshold and Error Amplifi er Compensation Point. The current comparator threshold increases with this control voltage. Tie together in parallel operation. I THM (F5): Negative Input to the Internal I TH Differential Amplifi er . Tie this pin to SGND for single phase operation. For PolyPhase operation, tie the master’s I THM to SGND while connecting all of the ITHM pins together . PIN FUNCTIONS VIN (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. VOUT (C10-C11, D10-D11, E9-E11, F9-F11, G9-G11): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 1. GND (A1-A11, B1, B9-B11, F3, F7-F8, G1-G8): Power Ground Pins for Both Input and Output Returns. SV IN (F4): Signal Input Voltage. This pin is internally con- nected to VIN through a lowpass fi lter . SGND (E1): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to GND in the application. MODE (B5): Mode Select Input. Tying this pin high enables Burst Mode operation. Tying this pin low enables forced continuous operation. Floating this pin or tying it to V IN/2 enables pulse-skipping operation. CLKIN (B3): External Synchronization Input to Phase Detector . This pin is internally terminated to SGND with a 50k resistor . The phase locked loop will force the internal top power PMOS turn on to be synchronized with the rising edge of the CLKIN signal. Connect this pin to SV IN to enable spread spectrum modulation. During external synchronization, make sure the PLLLPF pin is not tied to V IN or GND. PLLLPF (E3): Phase Locked Loop Lowpass Filter . An in- ternal lowpass fi lter is tied to this pin. In spread spectrum mode, placing a capacitor here to SGND controls the slew rate from one frequency to the next. Alternatively, fl oat- ing this pin allows normal running frequency at 1.5MHz, tying this pin to SV IN forces the part to run at 1.33 times its normal frequency (2MHz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1MHz). PolyPhase is a registered trademark of Linear Technology Corporation.

PGOOD (C7): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. Disabled during margining. RUN (F1): Run Control Pin. A voltage above 1.5V will turn on the module. SW (C3-C5): Switching Node of the Circuit is Used for Testing Purposes. This can be connected to copper on the board for improved thermal performance. CLKOUT (F2): Output Clock Signal for PolyPhase Opera- tion. The phase of CLKOUT is determined by the state of the PHMODE pin. PIN FUNCTIONS GND GND GND SW A BCD LGA PACKAGE 68-PIN (15mm × 9mm × 2.8mm) EFG CNTRL CNTRL V OUT VIN TOP VIEW

Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Confi guration. Figure 1. Simplifi ed L TM4608 Block Diagram current with few external input and output capacitors. application schematic is shown in Figure 18. be externally synchronized from 0.75MHz to 2.25MHz.

limit and thermal shutdown in an overcurrent condition. age exits a ±10% window around the regulation point. output voltage ramp and voltage tracking during start-up. See Applications Information. external resistor to ground. Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. other by programming the PHMODE pin to different levels. multiple devices or frequency synchronization. light load features will accommodate battery operation. the Typial Performance Characteristics. gramed from ±5% to ±15% using the MGN and BSEL pins. Table 2. RFB Resistor vs Output Voltage ductive leads, traces or not enough source capacitance.

V OUT IN Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% D  1 – D() In the above equation, η% is the estimated effi ciency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , polymer capacitor for bulk input capacitance due to high inductance traces or leads. If a low inductance plane is used to power the device, then only one 10μF ceramic is required. The three internal 10μF ceramics are typically rated for 2A of RMS ripple current, so the ripple current at the worse case for 8A maximum current is 4A or less. Output Capacitors The L TM4608 is designed for low output voltage ripple noise. The bulk output capacitors defi ned as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient require- ments. C OUT can be a low ESR tantalum capacitor , a low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range is from 47μF to 220μF . Additional output fi ltering may be required by the system designer , if further reduction of output ripple or dynamic transient spikes is required. Table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3A/μs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 3 matrix, and the Linear Technology μModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance will be more a function of stability and transient response. The Linear Technology μModule Power Design Tool will calculate the output ripple reduction as the number phases implemented increases by N times. Burst Mode Operation The L TM4608 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the effi ciency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply tie the MODE pin to V IN. During this operation, the peak current of the inductor is set to approximately 20% of the maximum peak current value in normal operation even though the voltage at the I TH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the I TH voltage drops below 0.2V , the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, re- ducing the quiescent current to about 450μA. The load cur- rent is now being supplied from the output capacitor . When the output voltage drops, causing I TH to rise above 0.25V , the internal sleep line goes low, and the L TM4608 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high effi ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the L TM4608 to skip cycles at low output loads, thus increasing effi ciency by reducing switching loss. Floating the MODE pin or tying it to V IN/2 enables pulse-skipping operation. This allows discontinuous conduction mode (DCM) opera- tion down to near the limit defi ned by the chip’s minimum on-time (about 100ns). Below this output current level, the converter will begin to skip cycles in order to main- tain output regulation. Increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency PWM. Forced Continuous Operation In applications where fi xed frequency operation is more critical than low current effi ciency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by

until the L TM4608’s output voltage is in regulation. Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step IN has very low input impedance.

sharing. This will balance the thermals on the design. Figure 2. 6-Phase Operation Figure 3. 12-Phase Operation

4608 F02

4608 F03

reduction as a function of the number of interleaved phases. electromagnetic interference (EMI) is concerned. operating frequency (harmonics). slew rate of the spread spectrum frequency change.

4608 F04

Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Modules (Phases)

VTRACK is the track ramp applied to the slave’s track pin. this resistor divider is connected to the slave’s track pin. 5 will be equal to RFB2 for coincident tracking.

4608 F05

Figure 5. Dual Outputs (3.3V and 1.5V) with T racking

4608 F06

voltage will reach it fi nal value before the master output. FB3 = 22.1k. Solve for RFB4 to equal to 4.87k. needs to be present during track down. between the core and sub-power supplies. TH pins together to share currents evenly for all phases.

4608 F07

4608 F08

Figure 11. No Heat Sink with 5VIN to 1.5VOUT Figure 12. BGA Heat Sink with 5VIN to 1.5VOUT

4608 F09

4608 F10

4608 F11

4608 F12

4608 F13

4608 F14

Table 4. 1.5V Output Table 5. 3.3V Output Figure 15. No Heat Sink with 5VIN to 3.3VOUT Figure 16. BGA Heat Sink with 5VIN to 3.3VOUT

4608 F15

4608 F16

±5%, ±10% or ±15% of its normal operational voltage. analysis for the thermal models and the derating curves. or below for the derating curves. provided to protect each unit from catastrophic failure. siderations are still necessary.

• Use large PCB copper areas for high current path, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci- tors next to the V IN, GND and V OUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put vias directly on the pads, unless they are capped.
• Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to GND underneath the unit. Figure 17 gives a good example of the recommended layout.

Figure 17. Recommended PCB Layout

4608 F17

Figure 18. Typical 3V to 5.5VIN, 2.5V at 8A Design Figure 19. T wo L TM4608s in Parallel, 1.5V at 16A Design

4608 F19

4608 F18

Figure 20. Dual L TM4608 Output Sequencing Application Figure 21. 2.5V to 5.5VIN, 1.2VOUT Design

4608 F20

4608 F21

4608 F22

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 68 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR A MARKED FEATURE SYMBOL aaa bbb TOLERANCE 0.15 0.10 9.00 BSC PACKAGE TOP VIEW LGA 68 0607 REV A 15.00 BSC PAD “A1” CORNER PADS SEE NOTES X Y aaa Z aaa Z 2.69 – 2.95 DETAIL A PACKAGE SIDE VIEW DETAIL A SUBSTRATEMOLD CAP 0.290 – 0.350 2.400 – 2.600 bbb Z Z 1.27 BSC 0.737 – 0.787 0.737 – 0.787 12.70 BSC 7.620 BSC PAD 182 1 43 F G E A B C D PACKAGE BOTTOM VIEW PACKAGE IN TRAY LOADING ORIENTATION 711 9 10 2.540 2.540 1.270 1.270 5.080 5.080 6.350 6.350 3.810 3.810 0.000 0.381 0.381 3.810 3.810 2.540 2.540 1.270 1.270 0.000 0.381 0.381 SUGGESTED PCB LAYOUT TOP VIEW LTMXXXXXX μModule TRAY PIN 1 BEVEL COMPONENT PIN “A1” 68-Lead (15mm × 9mm × 2.82mm) (Reference L TC DWG # 05-08-1808 Rev A)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0907 • PRINTED IN USA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer L TC2923 Power Supply T racking Controller T racks Both Up and Down; Power Supply Sequencing L T3825/L T3837 Synchronous Isolated Flyback Controllers No Optocoupler Required; 3.3V , 12A Output; Simple Design L TM4600 10A DC/DC μModule Basic 10A DC/DC μModule, LGA Package L TM4600HVMP Military Plastic 10A DC/DC μModule Guaranteed Operation from –55°C to 125°C Ambient, LGA Package L TM4601/ L TM4601A 12A DC/DC μModule with PLL, Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version has no Remote Sensing, LGA Package L TM4602 6A DC/DC μModule Pin Compatible with the L TM4600, LGA Package L TM4603 6A DC/DC μModule with PLL and Outpupt T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4603-1 Version have no Remote Sensing, Pin Compatible with the L TM4601, LGA Package L TM4604 Low V IN 4A DC/DC μModule 2.375V ≤ V IN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm LGA Package PACKAGE DESCRIPTION Pin Assignment Table (Arranged by Pin Number) PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 GND B1 GND C1 V IN D1 V IN E1 SGND F1 RUN G1 GND A2 GND B2 – C2 – D2 – E2 – F2 CLKOUT G2 GND A3 GND B3 CLKIN C3 SW D3 V IN E3 PLLLPF F3 GND G3 GND A4 GND B4 PHMODE C4 SW D4 V IN E4 – F4 SV IN G4 GND A5 GND B5 MODE C5 SW D5 V IN E5 TRACK F5 I THM G5 GND A6 GND B6 – C6 – D6 – E6 – F6 I TH G6 GND A7 GND B7 BSEL C7 PGOOD D7 V IN E7 FB F7 GND G7 GND A8 GND B8 MGN C8 V IN D8 V IN E8 V IN F8 GND G8 GND A9 GND B9 GND C9 V IN D9 V IN E9 V OUT F9 V OUT G9 V OUT A10 GND B10 GND C10 V OUT D10 V OUT E10 V OUT F10 V OUT G10 V OUT A11 GND B11 GND C11 V OUT D11 V OUT E11 V OUT F11 V OUT G11 V OUT