LPV3000 FILTRONIC | Alldatasheet

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Technical content

Solid State 2W Power PHEMT Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950

FEATURES

  • +33.5 dBm Typical Power at 18 GHz
  • 7 dB Typical Power Gain at 18 GHz
  • +30.5 dBm at 3.3V Battery Voltage
  • Low Intermodulation Distortion
  • 45% Power-Added-Efficiency at 18 GHz DIE SIZE: 28.3 x 16.5 mils (720 x 420 µm) DIE THICKNESS: 2.6 mils (65 µm typ.) BONDING PADS: 1.9 x 2.4 mils (50 x 60 µm typ.) DESCRIPTION AND APPLICATIONS The LP3000 is an Aluminum Gallium Arsenide / Indium Gallium Arsenide (AlGaAs/InGaAs) Pseudomorphic High Electron Mobility Transistor (PHEMT), utilizing an Electron-Beam direct-write 0.25 µm by 3000 µm Schottky barrier gate. The recessed “mushroom” gate structure minimizes parasitic gate-source and gate resistances. The epitaxial structure and processing have been optimized for reliable high-power applications. The LP3000 also features Si 3N 4 passivation and is available with plated source via-holes (LPV 3000) as an option for improved high-frequency performance. Also available in a ceramic flanged package (P100) and ball grid array package. Typical applications include commercial and military high-performance power amplifiers, including SATCOM uplink transmitters, PCS/Cellular low-voltage high-efficiency output amplifiers, and medium-haul digital radio transmitters. The LPV 3000/LP 3000 may be procured in a variety of grades, depending upon specific user requirements. Standard lot screening is patterned after MIL-STD-19500, JANC grade. Space-level screening to FSS JANS grade is also available. PERFORMANCE SPECIFICATIONS (T A = 25°C) SYMBOLS PARAMETERS MIN TYP MAX UNITS IDSS Saturated Drain-Source Current VDS = 2V VGS = 0V 800 1060 1100 mA P1dB Output Power at 1dB Gain Compression VDS = 8.0V, IDS = 50% IDSS (LP. LPV) f = 18 GHz 33.0 33.5 dBm G 1dB Power Gain at 1dB Gain Compression V DS = 8.0V, IDS = 50% IDSS (LP) f = 18 GHz VDS = 8.0V, IDS = 50% IDSS (LPV) f = 18 GHz 4.0 6.0 6.0 7.0 dB dB ηADD Power-Added Efficiency (typ. for Class A operation) 45 % IMAX Maximum Drain-Source Current V DS = 2V VGS = +1V 1700 mA G M Transconductance V DS = 2V VGS = 0V 725 900 mS VP Pinch-Off Voltage V DS = 2V IDS = 10mA -0.25 -1.2 -2.0 V IGSO Gate-Source Leakage Current V GS = -5V 15 125 µA BV GS Gate-Source Breakdown Voltage I GS = 15mA -12 -15 V BV GD Gate-Drain Breakdown Voltage I GD = 15mA -12 -16 V Θ J Thermal Resistivity 20 °C/W Get Curtice Model DSS-027 WG DRAIN PAD (x4) SOURCE BOND PAD (x2) GATE PAD (x4)

Solid State 2W Power PHEMT Phone: (408) 988-1845 Internet: http://www.filtronicsolidstate.com Fax: (408) 970-9950 ABSOLUTE MAXIMUM RATINGS (25°C) RECOMMENDED CONTINUOUS OPERATING LIMITS SYMBOL PARAMETER RATING 1 SYMBOL PARAMETER RATING 2 VDS Drain-Source Voltage 12V V DS Drain-Source Voltage 8V VGS Gate-Source Voltage -5V V GS Gate-Source Voltage -1V IDS Drain-Source Current 2 x IDSS IDS Drain-Source Current 0.8 x IDSS IG Gate Current 120 mA I G Gate Current 40 mA PIN RF Input Power 1.2 W P IN RF Input Power 600 mW TCH Channel Temperature 175°C TCH Channel Temperature 150°C TSTG Storage Temperature -65/175°C TSTG Storage Temperature -20/50°C PT Power Dissipation 6.0W 3,4 PT Power Dissipation 5.0 W 3,4 G XdB Gain Compression 8 dB NOTES: 1. Operating conditions that exceed the Absolute Maximum Ratings could result in permanent damage to the device. 2. Recommended Continuous Operating Limits should be observed for reliable device operation. 3. Power Dissipation defined as: PT ≡ (PDC + PIN) - POUT , where: PDC = DC bias power, POUT = RF output power, and PIN = RF input power. 4. Power Dissipation to be de-rated as follows: 5. Specifications subject to change without notice. Example #1 : V DS = 8V, IDS = 535 mA PIN = POUT = 0 dBm (quiescent condition): PT = PDC = 4.28W Max. continuous THS = 25°C Example #2: VDS = 8V, IDS = 535 mA PIN = 26.5 dBm POUT = 33.5 dBm Max. continuous THS = 88°C HANDLING PRECAUTIONS: PHEMT chips should be stored in a dry nitrogen environment until assembly. Care should be exercised during handling to avoid damage to the devices. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. These devices should be treated as Class 1A (0-500V), and further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263. ASSEMBLY INSTRUCTIONS: The recommended die attach is gold/tin eutectic solder under a nitrogen atmosphere. Stage temperature should be 280- 290°C; maximum time at temperature is 1 min. The recommended wire bond method is thermo-compression wedge APPLICATIONS NOTES AND DESIGN DATA: Applications Notes are available from your local FSS Sales Representative, or directly from the factory. Complete design data, including S-parameters, Noise data, and Large-Signal models, is available on 3.5” diskette, or may be down-loaded from our Web Page. Get Curtice Model DSS-027 WG PT(W) 6.0 -40 mW/°C 5.0 -40 mW/°C 175 150 THS (°C)