LM7000

LM7000 SANYO | Alldatasheet

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• The LM7000N is a modified version of the LM7000 whose phase comparator dead zone is changed. - High-speed programmable divider capable of direct dividing FM band VCO frequency. - Reference frequency (7 kinds) : 100,50,25,10,9,5,1kHz - Output for band select (3 bits) + Clock output for controller (400kHz) - Time base output for clock (8Hz) . - Data input : Serial input (CE,CL,DATA pins) + On-chip IF count circuit: FM: +10kHz MW, SW: +3kHz LW: £0.6kHz Absolute Maximum Ratings at Ta=25°C,Vgs=0V unit Maximum Supply Voltage Vpp max Vpp1,Vpp2 —0.3 to +7.0 Vv Maximum Input Voltage Vini max CE,CL,DATA,STRQ —0.3to +7.0 v Ving max Input pins other than Vyy1 —0.3 to Vpp + 0.3 Vv Maximum Output Voltage Vour;max SYC,STOUT -0.3 to +7.0 v Vourzmax BO0i,B02,BO03 ~0.3 to +13 v Voutsmax Output pins other than Voyri,2 —0.3 to Vpp+ 0.3 Vv Allowable Power Dissipation Pd max Ta=85°C 300 mW Operating Temperature Topr —40 to +85 °C Storage Temperature Tstg —55 to +125 °C Pin Assignment j bo we RB EZEZEESE Package Dimensions 3021B 2288 88 23 22 (unit : mm) irate econ | = fees oreeeooo th Tee ee UT Top View) me 8 Fe ce BE REE ANA 32 0Ots OG SANYO: DIP20S SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bidg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN D1593M0,02693JN/6018TA/5155KI/3104/2244 ° /9303KI,TS No.1434-1/7

LM7000,7000N ee Allowable Operating Conditions at Ta= — 40 to +85°C,Vsg=0V unit Supply Voltage Vpp1 Vpp1,PLLoperation ~ 4.5 to 6.5 Vv Vpp2 Vppe,Xtal OSC time base 3.5 to 6.5 v Input ‘H’-Level Voltage Vin = CE,CL,DATA,STRQ 2.2 t0 6.5 Vv Input ‘L’-Level Voltage Vit = CE,CL,DATA,STRQ 0t00.7 V Output Voltage Voun SYC,STOUT_ 006.5 Vv : Voutz BO1,B02,B03 0to13 v Output Current ‘Tour BO1,B02,B03,Vpp=4.5 to 6.5V 0to3.0 mA Input Frequency finl XIN, sine wave,capacitive coupling 1.0 to 7.2typ to 8.0 MHz fin2 FMIN, ¢ (Note 1),x(S=1) 45to0130 MHz fin3 FMIN, * (Note 2),%(S=1) 5to30 MHz _ find AMIN, *% 3x(S=0) 0.5t010 MHz fins FMIF, 7” 10.0 to 10.7typ to 11.5 MHz finé AMIF, 7 400 to 450typto500 kHz Oscillation-Guaranteed Xtal XIN-XOUT,C;=300, 5.0 to 7.2typ to 8.0 MHz Crystal Resonator Input Amplitude Vin1 XIN,sine wave,capacitive coupling 0.5 to 1.5 Vrms Vin2 FMIN, 7 0.1 to 1.5 Vrms Vin3 AMIN, + 0.1 to 1.5 Vrms Vind FMIF, 7% 0.1t01.5 Vrms Vind AMIF, ¢ 0.1t01.5 Vrms % : ‘8’: Control bit in serial data (Note 1) : fref=100,50,25kHz (Note 2): Reference freqeuncy other than fref= (Note 1) Electrical Characteristics / Under allowable operating conditions min typ max unit On-chip Feedback Resistance Rr, XIN 1.0 MQ Re FMIN 0.5 MQ Rg AMIN 0.5 Mo Ry FMIF 0.5 MQ Res AMIF 0.5 MQ Input ‘H’-Level Current ly = CE,CL,DATA,STRQ Vi=6.5V 5.0 vA Input ‘L’-Level Current I CE,CL,DATA,STRQ Vj=0V 5.0 pA Output ‘L’-Level Voltage Vou FMIF,AMIF,FMIN,AMIN Ip=0.5mA 35 V Vouz SYC Ip=0.1mA,(Note 3) 0.02 03 Vv Output Off Leak Current Io =SYC Vo=6.5V 5.0 wA Output ‘L’-Level Voltage Voits STOUT . I9=1.0mA 1.0 Vv Output Off Leak Current Torre +STOUT_ Vo=6.5V 5.0 pA Output ‘L’-Level Voltage Vora BO1to3. I9=2.0mA 1.0 v Output Off Leak Current Iogg3 BO1 to3 Vo=18V 3.0 pA Output ‘H’-Level Voltage Von1 PD1,2 I9=0.1mA 0.5Vpp v Output ‘L’-Level Voltage Vous PD1,2 I9=0.1mA 0.3 v (ore Tri-state Io PD1,2 Vo=Vpp 0.01 10.0 nA Off Leak Current (ore Tri-state Ibe. PD1,2 Vo=0V 0.01 10.0 nA Off Leak Current Supply Voltage Ipp1 Vpp1+Vpp2 (Note 4) 25 40 mA Ippe Vppe PLL stop 2.0 3.5 mA Input Capacitance Cin FMIN 1 2 3 pF (Note 3) Vpp=3.5 to 6.5V (Note 4) 7.2MHz Xtal connected across XIN and XOUT . ~ fin2= 130MHz | Vin2=100mVrms chy XIN Other input pins = Vgg & og Output pins= Open mL Kinseki Co.,Ltd HC43/U: 2114-84521(1) : CL=10pF C1=15(10to22)pF C2=15pF HC43/U: 2114-84521(2) : CL=16pF C1=22(15to33)pF C2=33pF Nihon Denpa Kogyo Co.,Ltd NR-18: LM-X-0701 : CL=10pF C1l=15pF C2=15pF No.1434-2/7

LM7000, 7000N eee “Equivalent Circuit Block Diagram Be - ‘ oF XIN FIN In] | =A eae AMIN iF i All 2 oeuie Bown — £0 vz pens

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EGov BOL we BOF so | STOUT Pin Description SYC : Controller clock (400kHz) XIN,XOUT : Xtal OSC (7.2MHz), on-chip feedback resistor FMIN,AMIN : Local oscillation signal input CE,CL,DATA : Data input __ BO1,B02,B03 : Band data output, BO] can be also used for time base output (8Hz) STRQ : IF count request input STOUT : Auto search stop signal output Vpp1,Vpp2,Vss : Power supply (Vppo is for backup) AMIF,FMIF LIF signal input PD1,PD2 : Charge pump output Data Input. Hytiyt att 2 ty > 1.Susec cu 12. € 1,5 usec 7 eneeeeeee S LLL Ei ce amin 1 enn nnenen. 1 cE | <——— Inputting starts at DO. Do | D1 | De [ps [pa | ps [ps | D7 | D8 | D9 [D10|D11 piepi3| 70 | m1 | Bo | BI | B2 | TB [Ro Ri | R2| s (1) DO (LSB) to D13 (MSB) : Division ratio data For FMIN, use D0 to D18 ; for AMIN, use D4to D3, po| pi | pz | ps [ps | ps [ps [D7 [8 | Do | p10 pufpie[pis 1 101 10 21 21 2 1 100 0 0 LSB MSB ————> FMIN division ratio= 1007 xX X X KX 1 00 0 1 00100 LSB MSB _————> AMIN division ratio=145. Continued on next page. eee . No.1434-3/7

LM7000,7000N ee Continued from preceding page. Example OFM 100kHz Step (frer= 100kHz) FM VCO=100.7MHz (FM RF =90.0MHz, IF= + 10.7MHz) Division Ratio=100.7MHz (FM VCO) + 100kHz(f,es) = 1007 > 3EF qyzx) @ AM 10kHz Step (frep= 10k Hz) AM VCO=1450kHz (AM RF = 1000kHz, IF = +450kHz) Division Ratio=1450kHz (AM VCO) + 10kHz (fre) = 145 > 91q7Ex) (2) TO, T1 : For LSI test (0, 0) (3) BO to B2, TB: Band data [__Topat : Time base data Bo] Bi | B2 TB] Bor [Boz [Bos [o]o;orolt* * ofojifofo Toy iy reps t a [i foloyol | o | 1 [oti toy [1 1iifetol Q xjivotit mpi To] * :DeterminedbyROtR2 6x) 0/1]/1| TR] Oo | 1 | Xx :Don'tcare rxtrtili lt tp 1 1 TB :8Hz iofoto yo | (4) RO to R2: Reference frequency data [RORUR2 fret Gol Boe uO) Count [ojoloj 100 ke f1iiilo. —— _ | ofoltl 0 vito: 10. 7MHz= 10kHe 0/10] 2% Tito! lo [ojo|ti 1 fi fio ti 450kHe + 3 kHz rfofay fiiojr fi vito] ofilil 450kH2 £0, 6kHlz rfifiy ss fo:ofil 4$50kH2= 3 kHa _ Wote) BO to B2=0 (5) S: Divider select data ‘1’: FMIN, ‘0’: AMIN eee . No.1434-4/7

LM7000,7000N —_—. J IF Count Circuit : Circuit to stop auto tuning Q [FMAMIF IC Catz66, etc. Bd 3 ee H ii | is Tp ee a 2 8 g LIM7000,7000N BE Yoo controller - When in the neighborhood of a broadcasting station, “SIG” signal is output, setting SIG of the controller to “0”. - “STRQ” signal is applied to the LM7000 and IF IC from the controller. - IF signal is applied to the LM7000 from the IF IC and the LM7000 counts this signal. - When a specified count value is reached, “STOUT” signal is applied to the controller from the M7000, stopping auto tuning. t 516 (controtter) e STRQ(controller) eS | | ‘STOUT(LM7000) __ | Bi 350m SiGcheck STOUT check "STOUT check - Counting is performed only at “STRQ”=1. + The count time is 120msec. + For FM, the count error is shown below. (Example : For 50Hz-100% modulation, the maximum count error is 5kHz.) Count Error = Period ee . pf ot tt ep} | fe Pant | EPP 1 4g Pa Plu TP 2 30) . pu TP oO 10} [\\ O° me uk GRC:SCOKC«*dR:SC<“<«‘iz OCCUR Period a No.1434-5/7

LM7000,7000N See Sample Connection to Controller . | r@ 7.2MHz : é ' Z dod CE,CL, DATA aro controler 1LC7573,7574 Bitter! FERRY GEG Notes for Using PLLIC. (1) The layout nearby PLL-IC. Connected to eliminate noise “p ? soncor{ woo (VSS. o——| | amir S0-10DpF| LM7000,7000N o——fFE— FMF Ts Shorten. 3 Pr ad veo (it Shorten. a Surround this section with the ground pattern, because it is in a high impedance state and is very susceptible to noise. (2) State of output ports (BO! to BOS) at power-on. The output ports are undefined until the control data is transmitted. The BO1 and BO3 ports may output a internal clock of PLL-IC, and so don’t forget to transmitte of control data after power-on, The control data should be input only after X’tal OSC have become stable. (3) VCO design. At design of the VCO, try to do not stop oscillation no matter what Tuning Voltage(Vtune) is 0 Volt. When the VCO oscillation stops, the PLL is possible to become a dead -lock condition. Differences Between the LM7000 and LM7000N The only difference between LM7000 and LM7000N is the phase detector dead zone. Otherwise, they are identical. Continued on next page. No.1434-6/7

LM7000,7000N Gomtinued Fromy re Continued from preceding page. . Dead Zone The phase detector shown in figure 1 compares the reference frequency (f,) with fp. The characteristics of the phase detector are shown in figure 2. A phase detector ideally should output a voltage proportional to the phase difference (¢) as shown by curve (A), but in reality,-delays in the internal circuitry mean that small phase differences cannot be detected. This causes the dead zone shown by curve (B). To realize a large signal-to-noise ratio, this dead zone should be made as small as possible. Standard models, however, can have a rather wide dead zone. When there is a strong RF input signal, with these models, the VCO can be modulated to compensate for part of the RF signal being leak to the VCO from the MIX. In the case of dead zone is small, the VCO output is modulated and a beat between the RF and VCO is created. Figure 1 Figure 2 v Ma) ‘ Ve ivider T Phase © tft tft | tpead zone 1LM7000/LM7000N Because of the above reasons, the LM7000 and LM7000N were developed with different dead zones. LM7000 : Dead zone <0 ns, S/N is 90 to 100 dB or greater LM7000N : Dead zone=5 to 10 ns, for standard models Note If the LM7000N is used in a circuit designed for the LM7000, the S/N ratio will decrease. No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may direotly or indireotly cause injury, death or property loss. MI Anyone purchasing any’ products described or contained herein for an above-mentioned use shalt ; ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: - ® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Wi Information (including circuit diagrams and circuit parameters) herein is for example only: it is not guarant- ‘eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees . are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, eee No.1434-7/7