LH0043

LH0023 NSC | Alldatasheet

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$ - s GA National = rt a Semiconductor oO oe ¢ | LH0023/LH0023C/LH0043/LH0043C Sample 3 . . 5 | and Hold Circuits oO ax . $ | General Description Features = | The LHo0z3/L.Hooasc and LH0043/LH0043C are com- , wo929/LH0023C a plete sample and 1old circuits including input butter amplifi- Sample accuracy-0.01% max & | ©. FET output amplifier, analog signal sampling gato, TTL od artt rato. mV/see S | compatible logic circuitry and level shifting. They are de- rate-0.5 m typ | signed to operate from standard +15V OC supplies, but ™% Sample acquisition time-100 ys max for 20V 1 | provision is made on the LH0023/LH0023C for connection ™ Aperture time-150 ns typ of a separate +5V logic supply in minimum noise applica- ™ Wide analog input range- + 10V min tions. The principal difference between the LH0023/ ™ Logic input-TTL/DTL compatible LHO02SC and the LHO043/LH0043C is a 10:1 trade-off in m Offset adjustable to zero with single 10k pot Performance between sample accuracy and sample acquisi- Output short circuit proof tion time. Devices are pin compatible except for TTL logic polarity. LH0043/LH0043C The LH0023/LH0023C and LH0043/LH0043C are ideally Sample acquisition time-15 ws max for 20V suited for a wide variety of sample and hold applications 4 us typ for 5V including data acquisition, analog to digital conversion, syn- _ m Aperture time-20 ns typ chronous demodulation, and automatic test setup. They of- i Hold drift rate-1 mV/sec typ fer significant cost and size reduction over equivalent mod- 4g Sample accuracy-0.1% max Ule or discrete designs. Each device is available in a her- gq wide analog input range-+ 10V min metic TO-8 package and is completely specified over both in ss a - @ Logic input-TTL/DTL compatible full military and industrial temperature ranges. ee ci : . '™ Offset adjustable to zero with single 10k pot The LH0023 and LHO043 are specified for operation over Gutaut short circuit protection the —55°C to +125°C military temperature range. The Pr LHO023C and LH0043C are specified for operation over the 25°C to +85°C temperature range. a ca Connection Diagrams LH0023/LH0023C LH0043/LH0043C we. STORAGE we. STORAGE cap car a ws / ADJUST » ADUUST <» AON v POOH ¢ ANALOG GI O) - Logic ~ mi LOOQ?>» wi NOOO “Tie for operation * GROUND we. GROUND with V+ = 15V only Vee ne. Tor view Tor view TUK/5693-8 TL/K/5693-1 Order Number LH0023G or LH0023CG or LH0043G or LH0043CG i See Package Number G12B 1 5-22

8, 0 9 g a 3 ANALOG oS_, 20K | : g Wout D a " 3 © ovrpuT =) 1 1 oO | | © STORAGE | i] RI CAPACITOR 10K 92 Logic 66 v te >So | ! Tw *Tie to pin & for operation without V s pin, ‘oper ioc supply. OVec —o ono —dv TL/k/s600-9 LH0043/LH0043C OFFSET ADJUST n ANALOG 6 Ss INPUT o n an - | 4 STORAGE { CAPACITOR cosic & -—4 Re INPUT —_Ov —ov 3 5 | —Osno TL/K/5683-10 5-23

t+] Fs Absolute Maximum Ratings S| ft Military/Aerospace specified devices are required, Power Dissipation See graph 2 please contact the National Semiconductor Sales Output Short Circuit Duration Continuous 3 Office/Distributors for availability and specifications. Operating Temperature Range Supply Voltage (Vs) +20V s LH0023, LHO043 —55°C to + 125°C = Logic Supply Voltage (Voc) LH0023, LHO023C. +7.0V LH0023C, LHO043C —25°C to +85°C | Logic input Voltage (Ve) +55V Storage Temperature Range 65°C to — 150°C

8 Analog Input Voltage (Vs) #tev Lead Soldering (10 seconds) 300°C

Z| Electrical Characteristics .H0023/LH0023¢ (Note 1) 3 | ne a s Parameter [|__tHoozsTkHonzsc | Units = [ min [typ | Max | min [typ | Max | Sample (Logic 1”) Voc = 4.5V 20 Vv Input Voltage Sample (Logic 1") Ve = 2.4V, Voc = 5.5V BA Input Current Hold (Logic “0”) Voc = 4.5V v Input Voltage Hold (Logic “O”) Ve = 0.4V, Voc = 5.5V mA Input Current Analog Input +10 | £11 410 | 1 v Voltage Range ‘Supply Current - ly V5 = OV, Vg = 2V, 45 mA Vy1=0V ‘Supply Current ~ I2 Vs = ov, ve = 0.4V, 45 mA Vit = OV Supply Current—ig | Va=sov,vs=0 | | x0 [| x6 [| [xo | 16 | ms Sample Accuracy Vour = #10v(FuiiScaley [| 0.002 [ oo1 | | 0002 | 002 | % DC input Resistance | Sample Mode 1000 ka Hold Mode 25 ka Input Current ~ Is Sample Mode [ff o2 | ro | fos | 5 Tua InputCapactance [| To fT To Leakage Current- | Vs= +t0Vivis= tov, [| | 100 | 200 [| | 200 | 500 | pa pin —55°CSTa < 125°C V5 = £10V; V4 = +10V nA Drift Rate Vout = £5V,Cg = 0.01 nF, mV/s Ta = 26°C Drift Rate Vout = +10V, 1.0 mV/s Cg = 0.01 pF, Ta = 25°C Drift Rate Vout = £10V, mV/ms Cg = 0.01 pF Aperture Time Po to Tt Ts ‘Sample Acquisition AVout = 20V, ps Time Cg = 0.01 pF Output Amplifier V/ps Slew Rate Output Offset Voltage | Ag < 10k, V5 = OV, +20 +20 mv (without null) Ve = 2.0V Analog Voltage [ Fuetktasasc | sto | en [feo | en [fy Output Range [mz | eto | ea Tf ttf ee | |v ‘Note 1: Uniess otherwise noted, these specifications apply for V+ = +15V, Voc = +5V,V- = —15V, pin 9 grounded, a 0.01yF capacitor connected between pin 1 and ground over the temperature range —55°C to + 125°C for the LH0023, and — 25°C to +85°C for the LHOO23C. All typical values are for Ta = 25°C. 5:24

. x= Electrical Characteristics 1110043/LHo049c: (Note 2) 3s es 8 Parameter Conditions | __twooas_[_uooac units | = [ min | typ | Max | Min | typ | Mex | 3 Hold (Logic “1”) Vv 3S Input Voltage 8 Hold (Logic “1") Ve = 2.4V ry 4 Input Current £ ‘Sample (Logic “0”) Vv s Input Voltage & ‘Sample (Logic “0”) Ve = 0.4V mA Pa Input Current - Analog Input £10 21 +10 #11 v 3 Voltage Range 5 ‘Supply Current V5 = OV, Vg = 2V, x1 = OV 20 mA V5 = OV, Vg = 0.4V, 14 mA Vi = 0V ‘Sample Accuracy Vout = + 10V (Full Scale) | oo2 Tot [ [002 [os [ % DCinputResistance | To=2rc toro | 012 [soto | tore [Tn inputCurent=ig [to 0 TT 20 00 [na InputCapactancs | Ts ns Leakage Current- V5 = £10V; V4 = +10, pA pind To = 26°C V5 = +10V; Viq = £10V nA Drift Rate Vout = +10V, Cg = 0.001 pF, mV/s To = 25 Drift Rate Vour= #10v,Cs=o.001pF [ [to | 25 | [2 [5 | mv/ms Drift Rate Vout = +10V, Cg = 0.01 uF, mV/s Tc = 25°C Drift Rate Vour=#10v,Cs=o0rme [ [4 | as | | o2 [os | mvms ‘Aperture Time po 20 co 20 0s Sample Acquisition AVout = 20V, Cg = 0.001 p F us Time AVout = 20V, Cs = 0.01 uF ys AVout = 5V, Cs = 0.001 pF S Output Amplifier Vout = 5V, Cg = 0.001 pF Vins Slew Rate Output Offset Voltage Rg < 10k, V5 = OV, Vg = OV +40 +40 mV (without null) Analog Voltage RL> 1k, Ta = 25°C +10 | +11 +10 | £11 Vv Output Range Ry > 2k +10 | +12 +10 | +12 v Note 2: Uniess otherwise noted, these specifications apply for V+ = +15V, V- = —15V, pin 8 grounded, a 5000 pF capacitor connected between pin 1 and ground over the temperature range — 55°C to + 125°C for the LH0043, and —25°C to +85°C for the LHO043C. All typical values are for To = 25°C. 5-25

g Typical Performance Characteristics ~ Sample Acquisition Sample Acquisition

3 Power Dissipation Time—LH0043 Time—LH0043

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‘Sample Acquisition Pin 1 Leakage Current Pin 1 Leakage Current s Time—LH0023 vs Output Voltage vs Temperature ” e °° 3 >sCLLOOo AAA _SSa-_--_=_= 2 (Cee Se sso EEE EEE EH Et eeepc GREE SEER (oN ocseeseee ee ee — —— i ” gs *eescooee eee bomen Ol 3 oP sce se ZZ! Peed ty Ne eee ee ee BCC) 2 EEE SS? ee ge hs 3 - BC Nt Ee FRESE pp »ZLEUTT TRAE! See ee =

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° © 20 60 oo on son 120 100 108 200 AV-4-4 202 48 8 tO o ms ms ‘THRE Ga) OUTPUT VOLTAGE (v) TEMPERATURE { <> Output Current Drift vs Capacitance Drift vs Capacitance Limiting om (10023) (LHO043) od a [N] TTT TT TT “TACO Posse err eNscooeey AES Pa ANN TENS Too sg N i i IN BLE ) f cee E eet st E | [true] ewe] | 2 oN TEE ENTE = WONT OONG Bw FUONPEOOINT OE “CONT rt tii i Newwenere KT] 8 CCN ON Cloron COANE ETT] COOP N OTT) . eC LCPSET TTS JCOCPCRET TY ' s 8 bh mm com nee an “ ' Ld ‘an mT a ’ @ OUTPUT CURRENT (mA) CAPACITANCE UF] CAPACITANCE UF) (LH0023) “CLL = Tr oe 2 oa 2 “COTA PeLlhrA "TTA "COTE (oZccrrr w@L CCT Teer CRT 110 100 Oe FREOUENEY TUK 5609-3 5-26

r Typical Applications s nN Py How to Bulld a Sample and Hold Module ec peooccceoerer er --4 & Vv" (-18¥) 8 | | 8 Al | 10K2 | g ) fd 3 ANALOG. § & impuT uH0023, & ls oR ouTPUT Pad SAMPLE/ re coos | 3 HOLD | = cocic 7 7 | 3 INPUT | ic °o ve (+15v) | ce cz 3 DWF OF OWE | i GROUND | GUARD SHIELD Pc. BOARD | ay Loe EEE suena Note 1: C1 is polystyrene. Note 2: C2, C3, C4 are ceramic disc. Note 3: Jumper 7-8 and C4 not required for LHOO43. Note 4: R1 optional if zero trim is required. Forcing Function Setup for Automatic: Test Gear Losic PIN SELECT ire jew Oeciraty oA DEMULTIPLEXER baie pevict wut POINT | ' CONVERTER Anes Ea MATRIX PINS ' ' LJ . ‘TL/K/5683-5. Data Acquisition System 1 1 | > ' wuts) | Neen ourruts a s . ‘S/H LOGIC CHANNEL SELECT TL/K/5603-11 ‘*See op amp selection guide for details. Most popular types include LHO052, LM108, LM112, LH0044, LH0036, and LH0038. 5-27

[5]

3 Typical Applications (continued)

2 Single Pulse Sampler

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8 I O | Analog

5 I ! ourrurs \\ | | | | I EI VOLTAGE AT ty | ---~- | 0 = | MULTIPLEXER | *W" STAGE TTL antoars TRIGGER (AND DM54156 cuocK TL/K/5693-12, Two Channel Double Sideband Demodulator COMPOSITE O 5 | SIGHAL | a | _ a ! | I ‘SIGNAL =1 OUTPUT UU I | CARRIER 4 ll > J I AEFERENCE —_ L ee Bad ! eoome 5 7 oy Ny ; | | | | SIGWAL =2 OUTPUT mati f Sot > — J Le fie i

7 TUK/5683-13

e . = Applications Information S 4.0 DRIFT ERROR MINIMIZATION amplifier, but it will not be available at the output). For larger 8 In order to minimize drift error, care in selection of Cg and Values of storage capacitance, the limitation is the current in " ‘sinking capability of the input amplifier, typically 10 mA. With layout of the printed circuit board is required. The capacitor © °"1"G 01 uF, the slew rate can be estimated by 3 should be of high quality Teflon, polycarbonate, or polysty: to to. i" 3 rene construction. Board cleaniness and layout are critical dV_ 10¢10-9 _ aa particularly at elevated temperatures. See AN-63 for de- dt 0,01 1076 ~ ¥/HS Ora Siewing time for a 5 volt 8 tailed recommendations. A guard conductor connected to ignal change of Sus. c the output surrounding the storage node (pin 1) will be help- Inge Of Sus. x= ful in meeting severe environmental conditions which would 3.0 OFFSET NULL 3 otherwise cause leakage across the printed circuit board. Provision is made to null both the LH0023 and LH0043 by S 2.0 CAPACITOR SELECTION use of a 10k pot between pins 3 and 4. Offset null should be = The size of the capacitor is dictated by the required drift rate accomplistied ne sample mode atone half the input volt- 3 and acquisition time. The drift is determined by the leakage 99° F8Ng himum average error. 5 avo 4.0 SWITCHING SPIKE MINIMIZATION-LH0043 rent at pin 1 and may be calculated by —- = —, where | current at pin 1 and may ulated by Ge = GWhere lL capacitive divider is formed by the storage capacitor and is the total leakage current at pin 1 of the device, andC,is the capacitance of the internal FET switch which causes a the value of the storage capacitor. small error current to be injected into the storage capacitor . at the termination of the sample interval. This can be con-

2.1 Capacitor Selection ~ LH0023 ; sidered a negative DC offset and nulled out as described in

‘At room temperature leakage current for the LH0023 is ap- (3.0), or the transient may be nulled by coupling an equal proximately 100 pA. A drift rate of 10 mV/sec would require but opposite signal to the storage capacitor. This may be 0.01 uF capacitor. accomplished by connecting a capacitor of about 30 pF (or For values of Cs up to 0.01 pF the acquisition time is limited a trimmer) between the logic input (pin 6) and the storage by the slew rate of the input buffer amplifier, A1, typically 0.5 capacitor (pin 1). Note that this capacitor must be chosen as V/s. Beyond this point, current availability to charge Cs _ carefully as the storage capacitor itself with respect to leak- also enters the picture. The acquisition time is given by: age. The LH0023 has switch spike minimization circuitry a0 ACs built into the device. j—_ $= -3 ™ Vos x 195 — 2% 10 SYaeo RCs 5.0 ELIMINATION OF THE 5V LOGIC SUPPLY - LH0023 z . ; The 5V logic supply may be eliminated by shorting pin 7 to where: R= the internal resistance in series with Cs pin 8 which connects a 10k dropping resistor between the A@_ = change in voltage sampled +15V and Vc. Decoupling pin 8 to ground through 0.1 wF An average value for R is approximately 600 ohms. The disc capacitor is recommended in order to minimize tran- expression for ta reduces to: sients in the output. ty = Woes 6.0 HEAT SINKING ar) The LH0023 and LHO043G may be operated without dam- age throughout the military temperature range of —55 to For a —10V to +10V change and C.=.05 pF, acquisition +125°C (-25 to +85°C for the LHO023CG and time is typically 50 ps. LH0043CG) with no explicit heat sink, however power dissi- pation will cause the intemal temperature to rise above am- 2.2 Capacitor Selection-LH0043 bient. A simple clip-on heat sink such as Wakefield At 25°C case temperature, the leakage current for the —#215—1.9 or equivalent will reduce the internal tempera- LH0043G is approximately 10 pA, so a drift rate of SmV/s ture about 20°C thereby cutting the leakage current and drift would require a capacitor of Cs = 10¢1012/5¢103 = 2000 rate by one fourth at max. ambient. There is no internal PF or larger. electrical connection to the case, so it may be mounted For values of Cs below about 5000 pF, the acquisition time directly to a grounded heat sink. of the LH0043G will be limited by the slew rate of the output | amplifier (the signal will be acquired, in the sense that the 7.0 THEORY OF OPERATION LHO023 voltage will be stored on the capacitor, in much less time as The LH0023/LH0023C is comprised of input buffer amplifi- dictated by the slew rate and current capacity of the input @" A, analog switches, S1 and S2, a TTL to MOS level 5-20

3 Applications Information (continued)

£ | translator, and output butter amplifier, A2. In the “sample” —_and allows A1 to make the storage capacitor voltage equal =i | mode, the logic input is raised to logic “1” (Vg < 2.0V) _ to the analog input voltage. in the “hold” mode (V¢=2.0V), & | Which closes S1 and opens S2. Storage capacitor, Cs, is S1 is opened isolating the storage capacitor from the input 3 charged to the input voltage through S1 and the output and leaving it charged to a voltage equal to the iast analog slews to the input voltage. In the “hold” mode, the logic —_input voltage before entering the hold mode. The ‘storage | input is lowered to logic “0” (Vg < 0.8V) opening S1 and capacitor voltage is brought to the output by low leakage Pay closing S2. Cs retains the sample voltage which is applied to amplifier A2. the output via A2. Since S1 is open, the input signal is over- §¥ | riden, and leakage across the MOS switch is therefore mini SODEFINITIONS = ; = mized. With S1 open, drift is primarily determined by input Vs: The voltage at pin 5, e.g., the analog input voltage. 5 bias current of A2, typically 100 pA at 25°C. Ve: The voltage at pin 6, 6.g., the logic control input sig- Ss nal. 9 | 7.1 Theory of Operation-LH0043 . . 3 The LH0043/LH0043C is comprised of input buffer amplifier 11" The voltage at pin 11, e.g., the output signal. £ | A1, FET switch S1 operated by a TTL compatible level Ta: The temperature of the ambient air. =! | translator, and output buffer amplifier A2. To enter the Tc: The temperature of the device case at the center of “sample” mode, the logic input is taken to the TTL logic “0” the bottom of the header. state (Vg=0.8V) which commands the switch S1 closed Acquisition Time: The time required for the output (pin 11) to settle within the amangg fated accuracy after a specified input change is applied to A the input (pin 5) with the logic input (pin 6) in the tow state. Aperture Time: vce The time indeterminacy when switching from sample mode wr : to hold including the delay from the time the mode contro! signal {pin 6) passes through its threshold (1.4 volts) to the time the circuit actually enters the hold mode. save Output Offset Voltage: urna The voltage at the output terminal (pin 11) with the analog input (pin 5) at ground and logic input (pin 6) in the “sample” TuK/seea-7 - Mode. This will always be adjustable to zero using a 10k pot between pins 3 and 4 with the wiper arm returned to V-. 5-30