LD9162K LEADTREND | Alldatasheet
Document overview
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Technical content
Features
Primary-Side Feedback Control with Quasi-Resonant Operation Built-in 650V MOSFET Switch Built-in Load Regulation Compensation Constant Current Control Ultra-Low Startup Current (<1.9A) 80 kHz Maximum Switching Frequency. Green Mode Control to enhance Efficiency LEB (Leading-Edge Blanking) On CS Pin VCC OVP (Over Voltage Protection) Adjustable Brown in/out and Bulk_OVP on FB pin. Internal OTP (Over Temperature Protection) SDSP (Secondary Diode Short Protection)
Applications
Mobile Phone Charger Low Power AC/DC Adaptor VCC AC Input AC Input EMI Filter DRAIN CS LD9162K GND FB
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Pin Configuration YY: Year code WW: Week code PP: Production code 2 3 4 6 5 TOP MARK YYWWPP YYWWPP VCC GND FB CS DRAIN DRAIN DRAIN DRAIN SOP-8 (TOP VIEW)
Ordering Information
Part number Package TOP MARK Shipping LD9162K GS SOP-8 LD9162KGS 2500 / tape & reel The LD9162K is ROHS compliant/ green packaged. Protection Mode Part number VCC_OVP BULK_OVP OLP BNI/BNO FB_OVP FB Open/Short SDSP LD9162K Auto-Restart Auto-Restart Auto-Restart Auto-Restart Auto-Restart Auto-Restart Auto-Restart Pin Descriptions NAME PIN (SOP-8) FUNCTION VCC 1 Voltage supply pin. GND 2 Ground FB 3 Auxiliary voltage sensing and Quasi Resonant detection. CS 4 Current sense pin, connect it to sense the switch current. DRAIN 5,6,7,8 The drain of internal power MOSFET
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Block Diagram DRAIN internal bias & Vref GND 16.0V/ 6.5V Vref OK PG 28V VCC Protection OVPUVLO Comparator Base Driver OVP Comparator VCC OK FB PWM Comparator R R S Q Error Amplifier Load Compensation Max. Frequency & Green Mode CS 0.7V Leading Edge Blanking Internal OTP 0.4V/0.2V QRD GM 2.0V QRD Blanking Time Time-Out 1 Buffer QRD VCOMP Time-Out 2 Delay Counter Protection PG R S Q Q OVP 2.4V FB OVP C.C. FB VCC Delay Counter 3.5V VCOMP OLP FB Detection BNI/BNO Bulk OVPDetection
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Absolute Maximum Ratings Supply Voltage VCC 32V DRAIN -0.3V~650V FB, CS -0.3V~6.0V Maximum Junction Temperature 150C Storage Temperature Range -65C to 150C Package Thermal Resistance (SOP-8, θJA) 106C/W Junction to Case Thermal Resistance (SOP-8, θJC) 20C/W Power Dissipation (SOP-8, at Ambient Temperature = 85C) 377mW Lead temperature (Soldering, 10sec) 260C ESD Voltage Protection, Human Body Model (DRAIN pin is exclusive) 2.5 KV ESD Voltage Protection, Machine Model (DRAIN pin is exclusive) 250 V Note1: The value of JA is measured with the device mounted on 1oz one layer FR-4 board, in a still air environment with TA = 25°C. The value in any given application depends on the user’s specific board design. Caution: Stress exceeding maximum ratings may damage the device. Maximum ratings are stress ratings only. Functional operation above the recommended operating conditions is not implied. Extended exposure to stress above recommended operating conditions may affect device reliability. Recommended Operating Conditions Item Min. Max. Unit Operating Junction Temperature -40 125 C VCC voltage 9 15 V VCC capacitor 4.7 10 F Start-up resistor Value (AC Side, Half Wave) 2 6.2 M Note: 1. It’s essential to connect VCC pin with an SMD ceramic capacitor (0.1F~0.47F) to filter out the undesired switching noise for stable operation. This capacitor should be placed close to IC pin as possible. 2. If the peak of the noise coupled in FB pin is higher than 4.0V, an SMD ceramic capacitor with 10pF is recommended to connect the FB and GND pin. 3. The small signal components should be placed to IC pin as possible.
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021
Electrical Characteristics
(TA = +25oC unless otherwise stated, VCC=12.0V) PARAMETER CONDITIONS SYM. MIN TYP MAX UNITS Supply Voltage (Vcc Pin) Startup Current VCC=UVLO-ON-0.1V ICC_ST 1.0 1.9 A Operating Current VCOMP=0V, OUT=open* ICC_OP 0.65 1.5 mA UVLO (off) VCC_OFF 6 6.5 7 V UVLO (on) VCC_ON 15 16 17 V VCC OVP Level VCC_OVP 26.5 28 29.5 V QRD (Quasi Resonant Detection, FB Pin) Reference Voltage, VREF VREF 1.98 2.00 2.02 V FB OVP Level * V FB_OVP 2.4 V Load Compensation Current VCS=0.55V ILOAD_COMP 15.5 17 18.5 A Current Sensing (CS Pin) Maximum Input Voltage, VCS(OFF) VCS_MAX 0.65 0.7 0.75 V Minimum VCS-OFF At Low Line VCS_MIN_L 0.15 0.165 0.18 V At High Line* VCS_MIN_H 0.125 V Leading Edge Blanking Time TLEB 300 450 600 ns QRD (Quasi Resonant Detection, FB Pin) QRD Trip Level * VQRD 400 mV Hysteresis* VQRD_HYS 200 mV Brown In Trip Level * IBNI 85 95 105 A Brown Out Hysteresis * IBNO_HYS 10 A Brown Out De-bounce Time * TDB_BNO 70 ms Bulk cap OVP level * IBULK_OVP 350 380 410 A Bulk cap OVP delay * TBULK_OVP 450 ms Oscillator for Switching Frequency Maximum Frequency FSW_MAX 72 80 88 kHz Minimum Frequency FSW_MIN 1.35 1.5 1.65 kHz Maximum On Time TON_MAX 22 25 30 s SDSP (Secondary Diode Short Protection) SDSP CS Pin Level Secondary diode short* VCS_SDSP 1.2 V
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 PARAMETER CONDITIONS SYM. MIN TYP MAX UNITS SDSP (Secondary Diode Short Protection) De-bounce Cycle Counts in 20ms* TD_SDSP 6 Cycle OLP (Over Load Protection) OLP Delay time * TD_OLP 50 ms On Chip OTP (Over Temperature) OTP Level * TINOTP 140 C OTP Hysteresis * TINOTP_HYS 22 C MOSFET Drain (DRAIN Pin) Breakdown Voltage VDS 650 V On Resistance RDS_ON 4.5 *: Guaranteed by design.
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Typical Performance Characteristics VCC-ON (V) Fig. 1 UVLO (on) vs. Temperature Temperature (C) 13.0 14.0 15.0 16.0 17.0 18.0 -40 0 40 80 120 125 VCC-OFF (V) Temperature (C) Fig. 2 UVLO (off ) vs. Temperature 4.0 6.0 7.0 9.0 5.0 -40 0 40 80 120 125 8.0 ICC-ST (A) Temperature (C) Fig. 3 Startup Current vs. Temperature 0.5 1.0 2.0 0.0 -40 0 40 80 120 125 1.5 FSW-MAX (KHz) Fig. 4 Max Frequency vs. Temperature Temperature (C) -40 65 0 40 80 120 125 FSW-MIN (KHz) Temperature (C) Fig. 5 Min Frequency vs. Temperature 0.32 0.33 0.34 0.35 0.36 0.37 -40 0 40 80 120 125 Rds(on) (Ohm) Temperature (C) Fig. 6 Rds(on) vs. Temperature 3.5 4.0 4.5 5.0 5.5 6.0 -40 0 40 80 120 125
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 VREF (V) Temperature (C) Fig. 7 Reference Voltage vs. Temperature -40 0 40 80 120 125 1.93 1.94 2.00 2.01 2.02 1.92 -40 -20 0 20 40 60 80 100 120 Y Axis Title X Axis Title ILoad Comp (A) Temperature (C) Fig. 8 Load Compensation vs. Temperature -40 0 40 80 120 125 16.0 16.5 17.0 17.5 18.0 15.5 18.5 VCS-MAX (V) Temperature (C) Fig. 9 VCSMAX vs. Temperature 0.4 0.5 0.6 0.7 0.8 0.9 -40 0 40 80 120 125 VCC-OVP (V) Temperature (C) Fig. 10 VCC OVP vs. Temperature -40 0 40 80 120 125
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021
Application Information
The LD9162K is an excellent primary -side feedback controller with integrated MOS switch to provide a minimum components solution . The LD9162K removes the need for secondary feedback circuits while achieving excellent line and load regulation. It meets the green-power requirement and is intended for the use in those modern switching power suppliers and linear adaptors that demand high er power efficiency and power-saving. It is built-in with several functions to reduce the external components counts and the size. The major features are described as below. Under Voltage Lockout (UVLO) An UVLO comparator is implemented to detect the voltage on the VCC pin. The supply voltage should be large enough to turn on the controllers and further drive the power MOS. As shown in Fig. 11, a hysteresis window is built in to prevent the shutdown from unwanted voltage dip during the start-up. Vcc UVLO(on) UVLO(off) t t I(Vcc) operating current (~ mA) startup current (~µA) Fig. 11 Startup Current and Startup Circuit The typical startup circuit to generate VCC of the LD9162K is shown in Fig. 12 . At startup transient, the VCC is below the UVLO _ON threshold, so LD9162K will not work in this condition . Therefore, the current through R1 will be used to charge the capacitor C1. Until the VCC is fully charged to enable the LD9162K to start switching, the auxiliary winding will provide the supply power instead. If PWM controller requires less current to st art up, it will allow less power consumption on R1. By using CMOS process and some unique circuit design, the LD9162K requires only 1. 9A max to start up. Higher resistance of R1 will spend much more time to start up. The user is recommended to select proper value of R1 and C1 to optimize the power consumption and startup time. Fig. 12 Principle of CV Operation In the DCM flyback converter, it senses the output voltage through auxiliary winding. LD9162K samples the auxiliary winding on the primary-side to regulate the output voltage, as shown in the Fig . 13. The voltage induced in the auxiliary winding is a reflection of the secondary winding voltage while the MOS is in off state. Via a resistor divider connected between the auxiliary winding and FB pin, the EMI Filter Drain CS VCC GND LD9162K AC input Cbulk D1
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 auxiliary voltage is sampled after the sample delay time and will be h eld until the next sampling. The sampled voltage is compared with internal reference VREF and the error will be amplified. The error amplifier output COMP reflects the load condition and controls the duty cycle to regulate the output voltage, thus constant output voltage can be achieved. The output voltage is given as: VOUT=2.0V× (1 + Ra Rb ) (Ns Na ) − VF Where VF indicates the drop voltage of the output Diode, Ra and Rb are top and bottom feedback resistor value, Ns and N a are the turns of transformer secondary and auxiliary. In case that the output voltage is sensed through the auxiliary winding; the leakage inductance will induce ringing to affect output regulation. To optimize the drain voltage, a proper clamp circuit will minimize the high frequency ringing and achieve the best regulation. Fig . 14 shows the desired drain voltage waveform in compare to those with large undershoot due to leakage inductance induced ring (Fig. 15). This will make the sample error and cause poor performance for output voltage regulation. A proper selection for resistor R S, in ser ies with the clamp diode, may reduce any large undershoot, as shown in Fig. 13. Drain CSFB Na NsNp Ra Rb VIN LD9162K Rs LEB time Fig. 13 VDS The overshoot here is minor Fig. 14 VDS The undershoot would make the sample error. Fig. 15 Load Regulation Compensation With the purpose of keeping the voltage of the cable end constant, LD9162K is implemented with the load regulation compensation to counteract the cable voltage drop. The compensated voltage is created by sinking a certain current through the FB pin during the sampling period. The internal sinking current source is proportional to the value of VCS, as shown in Fig. 16 . Therefore, the voltage drop caused by the cable loss can be compensated as the load becomes heavy. It can also be programmed by adjusting the resistance of the voltage divider to compensate for different types or length of cable lines. The equation of the internal sink current is shown as: ILOAD_COMP ≅ Vcs× 25.83 (μA) The percentage of maximum compensation is shown as:
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Fig. 16 Quasi-Resonant Mode Detection LD9162K employs quasi-resonant (QR) switching scheme to switch at the valley of the drain voltage. This feature is able to reduce the switching loss and dv/dt in the operating range of the power supply substantially. The QR detection comparator detects the FB pin after the switch is turned off, and triggers QRD signal if the voltage drops to 0. 2V. The QR D signal remains low if VFB stays above 0.4V. Under light load condition, the resonant signal damps gradually. After the QRD signal disappears for a certain time interval, defined as time-out 1, the controller is forced to turn on the switch as soon as the limited period ends. Multi-Mode Operation The controller changes its operating frequency according to the load condition and line voltage. At heavy load condition, the operating frequency may change according to the line voltage . If the AC input is in low line, the controller usually turns on at the first valley because of the large duty cycle and long period time . If in high line, the switching frequency increases till it reaches the limit and skip s the first valley to turn on at the 2nd, 3rd….valley. The switching frequency vari es generally when the system is operated in QR mode. At medium load conditions , the frequency clamp is reduced to 25 kHz maximum. However, the characteristic in valley switching behaves as well. The LD9162K turns on the switch at the 3rd, 4th… valley. That is, when the load decreases, the system autom atically skip s some valleys and the switching frequency is thereby limited. Therefore, the smooth frequency fold-back and high power efficiency are achieved. At no load or ultra-light load conditions , the system operates in minimum frequency for lower power saving . LD9162K modulates the frequency according to the load. Current Sensing and Leading -Edge Blanking The typical current mode of PWM controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. As shown in Fig. 13, the LD9162K detects the primary MOS current from the CS pin, which is not only for the peak current mode control but also for the pulse -by-pulse current limit. The maximum voltage threshold for the current sensing pin is set at 0.7V. From above, the MOS peak current can be obtained from below. IPEAK(MAX) = 0.7V RCS A leading-edge blanking (LEB) time is included in the input of CS pin to prevent the false -trigger from the current spike. High/Low Line Detection LD9162K has s etting the high/low line detect voltage through (Ra), assume that V HL_H is the boundary voltage between high/low line detect level. The equation of Ra is shown as: VCS(V)0 0.55 IFB(A)
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Ra = VHL_H × √2 × Na NP 205μA The low line current as 197μA, according to the Ra value the C.C. compensation will adjust at different lines voltage. Principle of C.C. Operation The p rimary side control scheme is applied to eliminate secondary feedback circuit or o pto-coupler, which will reduce the system cost. The switching waveforms are shown in Fig. 17. The output current “Io” can be expressed as: S DIS CS CS S P S DISPKP, S P S DISPKS, T T R V N N T TiN N T Ti 1Io The primary peak current (iP,PK), inductor current discharge time (TDIS) and switching period (T S) can be detected by the IC . T he ratio of V CS*TDIS/TS will be modulated as a constant (VCS*TDIS/TS =1/3), so that IO can be obtained as 1×R 1×N N T T×R V×N N 1=Io CSS P S DIS CS CS S P However this is an approximate equation. The user may fine-tune it according to the experiment result. Out iP iS iP,PK iS,PK TON TDIS TS Fig. 17 Over Load Protection (OLP) - Auto Recovery To protect the circuit from damag e in over-load condition or open -loop fault, LD9162K is implemented with the smart OLP function. It also features auto recovery mechanism, referring to Fig. 18. In detail, if the protection condition is removed, the V CC level will get back to normal and the output will automatically return to the normal operation. In the case of fault condition, the voltage loop is forced toward saturation and then pull s the voltage high on the COMP signal. When it ramps up to the OLP th reshold voltage and stays longer than the delay time, the protection is activated when the output gate signals are forced to stop. With the protection mechanism, the average input power is minimized to remain the component temperature and stress within the safe operating area (SOA).
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Fig. 18 OVP (Over Voltage Protection) on V CC – Auto Recovery LD9162K is implemented with OVP function over VCC. As the VCC voltage rises over the OVP threshold voltage, the output drive circuit will be shutdown simultaneously to stop the switching of the power MOS until the next UVLO (on) arrives. The V CC OVP function of LD9162K is an auto-recovery type protection. The Fig. 19 shows its operation. On the other hand, if the OVP condition is removed, the V CC level will get back to normal level and the output will automatically return to the normal operation. Fig. 19 Brown-In/ Brown -Out Protection (BNI/BNO) and Bulk Cap OVP– Auto Recovery The LD9162K integrates the brown in, brownout protection and valley detection into FB pin. The auxiliary voltage reflects a proportional bulk voltage during the on time. Fix the internal current at the BNI, BNO and BULK_OVP, the BNI level could be set by modulating the FB divided resistors and auxiliary voltage, as shown in Fig. 13. For preventing the abnormal condit ion of line voltage to causing damage, BNO function is implemented, while turns off the gate signal after de -bounce time 70ms as BNO occurring, as shown in Fig. 20. The BULK_OVP is implemented as shown in Fig. 21. The gate signal will be turned off after d e-bounce time 450ms, while I BULK_OVP is tripped. If V BULK over V DC_BULK_OVP before start up then de-bounce time is 5ms. The relationship of input voltage and BNI/BNO and BULK_OVP is as follows. VDC_BNI = NP Na ∙ IBNI ∙ Ra VDC_BNO = NP Na ∙ IBNO ∙ Ra VDC_BULK_OVP = NP Na ∙ IBULK_OVP ∙ Ra VCC UVLO(on) UVLO(off) t t VCS OLP t Drain OLP delay time Switching SwitchingNon-Switching OLP trip Level UVLO(off) OLP Reset VCC UVLO(on) UVLO(off) t OVP Tripped t Drain Switching SwitchingNon-Switching OVP Level
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Where VDC_BNI is predicted BNI DC value of input voltage. VDC_BNO is predicted BNO DC value of input voltage. VDC_BULK_OVP is predicted BULK_OVP DC value of input voltage. IBNI is BNI trip current, IBNO is BNO trip current. IBULK_OVP is BULK OVP trip current. Np is turns ration of primary-side winding. Na is turns ration of auxiliary winding. Fig. 20 Over Voltage Protection on FB Pin (FB OVP) – Auto Recovery An output overvoltage protection is implemented in the LD9162K. The auxiliary winding voltage can be reflected from secondary winding, in which the FB pin voltage is proportional to output voltage during the gate off time. OVP is worked by sensing the auxi liary voltage via the divided resistors Rb, refereeing to Fig. 22. If VFB overs the FB OVP trip level, the internal counter starts counting 6 cycles, and then LD9162K goes to auto -recovery protection mode till the FB OVP status is defused. Fig. 21 Fig. 22 95µA t Vcc t Drain SwitchingNon-Switching t IFB t Line Voltage 85µA Non- Switching Normal Range UVLO(on) UVLO(off) LD9162K Ra Rb VCC FB GND VFB 380µA t De-Bounce Time t OUT Switching t IFB t Line Voltage Non-Switching Switching 450ms
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021 Secondary Diode Short Protection (SDSP) – Auto Recovery The logic of SDSP is described briefly as follows. If VCS is higher than 1 .2V, the count is up to 6 times in 20ms. Its gate will be turned-off, shown as Fig. 23. Fig. 23 VCOMP VCS 1.2V 6 cycle in 20ms
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021
Package Information
Dimensions in Millimeters Dimensions in Inch MIN MAX MIN MAX A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 θ 0° 8° 0° 8°
Leadtrend Technology Corporation www.leadtrend.com.tw LD9162K-DS-00 March 2021
Revision History
REV. Date Change Notice 00 03/10/2021 Original Specification Important Notice Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order.