LD7832A LEADTREND | Alldatasheet
Document overview
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Technical content
Features
Built-in 600V HV startup High power factor controller integrated High efficiency transition mode operation Accurate current regulation Wide range of UVLO (17.5 VON and 8 VOFF) VCC OVP (VCC over Voltage Protection) ZCD UVP (ZCD under voltage protection) OCP (Cycle by cycle current limit) CSSP (CS short protection) Open feedback protection OTP (Over Temperature Protection) 250/-500mA Driving Capability
Applications
LED Lamp、LED bulb Application Typical Application LD7832A HV GATE COMP VCCZCD Rs RZCD GND 2 4 EMI Filter AC Input CS 3 Fig. 1 Application Circuit
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Pin Configuration 2 3 4 TOP MARK YYWWPP ZCD COMP CS GND HV
6 VCC
SOP-7 SOP-8, DIP-8 YY: Year code WW: Week code PP: Production code
Ordering Information
Part number Package Top Mark Shipping LD7832A GR SOP-7 LD7832A GR 2500 /tape & reel LD7832A GS SOP-8 LD7832A GS 2500 /tape & reel LD7832A GN DIP-8 LD7832A GN 3600 /tube /Carton The LD7832A is ROHS compliant/ green packaged. Pin Descriptions Pin NAME FUNCTION
1 ZCD Quasi resonance detector
2 COMP Compensation pin for internal error amplifier
Current sense pin, connect to sense the MOSFET current for FB and OCP.
4 GND Ground
5 OUT Gate signal output
6 VCC Power supply to VCC
7 NC No connection
Connect this pin to th e positive of main bulk cap to provide the startup current for controller. When VCC is UVLO on , the HV loop will open and turn off internal current source to minim ize the power loss.
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Block Diagram CSLEB PWM Comparator R S OCP 1V/1.3V Ramp Generator Comparator Comp Q GM Fmax Limit Time Out Vref ZCD Driver Stage UVLO On/Off UVLO Comparator internal bias & Vref Vref OK VCC OK All Block VCC VOVP /28V VCC OVP VCC OVP R S Q GND FB PG CSSP/ Ouput SCP HV Regulator PG CounterR SQ Delay Counter CSSP PDR 6.5V PDR PG 0.08V VUVPDelay CounterOutput SCP ZCD CSSP/ Ouput SCP Max On Limit OUT HV
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Absolute Maximum Ratings VCC -0.3 ~ 30V CS -3 ~ 6V ZCD -0.3 ~ 6V IZCD -4 ~ 2mA HV -0.3 ~ 600V COMP -0.3 ~ 6V OUT -0.3 ~ 30V Maximum Junction Temperature 150C Storage Temperature Range -65C to 150C Package Thermal Resistance (SOP-7/SOP-8, JA) 160C/W Package Thermal Resistance (DIP-8, JA) 100C/W Power Dissipation (SOP-7/SOP-8) 250mW Power Dissipation (DIP-8, at Ambient Temperature = 85C) 400mW Lead temperature (Soldering, 10sec) 260C ESD Voltage Protection, Human Body Model (except HV pin) 2.5KV ESD Voltage Protection, Machine Model 250 V Caution: Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stress above Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions Item Min. Max. Unit Vcc 13 24 V Vcc pin capacitor 4.7 22 F Comp pin capacitor 0.1 2.2 F Operating Junction Temperature Range -40 125 C Operating Ambient Temperature Range -40 85 C
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013
Electrical Characteristics
(VCC=14.0V, TA = 25C unless otherwise specified.) PARAMETER CONDITIONS MIN TYP MAX UNITS High voltage Supply(HV Pin) High-voltage Current Source VCC<6V , HV=80V 0.8 1 1.2 mA 6V<VCC<UVLO(ON) 2.5 3 3.5 mA Off-state Leakage Current VCC>UVLO(ON), HV=600V - - 35 A Supply Voltage (VCC Pin) Startup Current VCC<UVLO(ON) @VCC=14V - 280 350 A Operating Current (with 1nF Load on OUT pin) COMP pin open, ZCD=12V - 1.2 1.6 mA VCC OVP tripped - 0.4 0.6 mA UVLO(OFF) 7.5 8 8.5 V UVLO(ON) 16.5 17.5 18.5 V VCC OVP Level 26 28 30 V HV Self Bias (Linear Regulator) 12 13 14 V De-latch VCC Voltage PDR 6.0 6.5 7.5 V Compensation (COMP Pin) Open Loop Voltage COMP pin open 5 5.5 6 V On Time VCOMP=2V 5 6 7 s Current Sensing (SOURCE Pin) Reference Voltage(VREF) 0.194 0.2 0.206 V OCP Threshold (cycle-by-cycle) 0.9 1 1.1 V LEB Time(1) - 250 - ns The trip level for Rs Short protection 0.05 0.08 0.1 V Delay Counter for RsSP - 20 - ms Zero Current Detector (ZCD Pin) Upper Clamp Voltage ZCDIN=12V 4.9 5.3 5.7 V Lower Clamp Voltage ZCDIN=0V 0.2 0.3 0.4 V Input Voltage Threshold(1) - 1 - V Hysteresis - 0.3 - V The trip level for ZCD UVP(1) - 4.2 - V Delay Counter of ZCD UVP - 20 - ms
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum (ON+OFF)-Time, FSW,MAX (ZCD Pin) FSW,MAX (1) Minimum (ON+OFF)-Time 200 - 300 KHz Gate Drive Output (OUT Pin) Output Low Level VCC=15V, IO=20mA - - 0.5 V Output High Level VCC=15V, IO=20mA 8 - VCC V Output High Clamp Level VCC=16V 12 13 14 V Rising Time(1) VCC =15V, CL=1nF - 100 - ns Falling Time(1) VCC =15V, CL=1nF - 25 - ns Starter Start Timer Period 60 75 90 s OTP (Over Temp. Protection) OTP Trip Level(1) 135 145 155 C OTP Hysteresis(1) 20 30 40 C Note: (1) Guaranteed by design
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Typical Performance Characteristics UVLO (on) (V) Fig. 1 UVLO (on) vs. Temperature Temperature (C) 16.8 17.0 17.2 17.4 17.6 17.8 -40 0 40 80 120 125 UVLO (off) (V) Temperature (C) Fig. 2 UVLO (off ) vs. Temperature 7.5 7.9 8.1 8.5 7.7 -40 0 40 80 120 125 8.3 HV Slef Bias (V) Temperature (C) Fig. 3 HV Slef Bias vs. Temperature -40 0 40 80 120 125 13.2 13.4 13.6 13.8 14.0 13.0 HV Current Source (mA) Temperature (C) Fig. 4 HV Current source(Vcc=1V) vs. Temperature -40 0 40 80 120 125 0.80 0.85 0.90 0.95 1.00 0.75 HV Current Source (mA) Temperature (C) Fig. 5 HV Current source(Vcc=14V) vs. Temperature -40 0 40 80 120 125 2.6 2.8 3.0 3.2 3.0 2.4 De-latch Vcc Voltage (V) Temperature (C) Fig. 6 De-latch Vcc Voltage vs. Temperature -40 0 40 80 120 125 6.6 6.7 6.8 6.9 7.0 6.5
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 On Time (us) Temperature (C) Fig. 7 On Time(Comp=2V) vs. Temperature -40 0 40 80 120 125 5.9 6.2 6.5 6.8 7.1 5.6 Reference Voltage (V) Temperature (C) Fig. 8 Reference Voltage vs. Temperature -40 0 40 80 120 125 0.18 0.19 0.20 0.21 0.22 0.17 VCS (off) (V) Temperature (C) Fig. 9 VCS (off) vs. Temperature 0.94 0.96 0.98 1.00 1.02 1.04 -40 0 40 80 120 125 Standby Current (mA) Temperature (C) Fig. 10 Standby Current vs. Temperature -40 0 40 80 120 125 0.20 0.22 0.24 0.26 0.28 0.30 VCC OVP (V) Temperature (C) Fig. 11 VCC OVP vs. Temperature 27.0 27.2 27.4 27.6 27.8 28.0 -40 0 40 80 120 125 VCOMP (V) Temperature (C) Fig. 12 VCOMP open loop voltage vs. Temperature -40 0 40 80 120 125 5.2 5.3 5.4 5.5 5.6 5.7
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013
Application Information
LD7832A is an LED controller for lighting application . The transition mode (TM) technique meets the requirement of high power factor in high efficiency. It minimizes the external component counts and the PCB size for compact application. LD7832A is also designed to operate in voltage-mode TM mode. The switch turn-on time is fixed while the turn-off time varies in steady state. Therefore, the switch frequency changes in response to the different voltages. The affected frequency reduces EMI noise. LD7832A also features LED open protection, LED short protection, over current protection, CS short protection, open feedback protection , and over temperature protection. No extra mains voltage sensing is required as what the traditional current mode PFC controllers behave s for power saving. Internal High-Voltage Startup Circuit and Under Voltage Lockout (UVLO) The traditional circuit provides the startup current through a resistor to power up the PWM controller. However, it consumes too significant power to meet the current power saving requirement. In most cases, larger resistor carries larger resistance; it wastes more time to startup. To achieve the optimized topology, as shown in Fig.1, LD7832A is implemented with a high -voltage startup circuit on HV pin for it. During startup, a high -voltage current source sinks current from the output of full-bridge rectifier to provide the startup current and charge the VCC capacitor. Once VCC drops below PDR, the charge current will remain at 1mA to protect the circuit from being damaged, even in case V CC pin is shorted to ground. In contrast, the charge current will increase to 3mA once V CC rises above PDR voltage threshold during start -up. Meanwhile, the V CC supply current is as low as 280A that most of the HV current is reserved to charge the V CC capacitor. By using such configuration, the turn-on delay time will be almost same no matter under low-line or high-line conditions. As the V CC voltage rises higher than UVLO(on) to power the LD7832A and further to deliver the gate drive signal, the high -voltage current source will be disabled and the supply current is provided from the inductor. Therefore, it would reduce the power loss on the startup circuit and perform highly power saving. An UVLO comparator is embedded to detect the voltage on the VCC pin to ensure the supply voltage enough to power on the LD7832A controller and in addition to drive the power MOSFET. As shown in Fig. 2, a hysteresis is provided to prevent the shutdown from the voltage dip during startup. Vcc UVLO(on) UVLO(off) t t HV Current 1mA Startup Current Vcc current ~ 0mA (off) Operating Current (Supply from Inductor) PDR 3mA Fig. 2
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Ramp Generator Block and Zero Current Detection (ZCD) Fig. 3 shows typical ramp generator block and ZCD block. The COMP pin voltage and the output of the ramp generator block are compared to determine the MOSFET On-time, as shown in Fig. 4. The LD7832A features transition mode operation. The zero current detection block circuit detects the ZCD signal to turn on the MOSFET soon after the voltage across ZCD falls to 1V and also the current through the inductor reaches zero. Instead, if there’s no signal detected within 70s, the time-out will generate a signal to turn on MOSFET to ensure the system operate properly. PWM Comparator R S OCP 1V/1.3V Ramp Generator Comparator Comp Q GM Fmax Limit Time Out Vref ZCD FB Max On Limit Fig. 3 During the delay time as shown in Fig. 4, the junction capacitor of the MOSFET resonates with the inductor and the drain -source voltage (VDS) decreases accordingly. So, the MOSFET consumes less voltage and the power dissipation will be minimized. As recommended in Fig. 1, only one resistor (RZCD) is required to connect ZCD pin in series with the inductor to detect the inductor signal and protect ZCD pin from damage. It makes the circuit simple and easy to design with. Fig. 4 shows the related waveforms between the changing inductor voltage and ZCD vo ltage. ZCD pin is clamped at 5. 3V or 0.3V in accordance with var ious inductor voltages. IPEAK TON TDIS Inductor Current Inductor Voltage VDS VOUT-VIN Delay Time VOUT VIN Minimum Voltage Turn-on OUT VCOMP RAMP ZCD Voltage 5.3V 0.3V Fig. 4 LED Short Protection (ZCD UVP) – Auto Recovery To protect the circuit from damage due to LED short condition, an auto-recovery type of ZCD UVP protection is implemented for it. Fig. 5 shows the waveforms of the ZCD UVP operation. In LED short condition, the reflected output voltage of inductor will cause ZCD voltage drop. If the ZCD voltage sinks below 4 .3V for more than the delay time of ZCD UVP , the protection will be activated to turn off the gate until the 4th cycle of Vcc hiccup is tripped. The ZCD UVP delay time is to prevent the false-triggering.
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 ZCD Lower Clamp UVP Level t ZCD UVP Tripped t OUT Switching Switching Non-Switching Inductor Voltage t Upper Clamp Vcc t LED Shorted Vout ZCD UVP Delay Time -Vin UVLO(on) UVLO(off) VD+VRS GND ZCD UVP Delay Time CSSP Blacking Time 4 times Hiccup Fig. 5 Over Current Protection (OCP) The LD7832A detects the MOSFET current from the CS pin, which is for the pulse -by-pulse current limit and output current feedback. The maximum voltage threshold of the CS pin is set at 1.0V. From above, the MOSFET peak current can be obtained from below. S )MAX(PEAK R V0.1I CS Short Protection (CSSP) – Auto Recovery In order to pr event the LED driver from damage due to the shorted sense resistor (Rs), CS pin is built in with CSSP protection. See Fig. 6. Once the fault condition occurs, the CS voltage will drop to GND level instantaneously and it will enable the protection with CSSP delay time to avoid the false -trigger. When VCC achieves the UVLO(on), the LD7832A will start the CSSP blanking time to ignore CSSP function to pass the start-up transient. t OUT Switching SwitchingNon-Switching VRS t Vcc t RS Shorted VRS_PEAK CSSP Delay Time UVLO(on) UVLO(off) CSSP Delay Time CSSP Blacking Time CSSP Level CSSP Tripped 4 times Hiccup Fig. 6 Over Voltage Protection (VCC OVP) The maximum rating of the VCC pin is limited below 30V. To prevent VCC from damage due to fault condition, the LD7832A is implemented with OVP function on VCC pin. As soon as the V CC voltage is over OVP threshold voltage, the output gate drive circuit will be shutdow n simultaneously thus to stop the switching of the power MOSFET until the next UVLO(on) arrives. The V CC OVP function of the LD7832A is an auto -recovery protection. The Fig. 7 shows its operation. Upon removal of the OVP condition will resume the VCC level and the output operation VCC UVLO(on) UVLO(off) t OVP Tripped t OUT Switching SwitchingNon-Switching OVP Level Fig. 7
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Output Drive Stage An output stage of a CMOS buffer, with typical 250mA/-500mA driving capability, is incorporated to drive the power MOSFET directly. The output voltage is clamped at 13V to protect the MOSFET gate even when the VCC voltage rises over 13V.
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013
Package Information
Dimensions in Millimeters Dimensions in Inch MIN MAX MIN MAX A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 θ 0° 8° 0° 8°
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Dimensions in Millimeters Dimensions in Inch MIN MAX MIN MAX A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 θ 0° 8° 0° 8°
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013 Dimension in Millimeters Dimensions in Inches Min Max Min Max A 9.017 10.160 0.355 0.400 B 6.096 7.112 0.240 0.280 D 0.356 0.584 0.014 0.023 E 1.143 1.778 0.045 0.070 F 2.337 2.743 0.092 0.108 I 2.921 3.556 0.115 0.140 J 7.366 8.255 0.29 0.325 Important Notice Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order.
Leadtrend Technology Corporation www.leadtrend.com.tw LD7832A-DS-00 April 2013
Revision History
Rev. Date Change Notice 00 2013/04/17 Original Specification.