LD7750

LD7750 LEADTREND | Alldatasheet

Document overview

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Technical content

Features

z High-Voltage (500V) Startup Circuit z Current Mode Control z Non-Audible-Noise Green Mode Control z UVLO (Under Voltage Lockout) z LEB (Leading-Edge Blanking) on CS Pin z Internal Frequency Swapping z Internal Slope Compensation z Internal Over Current Protection z OVP (Over Voltage Protection) on Vcc z OLP (Over Load Protection) z External OTP through a NTC z 500mA Driving Capability

Applications

z Switching AC/DC Adaptor and Battery Charger z Open Frame Switching Power Supply z LCD Monitor/TV Power Typical Application EMI Filter photocoupler AC input *See Application Information LD7750 VCCHV OTP GND COMP CS OUT

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Pin Configuration YY: Year code WW: Week code PP: Production code 2 3 4 7 6 5 TOP MARK YYWWPP OTP COMP CS GND HV NC VCC OUT SOP-8 & DIP-8 (TOP VIEW) 2 3 4 6 5 TOP MARK YYWWPP OTP COMP CS GND HV VCC OUT SOP-7 (TOP VIEW)

Ordering Information

Freq. Protection Mode Package Top Mark Shipping LD7750 GR 65KHz Auto recovery SOP-7 G reen package LD7750GR 2500 /tape & reel LD7750 GS 65KHz Auto recovery SOP-8 G reen package LD7750GS 2500 /tape & reel LD7750 GN 65KHz Auto recovery DIP-8 Green package LD7750GN 3600 /tube /Carton The LD7750 is ROHS compliant. Pin Descriptions PIN DIP-8 SOP-8 SOP-7 NAME FUNCTION 1 1 OTP Pulling this pin below 0.95V will shutdo wn the controller to enter latch mode until the AC power-on recycles. Connecting a NTC between this pin and ground will achieve OTP protecti on function. Let this pin float to disable the latch protection. 2 2 COMP Voltage feedback pin. By connecting a photo-coupler to close the control loop can achieve the regulation. 3 3 CS Current sense pin, fo r sensing the MOSFET current. 4 4 GND Ground. 5 5 OUT Gate drive output to drive the external MOSFET. 6 6 VCC Supply voltage pin. 7 *** NC Unconnected Pin. 8 7 HV Connect this pin to a positive terminal of bulk capacitor to provide the startup current for the controller. When Vcc voltage trips the UVLO(on), this HV loop will be turned off to reduce the power loss on the startup circuit.

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Block Diagram

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Absolute Maximum Ratings Supply Voltage VCC 30V High-Voltage Pin, HV -0.3V~500V COMP,OTP, CS -0.3V ~7V OUT -0.3V ~Vcc+0.3 Maximum Junction Temperature 150 °C Operating Ambient Temperature -20 °C to 85°C Operating Junction Temperature -40 °C to 125°C Storage Temperature Range -65 °C to 150°C Package Thermal Resistance (SOP-8, SOP-7) 160 °C/W Package Thermal Resistance (DIP-8) 100 °C/W Power Dissipation (SOP-8, SOP-7, at Ambient Temperature = 85°C) 400mW Power Dissipation (DIP-8, at Ambient Temperature = 85°C) 650mW Lead temperature (Soldering, 10sec) 260 °C ESD Voltage Protection, Human Body Model (except HV Pin) 2.5KV ESD Voltage Protection, Machine Model 250V Gate Output Current 500mA Caution: Stresses beyond the ratings specified in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this s pecification is not implied.

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010

Electrical Characteristics

(TA = +25°C unless otherwise stated, VCC=15.0V) PARAMETER CONDITIONS MIN TYP MAX UNITS High-Voltage Supply (HV Pin) High-Voltage Current Source V CC< UVLO(on), HV=500V 0.5 1.0 1.5 mA Off-State Leakage Current V CC> UVLO(off), HV=500V 35 μA Supply Voltage (Vcc Pin) Startup Current 200 320 400 μA VCOMP=0V, LD7750 2.5 mA VCOMP=3V, LD7750 2.9 mA OLP tripped, LD7750 0.50 mA Operating Current (with 1nF load on OUT pin) OVP tripped, VCC=OVP 0.63 mA UVLO (off) 9.0 10.0 11.0 V UVLO (on) 15.0 16.0 17.0 V OVP Level 24.5 26.0 27.5 V Voltage Feedback (COMP Pin) Short Circuit Current V COMP=0V 1.45 1.75 mA Open Loop Voltage COMP pin open 5.3 5.7 V Green Mode Threshold VCOMP 2.75 V Burst Mode 2.0 V Current Sensing (CS Pin) Maximum Input Voltage,Vcs_off 0.80 0.85 0.90 V Leading Edge Blanking Time 250 nS Input impedance 1 M Ω Delay to Output 100 nS

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 (TA = +25°C unless otherwise stated, VCC=15.0V) PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator for Switching Frequency Frequency LD7750 61.0 65.0 69.0 KHz Green Mode Frequency LD7750 20 KHz Swapping Frequency LD7750 ±4 KHz Temp. Stability -20 °C~85°C 5 % Voltage Stability (VCC=11V-25V) 1 % OTP Pin Latch Protection (OTP Pin) OTP Pin Source Current 92 100 108 μA Turn-On Trip Level 0.95 1.05 1.10 V Turn-Off Trip Level 0.85 0.95 1.0 V De-latch VCC Level (PDR, Power Down Reset) 8.0 V Gate Drive Output (OUT Pin) Output Low Level VCC=15V, Io=20mA 1 V Output High Level VCC=15V, Io=20mA 9 V Rising Time Load Capacitance=1000pF 100 160 nS Falling Time Load Capacitance=1000pF 30 60 nS OLP (Over Load Protection) OLP Trip Level 4.8 5.0 5.2 V OLP Delay Time 64 mS Soft Start Duration Soft Start Duration 2 ms On Chip OTP (Internal Over Temperature Protection, Auto-Recovery) OTP Level 140 °C OTP Hysteresis 30 °C

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Typical Performance Characteristics HV Current Source (mA) Temperature (°C) Fig. 1 HV Current Source vs. Temperature (HV=500V, Vcc=0V) 0.7 0.9 1.1 1.3 1.5 -40 0 40 80 120 125 VCS (off) (V) Temperature (°C) Fig. 2 V CS (off) vs. Temperature 0.83 0.84 0.85 0.86 0.87 0.88 -4 0 0 40 80 120 125 UVLO (on) (V) Fig. 3 UVLO (on) vs. Temperature T emperature (°C) 14.0 14.8 15.6 16.4 17.2 18.0 -4 0 0 40 80 120 125 UVLO (off) (V) Temperature (°C) Fig. 4 UVLO (off ) vs. T emperature 9. 6 10 .4 8.8 -40 0 40 80 120 12 5 11 .2 Frequency (KHz) Fig. 5 Frequency vs. Temperature Temperature (°C) -40 60 0 40 80 120 125 Frequency (KHz) Temperature (°C) Fig. 6 Green Mode Frequency vs. Temperature -40 0 40 80 120 125

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Frequency (KHz) Vcc (V) Fig. 7 Frequency vs. Vcc 12 14 16 18 20 22 24 11 25 Green mode frequency (KHz) Vcc (V) Fig. 8 Green mode frequency vs. Vcc 12 14 16 18 20 22 2411 25 Max Duty (%) Temperature (°C) Fig. 9 Max Duty vs. Temperature -40 0 40 80 120 125 VCC OVP (V) Temperature (°C) Fig. 10 VCC OVP vs. Temperature -40 0 40 80 120 125 VCOMP (V) Temperature (°C) Fig. 11 V CO MP open loop voltage vs. Temperature -40 0 40 80 120 125 4.5 5.0 5.5 6.0 6.5 7.0 OLP (V) T emperature (°C) Fig. 12 OLP-Trip Level vs. T emperature -40 0 40 80 120 125 3.5 4.0 4.5 5.0 5.5 6.0

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010

Application Information

As green power requirements become a trend and the power saving gets more and more important for the switching power supplies a nd switching adaptors, the traditional PWM controllers are not able to support such new requirements. Furthermore, the cost and size limitations force PWM controllers to be more powerful by integrating more function s and, thus, reducing the external part count. LD7750 is designed for such application to provide an easy and cost effective solution. Its detail features are described as below. Internal High-Voltage Startup Circuit and Under Voltage Lockout (UVLO) Traditional circuits power on the PWM controller through a startup resistor to constant ly provide current from a rectified voltage to the capac itor connected to Vcc pin. Nevertheless, this startup resi stor was usually of larger resistance, and it therefor e consumed more power and required longer time to start up. To achieve an optimized topology, as shown in Fig. 13, The LD7750 is built in with high voltage startup circuit to optimize the power saving. During the startup sequence, a high-voltage current source sinks current from C BULK capacitor to provide the star tup current as well as to charge the Vcc capacitor C1. During the initialization of the startup, Vcc voltage is lower than the UVLO(off) threshold thus the current source is on to supply a current of 1mA. Meanwhile, as the Vcc current consumed by the LD7750 is as low as 320μA thus most of the HV current is utilized to charge the Vcc capacitor. By using such configuration, the turn-on del ay time will be almost the same no matter whether operation condition is under low-line or high-line. When Vcc voltage reaches UV LO(on) threshold, the LD7750 is powered on to start issuing the gate drive signal, the high-voltage current source is then disabled, and the Vcc supply current will be only provided from the auxiliary winding of the trans former. Therefore, the power loss on the startup circuit beyond the startup period can be eliminated and the power saving can be easily achieved. In general application, a 39K Ω resistor is still recommended to be placed in high voltage path to limit the current if there is a negat ive voltage applying in any case. An UVLO comparator is incl uded to detect the voltage on the V CC pin to ensure the supply voltage is high enough to power on the LD7750 PWM controller and in addition to drive the power MOSFET as well. As shown in Fig. 14, a Hysteresis is provided to prevent the shutdown caused by the voltage dip during startup. The turn-on and turn-off threshold levels are set at 16V and 10.0V, respectively. Fig. 13

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Fig. 14 Current Sensing, Leading-edge Blanking and the Negative Spike on CS Pin The typical current mode PWM controller feeds back both current signal and voltage signal to close the control loop and achieve regulation. The LD7750 detects the primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. The maximum voltage threshold of the current sensing pin is set as 0.85V. Thus the MOSFET peak current can be calculated as: S )MAX(PEAK R V85.0I = A 250nS leading-edge blanking (LEB) time is included in the input of CS pin to prevent false-trigger caused by the current spike. For low power app lication, if the total pulse width of the turn-on spike is less than 250nS and the negative spike on the CS pin is not as low as -0.3V, the R-C filter (as shown in Fig.15) can be eliminated. However, the total pulse widt h of the turn-on spike is related to the output power, circuit design and PCB layout. Nevertheless, it is strongly recommended to add a small R-C filter (as shown in Fig. 16) for higher power applications to avoid the CS pin being damaged by the negative turn-on spike. Output Stage and Maximum Duty-Cycle An output stage of a CMOS buffer, with typical 500mA driving capability, is incorporated to drive a power MOSFET directly. And the maximum duty-cycle of LD7750 is limited to 75% to avoid the transformer saturation. Voltage Feedback Loop The voltage feedback signal is provided from the TL431 in the secondary side through the photo-coupler to the COMP pin of LD7750. The input stage of LD7750, like the UC384X, is incorporated wi th 2 diodes voltage offset circuit and a voltage divider with 1/3 ratio. Therefore, )V2V(3 1)V FCOMPPWM( COMPARATOR −×=+ A pull-high resistor is embedded internally and thus an external one is not required. Switching Frequency The LD7750 is implemented with frequency swapping function which helps the power supply designers both optimize EMI performance and lower system cost. The switching frequency substant ially centers at 65KHz, and trembles within the range of ±4KHz.

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Fig. 15 Fig. 16 Internal Slope Compensation Stability is crucial for current mode control when it operates at more than 50% of duty-cycle. To stabilize the control loop, the slope com pensation is required in the traditional UC384X design by injecting the ramp signal from the RT/CT pin through a coupling capacitor. In the LD7750, the internal slope compensation circuit has been implemented to simplify the external circuit design. On/Off Control The LD7750 can be turned off by pulling COMP pin to lower than 2.0V. The gate output pin of LD7750 will be disabled immediately under such condition. The off-mode can be released when the pull-low signal is removed. Green-Mode Operation By using the green-mode control, the switching frequency can be reduced under the light load condition. This feature helps to improve the efficiency in light load conditions. The green-mode control is Leadtrend Technology’s own IP. Over Load Protection (OLP) - Auto Recovery To protect the circuit from the damage caused by overload condition or output short condition, a smart OLP function is implemented in the LD7750 for it. The OLP function in LD7750 is an auto-recovery type protection. Fig. 17 shows the waveform s of the OLP operation. Under such fault condition, the feedback system will force the voltage loop toward saturation and thus pull the voltage on COMP pin (VCOMP) to high. Whenever the VCOMP trips the OLP threshold of 5.0V and stays for over 63mS, the protection will be ac tivated to turn off the gate output and to shutdown the sw itching of power circuit. The 63mS delay time is to prevent the false-trigger during the power-on and turn-off transient.

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 A divided-by-2 counter is implemented to reduce the average power consumption under OLP behavior. Whenever OLP is activated, the output is latched off and the divided-by-2 counter star ts to count the number of UVLO(off). The latch will be released if the 2nd UVLO(off) point is counted, and then the output recovers switching again. By using such protection me chanism, the average input power can be reduced to a very low level so that the component temperature an d stress can be controlled within a safe operating area. Fig. 17 OVP (Over Voltage Protection) on Vcc- Auto Recovery The V GS ratings of the nowadays power MOSFETs are mostly with 30V maximum. To protect the V GS from the fault condition, LD7750 is implemented with OVP function on Vcc. Whenever the Vcc voltage is larger than the OVP threshold voltage, the output gate drive circuit will be shut down simultaneously and stop switching of the power MOSFET until the next UVLO(ON). The Vcc OVP function in LD7750 is an auto-recovery type protection. If the OVP condition, usually caused by open feedback loop, is not released, the Vcc will trip the OVP level again and shutdown the output. The Vcc is working in hiccup mode. Fig. 18 shows its operation. Once the OVP condition is removed, the Vcc and the output will resume to normal operation. Fig. 18 OTP Pin --- Latched Mode Protection To protect the power circuit from damage due to system failure, over temperature protection (OTP) is required. The OTP circuit is implemented to sense a hot-spot of power circuit like power MOSFET or output rectifier. It can be easily achieved by connecting a NTC with OTP pin of LD7750. As the device temperature or ambient temperature rises, the resi stance of NTC decreases. So, the voltage on the OTP pin could be written as below. NTCOTP RAμ100V ⋅= When the VOTP is less than the defined threshold voltage (typical 0.95V), LD7750 will shutdown the gate output and then latch the power supply off. The controller will remain latched unless the Vcc drops below 8V (power down reset) and the fault condition is removed at the same time. There are 2 conditions required to restart it successfully. First, cool down the circuit so that NTC resistance will increase and raise V OTP above 1.05V. Then,

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 remove the AC power cord and restart AC power-on recycling. The detailed operation is depicted in Fig. 19. Pull-Low Resistor on the Gate Pin of MOSFET An anti-floating resistor is built in with the OUT pin to prevent the output from any un certain state. Otherwise, it may cause the MOSFET to work abnormally or mis-trigger. However, such design won’t cover the condition of disconnection between the OUT pin and the gate terminal for the MOSFET. Thus it is still strongly recommended to have a resistor connec ted at the MOSFET gate terminal (as shown in Fig. 20) to provide extra protection for fault conditions. This external pull-low resistor is to prevent the MOSFET from damage during power-on when the gate resistor R g is disconnected. In such a fault condition, as show in Fig. 21, the resistor R8 can prov ide a discharge path to avoid the MOSFET from being falsel y triggered by the current through the gate-to-drain capacitor C GD. Therefore, the MOSFET should be always pulled-low to persist in off-state. UVLO(on) UVLO(off) t AC input Voltage OTP t OUT Switching Switching Non-Switching t VCC t 1.05V 0.95V V(-)Latch OTP Release PDR (8V) AC Off AC On (Recycle) Latch Released Fig. 19 Fig. 20

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 dt dVCgdi bulk⋅= Fig. 21 Protection Resistor on the Hi-V Path In some other Hi-V processes and designs, there may be a parasitic SCR between HV pin, Vcc and GND. As shown in Fig. 22, a small negative spike on the HV pin may trigger this parasitic SCR and cause latchup between Vcc and GND. And such latchup will easily damage the chip because of the equivalent short-circuit induced. With the Leadtrend’s proprietary Hi-V technology, there is no such parasitic SCR in LD7750. Fig. 23 shows the equivalent circuit of LD77 50’s Hi-V structure. The LD7750 has higher capability to sustain negative voltage than similar products. Nevertheless, a 39K Ω resistor is recommended to implement on the Hi-V path as a current limit resistor no matter what negative voltage is present in a n y s i t u a t i o n . Fig. 22 Fig. 23

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Reference Application Circuit --- 10W (5V/2A) Adapter Pin < 0.15W when Pout = 0W & Vin = 264Vac photocoupler IC1 RS2 IC2 CY1 LD7750 (-)LATCH VCC GND COMP CS OUT AC input NTC1 CX1 R1A R1B D1A~D1D R6D4 R4A CR51 C51 R51A L51 C52 R51B C54 FL1 R4BZD51 R56AR56B R54R52 C55 R55 R53 IC5 HV RS1 N L Schematic NTC2

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 BOM P/N Component Value Original R1A N/A R1B N/A R4A 39K Ω, 1206 R4B 39K Ω, 1206 R6 2.2 Ω, 1206 R7 10 Ω, 1206 R8 10K Ω, 1206 R9 40K Ω, 1206 RS1 2.7 Ω, 1206, 1% RS2 2.7 Ω, 1206, 1% RT 100K Ω, 0805, 1% R51A 100 Ω, 1206 R51B 100 Ω, 1206 R52 2.49K Ω, 0805, 1% R53 2.49K Ω, 0805, 1% R54 100 Ω, 0805 R55 1K Ω, 0805 R56A 2.7K Ω, 1206 R56B N/A NTC1 5 Ω, 3A 08SP005 FL1 20mH UU9.8 T1 EI-22 L51 2.7 μH P/N Component Value Note C1 22 μF, 400V L-tec C2 22 μF, 50V L-tec C4 1000pF, 1000V, 1206 Holystone C5 0.01 μF, 16V, 0805 C51 1000pF, 50V, 0805 C52 1000 μF, 10V L-tec C54 470 μF, 10V L-tec C55 0.022 μF, 16V, 0805 CX1 0.1 μF X-cap CY1 2200pF Y-cap D1A 1N4007 D1B 1N4007 D1C 1N4007 D1D 1N4007 D2 PS102R D4 1N4007 Q1 2N60B 600V, 2A CR51 SB540 ZD51 6V2C IC1 LD7750 GS SOP-8 IC2 EL817B IC51 TL431 1% F1 250V, 1A Z1 N/A

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010

Package Information

Dimensions in Millimeters Dimensions in Inch Symbols MIN MAX MIN MAX A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.229 0.007 0.009 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 θ 0° 8° 0° 8°

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 SOP-8 Dimensions in Millimeters Dimensions in Inch Symbols MIN MAX MIN MAX A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.229 0.007 0.009 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 θ 0° 8° 0° 8°

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010 Dimension in Millimeters Dimensions in Inches Symbol Min Max Min Max A 9.017 10.160 0.355 0.400 B 6.096 7.112 0.240 0.280 D 0.356 0.584 0.014 0.023 E 1.143 1.778 0.045 0.070 F 2.337 2.743 0.092 0.108 I 2.921 3.556 0.115 0.140 J 7.366 8.255 0.29 0.325 Important Notice Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Custom ers should verify the datasheets are current and complete before placing order.

Leadtrend Technology Corporation www.leadtrend.com.tw LD7750-DS-00b February 2010

Revision History

Rev. Date Change Notice 00 9/16/2009 Original specification 00a 11/11/2009 Package option: SOP-7 00b 2/22/2010 Frequency Trembling ÆFrequency Swapping