LCX032AK

LCX032AK SONY | Alldatasheet

Document overview

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• PDF pages: 23

Technical content

Features

• The number of active dots: 113,578 (0.44 Type; 1.115cm in diagonal)
• Horizontal resolution: 260 TV lines
• High optical transmittance: 4.8% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, TTL drive possible)
• High quality picture representation with RGB delta arranged color filters
• Full-color representation
• NTSC/PAL compatible
• Up/down and/or right/left inverse display function
• 4:3 and 16:9 aspect switching function
• Power save mode (Through current reduction by stop of level shifter and scanner during power supply cutoff) Element Structure
• Dots Total dots : 537 (H) Active dots: 521 (H) · 218 (V) = 113,578
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.

Applications

• Viewfinders
• Super compact liquid crystal monitors etc. LCX032AK

– 2 – LCX032AK Block Diagram 12345678910111213141516 H Shift R egister V Level C onversion C ircuit V Shift Register C S LC C O M Pad V DD V SS VST VCK STB EN DW N RGT HST HCK2 HCK1 BLK BLUE RED GREEN COM H Level C onversion C ircuit

– 3 – LCX032AK Absolute Maximum Ratings(VSS = 0V)

• H and V driver supply voltages VDD –1.0 to +17 V
• Common pad voltage COM –1.0 to +17 V
• H driver input pin voltage HST, HCK1, HCK2 –1.0 to +17 V RGT
• V driver input pin voltage VST, VCK, DWN, –1.0 to +17 V EN, BLK
• Power save mode input pin voltageSTB –1.0 to +17 V
• Video signal input pin voltage GREEN, RED, BLUE –1.0 to +15 V
• Operating temperature Topr –10 to +70 °C
• Storage temperature Tstg –30 to +85 °C Operating Conditions(VSS = 0V) Supply voltage VDD 11.4 to 14.0 V Input pulse voltage (Vp-p of all input pins except video signal input pins) Vin 2.6V (more than) Pin Description Pin No. COM GREEN RED BLUE BLK HCK1 HCK2 HST Common voltage of panel Video signal (G) to panel Video signal (R) to panel Video signal (B) to panel Top/bottom block display pulse Clock pulse for H shift register drive Clock pulse for H shift register drive Start pulse for H shift register drive RGT DWN EN STB VCK VST Vss V DD Drive direction pulse for H shift register (H: normal, L: reverse) Drive direction pulse for V shift register (H: normal, L: reverse) Enable pulse for gate selection For power save mode control (L-power save mode) Clock pulse for V shift register drive Start pulse for V shift register drive GND (H, V drivers) Power supply for H and V drivers Symbol Description Pin No. Symbol Description

– 4 – LCX032AK Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supply. In addition, protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.) (1) Video signal input Input VD D From H driver Signal line 1M Ω (2) HCK1, HCK2 VD D 250Ω 250Ω 250Ω250Ω Level conversion circuit (2-phase input)H C K1 H C K2 1M Ω 1M Ω (3) HST Level conversion circuit (single- phase input) 250Ω250Ω VD D Input 1M Ω (4) RGT, VST, EN, VCK, DWN, STB Level conversion circuit (single- phase input) 2.5kΩ2.5kΩ VD D Input 1M Ω (6) COM Input 1M Ω LC VD D Level conversion circuit (single- phase input) 2.5kΩ2.5kΩ VD D Input 1M Ω28kΩ (5) BLK

– 5 – LCX032AK Level Conversion Circuit The LCX032AK has a built-in level conversion circuit in the clock input unit located inside the panel. The circuit voltage is stepped up to V DD inside the panel. This level conversion circuit meets the specifications of a 3.0V power supply of the externally-driven IC. 1. I/O characteristics of level conversion circuit (For a single-phase input unit) An example of the I/O voltage characteristics of a level conversion circuit is shown in the figure to the right. The input voltage value that becomes half the output voltage (after voltage conversion) is defined as Vth. The Vth value varies depending on the V DD voltage. The Vth values under standard conditions are indicated in the table below. (HST, VST, EN, DWN, STB, RGT, VCK and BLK in the case of a single-phase input) V DD = 12.0V VD D VD D Vth Input voltage [V] Exam ple of single-phase I/O characteristics Output voltage (inside panel) Item Vth voltage of circuitVth 0.35 1.50 2.60 V Symbol Min. Typ. Max. Unit (For a differential input unit) An example of I/O voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. Although the characteristics, including those of the Vth voltage, are basically the same as those for a single-phased input, the two- phased input phase is defined. (Refer to clock timing conditions.) VD D VD D Vth Input voltage [V] Exam ple of differential I/O characteristics Output voltage (inside panel) 2. Current characteristics at the input pin of level conversion circuit A slight pull-in current is generated at the input pin of the level conversion circuit. (The equivalent circuit is shown to the right.) The current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (Refer to electrical characteristics.) VD D output H C K1 input H C K2 input Level conversion equivalent circuit M ax. value Input pin voltage [V] 10 Pull-in current characteristics at the input pin Input pin current

– 6 – LCX032AK Input Signals 1. Input signal voltage conditions(VSS = 0V, VDD = 11.4 to 14V) Item H driver input voltage (HST, HCK1, HCK2, RGT, STB) (Low) (High) (Low) (High) VHIL VHIH VVIL VVIH V COM –0.35 2.6 –0.35 2.6 VVC – 0.45 0.0 5.0 0.0 5.0 VVC – 0.3 0.35 5.5 0.35 5.5 VVC – 0.15 V V V V V V driver input voltage (VST, VCK1, VCK2, DWN, EN) Common voltage of panel Symbol Min. Typ. Max. Unit Note)Video signal shall be symmetrical to video signal center voltage VVC. Supplement1) Video signal input range is set within the range shown below for V DD and VSS . Also, video signal white level is defined for VVC as shown below. Item Video signal input range Video signal input white level Vsig VsigL VSS + 1.3 0.5 VDD – 1.8 V V Symbol Min. Typ. Max. Unit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines VsigL W hite level VsigL Video signal input range M ax. VD D – 1.8 [V] M in. VSS + 1.3 [V] VD D VD D – 1.8 VVC VSS + 1.3 VSS Supplement2) When power save mode is used, use video signal and COM pin within the condition ±0.15V to prevent DC applying to LCD.

– 7 – LCX032AK Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn* 2 rise time Hckn*2 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time En rise time En fall time Vck fall to En fall time Vck rise to En rise time BLK rise time BLK fall time BLK pulse width BLK fall to CLR fall time trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEn tfEn tdVck2 tdVck1 trBlk tfBlk twBlk toClr –170 –455 –15 –15 –50 –50 –100 –100 600 135 –135 –32 1.0 700 170 –50 100 100 –20 100 100 100 100 100 100 100 100 800 ns µs ns ms ns Item Symbol Min. Typ. Max. Unit HST HCK VST VCK EN BLK * *2 Hckn means Hck1, Hck2. (fHckn = 1.84MHz, fVckn = 7.865kHz) *3 BLK pulse is used only for 16:9 mode. For 4:3 mode, connect to VSS . 2. Clock timing conditions(Ta = 25°C, Input voltage = 3.0V, VDD = 12.0V)

– 8 – LCX032AK <Horizontal Shift Register Driving Waveform> Hst rise time HST HCK Hst fall time Hst data set-up time Hst data hold time Hckn*2 rise time Hckn*2 fall time Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time

• HCKn *2 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• HCKn * duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• HCKn * duty cycle 50% to1Hck = 0ns to2Hck = 0ns tdHst = 135ns thHst = –135ns
• tdHst = 135ns thHst = –135ns trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck Item Symbol Waveform Conditions 90% 10% 10% 90% H ST trH st tfH st 50% 50% H ST H C K1 tdH st thH st 50%50% H C Kn 10% 10% 90% 90% trH ckn tfH ckn 50% 50%∗4 H C K1 to2H ck to1H ck 50%50% H C K2

– 9 – LCX032AK *4 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. <Vertical Shift Register Driving Waveform> Vst rise time VST VCK EN Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time En rise time En fall time Vck rise to En rise time Vck rise to En fall time

• VCK duty cycle 50%
• VCK duty cycle 50%
• VCK duty cycle 50% tdVst = 32µs thVst = –32µs
• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns
• VCK duty cycle 50% to1Vck = 0ns to2Vck = 0ns trVst tfVst tdVst thVst trVck tfVck trEn tfEn tdVck tdVck BLK BLK rise time BLK fall time BLK pulse width BLK fall to CLR fall time trBlk tfBlk twBlk toClr Item Symbol Waveform Conditions 90% 10% 10% 90% VST trVst tfVst 50% 50% VST VC K tdVst thVst 50%50% VC K 10% 10% 90% 90% trVck tfVck 90% 90% 10%10% tfEn trEn EN 50% VC K tdVck tdVck 50%50% EN 50% 90% 10% 10% 90% trBlk tfBlk 50% 50% BLK C LR tw Blk 50%

– 10 – LCX032AK

Electrical Characteristics

1. Horizontal drivers (Ta = 25°C, VDD = 12.0V, Input voltage = 3.0V) Item Input pin capacitanceHCKn HST Input pin current HCK1 HCK2 HST RGT STB Video signal input pin capacitance CHckn CHst IHck1 IHck2 IHst IRgt Istb Csig HCK1 = GND HCK2 = GND HST = GND RGT = GND STB = GND –500 –500 –300 –100 –100 –250 –250 –100 –25 –25 pF pF µA µA µA µA µA pF Symbol Min. Typ. Max. Unit Condition 2. Vertical drivers Item Input pin capacitanceVCK VST VST EN DWN VCK BLK CVck CVst IVst IEn IDwn IVck IBlk –100 –25 pF pF µA Symbol Min. Typ. Max. Unit Condition 3. Total power consumption of the panel Item Total power consumption of the panel (NTSC) Power consumption during power save PWR 30 0.6 50 mW mW Symbol Min. Typ. Max. Unit 4. VCOM input resistance, Video signal input resistance Item VCOM – Vss input resistance Video signal – Vss input resistance Rcom Rsig 0.5 0.5 1.2 1.2 M Ω M Ω Symbol Min. Typ. Max. Unit VST, EN, DWN, VCK, BLK = GND

– 11 – LCX032AK Electro-optical Characteristics (Ta = 25°C, NTSC mode) Item Contrast ratio VDD = 12.0V Vsig = 6.0 ± 4.0V 60°C 25°C 60°C X Y X Y X Y 25°C 60°C 25°C 60°C 25°C 60°C R vs. G B vs. G 0°C 25°C 0°C 25°C 60°C 60 min. CR 4.060 CR 4.025 T Rx Ry Gx Gy Bx By V 90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT60 3.8 0.580 0.300 0.250 0.550 0.105 0.070 1.1 1.0 1.5 1.5 2.2 2.1 200 200 4.8 0.620 0.340 0.290 0.590 0.140 0.110 1.6 1.5 2.0 1.9 2.5 2.4 –0.10 0.10 0.660 0.380 0.330 0.630 0.175 0.150 2.2 2.1 2.5 2.5 3.2 3.1 –0.25 0.45 100 150 –40 CIE standards V V ms dB s Optical transmittance Chromaticity R G B V90 V50 V10 ON time OFF time V-T characteristics Half tone color reproduction range Response time Flicker Image retention time Symbol Measurement method Min Typ. Max. Unit

– 12 – LCX032AK <Electro-optical Characteristics Measurement> Basic m easurem ent conditions (1) D riving voltage VD D = 12.0V VVC = 6.0V, VC O M = 5.7V (2) M easurem ent tem perature 25°C unless otherw ise specified. (3) M easurem ent point O ne point in the center of screen unless otherw ise specified. (4) M easurem ent system s Tw o types of m easurem ent system are used as show n below . (5) R G B input signal voltage (Vsig) Vsig = 6.0 ± VAC [V] (VAC : signal am plitude) ∗ M easurem ent system I LC D panel Lum inance M eter M easurem ent Equipm ent Back light: color tem perature 8500K, +0.004uV (25°C ) ∗ Back light spectrum (reference) is listed on another page. O ptical fiber LC D panel Light receptor lens D rive C ircuit Light Source Back Light 3.5m m ∗ M easurem ent system II M easurem ent Equipm entLight D etector 1. Contrast Ratio Contrast Ratio (CR4.0) is given by the following formula (1). CR 4.0= ...(1) L4.0(White): Surface luminance of the TFT-LCD panel at VDD = 12.0V, VVC = 6.0V, VCOM = 5.7V and the RGB signal amplitude VAC = 0.5V. L4.0(Black): Surface luminance of the panel at VAC = 4.0V. L4.0(White) L4.0(Black)

– 13 – LCX032AK 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). L (White) is the same expression as defined in the "Contrast Ratio" section. 3. Chromaticity Chromaticity of the panels are measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses Chromaticity of x and y on the CIE standards here. Signal amplitudes (VAC ) supplied to each input R input G input B input R aster R G B 0.5 4.0 4.0 4.0 0.5 4.0 4.0 4.0 0.5 (Unit: V) 4. V-T Characteristics V-T characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by System II. V 90, V50 and V10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (Transmittance at V AC = 0.5V is 100%.) 5. Half Tone Color Reproduction Range Half tone color reproduction range of the LCD panels is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System IIdefines signal voltages of each R, G, B raster modes which correspond to 50% of transmittance, V 50R , V50G and V50B respectively. V50RG and V50BG , the voltage differences between V50R and V50G , V50B and V50G , are simply given by the following formulas (3) and (4) respectively. V V50BG = V50B – V50G ...(4) V90 V50 V10 VAC – Signal am plitude [V] Transm ittance [% 100 V50R V50B V50G VAC – Signal am plitude [V] Transm ittance [% V50R G V50BG G raster B rasterR raster L (White) Luminance of Back Light

– 14 – LCX032AK 6. Response Time Response time ton and toff are defined by the formulas (5) and (6) respectively. ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1:time which gives 10% transmittance of the panel. t2:time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. 7. Flicker Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster* mode are measured by a DC voltmeter and a spectrum analyzer in System II. F (dB) = 20log { }...(7) 8. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 6.0 ± VAC (VAC : 3 to 4V), judging by sight at VAC that hold the maximum image retention, measure the time till the residual image becomes indistinct. * Monoscope signal conditions: (shown in the right figure) V COM = 5.7V Input signal voltage (w aveform applied to the m easured pixels) 4.0V 0.5V 6.0V O ptical transm ittance output w aveform 100% 90% 10% tO N t1 ton tO FF t2 toff * R, G, B input signal condition for gray raster mode is given by Vsig = 6.0 ± V50 (V) where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. Black level W hite level Vsig w aveform 6.0V 4.0V 2.0V 4.0V 2.0V AC component DC component

– 15 – LCX032AK Example of Back Light Spectrum (Reference) 0.4 0.3 0.2 0.1 400 500 600 700 W avelength 380 – 780 [nm ]

– 16 – LCX032AK Description of Operation 1. Color Coding Color filters are coded in a delta arrangement. The shaded area is used for the dark border around the display.B R G B R G B R G B R G B R G B R GRBGRBGRBGRBGRBGR B R G B R G B R G B R G B R G B R GRBGRBGRBGRBGRBGR B R G B R G B R G B R G B R G B R GRBGRBGRBGRBGRBGR B R G B R G B R G B R G B R G B R GRBGRBGRBGRBGRBGR B R G B R G B R G B R G B R G B R RBGRBGRBGRBGRBGR G G ate SW G ate SW G ate SW G ate SW 537 3 521 13 218 222 G ate SW G ate SW G reen is not connected for only final stage. Photo-shielding G B G B G B G B G B Active area

– 17 – LCX032AK 2. LCD Panel Operations

• Through current of the level shifter during power supply cutoff can be reduced by STB pin. (power save mode) Power save mode is set at STB = Low level.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the gate lines from the top to bottom of the panel at DWN = High level.
• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by controlling the enable and VCK pin. The enable pin should be High when not in use.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to apply a video signal to the dot. The same procedures lead to the entire 218 · 521 dots to display a picture in a single vertical scanning period.
• Pixeldots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is required to apply video signal to the panel.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle are shown below:

– 18 – LCX032AK Vertical display cycle 218H (13.84m s) 1 2 218217 (1) Vertical display cycle VD VST VC K H orizontal display cycle (47.3µs) 1 2 3 4 5 175 174 (2) H orizontal display cycle (right scan) H D H ST H C K1 H C K2 ∗ H ST is sam pled at first for H C K1. The horizontal display cycle consists of 521/3 = 174 clock pulses because of R G B sim ultaneous sam pling. ∗ R efer to D escription of O peration "3. R G B Sim ultaneous Sam pling." ∗ VST is sam pled at first for VC K.

• This LCD panel provides the following functions.
• Right/left inverse mode
• Up/down inverse mode These modes are controlled by two signals, RGT and DWN. RGT Mode Right scan Left scan H L DWN Mode Down scan Up scan H L

– 19 – LCX032AK 3. RGB Simultaneous Sampling Horizontal driver samples R, G and B signal simultaneously, which requires the phase matching between R, G and B signals to prevent horizontal resolution from deteriorating. Thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the LCD panel. Two methods are applied for the delaying procedure: Sample and hold and Delay circuit. These two block diagrams are as follows. The LCX032AK has the right/left inverse function. The following phase relationship diagram indicates the phase setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be inverted between B and G signals. (1) Sam ple and hold (right scan) <Phase relationship of delaying sam ple-and-hold pulses> (right scan) S/H S/H AC Am p S/H AC Am p S/H AC Am p S/H (2) D elay circuit (right scan) D elay D elay AC Am p D elay AC Am p AC Am p B R G BLU E R ED G R EEN C KB C KR C KG C KG C KG H C Kn C KB C KR C KG BLU E R ED G R EEN B R G LCX032AK LCX032AK

– 20 – LCX032AK Example of Color Filter Spectrum (Reference) 400 500 600 700 W avelength [nm ] Transm ittance [% 100 B G R C olor Filter Spectrum

– 21 – LCX032AK Color Display System Block Diagram An example of single-chip display system is shown below. Y/color difference Y/C LC D panel N TSC /PAL LC X032AK R ED G R EEN BLU E H C K1 H ST VST H C K2 VC K EN STB +12V +3V VC O M C XA3503R +12V D W N R G T BLK C ontrol circuit (m icrocom puter, etc.) Serial control

– 22 – LCX032AK Notes on Handling (1)Static charge prevention Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mat on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2)Protection from dust and dirt a) Operate in clean environment. b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully not to damage the panel. c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stain on the surface. d) Use ionized air to blow off dust at a panel. (3)Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop a panel. c) Do not twist or bend a panel or a panel frame. d) Keep a panel away from heat source. e) Do not dampen a panel with water or other solvents. f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages.

– 23 – LCX032AK Package Outline Unit: mm PIN 1 PIN 16 0.5 ± 0.1 0.5 ± 0.15 3.0 ± 0.3 4.0 ± 0.5 16.0 ± 0.15 (8.97) 2.7 ± 0.15 (6.63) 15.4 ± 0.15 37.1 ± 0.9 1.2 ± 0.3 12.5 ± 0.3 8.5 ± 0.05 4-R1.0 Electrode (enlarged) Active area Thickness of the connector 0.3 ± 0.05 (21.7) Incident light D escription M olding m aterial O utside fram e R einforcing board R einforcing m aterial Polarizing film F P C N o M ass 1g 0.35 + 0.04 – 0.03 8.0 ± 0.25 6.1 ± 0.25 Sony Corporation