LCX026ALG

LCX026ALG SONY | Alldatasheet

Document overview

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Technical content

Features

• Number of active dots: 485,000 (0.9-inch, 2.3cm in diagonal)
• Accepts the computer requirements of SVGA (804 · 604), VGA (644 · 484) and PC98 (644 · 404) platforms
• Supports NTSC (644 · 484) and PAL (762 · 572) by processing the video signal at double speed
• High optical transmittance: 17% (typ.)
• Built-in cross talk free circuit and ghost free circuit
• High contrast ratio with normally white mode: 350 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• High durable polarizer used
• Built-in l/2 retardation film for green light (V) Element Structure
• Built-in peripheral driver using polycrystalline silicon super thin film transistors

Applications

• Liquid crystal data projectors
• Liquid crystal projectors, etc. – 1 – LCX026ALG E98537-PS 2.3cm (0.9-inch) Black-and-White LCD Panel Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 2 – LCX026ALG Block Diagram 1 18 H Shift R egister (Bidirectional Scanning) Up/Down and/or Right/Left Inversion Control Circuit V Shift Register (Bidirectional Scanning) Precharge Control Circuit C O M PAD V Shift Register (Bidirectional Scanning) COM SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 Vss VV DD HV DD M ODE1 ENB DW N PCG VCK VST RGT BLK HCK2 HCK1 HST PSIG 14 15 17 9 20 19 21 22 12 11 10 8 23 16 7 6435 2 24 Black Fram e C ontrol C ircuit Black Fram e Control Circuit Black Fram e Control Circuit M ODE2 M ODE3 Input Signal Level Shifter C ircuit

– 3 – LCX026ALG Absolute Maximum Ratings(VSS = 0V)

• H driver supply voltage HV DD –1.0 to +20 V
• V driver supply voltage VV DD –1.0 to +20 V
• Common pad voltage COM –1.0 to +17 V
• H shift register input pin voltageHST, HCK1, HCK2, –1.0 to +17 V RGT
• V shift register input pin voltageVST, VCK, PCG, –1.0 to +17 V BLK, ENB, DWN MODE1, MODE2, MODE3
• Video signal input pin voltageSIG1, SIG2, SIG3, SIG4, –1.0 to +15 V SIG5, SIG6, PSIG
• Operating temperature Topr –10 to +70 °C
• Storage temperature Tstg –30 to +85 °C Operating Conditions(V SS = 0V)
• Supply voltage HV DD 15.5 ± 0.5V VV DD 15.5 ± 0.5V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 ± 0.5V Pin Description Pin No. PSIG SIG4 SIG3 SIG5 SIG2 SIG6 SIG1 HV DD RGT MODE3 MODE2 MODE1 HST HCK1 HCK2 Vss BLK ENB VCK VST PCG DWN VV DD COM Start pulse for H shift register drive Clock pulse for H shift register drive Clock pulse for H shift register drive GND (H, V drivers) Black Frame display pulse Enable pulse for gate selection Clock pulse for V shift register drive Start pulse for V shift register drive Improvement pulse for uniformity Drive direction pulse for V shift register (H: normal, L: reverse) Power supply for V driver Common voltage of panel Symbol Description Pin No. Symbol Description Uniformity improvement signal Video signal 4 to panel Video signal 3 to panel Video signal 5 to panel Video signal 2 to panel Video signal 6 to panel Video signal 1 to panel Power supply for H driver Drive direction pulse for H shift register (H: normal, L: reverse) Display area switching 3 Display area switching 2 Display area switching 1

– 4 – LCX026ALG Input Equivalent Circuit To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except the video signal inputs. All pins are connected to V SS with a high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.) Input LC Level conversion circuit (single-phase input) 2.5kΩ2.5kΩ VVD D Input Level conversion circuit (single-phase input) 250Ω250Ω H VD D Input Level conversion circuit (single-phase input) 2.5kΩ2.5kΩ H VD D Input H VD D 250Ω 250Ω 250Ω250Ω Level conversion circuit (2-phase input) Input H VD D Signal line (1) SIG 1, SIG 2, SIG 3, SIG 4, SIG 5, SIG 6, PSIG (2) H C K1, H C K2 (3) R G T (4) H ST (5) PC G , VC K (6) VST, BLK, EN B, D W N , M O D E1, M O D E2, M O D E3 (7) C O M 1M Ω Input 1M Ω 1M Ω 1M Ω Level conversion circuit (single-phase input) 250Ω250Ω VVD D Input 1M Ω 1M Ω 1M Ω VVD D 1M Ω

– 5 – LCX026ALG Input Signals 1. Input signal voltage conditions(VSS = 0V) Item H shift register input voltage HST, HCK1, HCK2, RGT (Low) (High) (Low) (High) VHIL VHIH VVIL VVIH VVC Vsig Vcom Vpsig –0.5 4.5 –0.5 4.5 6.8 VVC – 4.5 VVC – 0.5 VVC ± 4.3 0.0 5.0 0.0 5.0 7.0 7.0 VVC – 0.4 VVC ± 4.5 0.4 5.5 0.4 5.5 7.2 VVC + 4.5 VVC – 0.3 VVC ± 4.7 V V V V V V V V V shift register input voltage MODE1, MODE2, MODE3, BLK, VST, VCK, PCG, ENB, DWN Video signal center voltage Video signal input range*1 Common voltage of panel*2 Uniformity improvement signal input voltage (PSIG)*3 Symbol Min. Typ. Max. Unit *1 Input video signal shall be symmetrical to VVC. *2 The typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. 3 Input a uniformity improvement signal PSIG in the same polarity with video signals SIG1 to 6 and which is symmetrical to VVC. Also, the rising and falling of PSIG are synchronized with the rising of PCG pulse, and the rise time trPSIG and fall time tfPSIG are suppressed within 800ns (as shown in a diagram below). The optimum input voltage of PSIG may be changed according as drive conditions of the drive side. Level Conversion Circuit The LCX026ALG has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HV DD or VVDD . The VCC of external ICs are applicable to 5 ± 0.5V. trPSIG tfPSIG VVC PSIG PC G 90% 10% Input waveform of uniformity improvement signal PSIG

– 6 – LCX026ALG 2. Clock timing conditions (Ta = 25°C) (SVGA mode: fHCKn = 4.0MHz, fVCK = 24.0kHz) *4 Hckn means Hck1 and Hck2. *5 Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz). Hst rise time Hst fall time Hst data set-up time Hst data hold time Hckn rise time* Hckn fall time*4 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time Vst fall time Vst data set-up time Vst data hold time Vck rise time Vck fall time Enb rise time Enb fall time Vck rise/fall to Enb rise time Enb pulse width Pcg rise time Pcg fall time Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time Blk fall time Blk fall to Vst rise time Blk pulse width trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb tdEnb twEnb trPcg tfPcg toVck twPcg trBlk tfBlk toVst twBlk –15 –15 400 2400 900 1100 500 2500 1000 1200 100 100 100 100 100 100 600 2600 1100 1300 100 100 ns µs ns Item Symbol Min. Typ. Max. Unit HST HCK VST VCK ENB PCG BLK * µs

– 7 – LCX026ALG *6 Definitions: The right-pointing arrow ( ) means +. The left-pointing arrow ( ) means –. The black dot at an arrow ( ) indicates the start of measurement. <Horizontal Shift Register Driving Waveform> Hst rise time HST HCK Hst fall time Hst data set-up time Hst data hold time Hckn rise time*3 Hckn fall time*3 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time

• Hckn*3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• Hckn* duty cycle 50% to1Hck = 0ns to2Hck = 0ns
• Hckn* duty cycle 50% to1Hck = 0ns to2Hck = 0ns trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck Item Symbol Waveform Conditions 90% 10% 10% 90% H st trH st tfH st 50% 50% H st H ck1 tdH st thH st 50% 50% H ckn 10% 10% 90% 90% trH ckn tfH ckn 50% 50%∗6 H ck1 to2H ck to1H ck 50%50% H ck2

– 8 – LCX026ALG <Vertical Shift Register Driving Waveform> VCK ENB Vck rise time Vck fall time Enb rise time Enb fall time Vck rise/fall to Enb rise time Enb pulse width trVck tfVck trEnb tfEnb tdEnb twEnb Item Symbol Waveform Conditions Vck 10% 10% 90% 90% trVckn tfVckn 90% 90% 10%10% tfEn trEn Enb Enb 50%50% 50% tw Enb tdEnb Vck PCG *7 Pcg rise time trPcg Pcg fall time tfBlk Pcg rise to Vck rise/fall time toVst Pcg pulse width twBlk BLK Blk rise time trPcg Blk fall time tfPcg Blk fall to Vst rise time Blk pulse width toVck twBlk Pcg 50%50% 50% tw Pcg toVck Vck Blk 50% 50% toVst Vst 50% tw Blk *7 Input the pulse obtained by taking the OR of the above pulse (PCG) and BLK to the PCG input pin. Vst rise time VST Vst fall time Vst data set-up time Vst data hold time trVst tfVst tdVst thVst 90% 10% 10% 90% Vst trVst tfVst 50% 50% Vst Vck tdVst thVst 50%50%

– 9 – LCX026ALG Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitanceHCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption CHckn CHst Csig IH HCK1 = GND HCK2 = GND HST = GND RGT = GND HCKn: HCK1, HCK2 (4.0MHz) –500 –1000 –500 –150 –250 –300 –150 –30 130 10.0 200 15.0 pF pF µA µA µA µA pF mA Symbol Min. Typ. Max. Unit Condition 2. Vertical drivers Item Input pin capacitanceVCK VST Input pin current VCK PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 Current consumption CVck CVst IV –1000 –150 –150 –30 3.0 6.0 pF pF µA µA mA Symbol Min. Typ. Max. Unit Condition 3. Total power consumption of the panel Item Total power consumption of the panel PWR — 200 300 mW Symbol Min. Typ. Max. Unit 4. Pin input resistance Item Pin – VSS input resistance Rpin 0.4 1 — M Ω Symbol Min. Typ. Max. Unit VCK = GND PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 = GND VCK: (24.0kHz) 5. Uniformity improvement signal Item Input pin capacitance for uniformity improvement signal CPSIGo 8 nF Symbol Min. Typ. Max. Unit — 12

– 10 – LCX026ALG Reflection Preventive Processing When a retardation film which rotates the polarization axis is used to adjust to the polarization direction of a polarization screen or prism, use a retardation film with reflection preventive processing on the surface. This prevents characteristic deterioration caused by luminous reflection. Electro-optical Characteristics (SVGA mode) Item Contrast ratio 25°C 25°C 25°C 60°C 25°C 60°C 25°C 60°C 0°C 25°C 0°C 25°C 60°C 25°C 25°C CR T RV 90-25 GV 90-25 BV 90-25 RV 90-60 GV 90-60 BV 90-60 RV 50-25 GV 50-25 BV 50-25 RV 50-60 GV 50-60 BV 50-60 RV 10-25 GV 10-25 BV 10-25 RV 10-60 GV 10-60 BV 10-60 ton0 ton25 toff0 toff25 F YT60 CTK 150 1.0 1.1 1.2 1.0 1.0 1.1 1.4 1.5 1.6 1.4 1.4 1.5 1.9 2.0 2.1 1.9 1.9 1.9 350 1.3 1.5 1.6 1.3 1.4 1.5 1.7 1.8 1.9 1.6 1.7 1.8 2.2 2.3 2.4 2.1 2.2 2.3 100 –65 1.7 1.9 2.0 1.6 1.7 1.9 2.0 2.1 2.2 1.9 2.0 2.1 2.5 2.6 2.7 2.4 2.5 2.6 200 –40 V ms dB s Optical transmittance V-T characteristics V V50 ON time OFF time V10 Response time Flicker Image retention time Cross talk Symbol Measurement method Min. Typ. Max. Unit

– 11 – LCX026ALG <Electro-optical Characteristics Measurement>

• M easurem ent system I
• M easurem ent system II Lum inance M eter M easurem ent Equipm ent Light D etector M easurem ent Equipm ent Screen: M ade by Sony (VPS-120FH : G ain 2.8, G lass Beaded Type) or equivalent Projection lens: Focal distance 80m m , F1.9 Light source: 155W m etal H aloid arc lam p (C olor tem perature 7500K ± 500) (× 24, Sensor area: 7m m φ) Polarizer: N itto D enko’s EG -1224D U or Polatechno’s SKN -1824ZT or equivalent O ptical fiber LC D panel Light receptor lens D rive C ircuit Light Source Basic m easurem ent conditions (1) D riving voltage H VD D = 15.5V, VVD D = 15.5V VVC = 7.0V, Vcom = 6.6V (2) M easurem ent tem perature 25°C unless otherw ise specified. (3) M easurem ent point O ne point in the center of the screen unless otherw ise specified. (4) M easurem ent system s Tw o types of m easurem ent system s are used as show n below . (5) Video input signal voltage (Vsig) Vsig = 7.0 ± VAC [V] (VAC = signal am plitude) Screen LC D Projector Approx. 2000m m 1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). L (White)CR = ... (1)L (Black) L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the center of the screen at VAC = 4.5V. Both luminosities are measured by System I.

– 12 – LCX026ALG 2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). White luminanceT = · 100 [%] ... (2)Luminance of light source "White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V on Measurement System I. 3. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panels, are measured by System II by inputting the same signal amplitude V AC to each input pin. V90, V50, and V10 correspond to the voltages which define 90%, 50%, and 10% of transmittance respectively. 4. Response Time Response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 – tON ...(5) toff = t2 – tOFF ...(6) t1:time which gives 10% transmittance of the panel. t2:time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure. V90 V50 V10 VAC – Signal am plitude [V] Transm ittance [% Input signal voltage (W aveform applied to the m easured pixels) 4.5V 0.5V 7.0V O ptical transm ittance output w aveform 100% 90% 10% tO N t1 ton tO FF t2 toff

– 13 – LCX026ALG 5. Flicker Flicker (F) is given by formula (7). DC and AC (SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster* mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20log AC component }...(7)DC component 6. Image Retention Time Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 ± VAC (VAC : 3 to 4V). Judging by sight at the VAC that holds the maximum image retention, measure the time till the residual image becomes indistinct. * Monoscope signal conditions: (shown in the right figure) Vcom = 6.6V 7. Cross Talk Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V). Cross talk value CTK = · 100 [%] * Each input signal voltage for gray raster mode is given by Vsig = 7.0 ± V 50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T characteristics. Black level W hite level Vsig w aveform 7.0V 4.5V 2.0V 4.5V 2.0V W 1 W 1' W 3 W 3' W 2 W 2' W 4' W 4 Wi' – Wi Wi

– 14 – LCX026ALG Viewing angle characteristics(Typical Value) 270 180 Theta Phi 30 70 θ φφ180° X φ270° Y φ0° φ90° Z θ0° M arking M easurem ent m ethod 5010

– 15 – LCX026ALG Optical transmittance of LCD panel(Typical Value) 400 500 600 700 W avelength [nm ] Trans. [% M easurem ent m ethod: M easurem ent system ΙΙ

– 16 – LCX026ALG 1. Dot Arrangement The dots are arranged in a stripe. The shaded area is used for the dark border around the display. 612 dots 4 dots 604 dots (Effective 13.89m m Active areaPhoto-Shielding G ate SW G ate SW G ate SW 6 dots 816 dots 6 dots 4 dots 804 dots (Effective 18.49m m )

– 17 – LCX026ALG 2. LCD Panel Operations [Description of basic operations]

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 604 gate lines sequentially in a single horizontal scanning period. (in SVGA mode)
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 804 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn on to apply a video signal to the dot. The same procedures lead to the entire 604 · 804 dots to display a picture in a single vertical scanning period.
• The data and video signals shall be input with the 1H-inverted system. [Description of operating mode] This LCD panel can change the active area by displaying a black frame to support various computer or video signals. The active area is switched by MODE1, 2 and 3. However, the center of the screen is not changed. The active area setting modes are shown below. MODE1 MODE2 MODE3 Display mode L H H L H L H L SVGA 804 · 604 PAL 762 · 572 VGA/NTSC 644 · 484 PC98 644 · 404 L L L H This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting systems.
• Right/left inverse mode
• Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are shown below. Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin block upside. To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for both the H and V systems nust be varied. The phase relationship between the start pulse and the clock for each mode is shown on the following pages. RGT Mode Right scan Left scan H L DWN Mode Down scan Up scan H L

– 18 – LCX026ALG VST (D W N = H ) VST (D W N = L) (1.2) PA L VD 1 2VC K 3 569 570 571 572 VST (D W N = H ) VST (D W N = L) (1.1) SVG A VD 1 2VC K 3 601 602 603 604 VD 1 2VC K 3 482 483 484 (1.3) VG A /N TSC VD 1 2VC K 3 401 402 403 404 (1.4) PC 98 VST (D W N = H ) VST (D W N = L) VST (D W N = H ) VST (D W N = L) 481 Vertical display cycle 572H Vertical display cycle 604H Vertical display cycle 484H Vertical display cycle 404H (1) Vertical direction display cycle

– 19 – LCX026ALG (2.1.1) SVG A , R G T = H H orizontal display cycle H ST H C K1 1 2 3 4 131 132 133 134 H C K2 H D (2.1.2) SVG A , R G T = L H orizontal display cycle H ST H C K1 H C K2 H D 1 2 3 4 131 132 133 134 1 2 3 4 H orizontal display cycle H ST H C K1 125 126 127 128 (2.2.1) PA L, R G T = H H C K2 H orizontal display cycle H ST H C K1 1 2 3 4 125 126 127 128 (2.2.2) PA L, R G T = L H C K2 H D H D (2) Horizontal direction display cycle

– 20 – LCX026ALG H orizontal display cycle H ST H C K1 105 106 107 108 (2.3.1) VG A /N TSC /PC 98, R G T = H H C K2 H orizontal display cycle H ST H C K1 1 2 3 4 105 106 107 108 (2.3.2) VG A /N TSC /PC 98, R G T = L H C K2 H D H D 1 2 3 4

– 21 – LCX026ALG 3. 6-dot Simultaneous Sampling The horizontal shift register samples signals SIG1 to SIG6 simultaneously. This requires phase matching between signals SIG1 to SIG6 to prevent the horizontal resolution from deteriorating. Thus, phase matching between each signal is required using an external signal delaying circuit before applying the video signal to the LCD panel. The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT = Low level), the phase settings for signals SIG1 to SIG6 are exactly reversed. S/H C K1 C K2 SIG 3 SIG 6 SIG 1 LCX026ALG SIG 3 SIG 6 SIG 1 SIG 2 SIG 2 SIG 4 SIG 4 SIG 5 SIG 5 C K3 C K4 C K5 S/H S/H S/H S/H S/H C K6 S/H S/H S/H S/H S/H H C Kn C K1 C K3 C K5 C K2 C K4 C K6 <Phase relationship of delaying sample-and-hold pulses> (right scan)

– 22 – LCX026ALG Display System Block Diagram An example of display system is shown below. R -IN G -IN B-IN Vsync H sync C LP, PR G M C K1 FR P, S/H C ontrol H ST, H C K, VST, VC K, PC G , EN B Pre D river C XA2111R Tim ing G enerator C XD 2464R PLL C XA3106Q S/H D river C XA2112R S/H D river C XA2112R S/H D river C XA2112R LC X026 R LC X026 G LC X026 B

– 23 – LCX026ALG Notes on Handling (1)Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2)Protection from dust and dirt a) Operate in a clean environment. b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the panel. c) Do not touch the panel surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow dust off the panel. (3)Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages. g) Minimum radius of bending curvature for a flexible substrate must be 1mm. h) Torque required to tighten screws on a panel must be 3kg · cm or less.

– 24 – LCX026ALG Package Outline Unit: mm Active Area The rotation angle of the active area relative to H and V is ± 1°. Incident light w eight 5.3g 2 3 D escription M olding m aterial O utside fram e R einforcing board R einforcing m aterial F P C N o C over 17

8 C over 2

λ/2 retardation film + Polarizing film electrode (enlarged) PIN 24PIN 1 31.0 ± 0.15 (18.5) (13.9) 15.5 ± 0.25 (74.0) 106.0 ± 1.4 27.0 ± 0.1 32.0 ± 0.15 8-R2.0 12.5 ± 0.05 3.7 ± 0.1 Thickness of the connector 0.3 ± 0.05 2.2 ± 0.1 2.5 ± 0.1 15.5 ± 0.25 5-φ2.2 ± 0.05 0.5 ± 0.1 0.5 ± 0.15 4.0 ± 0.4 0.35 ± 0.03