LC87F2J32A

LC87F2J32A SANYO | Alldatasheet

Document overview

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Technical content

Features

„Flash ROM

• Capable of on-board-programming with wide range (2.2 to 5.5V) of voltage source.
• Block-erasable in 128-byte units
• Writable in 2-byte units
• 32768 × 8 bits „RAM
• 1024 × 9 bits „Minimum Bus Cycle
• 83.3ns (12MHz) V DD=2.7 to 5.5V
• 100ns (10MHz) V DD=2.2 to 5.5V
• 250ns (4MHz) V DD=1.8 to 5.5V Note: The bus cycle time here refers to the ROM read speed. CMOS IC FROM 32K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No.A1384-2/30 „Minimum Instruction Cycle Time

• 250ns (12MHz) V DD=2.7 to 5.5V
• 300ns (10MHz) V DD=2.2 to 5.5V
• 750ns (4MHz) V DD=1.8 to 5.5V „Ports
• Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units 39 (P0n, P1n, P2n, P30 to P36, P70 to P73, PWM0, PWM1, XT2, CF2)
• Dedicated oscillator ports/input ports 2 (CF1, XT1)
• Reset pin 1 (RES )
• Power pins 6 (V SS1 to 3, VDD1 to 3) „Timers
• Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes „High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz) 2) Can generate output real-time „SIO
• SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) „UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator

No.A1384-3/30 „AD Converter: 12 bits/8 bits × 14 channels

• 12/8 bits AD converter resolution selectable „PWM: Multifrequency 12-bit PWM × 2 channels „Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) 1) Noise rejection function (Units of noise rejection filter : about 120μs, when selecting a 32.768kHz crystal oscillator as a clock.) 2) Supporting reception formats with a guide-pulse of halt-clock/clock/none. 3) Determines a end of reception by detecting a no-signal periods (No carrier). (Supports same reception format with a different bit length.) 4) X’tal HOLD mode release function „Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock.
• Can generate the source clock for the subclock. „Watchdog timer
• External RC watchdog timer
• Interrupt and reset signals selectable „Interrupts
• 24 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2 /T0L/INT4/REMOREC2 4 0001BH H or L INT3/INT5/ BT0/BT1 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table above). „Subroutine Stack Levels: 512 levels (the stack is allocated in RAM) „High-speed Multiplication/Division Instructions
• 16 bits × 8 bits (5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits (8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time)

No.A1384-4/30 „Oscillation Circuits

• Internal oscillation circuits 1) Low-speed RC oscillation circuit : For system clock(100kHz) 2) Medium-speed RC oscillation circuit : For system clock(1MHz) 3) Frequency variable RC oscillation circuit: For system clock(8MHz) (1) Adjustable in 0.5% (typ) step from a selected center frequency. (2) Measures oscillation clock using a input signal from XT1 as a reference.
• External oscillation circuits 1) Low speed crystal oscillation circuit: For lo w-speed system clock, with internal Rf 2) Hi-speed CF oscillation circuit: For system clock, with internal Rf (1) Both the CF and crystal oscillator circuits stop operation on a system reset. „System Clock Divider Function
• Can run on low current. and 76.8μs (at a main clock rate of 10MHz). „Internal Reset Function
• Power-on reset (POR) function 1) POR reset is generated only at power-on time. 4.35V) through option configuration.
• Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, „Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are three ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0 (5) Having an interrupt source established in the base timer circuit (6) Having an interrupt source established in the infrared remote controller receiver circuit

No.A1384-5/30 „On-chip Debugger

• Supports software debugging with the IC mounted on the target board (LC87D2J32A). LC87F2J32A has an On-chip debugger but its function is limited. „Data Security Function (flash versions only)
• Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. „Package Form
• SQFP48 (7×7): Lead-/Halogen-free type
• QIP48E (14×14): Lead-free type
• FLGA49 (5×5): Lead-free type (This package is Built To Order.) „Development Tools
• On-chip debugger: TCB87- TypeB + LC87D2J32A „Programming Board Package Programming boards SQFP48 (7×7) W87F55256SQ QIP48E (14×14) W87F55256Q „Flash ROM Programmer Maker Model Supported version Device Single programmer AF9708 AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) Rev 03.07 or later LC87F2J32A AF9723/AF9723B(Main body) (Including Ando Electric Co., Ltd. models) - Flash Support Group, Inc. (FSG) Gang programmer AF9833(Unit) (Including Ando Electric Co., Ltd. models) - AF9101/AF9103(Main body) (FSG models) Flash Support Group, Inc. (FSG) Sanyo (Note 1) In-circuit programmer SIB87(Inter Face Driver) (SANYO model) (Note 2) LC87F2J32A Single/Gang programmer SKK/SKK Type B (SANYO FWS) SANYO In-circuit/ Gang programmer SKK-DBG Type B (SANYO FWS) Application Version 1.04 or later Chip Data Version 2.16 or later LC87F2J32A Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from SANYO (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or SANYO for the information.

No.A1384-6/30 Package Dimensions unit : mm (typ) 3163B Package Dimensions unit : mm (typ) 3156A SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536 SANYO : QIP48E(14X14) 14.0 17.2 14.0 17.2 0.150.35 0.8 1.0 (1.5) 1 12 2536 48(2.7) 3.0max 0.1

No.A1384-7/30 Pin Assignment SANYO: SQFP48 (7×7) “Lead- / Halogen-free Type” SANYO: QIP48E (14×14) “Lead-free Type” SQFP/QIP NAME SQFP/QIP NAME SQFP/QIP NAME

1 P73/INT3/T0IN/RMIN 17 PWM1 33 P24/INT5/T1IN

2 RES 18 PWM0 34 P25/INT5/T1IN

3 XT1/AN10 19 V DD2 35 P26/INT5/T1IN

4 XT2/AN11 20 V SS2 36 P27/INT5/T1IN

5 V SS1 21 P00/AN0 37 P36

6 CF1/AN12 22 P01/AN1 38 P35

7 CF2/AN13 23 P02/AN2 39 V DD3

8 V DD1 24 P03/AN3 40 V SS3

9 P10/SO0 25 P04/AN4 41 P34

10 P11/SI0/SB0 26 P05/CKO/AN5 42 P33

11 P12/SCK0 27 P06/T6O/AN6 43 P32/DBGP2

12 P13/SO1 28 P07/T7O/AN7 44 P31/DBGP1

13 P14/SI1/SB1 29 P20/UTX/INT4/T1IN 45 P30/DBGP0

14 P15/SCK1 30 P21/URX/INT4 /T1IN 46 P70/INT0/T0LCP/AN8

15 P16/T1PWML 31 P22/INT4/T1IN 47 P71/INT1/T0HCP/AN9

16 P17/T1PWMH/BUZ

32 P23/INT4/T1IN 48 P72/INT2/T0IN

No.A1384-8/30 System Block Diagram Interrupt control Standby control IR PLA Bus interface Port 0 Port 1 SIO0 SIO1 Timer 0 Timer 1 Timer 4 Timer 5 Port 3 Port 7 ADC ALU Flash ROM PC ACC B register C register PSW RAR RAM Stack pointer Watchdog timer PWM0 UART1 Base timer Timer 6 INT0-2, INT4, 5 INT3 (Noise filter) Timer 7 On-chip debugger PWM1 Port 2 Remote control receiver circuit Clock generator CF/ X'tal RC MRC Reset control Reset circuit (LVD/POR) WDT RES SRC

No.A1384-9/30 Pin Description Pin Name I/O Description Option VSS1 to VSS3 - - power supply pins No VDD1 to VDD3 - + power supply pin No Port 0 P00 to P07 I/O • 8-bit I/O port

• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P07(AN7): AD converter input Yes Port 1 P10 to P17 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Yes Port 2 • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT4 INT5 enable enable enable enable enable enable disable disable disable disable P20 to P27 I/O Yes Port 3 P30 to P36 I/O • 7-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins On-chip debugger pins: DBGP0 to DBGP2 (P30 to P32) Yes Continued on next page.

No.A1384-10/30 Continued from preceding page. Pin Name I/O Description Option Port 7 • 4-bit I/O port

• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input P70(AN8), P71(AN9) : AD converter input Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 INT1 INT2 INT3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable P70 to P73 I/O No PWM0, PWM1 I/O • PWM0 and PWM1 output ports
• General-purpose I/O available No RES I/O External reset Input/internal reset output No XT1 Input • 32.768kHz crystal oscillator input pin
• Shared pins General-purpose input port AD converter input port: AN10 No XT2 I/O • 32.768kHz crystal oscillator output pin
• Shared pins General-purpose I/O port AD converter input port: AN11 No CF1 Input Ceramic resonator input pin
• Shared pins General-purpose input port AD converter input port: AN12 No CF2 Output Ceramic resonator output pin
• Shared pins General-purpose I/O port AD converter input port: AN13 No On-chip Debugger Pin Connection Requirements For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “RD87 On-chip Debugger Installation Manual” Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software P00 to P07 Open Output low P10 to P17 Open Output low P20 to P21 Open Output low P30 to P36 Open Output low P70 to P73 Open Output low PWM0,PWM1 Open Output low XT1 Pulled low with a 100k Ω resistor or less General-purpose input port XT2 Open Output low CF1 Pulled low with a 100k Ω resistor or less General-purpose input port CF2 Open Output low

No.A1384-11/30 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain Programmable (Note 1)

1 CMOS Programmable P10 to P17 1 bit

2 Nch-open drain Programmable

1 CMOS Programmable P20 to P27 1 bit

1 CMOS Programmable P30 to P36 1 bit

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No XT1 - No Input for 32.768kHz crystal oscillator (Input only) No XT2 - No Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No CF1 - No Input for ceramic resonator oscillator (Input only) No CF2 - No Output for ceramic resonator oscillator (Nch-open drain when in general-purpose output mode) No Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low- and high-impedance pull-up connection is exercised in 1-bit units.

No.A1384-12/30 User Option Table Option name Option to be applied on Flash-ROM versio n Option selected in units of Option selection CMOS P00 to P07 { 1 bit Nch-open drain CMOS P10 to P17 { 1 bit Nch-open drain CMOS P20 to P27 { 1 bit Nch-open drain CMOS Port output type P30 to P36 { 1 bit Nch-open drain 00000h Program start address - { - 07E00h Enable: Use Detect function { - Disable: Not Used Low-voltage detection reset function Detect level { - 7-level Power-on reset function Power-On reset level { - 8-level Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1: During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Example 2: During backup in hold mode, output is not held high and its value in unsettled. LSI VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power Supply Back-up capacitor VSS1V SS2V SS3 VDD1 VDD2 VDD3 Power Supply Back-up capacitor LSI

No.A1384-13/30 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1=VDD2=VDD3 -0.3 +6.5 Input voltage V I XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO Ports 0, 1, 2, 3, Port 7, PWM0, PWM1, XT2, CF2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 -20 Peak output current IOPH(3) P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 -15 Mean output current (Note 1-1) IOMH(3) P71 to P73 Per 1 applicable pin -3 ΣIOAH(1) P71 to P73 Total of all applicable pins -10 ΣIOAH(2) Port 0 Total of all applicable pins -25 ΣIOAH(3) Port 1, PWM0, PWM1 Total of all applicable pins -25 ΣIOAH(4) Ports 0, 1, PWM0, PWM1 Total of all applicable pins -45 ΣIOAH(5) Ports 2, P35, P36 Total of all applicable pins -25 ΣIOAH(6) P30 to P34 Total of all applicable pins -25 High level output current Total output current ΣIOAH(7) Pots 2, 3 Total of all applicable pins -45 IOPL(1) P02 to P07, Ports 1, 2, 3, PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Port 7, XT2, CF2 Per 1 applicable pin 10 IOML(1) P02 to P07, Ports 1, 2, 3, PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 Mean output current (Note 1-1) IOML(3) Port 7, XT2, CF2 Per 1 applicable pin 7.5 ΣIOAL(1) Port 7, XT2, CF2 Total of all applicable pins 15 ΣIOAL(2) Port 0 Total of all applicable pins 45 ΣIOAL(3) Port 1, PWM0, PWM1 Total of all applicable pins 45 ΣIOAL(4) Port 0, 1, PWM0, PWM1 Total of all applicable pins 80 ΣIOAL(5) Ports 2, P35, P36 Total of all applicable pins 45 ΣIOAL(6) P30 to P34 Total of all applicable pins 45 Low level output current Total output current ΣIOAL(7) Ports 2, 3 Total of all applicable pins 60 mA Pd max(1) Ta=-40 to +85 °C Package only 139 Pd max(2) SQFP48 (7×7) Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) 356 Pd max(3) Ta=-40 to +85 °C Package only 281 Power dissipation Pd max(4) QIP48E (14×14) Ta=-40 to +85°C Package with thermal resistance board (Note 1-2) 489 mW Operating ambient temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.

No.A1384-14/30 Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit VDD(1) 0.245 μs≤tCYC≤200μs 2.7 5.5 VDD(2) 0.294 μs≤tCYC≤200μs 2.2 5.5 Operating supply voltage (Note 2-1) VDD(3) VDD1=VDD2=VDD3 0.735μs≤tCYC≤200μs 1.8 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 1.6 5.5 VIH(1) Ports 1, 2, 3, P71 to P73 P70 port input/ interrupt side PWM0, PWM1 1.8 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 0 1.8 to 5.5 0.3VDD +0.7 V DD VIH(3) Port 70 watchdog timer side 1.8 to 5.5 0.9V DD V DD High level input voltage VIH(4) XT1, XT2, CF1, CF2, RES 1.8 to 5.5 0.75VDD V DD 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(1) Ports 1, 2, 3, P71 to P73 P70 port input/ interrupt side PWM0, PWM1 1.8 to 4.0 V SS 0.2V DD 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(2) Port 0 1.8 to 4.0 V SS 0.2V DD VIL(3) Port 70 watchdog timer side 1.8 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(4) XT1, XT2, CF1, CF2, RES 1.8 to 5.5 V SS 0.25VDD V 2.7 to 5.5 0.245 200 2.2 to 5.5 0.294 200 Instruction cycle time (Note 2-1) tCYC (Note 2-2) 1.8 to 5.5 0.735 200 μs 2.7 to 5.5 0.1 12• CF2 pin open

• System clock frequency division ratio=1/1
• External system clock duty= 50±5% 1.8 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 External system clock frequency FEXCF CF1
• CF2 pin open
• System clock frequency division ratio=1/2
• External system clock duty= 50±5% 2.0 to 5.5 0.2 8 MHzFmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 12 FmCF(2) CF1, CF2 10MHz ceramic oscillation See Fig. 1. 2.2 to 5.5 10 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. See Fig. 1. CFLAMP=0) 1.8 to 5.5 4 Oscillation frequency range (Note 2-3) FmCF(3) CF1, CF2 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) See Fig. 1. 2.2 to 5.5 4 MHz Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page.

No.A1384-15/30 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit FmMRC(1) Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) (Note 2-4) FmMRC(2) Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) Ta=-10 to +50°C (Note 2-4) FmRC Internal Medium-speed RC MHz FmSRC Internal Low-speed RC oscillation 1.8 to 5.5 50 100 200 Oscillation frequency range (Note 2-3) FsX’tal XT1, XT2 32.768kHz crystal oscillation kHz Frequency variable RC oscillation usable range OpVMRC Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) 2.4 to 5.5 6 8 10 MHz VmADJ(1) Each step of VMRCHBn 2.4 to 5.5 3.6 7.0 11 Frequency variable RC oscillation adjustment range Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.

No.A1384-16/30 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3 Ports 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 1.8 to 5.5 1 IIH(2) XT1, XT2, CF2 Input port selected VIN=VDD 1.8 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 1.8 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 1.8 to 5.5 -1 IIL(2) XT1, XT2, CF2 Input port selected VIN=VSS 1.8 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 1.8 to 5.5 -15 μA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.35mA 2.7 to 5.5 VDD -0.4 VOH(3) Ports 0, 1, 2, 3, P71 to P73 IOH=-0.15mA 1.8 to 5.5 VDD -0.4 VOH(4) I OH=-6mA 4.5 to 5.5 V DD-1 VOH(5) I OH=-1.4mA 2.7 to 5.5 VDD -0.4 High level output voltage VOH(6) PWM0, PWM1, P05(System clock output function used) IOH=-0.8mA 1.8 to 5.5 VDD -0.4 VOL(1) I OL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.4mA 2.7 to 5.5 0.4 VOL(3) Ports 0, 1, 2, 3, PWM0, PWM1, IOL=0.8mA 1.8 to 5.5 0.4 VOL(4) I OL=25mA 4.5 to 5.5 1.5 VOL(5) I OL=4mA 2.7 to 5.5 0.4 VOL(6) P00, P01 IOL=2mA 1.8 to 5.5 0.4 VOL(7) I OL=1.4mA 2.7 to 5.5 0.4 Low level output voltage VOL(8) Port 7, XT2, CF2 IOL=0.8mA 1.8 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80 Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD When Port 0 selected low-impedance pull-up. 1.8 to 4.5 18 50 230 Pull-up resistance Rpu(3) Port 0 V OH=0.9VDD When Port 0 selected High-impedance pull-up. 1.8 to 5.5 100 210 400 kΩ VHYS(1) 2.7 to 5.5 0.1 VDD Hysteresis voltage VHYS(2) Ports 1, 2, 3, 7, RES, XT2 1.8 to 2.7 0.07 VDD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS, f=1MHz, Ta=25°C 1.8 to 5.5 10 pF

No.A1384-17/30 Serial Input/Output Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 Input clock High level pulse width tSCKH(1) SCK0(P12) • See Fig. 6. 1.8 to 5.5 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) Serial clock Output clock High level pulse width tSCKH(2) SCK0(P12) • CMOS output selected

• See Fig. 6 1.8 to 5.5 tSCK Data setup time tsDI(1) 0.05 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig. 6. 1.8 to 5.5 0.05 tdD0(1) • Continuous data transmission/reception mode (Note 4-1-2) (1/3)tCYC +0.08 Input clock tdD0(2) • Synchronous 8-bit mode (Note 4-1-2) 1tCYC +0.08 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-2) 1.8 to 5.5 (1/3)tCYC +0.08 μs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) 2 Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) • See Fig. 6. 1.8 to 5.5 Frequency tSCK(4) 2 tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected
• See Fig. 6. 1.8 to 5.5 tSCK Data setup time tsDI(2) 0.05 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig. 6. 1.8 to 5.5 0.05 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
• Must be specified with respect to falling edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig. 6. 1.8 to 5.5 (1/3)tCYC +0.08 μs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A1384-18/30 Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23) INT5(P24 to P27)

• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are enabled. 1.8 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.8 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.8 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.8 to 5.5 256 tCYC High/low level pulse width tPIL(5) RES • Resetting is enabled. 1.8 to 5.5 200 μs AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V <12bits AD Converter Mode at Ta = -40 to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 2.4 to 5.5 12 bit (Note 6-1) 3.0 to 5.5 ±16Absolute accuracy ET (Note 6-1) 2.4 to 3.6 ±20 LSB 4.0 to 5.5 32 115• See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 64 115 Conversion time TCAD
• See Conversion time calculation formulas. (Note 6-2) 2.4 to 3.6 410 425 μs Analog input voltage range VAIN AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) AN12(CF1) AN13(CF2) 2.4 to 5.5 V SS V DD V IAINH(1) VAIN=V DD 2.4 to 5.5 1 IAINL(1) analog channel except AN12 VAIN=VSS 2.4 to 5.5 -1 IAINH(2) VAIN=V DD 2.4 to 5.5 15 Analog port input current IAINL(2) AN12 VAIN=VSS 2.4 to 5.5 -15 μA Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.A1384-19/30 <8bits AD Converter Mode at Ta = -40 to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 2.4 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 2.4 to 5.5 ±1.5 LSB 4.0 to 5.5 20 90• See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 40 90 Conversion time TCAD

• See Conversion time calculation formulas. (Note 6-2) 2.4 to 3.6 250 265 μs Analog input voltage range VAIN AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) AN12(CF1) AN13(CF2) 2.4 to 5.5 V SS V DD V IAINH(1) VAIN=V DD 2.4 to 5.5 1 IAINL(1) analog channel except AN12 VAIN=VSS 2.4 to 5.5 -1 IAINH(2) VAIN=V DD 2.4 to 5.5 15 Analog port input current IAINL(2) AN12 VAIN=VSS 2.4 to 5.5 -15 μA Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio))+2)×(1/3)×tCYC AD conversion time (TCAD) External oscillation (FmCF) Operating supply voltage range (VDD) System division ratio (SYSDIV) Cycle time (tCYC) AD division ratio (ADDIV) 12bit AD 8bit AD 4.0V to 5.5V 1/1 250ns 1/8 34.8 μs 21.5 μs CF-12MHz 3.0V to 5.5V 1/1 250ns 1/16 69.5 μs 42.8 μs 4.0V to 5.5V 1/1 300ns 1/8 41.8 μs 25.8 μs CF-10MHz 3.0V to 5.5V 1/1 300ns 1/16 83.4 μs 51.4 μs 3.0V to 5.5V 1/1 750ns 1/8 104.5 μs 64.5 μs CF-4MHz 2.4V to 3.6V 1/1 750ns 1/32 416.5 μs 256.5 μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. Power-on reset (POR) Characteristics at Ta = -40 to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min typ max unit 1.67V 1.55 1.67 1.79 1.97V 1.85 1.97 2.09 2.07V 1.95 2.07 2.19 2.37V 2.25 2.37 2.49 2.57V 2.45 2.57 2.69 2.87V 2.75 2.87 2.99 3.86V 3.73 3.86 3.99 POR release voltage PORRL • Select from option. (Note 7-1) 4.35V 4.21 4.35 4.49 Detection voltage unknown state POUKS • See Fig. 8. V Power supply rise time PORIS • Power supply rise time from 0V to 1.6V. 100 ms Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation.

No.A1384-20/30 Low voltage detection reset (LVD) Characteristics at Ta = -40 to +85°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min typ max unit 1.91V 1.81 1.91 2.01 2.01V 1.91 2.01 2.11 2.31V 2.21 2.31 2.41 2.51V 2.41 2.51 2.61 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 LVD reset Voltage (Note 8-2) LVDET 4.28V 4.18 4.28 4.38 V 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 60 3.79V 65 LVD hysteresis width LVHYS

• Select from option. (Note 8-1) (Note 8-3)
• See Fig. 9. 4.28V 65 mV Detection voltage unknown state LVUKS • See Fig. 9. (Note 8-4) 0.7 0.95 V Low voltage detection minimum width (Reply sensitivity) TLVDW • LVDET-0.5V
• See Fig. 10. 0.2 ms Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation.

No.A1384-21/30 Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 2.7 to 5.5 6.6 11.3 IDDOP(1) • FmCF=12MHz ceramic oscillation mode

• System clock set to 12MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 2.7 to 3.6 4.0 7.3 3.0 to 5.5 8.0 12.7 IDDOP(2) • CF1=24MHz external clock
• System clock set to CF1 side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 3.0 to 3.6 4.6 7.6 2.2 to 5.5 5.9 10.5 IDDOP(3) • FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 2.2 to 3.6 3.6 6.7 1.8 to 5.5 2.6 6.1 IDDOP(4) • FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 1.8 to 3.6 1.9 3.9 2.2 to 5.5 0.9 2.2 IDDOP(5) • CF oscillation low amplifier size selected. (CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio 2.2 to 3.6 0.5 1.1 1.8 to 5.5 0.5 1.5 IDDOP(6) • FsX’tal=32.768kHz Crystal oscillation mode
• Internal Low speed RC oscillation stopped.
• System clock set to internal Medium speed RC oscillation.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 1.8 to 3.6 0.3 0.8 2.7 to 5.5 5.6 10.8 IDDOP(7) • FsX’tal=32.768kHz crystal oscillation mode
• Internal Low speed and Medium speed RC oscillation stopped.
• System clock set to 8MHz with Frequency variable RC oscillation
• 1/1 frequency division ratio 2.7 to 3.6 3.8 6.6 mA 1.8 to 5.5 70 173 IDDOP(8) • External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC oscillation.
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 1.8 to 3.6 47 106 5.0 70 145 3.3 47 86 Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(9) VDD1 =VDD2 =VDD3
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC oscillation.
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C 2.5 35 65 μA Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified Continued on next page.

No.A1384-22/30 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 1.8 to 5.5 27 120 IDDOP(10) • FsX’tal=32.768kHz crystal oscillation mode

• System clock set to 32.768kHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 1.8 to 3.6 13 59 5.0 27 84 3.3 13 33 Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(11) VDD1
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C 2.5 8.1 22 μA 2.7 to 5.5 2.6 4.7 IDDHALT(1) • HALT mode
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 2.7 to 3.6 1.4 2.5 3.0 to 5.5 4.0 6.9 IDDHALT(2) • HALT mode
• CF1=24MHz external clock
• System clock set to CF1 side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 3.0 to 3.6 2.0 3.4 2.2 to 5.5 2.2 4.4 IDDHALT(3) • HALT mode
• FmCF=10MHz ceramic oscillation mode
• System clock set to 10MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 2.2 to 3.6 1.2 2.3 1.8 to 5.5 1.2 3.0 IDDHALT(4) • HALT mode
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 1.8 to 3.6 0.6 1.4 2.2 to 5.5 0.6 1.5 IDDHALT(5) • HALT mode
• CF oscillation low amplifier size selected. (CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• System clock set to 4 MHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio 2.2 to 3.6 0.3 0.7 1.8 to 5.5 0.3 0.9 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(6) VDD1
• HALT mode
• FsX’tal=32.768 kHz crystal oscillation mode
• Internal Low speed RC oscillation stopped.
• System clock set to internal Medium speed RC oscillation
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 1.8 to 3.6 0.2 0.5 mA Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified Continued on next page.

No.A1384-23/30 Continued from preceding page Specification Parameter Symbol Pin/ remarks Conditions VDD[V] min. typ. max. unit 2.7 to 5.5 2.5 5.0 IDDHALT(7) • HALT mode

• FsX’tal=32.768kHz crystal oscillation mode
• Internal Low speed and Medium speed RC oscillation stopped.
• System clock set to 8MHz with Frequency variable RC oscillation
• 1/1 frequency division ratio 2.7 to 3.6 1.4 2.6 1.8 to 5.5 26 91 IDDHALT(8) • HALT mode
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC oscillation.
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio 1.8 to 3.6 15 48 5.0 26 52 3.3 15 26 IDDHALT(9) • HALT mode
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC oscillation.
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
• Ta=-10 to +50°C 2.5 10 18 1.8 to 5.5 16 96 IDDHALT(10) • HALT mode
• FsX’tal=32.768 kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio 1.8 to 3.6 6.2 43 5.0 16 56 3.3 6.2 18 HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(11) VDD1
• HALT mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal Low speed and Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
• Ta=-10 to +50°C 2.5 3.4 11 μA 1.8 to 5.5 0.04 30IDDHOLD(1) HOLD mode
• CF1=VDD or open (External clock mode) 1.8 to 3.6 0.02 14 5.0 0.04 2.8 3.3 0.02 1.2 IDDHOLD(2) HOLD mode
• CF1=VDD or open (External clock mode) 1.8 to 5.5 2.9 35 IDDHOLD(3) HOLD mode
• CF1=VDD or open (External clock mode)
• LVD option selected 1.8 to 3.6 2.2 18 5.0 2.9 7.2 3.3 2.2 4.1 HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(4) VDD1 HOLD mode
• CF1=VDD or open (External clock mode)
• Ta=-10 to +50°C
• LVD option selected 2.5 1.9 3.4 1.8 to 5.5 14 89IDDHOLD(5) Timer HOLD mode
• FsX’tal=32.768kHz crystal oscillation mode 1.8 to 3.6 4.8 38 5.0 14 40 3.3 4.8 15 Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) VDD1 Timer HOLD mode
• FsX’tal=32.768kHz crystal oscillation mode μA Note 9-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified

No.A1384-24/30 F-ROM Programming Characteristics at Ta = -10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Only current of the Flash block. 2.2 to 5.5 5 10 mA tFW(1) • Erasing time 20 30 ms Programming time tFW(2)

• Programming time 2.2 to 5.5 40 60 μs UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Transfer rate UBR UTX(P20), URX(P21) 1.8 to 5.5 16/3 8192/3 tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Transmit data (LSB first) Start of transmission End of transmission UBR Start bit Stop bit Stop bit End of reception UBR Receive data (LSB first) Start of reception Start bit

No.A1384-25/30 Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator

• CF oscillation normal amplifier size selected (CFLAMP=0) Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Oscillator Name [pF] [pF] Rf1 [Ω] Rd1 [Ω] Operating Voltage Range [V] typ [ms] max [ms] Remarks 12MHz CSTCE12M0G52-R0 (10) ( 10) Open 680 2.7 to 5.5 0.1 0.5 CSTCE10M0G52-R0 (10) (10) Open 680 2.2 to 5.5 0.1 0.5 10MHz CSTLS10M0G53-B0 (15) (15) Open 680 2.2 to 5.5 0.1 0.5 8MHz 6MHz 4MHz MURATA Internal C1,C2
• CF oscillation low amplifier size selected (CFLAMP=1) Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Oscillator Name [pF] [pF] Rf1 [Ω] Rd1 [Ω] Operating Voltage Range [V] typ [ms] max [ms] Remarks 4MHz MURATA Internal C1,C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4).

No.A1384-27/30 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 4 Oscillation Stabilization Times Operating VDD lower limit Power supply RES Internal Medium speed RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD Internal Medium speed RC oscillation or Low speed RC oscillation CF1, CF2 XT1, XT2 State HOLD reset signal HOLD reset signal valid tmsCF tmsX’tal HOLD HALT HOLD reset signal absent

No.A1384-30/30 Figure 10 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) PS This catalog provides information as of April, 2009. Specifications and info rmation herein are subject to change without notice. SANYO Semiconductor Co.,Ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. Information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. When designing equip ment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. VDD LVD reset voltage tLVDW VSS LVD release voltage LVDET-0.5V