LC87F2C64A

LC87F2C64A SANYO | Alldatasheet

Document overview

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Technical content

Features

„Flash ROM

• On-board-programmable with wide range (3.0 to 5.5V) of voltage source
• Block-erasable in 128 byte units
• Writable in 2-byte units
• 65536 × 8 bits „RAM
• 2048 × 9 bits „Minimum Bus Cycle
• 83.3ns (12MHz at VDD=3.0V to 5.5V)
• 250ns (4MHz at VDD=2.4V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. CMOS IC 64K-byte FROM and 2048-byte RAM integrated 8-bit 1-chip Microcontroller * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd.

No.A1935-2/28 „Minimum Instruction Cycle Time

• 250ns (12MHz at VDD=3.0 to 5.5V)
• 750ns (4MHz at VDD=2.4 to 5.5V) „Temperature Range
• -30 to +70 degree Celsius „Ports
• Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units 71 (P0n, P1n, P2n, P30 to P34, P70 to P73, P8n, PAn, PBn, PCn, Pen, XT2, CF2)
• Normal withstand voltage input port (Oscillator) 2 (XT1, CF1)
• Reset pin 1 (RES
• Power pins 6 (V SS1 to VSS3, VDD1 to VDD3) „Timers
• Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with a 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer 1) The clock is selectable from the sub-clock (32.768kHz crystal oscillation/slow RC oscillation), system clock, and prescaler output from timer 0. 2) Interrupts are programmable in 5 different time schemes.
• Real time clock (RTC) 1) Used with a base timer, it can be used as a century + year + month + day + hour + minute + second counter. 2) Calendar counts up to December 31, 2799 with automatic leap-year calculation. „High-speed Clock Counter
• Count clocks with a maximum clock rate of 24MHz (when main clock is 12MHz)
• Real-time output

No.A1935-3/28 „SIO

• SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baud rate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) 4) HOLD/X’tal HOLD mode release function by receiving 1-byte (8-bit clock)
• SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baud rates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 TCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) „UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator „Remote Control Receiver Circuit
• Noise rejection function on P73/INT3/T0IN pin (noise rejection filter’s time constant can be selected from 1, 32 or 128 tCYC.) „AD Converter: 12 bits × 16 channels
• 12 bits/8 bits AD converter resolution selectable „PWM: 4 channels
• Multi frequency 12-bit PWM „Clock Output Function
• Output clock with a frequency 1/1, 1/2, 1/4, 1/8, 1/16, 1/32 or 1/64 of the source clock of the system clock.
• Output clock of the sub-clock. „Buzzer Output
• 2kHz or 4kHz buzzer output can be generated using base timer. „Watchdog Timer
• Watchdog timer can generate interrupt or system reset.
• Two types of watchdog timers are available: (1) External RC watchdog timer (2) Base timer watchdog timer
• Watchdog timer with base timer can select only one period (1, 2, 4 or 8s) by the user option. Once set the watchdog timer period and start the watchdog timer, the period is not changeable.

No.A1935-4/28 „Interrupts

• 28 sources, 10 vector addresses (1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. (2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/INT4/T0L 4 0001BH H or L INT3/INT5/Base timer0/ Base timer1/RTC 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive/UART2 receive 8 0003BH H or L SIO1/UART1 transmit/UART2 transmit 9 00043H H or L ADC/T6/T7/PWM4, 5/SPI 10 0004BH H or L Port0/T4/T5/PWM0, 1
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function) (1) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the table above). „Subroutine Stack Levels
• 1024 levels (Stack is allocated in RAM) „High-speed Multiplication/Division Instructions
• 16 bits×8 bits (5 tCYC execution time)
• 24 bits×16 bits (12 tCYC execution time)
• 16 bits÷8 bits (8 tCYC execution time)
• 24 bits÷16 bits (12 tCYC execution time) „Oscillation Circuits
• On-chip fast RC oscillation circuit : For system clock
• On-chip slow RC oscillation circuit : For system clock
• CF oscillation circuit : For system clock, with built in Rf
• Crystal oscillation circuit : For low-speed system clock
• On-chip Frequency variable RC oscillation circuit : For system clock (1) Adjustable by ±4% (typical) step from selected center frequency (2) Frequency measurable by referencing input signal from XT1 „System Clock Divider Function
• Enables low power consumption operation (at a main clock rate of 12MHz). „Internal Reset Function
• Power-on reset (POR) function (1) POR reset is generated only at power-on. (2) The POR release level can be selected through option configuration.
• Low-voltage detection reset (LVD) function (1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. (2) The use/no-use of the LVD function and the low voltage threshold level can be selected through option configuration.

No.A1935-5/28 „Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (1) Oscillation is not halted automatically. (2) There are three ways of resetting the HALT mode. 1) Setting the reset pin to the lower level 2) System resetting by watchdog timer 3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. (1) The CF, RC, crystal, and frequency variable RC oscillators automatically stop operation. (2) There are five ways of resetting the HOLD mode. 1) Setting the reset pin to the lower level 2) System resetting by watchdog timer 3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level 4) Having an interrupt source established at port 0 5) Having an interrupt source established in SPI receiving 1-byte (8-bit clock)
• X’'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. (1) The CF, RC, and frequency variable RC oscillators automatically stop operation. (2) The state of crystal oscillation established when the X’tal HOLD mode is entered is retained. (3) Power-save mode is available for even lower current consumption. (4) There are seven ways of resetting the X’tal HOLD mode. 1) Setting the reset pin to the low level 2) System resetting by watchdog timer 3) Setting at least one of the INT0, INT1, INT2, INT3, INT4, INT5 pins to the specified level 4) Having an interrupt source established at port0 5) Having an interrupt source established in the base timer circuit 6) Having an interrupt source established in the RTC 7) Having an interrupt source established in SPI receiving 1-byte (8-bit clock) „On-chip Debugging Function (flash ROM version)
• Supports software debugging with the test device installed on the target board. „Data Security Function (flash ROM version)
• Protects the program data stored in flash memory from unauthorized read or copy. Note: The data security function does not necessarily provide an absolute data security. „Shipping form
• QFP80 (14×14): Lead-free type
• TQFP80J (12×12): Lead-free type „Development Tools
• On-chip-debugger: TCB87 TypeB + LC87F2C64A

No.A1935-6/28 Package Dimensions unit : mm (typ) 3255 Package Dimensions unit : mm (typ) 3290 SANYO : QFP80(14X14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.250.65 (0.83)(2.7) 0.8 1 20 4160 12 0 4160 (1.25) 0.20.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0)0.1 1.2max SANYO : TQFP80J(12X12)

No.A1935-7/28 Pin Assignment SANYO: QFP80 (14×14) “Lead-free type” SANYO: TQFP80J (12×12) “Lead-free type” P02/UTX2 P01/URX1 P00/UTX1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P21/INT4/T1IN/T0LCP/T0HCP P20/INT4/T1IN/T0LCP/T0HCP PE3 P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN/NKIN P73/INT3/T0IN RES XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 PB0/AN8 VSS2 VDD2 PE2 PE1 PE0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7/AN15 PB6/AN14 PB5/AN13 PB4/AN12 PB3/AN11 PB2/AN10 PB1/AN9 P03/URX2 P04 P05/CKO P06/T6O P07/T7O VSS3 VDD3 PA0/PWM0 PA1/PWM0 PA2/PWM0 PA3/PWM0 PA4/PWM1 PA5/PWM1 PA6/PWM1 PA7/PWM1 P30/PWM4 P31/PWM5 P32/DBGP0 P33/DBGP1 P34/DBGP2 LC87F2C64A Top view

No.A1935-8/28 System Block Diagram RES Interrupt Control Stand-by Control Flash ROM IR PLA RC × 2 VMRC X’tal CF Clock Generator Reset Control WDT Reset Circuit (POR/LVD) PC ACC B Register PSW ALU RAR RAM Stack Pointer Watchdog Timer On-Chip-Debugger SIO0 SIO1 C Register Bus Interface Port 0 UART1 UART2 Timer 0 (High-speed clock counter) Timer 1 Timer 4 Timer 5 Timer 6 Timer 7 Base Timer RTC PWM0/1 Port 1 Port 2 Port 3 Port 7 Port 8 ADC Port A Port B Port C PWM4/5 INT0 to 5 Noise rejection filter Port E

No.A1935-9/28 Pin Description Pin Name I/O Description Option VSS1 to VSS3 - - Power supply pin No VDD1 to VDD3 - + Power supply pin No V1 - Open No VDC - Open No CUP1, CUP2 - Open No PORT 0 P00 to P07 I/O • 8-bit I/O port

• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• HOLD release input
• Port 0 interrupt input Other functions: P00: UART1 transmit P01: UART1 receive P02: UART2 transmit P03: UART2 receive P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output Yes PORT 1 P10 to P17 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Yes PORT 2 P20 to P27 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: P20 to P23: INT4 input/HOLD release input/timer 1 event input /timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD release input/timer 1 event input /timer 0L capture input/timer 0H capture input
• Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT4 INT5 Yes Yes Yes Yes Yes Yes No No No No Yes PORT 3 P30 to P34 I/O • 5-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: P30: PWM4 output P31: PWM5 output P32 (DBGP0) to P34 (DBGP2): On-chip-debugger port (Only on Flash version) Yes Continued on next page.

No.A1935-10/28 Continued from preceding page. Pin Name I/O Description Option PORT 7 P70 to P73 I/O • 4-bit I/O port

• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: P70: INT0 input/HOLD release input/timer 0L capture input /watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input /timer 0L capture input/high speed clock counter input P73: INT3 input (with noise filter)/ HOLD release input /timer 0 event input/timer 0H capture input
• Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 INT1 INT2 INT3 Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes No No No PORT 8 P80 to P87 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units Other functions: P80 to P87(AN0 to AN7): AD converter input No PORT A PA0 to PA7 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: PA0 to PA3: PWM0 output PA4 to PA7: PWM1 output Yes PORT B PB0 to PB7 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Other functions: PB0 to PB7 (AN8 to AN15): AD converter input Yes PORT C PC0 to PC7 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Yes PORT E PE0 to PE3 I/O • 4-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units. Yes RES I/O External reset input pin/Internal reset output pin No XT1 I • Input for 32.768kHz crystal oscillation Other functions:
• General purpose input port *Connect to VDD1 when the port is not used. No XT2 I/O • Output for 32.768kHz crystal oscillation Other functions:
• General-purpose I/O port *Must be set for oscillation mode and kept open if not to be used. No CF1 I • Input for ceramic resonator Other functions:
• General purpose input port *Connect to VDD1 when the port is not used. No CF2 I/O • Output for ceramic resonator Other functions:
• General-purpose I/O port *Must be set for oscillation mode and kept open if not to be used. No

No.A1935-11/28 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up/down resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected iIn Units of Option Type Output Type Pull-Up Resistor

1 CMOS Programmable P00 to P07

2 Nch-open drain Programmable

1 CMOS Programmable P10 to P17

1 CMOS Programmable P20 to P27

1 CMOS Programmable P30 to P34

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable P80 to P87 - No Nch-open drain No

1 CMOS Programmable PA0 to PA7

1 CMOS Programmable PB0 to PC7

1 CMOS Programmable PC0 to PC7

1 CMOS Programmable PE0 to PE3

XT2 - No 32.768kHz crystal oscillator output or Nch-open drain when selected as normal port No CF2 - No Ceramic resonator output or Nch-open drain when selected as normal port No

No.A1935-12/28 User Option Table Option Name Option to be Applied on Mask-ROM Version*1 Flash-ROM Version Option Selected in Units of Option Selection CMOS P00 to P07 Yes Yes 1 bit Nch-open drain CMOS P10 to P17 Yes Yes 1 bit Nch-open drain CMOS P20 to P27 Yes Yes 1 bit Nch-open drain CMOS P30 to P34 Yes Yes 1 bit Nch-open drain CMOS PA0 to PA7 Yes Yes 1 bit Nch-open drain CMOS PB0 to PB7 Yes Yes 1 bit Nch-open drain CMOS PC0 to PC7 Yes Yes 1 bit Nch-open drain CMOS Port output type PE0 to PE3 Yes Yes 1 bit Nch-open drain 0000H Program start address No*2 Yes - FE00H Base timer Watchdog timer Watchdog timer period Yes Yes - Detection level (Enable) - Yes - Low-Voltage detect function Power-on reset level (Disable) - Yes - *1: The option selection cannot to be changed after the mask is created. *2: Program start address for the mask-ROM version is 0000H.

No.A1935-13/28 *Note1: Connect the IC as shown below to minimize the noise input to the VDD1. Be sure to electrically short the VSS1, VSS2 and VSS3 pins. *Note2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. Example of power connection when power-save mode is used Power Supply VDD1 Back-up capacitors VDD2 VDD3 VSS3 VSS2 VSS1 LSI

No.A1935-14/28 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage V DD max V DD1, VDD2, VDD3 • VDD1=VDD2=VDD3 -0.3 +6.5 Input voltage VI XT1, CF1, RES -0.3 V DD+0.3 Input/output voltage VIO Ports 0, 1, 2, 3, 7, 8, A, B, C, E, XT2, CF2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2, 3, A, B, C, E

• CMOS output select
• Per 1 applicable pin -10 Peak output current IOPH(2) P71, P72, P73 • Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3, A, B, C, E
• CMOS output select
• Per 1 applicable pin -7.5 Mean output current (Note 1-1) IOMH(2) P71, P72, P73 • Per 1 applicable pin -3 ∑IOAH(1) Port 0, P14 to P17 • Total of all applicable pins -25 ∑IOAH(2) Port 3, A • Total of all applicable pins -25 ∑IOAH(3) Port 0, 3, A P14 to P17
• Total of all applicable pins -45 ∑IOAH(4) Port 2 P10 to P13,PE3
• Total of all applicable pins -25 ∑IOAH(5) Port B, C, PE0 to PE2
• Total of all applicable pins -25 ∑IOAH(6) Port 2, B, C, E P10 to P13
• Total of all applicable pins -45 High level output current Total output current ∑IOAH(7) P71, P72, P73 • Total of all applicable pins -5 IOPL(1) Ports 0, 1, 2, 3, A, B, C, E
• Per 1 applicable pin 20Peak output current IOPL(2) Port 7, 8 XT2, CF2
• Per 1 applicable pin 10 IOML(1) Ports 0, 1, 2, 3, A, B, C, E
• Per 1 applicable pin 15Mean output current (Note 1-1) IOML(2) Port 7, 8 XT2, CF2
• Per 1 applicable pin 7.5 ∑IOAL(1) Port 0, P14 to P17 • Total of all applicable pins 45 ∑IOAL(2) Port 3, A • Total of all applicable pins 45 ∑IOAL(3) Port 0, 3, A P14 to P17
• Total of all applicable pins 80 ∑IOAL(4) Port 2 P10 to P13, PE3
• Total of all applicable pins 45 ∑IOAL(5) Port B, C, PE0 to PE2
• Total of all applicable pins 45 ∑IOAL(6) Port 2, B, C,E P10 to P13
• Total of all applicable pins 80 ∑IOAL(7) Port 7, XT2 • Total of all applicable pins 15 ∑IOAL(8) Port 8, CF2 • Total of all applicable pins 15 Low level output current Total output current ∑IOAL(9) Port 7, 8, XT2, CF2 • Total of all applicable pins 20 mA
• Ta=-30 to +70°C
• Package only T.B.DPd max(1) QFP80
• Ta=-30 to +70°C
• Package with thermal resistance board (Note 1-2) T.B.D
• Ta=-30 to +70°C
• Package only T.B.D Power dissipation Pd max(2) TQFP80J
• Ta=-30 to +70°C
• Package with thermal resistance board (Note 1-2) T.B.D mW Operating ambient temperature Topr -30 +70 Storage ambient temperature Tstg -55 +125 Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6tmm, glass epoxy) is used.

No.A1935-15/28 Allowable Operating Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit VDD(1) • 0.245μs≤tCYC≤200μs 3.0 5.5Operating supply voltage (Note 2-1) VDD(2) VDD1=VDD2 =VDD3 • 0.735μs≤tCYC≤200μs 2.4 5.5 Memory sustaining supply voltage VHD V DD1 • RAM and register contents sustained in HOLD mode. 2.2 5.5 VIH(1) Ports 0, 1, 2, 3, 8, A, B, C, E, P71, P72, P73 P70 port input /interrupt side

• Output disabled 2.4 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 70 watchdog timer side
• Output disabled 2.4 to 5.5 0.9V DD V DD High level input voltage VIH(3) XT1, XT2, CF1, CF2, RES 2.4 to 5.5 0.75V DD V DD VIL(1) Ports 0, 1, 2, 3, 8, A, B, C, E, P71, P72, P73 P70 port input /interrupt side
• Output disabled 2.4 to 5.5 V SS 0.1VDD +0.4 VIL(2) Port 70 watchdog timer side
• Output disabled 2.4 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(3) XT1, XT2, CF1, CF2, RES 2.4 to 5.5 V SS 0.25V DD V 3.0 to 5.5 0.245 200Instruction cycle time (Note 2-1) tCYC (Note 2-2) 2.4 to 5.5 0.735 200 μs 3.0 to 5.5 0.1 12
• CF2 pin open
• System clock frequency division ratio = 1/1
• External system clock duty = 50±5% 2.4 to 5.5 0.1 4 3.0 to 5.5 0.2 24 External system clock frequency FEXCF CF1
• CF2 pin open
• System clock frequency division ratio = 1/2
• External system clock duty = 50±5% 2.4 to 5.5 0.2 8 MHz FmCF(1) CF1, CF2 • 12MHz ceramic oscillation
• See Fig. 1. 3.0 to 5.5 12 FmCF(2) CF1, CF2 • 4MHz ceramic oscillation
• See Fig. 1. 2.4 to 5.5 4 FmVMRC(1) • Frequency variable RC source oscillation
• VMRAJ2 to 0 = 4
• VMFAJ2 to 0 = 0
• VMSL4M = 0 3.0 to 5.5 10 FmVMRC(2) • Frequency variable RC source oscillation
• VMRAJ2 to 0 = 4
• VMFAJ2 to 0 = 0
• VMSL4M=1 2.4 to 5.5 4 MHz FmRC • Internal fast RC oscillation 2.4 to 5.5 500 FsRC • Internal slow RC oscillation 2.4 to 5.5 50 Oscillation frequency range (Note 2-3) FsX’tal XT1, XT2 • 32.768kHz crystal oscillation
• See Fig. 2. 2.4 to 5.5 32.768 kHz Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Table 1, 2 for the oscillation constants Continued on next page.

No.A1935-16/28 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit OpVMRC(1)

• VMSL4M=0 3.0 to 5.5 8 10 12Frequency variable RC oscillation usable range OpVMRC(2)
• VMSL4M=1 2.4 to 5.5 3.5 4 4.5 MHz VmADJ(1)
• 1 step of VMRAJn (large range) 2.4 to 5.5 8 24 64Frequency variable RC oscillation adjustment range VmADJ(2) • 1 step of VMFAJn (small range) 2.4 to 5.5 1 4 8 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3, 7, 8, A, B, C, E
• Output disabled
• Pull-up resistor off
• VIN=VDD (Including output Tr's off leakage current) 2.4 to 5.5 1 IIH(3) RES • VIN=VDD 2.4 to 5.5 1 IIH(4) XT1, XT2 CF1, CF2
• Configured as input ports
• VIN=VDD 2.4 to 5.5 1 High level input current IIH(5) CF1 • VIN=VDD 2.4 to 5.5 15 IIL(1) Ports 0, 1, 2, 3, 7, 8, A, B, C, E
• Output disabled
• Pull-up resistor off
• VIN=VSS (Including output Tr's off leakage current) 2.4 to 5.5 -1 IIL(2) RES • VIN=VSS 2.4 to 5.5 -1 IIL(3) XT1, XT2 CF1, CF2
• Configured as input ports
• VIN=VSS 2.4 to 5.5 -1 Low level input current IIL(4) CF1 • VIN=VSS 2.4 to 5.5 -15 μA VOH(1) • IOH=-1.0mA 4.5 to 5.5 V DD-1 VOH(2) • IOH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) Ports 0, 1, 2, 3, A, B, C
• IOH=-0.2mA 2.4 to 5.5 V DD-0.4 VOH(4) • IOH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(5) P71, P72, P73
• IOH=-0.2mA 2.4 to 5.5 V DD-0.4 VOH(6) • IOH=-10mA 4.5 to 5.5 V DD-1.5 VOH(7) • IOH=-1.6mA 3.0 to 5.5 V DD-0.4 High level output voltage VOH(8) P30, P31, Port A (using as PWM)
• IOH=-1.0mA 2.4 to 5.5 V DD-0.4 VOL(1) • IOL=10mA 4.5 to 5.5 1.5 VOL(2) • IOL=1.6mA 3.0 to 5.5 0.4 VOL(3) Ports 0, 1, 2, 3, A, B, C, E
• IOL=1.0mA 2.4 to 5.5 0.4 VOL(4) • IOL=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(5) Port 7, 8 XT2, CF2 • IOL=1.0mA 2.4 to 5.5 0.4 V 4.5 to 5.5 15 40 70Pull-up resistance Rpu Ports 0, 1, 2, 3, 7, A, B, C, E
• VOH=0.9VDD 2.4 to 4.5 25 70 150 kΩ Hysteresis voltage VHYS Ports 0, 1, 2, 3, 7, A, RES 2.4 to 5.5 0.1V DD V Pin capacitance CP All pins • f=1MHz
• Ta=25°C
• For pins other than that under test: VIN=VSS 2.4 to 5.5 10 pF

No.A1935-17/28 Serial I/O Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 tSCKH(1)

• See Fig. 6. Input clock High level pulse width tSCKHA(1) SCK0(P12)
• Continuous data transmission/reception mode
• See Fig. 6. (Note 4-1-2) 2.4 to 5.5 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) 1/2 tSCKH(2)
• CMOS output selected
• See Fig. 6. Serial clock Output clock High level pulse width tSCKHA(2) SCK0(P12)
• Continuous data transmission/reception mode
• CMOS output selected
• See Fig. 6. 2.4 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCK Data setup time tsDI 0.03 Serial input Data hold time thDI SB0(P11), SI0(P11)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig. 6. 2.4 to 5.5 0.03 tdD0(1) • Continuous data transmission/reception mode (Note 4-1-3) (1/3)tCYC +0.05 Input clock tdD0(2) • Synchronous 8-bit mode (Note 4-1-3) 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.4 to 5.5 (1/3)tCYC +0.05 μs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: When using serial clock input under continuous data transmission/reception mode, the time from SI0RUN is set while serial clock is “H” to the first falling edge of serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.

No.A1935-18/28 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) 2 Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) • See Fig. 6. 2.4 to 5.5 Frequency tSCK(4) 2 tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected

• See Fig. 6. 2.4 to 5.5 tSCK Data setup time tsDI(2) 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig. 6. 2.4 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
• Must be specified with respect to falling edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig. 6. 2.4 to 5.5 (1/3)tCYC +0.05 μs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tPIH(1) tPIL(1) INT0(P70) INT1(P71) INT2(P72) INT3(P73) INT4(P20 to P23) INT5(P24 to P27)
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are enabled. 2.4 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.4 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.4 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.4 to 5.5 256 tPIH(5) tPIL(5) NKIN(P72) • High speed clock counter countable 2.4 to 5.5 1/12 tCYC High/low level pulse width tPIL(6) RES • External reset input mode
• Resetting is enabled 2.4 to 5.5 200 μs

No.A1935-19/28 AD Converter Characteristics at VSS1=VSS2=VSS3=0V <12bits AD Converter Mode / Ta=-30 to +70°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 12 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±16 LSB 4.0 to 5.5 32 115Conversion time tCAD • See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 64 115 μs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH • VAIN=VDD 3.0 to 5.5 1Analog port input current IAINL AN0(P80) to AN7(P87) AN8(PB0) to AN15(PB7)

• VAIN=VSS 3.0 to 5.5 -1 µA <8bits AD Converter Mode / Ta=-30 to +70°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.0 to 5.5 20 95Conversion time tCAD • See Conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 40 95 μs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH • VAIN=VDD 3.0 to 5.5 1Analog port input current IAINL AN0(P80) to AN7(P87) AN8(PB0) to AN15(PB7)
• VAIN=VSS 3.0 to 5.5 -1 μA Conversion time calculation formulas: 12bits AD Converter Mode : TCAD(Conversion time) = ((52/(AD division ratio))+2)×(1/3)×tCYC 8bits AD Converter Mode : TCAD(Conversion time) = ((32/(AD division ratio))+2)×(1/3)×tCYC AD conversion time (TCAD) External oscillation (FmCF) Operating supply voltage range (VDD) System division ratio (SYSDIV) Cycle time (tCYC) AD division ratio (ADDIV) 12bit AD 8bit AD 4.0V to 5.5V 1/1 250ns 1/8 34.8 μs 21.5 μs CF-12MHz 3.0V to 5.5V 1/1 250ns 1/16 69.5 μs 42.8 μs CF-4MHz 3.0V to 5.5V 1/1 750ns 1/8 104.5 μs 64.5 μs Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.A1935-20/28 Power-on Reset (POR) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min typ max unit 1.67V 1.67 1.97V 1.97 2.07V 2.07 2.37V 2.37 2.57V 2.57 2.87V 2.87 3.86V 3.86 POR release voltage PORRL • Select from option. (Note 7-1) 4.35V 4.35 Detection voltage unknown state POUKS • See Fig. 8. V Power supply rise time PORIS • Power supply rise time from 0V to x V. 100 ms Note7-1: The POR release level can be selected out of 7 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta=-30 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage min typ max unit 1.91V 1.91 2.01V 2.01 2.31V 2.31 2.51V 2.51 2.81V 2.81 3.79V 3.79 LVD reset Voltage (Note 8-2) LVDET 4.28V 4.28 V 1.91V 55 2.01V 55 2.31V 55 2.51V 55 2.81V 60 3.79V 65 LVD hysteresis width LVHYS

• Select from option. (Note 8-1) (Note 8-3)
• See Fig. 9. 4.28V 65 mV Detection voltage unknown state LVUKS • See Fig. 9. (Note 8-4) 0.7 0.95 V Low voltage detection minimum width (Reply sensitivity) TLVDW • LVDET-0.5V
• See Fig. 10. 0.2 ms Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation.

No.A1935-21/28 Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 4.5 to 5.5 8.4 22.1 IDDOP(1) • FmCF=12MHz Ceramic resonator oscillation

• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 12MHz
• Divider : 1/1 3.0 to 3.6 4.9 12.1 4.5 to 5.5 3.5 10.0 IDDOP(2) • FmCF=4MHz Cera mic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 4MHz
• Divider : 1/1 2.4 to 3.6 2.8 6.3 4.5 to 5.5 6.9 16.6 IDDOP(3) • FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=10MHz Frequency variable RC oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC oscillation 10MHz
• Divider :1/1 2.4 to 3.6 4.2 101 4.5 to 5.5 2.8 8.5 IDDOP(4) • FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=4MHz Frequency variable RC oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC oscillation 4MHz
• Divider :1/1 2.4 to 3.6 2.5 5.4 mA 4.5 to 5.5 400 1000 IDDOP(5) • FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation=Fast RC oscillation
• System clock: Fast RC oscillation
• Divider :1/1 2.4 to 3.6 300 600 4.5 to 5.5 74 269.4 Current consumption during normal operation (Note 9-1) IDDOP(6) VDD1 =VDD2 =VDD3
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: 32.768kHz
• Divider :1/1 2.4 to 3.6 26.1 110.1 μA Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Continued on next page.

No.A1935-22/28 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 4.5 to 5.5 3.3 8.4 IDDHALT(1) HALT mode

• FmCF=12MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 12MHz
• Divider : 1/1 3.0 to 3.6 1.7 4.3 4.5 to 5.5 0.3 4.1 IDDHALT(2) HALT mode
• FmCF=4MHz Ceramic resonator oscillation
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: CF oscillation 4MHz
• Divider : 1/1 2.4 to 3.6 0.1 1.8 4.5 to 5.5 2.3 5.8 IDDHALT(3) HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=10MHz Frequency variable RC oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC oscillation 10MHz
• Divider :1/1 2.4 to 3.6 1.3 3.2 4.5 to 5.5 1.0 2.5 IDDHALT(4) HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• FmVMRC=4MHz Frequency variable RC oscillation
• Internal RC oscillation stopped.
• System clock: Frequency variable RC oscillation 4MHz
• Divider :1/1 2.4 to 3.6 0.5 1.3 mA 4.5 to 5.5 200 500 IDDHALT(5) HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation=Fast RC oscillation
• System clock: Fast RC oscillation
• Divider :1/1 2.4 to 3.6 100 200 4.5 to 5.5 57.2 230.9 Current consumption during HALT mode (Note 9-1) IDDHALT(6) VDD1 = VDD2 = VDD3 HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Frequency variable RC oscillation stopped.
• Internal RC oscillation stopped.
• System clock: 32.768kHz
• Divider :1/1 2.4 to 3.6 13.6 83.2 μA Note 9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Continued on next page.

No.A1935-23/28 Continued from preceding page Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit 4.5 to 5.5 0.1 52 Current consumption during HOLD mode (Note 9-1) IDDHOLD(1) HOLD mode

• CF1=VDD or open (when using external clock) 2.4 to 3.6 0.04 22 4.5 to 5.5 49.9 213IDDHOLD(3) Date/time clock HOLD mode
• CF1=VDD or open (when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• Normal mode 2.4 to 3.6 9.6 73.4 4.5 to 5.5 1.0 94.3 Current consumption during Date/time clock HOLD mode (Note 9-1) IDDHOLD(4) VDD1 = VDD2 = VDD3 Date/time clock HOLD mode
• CF1=VDD or open (when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• Power save mode 2.4 to 3.6 0.76 39.3 μA Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Onboard programming current IDDFW V DD1 • Current of the Flash module 3.0 to 5.5 5 10 mA tFW(1) • Erase time 20 30 ms Programming time tFW(2)
• Program time 3.0 to 5.5 40 60 μs UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Transfer rate UBR UTX1(P00), URX1(P01) UTX2(P02), URX2(P03) 2.4 to 5.5 16/3 8192/3 tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Transmit data (LSB first) Start of transmission End of transmission UBR Start bit Stop bit Stop bit End of reception UBR Receive data (LSB first) Start of reception Start bit

No.A1935-25/28 Reset Time and Oscillation Stable Time HOLD Release Signal and Oscillation Stable Time Figure 4 Oscillation Stabilization Times Internal RC oscillation CF1, CF2 XT1, XT2 Operation mode HOLD release signal Without HOLD release signal HOLD release signal VALID tmsCF tmsXtal HOLD HALT Power supply RES Internal RC oscillation CF1, CF2 XT1, XT2 Reset time tmsCF tmsXtal Operating mode Unfixed Reset Instruction execution VDD VDD limit

No.A1935-28/28 Figure 10 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) PS This catalog provides information as of February, 2010. Specificati ons and information herein are subject to change without notice. PS VDD LVD reset voltage tLVDW VSS LVD release voltage LVDET-0.5V SANYO Semiconductor Co.,Ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equip ment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd.