LC87F1HC8A_0812

LC87F1HC8A_0812 SANYO | Alldatasheet

Document overview

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Technical content

Features

Flash ROM

Capable of on-board programming with a wide range of supply voltages: 3.0 to 5.5V
Block-erasable in 128 byte units
Writes data in 2-byte units
131072 × 8 bits RAM
16384 × 9 bits Bus Cycle Time
83.3ns (When CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. CMOS IC 128K-byte FROM and 16384-byte RAM integrated 8-bit 1-chip Microcontroller with USB-host controller * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No.A0956-2/27 Minimum Instruction Cycle Time (tCYC)

250ns (When CF=12MHz) Ports
I/O ports Ports whose I/O direction can be designated in 1-bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P00 to P07)
USB ports 2 (UHD+, UHD-)
Dedicated oscillator ports 2 (CF1, CF2)
Input-only port (also used for oscillation) 1 (XT1)
Reset pins 1 ( RES)
Power supply pins 6 (V SS1 to 3, VDD1 to 3) Timers
Timer 0: 16-bit timer/counter with 2 capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers)
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as a PWM output)
Timer 4: 8-bit timer with a 6-bit prescaler
Timer 5: 8-bit timer with a 6-bit prescaler
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO
SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units) (Suspension and resumption of data transmission possible in 1 byte units)
SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or in word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Continued on next page.

No.A0956-3/27 Continued from preceding page.

SIO9: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1 byte units) (Suspension and resumption of data transmission possible in 1 byte units or word units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter: 8 bits × 12 channels PWM: Multifrequency 12-bit PWM × 2 channels Infrared Remote Control Receiver Circuit 1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is selected as the base clock) 2) Supports data encoding systems such as PPM (Pulse Position Modulation) and Manchester encoding. 3) X'tal HOLD mode reset function USB Interface (host control function) 1) Compliant with full-speed (12M bps) specifications 2) Supports 4 transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer). Audio Interface 1) Sampling frequency (fs): 32kHz, 44.1kHz, 48kHz 2) Master clock frequency (internal PLL): 12.288MHz, 16.9344MHz, 18.432MHz 3) Bit clock selectable: 48fs/64fs 4) Data bit length: 16/18/20/24 bits 5) LSB first/MSB firsts selectable 6) Left-justification/right-justification selectable Watchdog Timer
Watchdog timer using external RC circuitry
Interrupt and reset signals selectable Clock Output Function 1) Can output a clock with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillator clock selected as the system clock. 2) Can output the source oscillation clock for the subclock.

No.A0956-4/27 Interrupts

40 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/IN T4/UHC bus active/remote control signal receive 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6/UHC device connected/UHC disconnected/UHC resume 6 0002BH H or L T1L/T1H/INT7/SIO9/AIF start 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/SIO4/UART1 transmit/end of AIF 9 00043H H or L ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5/UHC-SOF/DMCOPY
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 8192 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions
16 bits × 8 bits (5 tCYC execution time)
24 bits × 16 bits (12 tCYC execution time)
16 bits ÷ 8 bits (8 tCYC execution time)
24 bits ÷ 16 bits (12 tCYC execution time) Oscillation and PLL Circuits
RC oscillation circuit (internal): For system clock
CF oscillation circuit: For system clock
Crystal oscillation circuit: For system clock, time-of-day clock
PLL circuit (internal): For USB interface (s ee Fig.5) ), audio interface (see Fig. 6) Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB host controll circuit
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB host controll circuit (6) Having an interrupt source established in the infrared remote controller receiver circuit

No.A0956-5/27 Package Form

SQFP48(7×7): Lead-free type Development Tools
On-chip debugger: TCB87- type-B + LC87F1HC8A Flash ROM Programming Boards Package Programming boards SQFP48(7×7) W87F55256SQ Recommended EPROM Programmer Maker Model Supported version Device Flash Support Group, Inc. (FSG) Single Programmer AF9708/ AF9709/AF9709B/AF9709C (Including Ando Electric Co., Ltd. models) Rev 02.82 or later LC87F1HC8A AF9101/AF9103(Main body) (FSG models) Flash Support Group, Inc. (FSG) SANYO(Note 1) Onboard Single/Gang Programmer SIB87(Inter Face Driver) (SANYO model) (Note 2) LC87F1HC8A Single/Gang Programmer SKK/SKK TypeB (SANYO FWS) SANYO Onboard Single/Gang Programmer SKK-DBG TypeB (SANYO FWS) Application Version 2.04 or later Chip Data Version 2.11 or later LC87F1HC8 Note 1: With the FSG onboard programmer (AF9101/AF9103) and the serial interface driver (SIB87) provided by SANYO, PC-less standalone onboard programming is possible Note 2: Depending on programming conditions, it is necessary to use a dedicated programming device and a program. Please contact SANYO or FSG if you have any questions or difficulties regarding this matter. Package Dimensions unit : mm (typ) 3163B SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536

No.A0956-6/27 Pin Assignment SANYO : SQFP48(7×7) “Lead-free Type” SQFP48 NAME SQFP48 NAME

1 P73/INT3/T0IN/RMIN 25 P04/AN4/DBGP2

2 RES 26 P05/AN5/CKO/SDAT

3 XT1/AN10 27 P06/AN6/T6O/BCLK

4 XT2/AN11 28 P07/AN7/T7O/LRCK

5 V SS1 29 P20/INT4/INT6

6 CF1 30 P21/INT4

7 CF2 31 P22/INT4/SO4/ RD

8 V DD1 32 P23/INT4/SI4/ WR

9 P10/SO0 33 P24/INT5/INT7/SCK4

10 P11/SI0/SB0 34 P25/INT5/SO9/ RD9

11 P12/SCK0 35 P26/INT5/SI9/ WR9

12 P13/SO1 36 P27/INT5/SCK9

13 P14/SI1/SB1 37 UHD-

14 P15/SCK1 38 UHD+

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1/MCLKI 41 P34/UFILT

18 PWM0/MCLKO 42 P33/AFILT

19 V DD2 43 P32

20 V SS2 44 P31/URX1

21 P00/AN0 45 P30/UTX1

22 P01/AN1 46 P70/INT0/T0LCP/AN8

23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9

24 P03/AN3/DBGP1

48 P72/INT2/T0IN

No.A0956-7/27 System Block Diagram Interrupt control FROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Base timer Timer 4 PWM1 INT0 to INT7 Noise filter SIO0 Port 2 USB PLL Port 7 Port 3 ADC SIO1 Timer 0 Timer 1 PWM0 Timer 5 Timer 6 Timer 7 UART1 SIO4 Onchip debugger USB host SIO9 Audio interface Infrared remote control receiver circuit

No.A0956-8/27 Pin Description Pin Name I/O Description Option VSS1,VSS2, VSS3 - - power supply No VDD1, VDD2 - + power supply No VDD3 - USB reference voltage Yes Port 0 P00 to P07 I/O • 8-bit I/O ports

I/O specifiable in 4-bit units
Pull-up resistors can be turned on and off in 4-bit units.
HOLD reset input
Port 0 interrupt input
Pin functions AD converter input ports: AN0 to AN7(P00 to P07) Onchip debugger pins: DBGP0 to DBGP2(P02 to P04) P05: System clock output/audio interface SDAT input/output P06: Timer 6 toggle output/audio interface BCLK input/output P07: Timer 7 toggle output/audio interface LRCK input/output Yes Port 1 P10 to P17 I/O • 8-bit I/O ports
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P10: SIO0 data output P14: SIO1 data input/bus input/output P11: SIO0 data input/bus input/output P15: SIO1 clock input/output P12: SIO0 clock input/output P16: Timer 1 PWML output P13: SIO1 data output P17: Timer 1 PWMH output/beeper output Yes Port 2 • 8-bit I/O ports
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: INT6 input/timer 0L capture 1 input P22: SIO4 data input/output/parallel interface RD output P23: SIO4 data input/output/parallel interface WR output P24: SIO4 clock input/output/INT7 input/timer 0H capture 1 input P25: SIO9 data input/output/parallel interface RD9 output P26: SIO9 data input/output/parallel interface WR9 output P27: SIO9 clock input/output Interrupt acknowledge types Rising Falling Rising & Falling H level L level INT4 enable enable enable disable disable INT5 enable enable enable disable disable INT6 enable enable enable disable disable INT7 enable enable enable disable disable P20 to P27 I/O Yes Port 3 P30 to P34 I/O • 5-bit I/O ports
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P30: UART1 transmit P31: UART1 receive P33: Audio interface PLL filter pin (see Fig. 6.) P34: USB interface PLL filter pin (see Fig. 5.) Yes Continued on next page.

No.A0956-9/27 Continued from preceding page. Pin Name I/O Description Option Port 7 • 4-bit I/O port

I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (input with noise filter)/timer 0 event input/timer 0H capture input/ IR remote controller receiver input AD converter input ports: AN8(P70), AN9(P71) Interrupt acknowledge types Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable P70 to P73 I/O No PWM0 PWM1 I/O PWM0, PWM1 output port General-purpose input port
Pin functions PWM0: Audio interface master clock output PWM1: Audio interface master clock input No UHD- I/O USB data I/O pin UHD-/general-purpose I/O port No UHD+ I/O USB data I/O pin UHD+/general-purpose I/O port No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input
Pin functions General-purpose input port AD converter input ports: AN10 Must be connected to VDD1 when not to be used. No XT2 I/O • 32.768kHz crystal oscillator output
Pin functions General-purpose I/O AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 Input Ceramic/crystal resonator input No CF2 Output Ceramic/crystal resonator output No

No.A0956-10/27 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type Output type Pull-up resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No UHD+, UHD- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal resonator output (N channel open drain when in general-purpose output mode) No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin. and extend the backup period. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI LSI VSS1V SS2V SS3 VDD1 VDD2 VDD3 Power supply For backup

No.A0956-11/27 USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by option select. The procedure for marking the option selection is described below. (1) (2) (3) (4) USB regulator USE USE USE NONUSE USB regulator at HOLD mode USE NONUSE NONUSE NONUSE Option settings USB regulator at HALT mode USE NONUSE USE NONUSE Normal mode active active active inactive HOLD mode active inactive inactive inactive Reference voltage circuit state HALT mode active inactive active inactive

When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1.
Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
When the reference voltage circuit is activated, the current drain increases by approximately 100μA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V
Inactivating the reference voltage circuit (selection (4)).
Connecting VDD3 to VDD1 and VDD2. Example 2: VDD1=VDD2=5.0V
Activating the reference voltage circuit (selection (1)).
Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2V SS3 VDD1 VDD2 VDD3 Power Supply 3.3V For backup LSI UHD+ UHD- UFILT 15kΩ To USB connector 33Ω 5pF 2.2μF VSS1 VSS2 V SS3 VDD1 VDD2 VDD3 Power Supply For backup LSI UHD+ UHD- UFILT 2.2μF 15kΩ To USB connector 33Ω 5pF 2.2μF 0.1μF

No.A0956-12/27 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1= VDD2= VDD3 -0.3 +6.5 Input voltage V I(1) XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 Per 1 applicable pin -20 Peak output current IOPH(3) Port 3 P71 to P73
When CMOS output type is selected
Per 1 applicable pin IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 Average output current (Note 1-1) IOMH(3) Port 3 P71 to P73
When CMOS output type is selected
Per 1 applicable pin ΣIOAH(1) Ports 0, 2 To tal current of all applicable pins -25 ΣIOAH(2) Port 1 PWM0, PWM1 Total current of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins -45 ΣIOAH(4) Port 3 P71 to P73 Total current of all applicable pins -10 High level output current Total output current ΣIOAH(5) UHD+, UHD- Total current of all applicable pins -25 IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Ports 3, 7 XT2 Per 1 applicable pin 10 IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 Average output current (Note 1-1) IOML(3) Ports 3, 7 XT2 Per 1 applicable pin 7.5 ΣIOAL(1) Ports 0, 2 Total current of all applicable pins 45 ΣIOAL(2) Port 1 PWM0, PWM1 Total current of all applicable pins 45 ΣIOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total current of all applicable pins 80 ΣIOAL(4) Ports 3, 7 XT2 Total current of all applicable pins 15 Low level output current Total output current ΣIOAL(5) UHD+, UHD- Total current of all applicable pins 25 mA Allowable power Dissipation Pd max SQFP48(7 ×7) Ta=-40 to +85 °C 140 mW Operating ambient Temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: The average output current is an average of current values measured over 100ms intervals.

No.A0956-13/27 Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit 0.245µs ≤ tCYC ≤ 200µs 3.0 5.5Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.490µs ≤ tCYC ≤ 200µs Except in onboard programming mode 2.7 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 VIH(1) Port 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 70 watchdog timer side 2.7 to 5.5 0.9V DD V DD High level input voltage VIH(3) XT1, XT2, CF1, RES 2.7 to 5.5 0.75V DD V DD VIL(1) 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) Port 1, 2, 3 P71 to P73 P70 port input/ interrupt side 2.7 to 4.0 V SS 0.2V DD VIL(3) 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) Port 0 PWM0, PWM1 2.7 to 4.0 V SS 0.2V DD VIL(5) Port 70 watchdog timer side 2.7 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(6) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25V DD V 3.0 to 5.5 0.245 200Instruction cycle time (Note 2-2) tCYC Except for onboard programming mode 2.7 to 5.5 0.490 200 μs

CF2 pin open
System clock frequency division ratio=1/1
External system clock duty =50±5% 3.0 to 5.5 0.1 12 External system clock frequency FEXCF(1) CF1
CF2 pin open
System clock frequency division ratio=1/1
External system clock duty =50±5% 2.7 to 5.5 0.1 6 MHz FmCF(1) CF1, CF2 When 12MHz ceramic oscillation See Fig. 1. 3.0 to 5.5 12 FmCF(2) CF1, CF2 When 6MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 6 MHz Oscillation frequency range (Note 2-3) FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.

No.A0956-14/27 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 IIH(2) XT1, XT2 Input port configuration VIN=VDD 2.7 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 -1 IIL(2) XT1, XT2 Input port configuration VIN=VSS 2.7 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 2.7 to 5.5 -15 μA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) Ports 0, 1, 2, 3 P71 to P73 IOH=-0.2mA 2.7 to 5.5 V DD-0.4 VOH(4) I OH=-10mA 4.5 to 5.5 V DD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 High level output voltage VOH(6) PWM0, WM1 P05 to P07 (Note 3-1) IOH=-1mA 2.7 to 5.5 V DD-0.4 VOL(1) I OL=30mA 4.5 to 5.5 1.5 VOL(2) I OL=5mA 3.0 to 5.5 0.4 VOL(3) P00, P01 IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) I OL=10mA 4.5 to 5.5 1.5 VOL(5) I OL=1.6mA 3.0 to 5.5 0.4 VOL(6) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=1mA 2.7 to 5.5 0.4 VOL(7) I OL=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(8) Ports 3, 7 IOL=1mA 2.7 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80Pull-up resistance Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 2.7 to 5.5 18 50 150 kΩ Hysteresis voltage VHYS RES Port 1, 2, 3, 7 2.7 to 5.5 0.1VDD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF Note 3-1: When the CKO system clock output function (P05) or audio interface output function (P05 to P07) is used.

No.A0956-15/27 Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 8. tSCKHA(1a) • Continuous data transfer mode

USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time.
See Fig. 8.
(Note 4-1-2) tSCKHA(1b) • Continuous data transfer mode
USB used at the same time.
AIF, SIO4, SIO9, and DMCOPY not used at the same time.
See Fig. 8.
(Note 4-1-2) Input clock High level pulse width tSCKHA(1c) SCK0(P12)
Continuous data transfer mode
USB, AIF, SIO4, SIO9, and DMCOPY used at the same time.
See Fig. 8.
(Note 4-1-2) 2.7 to 5.5 Frequency tSCK(2) tCYC Low level pulse width tSCKL(2) tSCKH(2)
When CMOS output type is selected
See Fig. 8. tSCK tSCKHA(2a) • Continuous data transfer mode
USB, AIF, SIO4, SIO9, and DMCOPY not used at the same time.
When CMOS output type is selected
See Fig. 8. tSCKH(2) +2tCYC tSCKH(2) (10/3)tCYC tSCKHA(2b) • Continuous data transfer mode
USB used at the same time.
AIF, SIO4, SIO9, and DMCOPY not used at the same time.
When CMOS output type is selected.
See Fig. 8. tSCKH(2) +2tCYC tSCKH(2) (19/3)tCYC Serial clock Output clock High level pulse width tSCKHA(2c) SCK0(P12)
Continuous data transfer mode
USB, AIF, SIO4, SIO9, and DMCOPY used at the same time
When CMOS output type is selected
See Fig. 8. 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) (25/3)tCYC tCYC Note 4-1-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-1-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the time from SI0RUN being set when serial clock is high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page.

No.A0956-16/27 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Data setup time tsDI(1) 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)

Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 tdD0(1)
Continuous data transfer mode
(Note 4-1-3) (1/3)tCYC +0.05 Input clock tdD0(2)
Synchronous 8-bit mode
(Note 4-1-3) 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig. 8. 2.7 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • When CMOS output type is selected
See Fig. 8. 2.7 to 5.5 tSCK Data setup time tsDI(2) 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-2-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions.

No.A0956-17/27 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(5) 2 Low level pulse width tSCKL(5) 1 tSCKH(5) See Fig. 8. tSCKHA(5a) • USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.

See Fig. 8.
(Note 4-3-2) tSCKHA(5b) • USB used at the same time
SIO0 continuous transfer mode, AIF, SIO9, DMCOPY not used at the same time.
See Fig. 8.
(Note 4-3-2) Input clock High level pulse width tSCKHA(5c) SCK4(P24)
USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time.
AIF not used at the same time.
See Fig. 8.
(Note 4-3-2) 2.7 to 5.5 Frequency tSCK(6) 4/3 tCYC Low level pulse width tSCKL(6) tSCKH(6)
When CMOS output type is selected.
See Fig. 8. tSCK tSCKHA(6a) • USB, SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.
When CMOS output type is selected.
See Fig. 8. tSCKH(6) (5/3)tCYC tSCKH(6) (10/3)tCYC tSCKHA(6b) • USB used at the same time.
SIO0 continuous transfer mode, AIF, SIO9, and DMCOPY not used at the same time.
When CMOS output type is selected.
See Fig. 8. tSCKH(6) (5/3)tCYC tSCKH(6) (19/3)tCYC Serial clock Output clock High level pulse width (Note 4-3-3) tSCKHA(6c) SCK4(P24)
USB, SIO0 continuous transfer mode, SIO9, and DMCOPY used at the same time.
AIF not used at the same time.
When CMOS output type is selected.
See Fig. 8. 2.7 to 5.5 tSCKH(6) (5/3)tCYC tSCKH(6) (34/3)tCYC tCYC Note 4-3-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-3-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI4RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Note 4-3-3: When using the serial clock output, make sure that the load at the SCK4 (P24) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V Continued on next page.

No.A0956-18/27 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Data setup time tsDI(3) 0.03 Serial input Data hold time thDI(3) SO4(P22), SI4(P23)

Must be specified with respect to falling edge of SIOCLK.
See Fig. 8 2.7 to 5.5 0.03 Serial output Output delay time tdD0(5) SO4(P22), SI4(P23)
Must be specified with respect to rising edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 μs 4. SIO9 Serial I/O Characteristics (Note 4-4-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(7) Low level pulse width tSCKL(7) 1 tSCKH(7) See Fig. 8. tSCKHA(7a) • USB, SIO0 continuous transfer mode, AIF, SIO4 and DMCOPY not used at the same time.
See Fig. 8.
(Note 4-4-2) tSCKHA(7b) • USB used at the same time.
SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
See Fig. 8.
(Note 4-4-2) Serial clock Input clock High level pulse width tSCKHA(7c) SCK9(P27)
USB, SIO0 continuous transfer mode, SIO4 and DMCOPY used at the same time.
AIF not used at the same time.
See Fig. 8.
(Note 4-4-2) 2.7 to 5.5 tCYC Note 4-4-1: These specifications are theoretical values. Margins must be allowed according to the actual operating conditions. Note 4-4-2: In an application where the serial clock input is to be used in the continuous data transfer mode, the period from the time SI9RUN is set with the serial clock set high to the falling edge of the first serial clock must be longer than tSCKHA. Continued on next page

No.A0956-19/27 Continued from preceding page Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(8) 4/3 tCYC Low level pulse width tSCKL(8) tSCKH(8)

When CMOS output type is selected.
See Fig. 8. tSCK tSCKHA(8a) • USB, SIO0 continuous transfer mode, AIF SIO4 DMCOPY not used at the same time.
When CMOS output type is selected.
See Fig. 8. tSCKH(8) (5/3)tCYC tSCKH(8) (10/3)tCYC tSCKHA(8b) • USB used at the same time.
SIO0 continuous transfer mode, AIF, SIO4, and DMCOPY not used at the same time.
When CMOS output type is selected
See Fig. 8. tSCKH(8) (5/3)tCYC tSCKH(8) (19/3)tCYC Serial clock Output clock High level pulse width (Note 4-4-3) tSCKHA(8c) SCK9(P27)
USB, SIO0 continuous transfer mode , SIO4, and DMCOPY used at the same time.
AIF not used at the same time.
When CMOS output type is selected.
See Fig. 8. 2.7 to 5.5 tSCKH(8) (5/3)tCYC tSCKH(8) (43/3)tCYC tCYC Data setup time tsDI(4) 0.03 Serial input Data hold time thDI(4) SO9(P25), SI9(P26)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 Serial output Output delay time tdDO(6) SO9(P25), SI9(P26)
Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 μs Note 4-4-3: When using the serial clock output, make sure that the load at the SCK9 (P27) pin meets the following conditions: Clock rise time tSCKR < 0.037μs (see Figure 12.) at Ta=+25°C, VDD=3.3V

No.A0956-20/27 Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tP1H(1) tP1L(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24)

Interrupt source flag can be set.
Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is
Interrupt source flag can be set.
Event inputs for timer 0 are nabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tCYC tPIL(5) RMIN(P73) Recognized by the infrared remote control receiver circuit as a signal 2.7 to 5.5 4 RMCK (Note 5-1) High/low level pulse width tPIL(6) RES Resetting is enabled. 2.7 to 5.5 200 μs Note 5-1: Represents the period of the reference clock (1 tCYC to 128 tCYC or the source frequency of the subclock) for the infrared remote control receiver circuit. AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.5 to 5.5 15.68 (tCYC= 0.490µs) 97.92 (tCYC= 3.06µs) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) 3.0 to 5.5 23.52 (tCYC= 0.735µs) 97.92 (tCYC= 3.06µs) 4.5 to 5.5 18.82 (tCYC= 0. 294µs) 97.92 (tCYC= 1.53µs) Conversion time TCAD AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 3.0 to 5.5 47.04 (tCYC= 0.735µs) 97.92 (tCYC= 1.53µs) μs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 μA Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. Note 6-2: The conversion time refers to the period from the time when an instruction for starting a conversion process is issued to the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value.

No.A0956-21/27 Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDOP(1) 4.5 to 5.5 9.8 24 IDDOP(2)

FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation stopped
Internal RC oscillation stopped
USB circuit stopped
1/1 frequency division ratio 3.0 to 3.6 5.7 14 IDDOP(3) 4.5 to 5.5 15 35 IDDOP(4)
FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation mode active
Internal RC oscillation stopped
USB circuit active
1/1 frequency division ratio 3.0 to 3.6 7.7 20 IDDOP(5) 4.5 to 5.5 6.7 16 IDDOP(6) 3.0 to 3.6 3.9 9.0 IDDOP(7)
FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 6MHz side
Internal RC oscillation stopped
1/2 frequency division ratio 2.7 to 3.0 3.2 7.3 IDDOP(8) 4.5 to 5.5 0.72 3.4 IDDOP(9) 3.0 to 3.6 0.41 1.9 IDDOP(10)
FmCF=0Hz(oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation.
1/2 frequency division ratio 2.7 to 3.0 0.35 1.5 mA IDDOP(11) 4.5 to 5.5 45 184 IDDOP(12) 3.0 to 3.6 18 65 Normal mode consumption current (Note 7-1) IDDOP(13)
FmCF=0Hz(oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to crystal oscillation. (32.768kHz)
Internal RC oscillation stopped
1/2 frequency division ratio 2.7 to 3.0 14 47 μA IDDHALT(1) 4.5 to 5.5 4.9 12 IDDHALT(2)
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation stopped
Internal RC oscillation stopped
USB circuit stopped
1/1 frequency division ratio 3.0 to 3.6 2.7 6.4 IDDHALT(3) 4.5 to 5.5 9.5 23 IDDHALT(4)
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation mode active
Internal RC oscillation stopped
USB circuit active
1/1 frequency division ratio 3.0 to 3.6 4.7 12 IDDHALT(5) 4.5 to 5.5 3.0 7.3 IDDHALT(6) 3.0 to 3.6 1.6 3.8 IDDHALT(7)
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 6MHz side
Internal RC oscillation stopped
1/2 frequency division ratio 2.7 to 3.0 1.3 2.9 IDDHALT(8) 4.5 to 5.5 0.41 2.0 IDDHALT(9) 3.0 to 3.6 0.20 0.95 HALT mode consumption current (Note7-1) IDDHALT(10) VDD1 =VDD2 =VDD3
HALT mode
FmCF=0Hz(oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation.
1/2 frequency division ratio 2.7 to 3.0 0.17 0.70 mA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A0956-22/27 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDHALT(11) 4.5 to 5.5 31 132 IDDHALT(12) 3.0 to 3.6 9.1 39 HALT mode consumption current (Note 7-1) IDDHALT(13) VDD1 =VDD2 =VDD3

HALT mode
FmCF=0MHz (oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to crystal oscillation. (32.768kHz)
Internal RC oscillation stopped
1/2 frequency division ratio 2.7 to 3.0 6.3 27 IDDHOLD(1) 4.5 to 5.5 0.14 39 IDDHOLD(2) 3.0 to 3.6 0.04 19 HOLD mode consumption current IDDHOLD(3)
HOLD mode
CF1=VDD or open (External clock mode) 2.7 to 3.0 0.04 17 IDDHOLD(4) 4.5 to 5.5 25 115 IDDHOLD(5) 3.0 to 3.6 6.0 32 Timer HOLD mode consumption current IDDHOLD(6) VDD1
Timer HOLD mode
CF1=VDD or open (External clock mode)
FsX’tal=32.768kHz crystal oscillation mode 2.7 to 3.0 3.7 20 μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors USB Characteristics and Timing at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Conditions min typ max unit High level output V OH(USB) • 15kΩ±5% to GND 2.8 3.6 V Low level output V OL(USB) • 1.5kΩ±5% to 3.6V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • ⏐(UHD+)-(UHD-)⏐ 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R • RS=33Ω, CL=50pF 4 20 ns USB data fall time t F • RS=33Ω, CL=50pF 4 20 ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Excluding power dissipation in the microcontroller block 3.0 to 5.5 5 10 mA tFW(1) • Erase operation 20 30 ms Programming time tFW(2)
Write operation 3.0 to 5.5 40 60 μs

No.A0956-23/27 Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 shows the characteristics of a oscillation circuit when USB host function is not used. If USB host function is to be used, it is absolutely recommended to use an oscillator that satisfies the precision and stability according to the USB standards. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Oscillator Name [pF] [pF] Rd1 [Ω] Operating Voltage Range [V] typ [ms] max [ms] Remarks 6MHz MURATA CSTCR6M00GH5L-R0 ( 39) (39) 1k 2.7 to 5.5 0.1 0.5 8MHz MURATA CSTCE8M00GH5L-R0 (33) (33) 470 3.0 to 5.5 0.1 0.5 10MHz MURATA CSTCE10M0GH5L-R0 (33) (33) 330 3.0 to 5.5 0.1 0.5 12MHz MURATA CSTCE12M0GH5L-R0 (33) (33) 330 3.0 to 5.5 0.1 0.5 C1 and C2 integrated SMD type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4):

Till the oscillation gets stabilized after VDD goes above the operating voltage lower limit.
Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed
Till the oscillation gets stabilized after the HOLD mode is reset.
Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0 Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO- designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Oscillator Name [pF] [pF] Rf [Ω] Rd2 [Ω] Operating Voltage Range [V] typ [s] max [s] Remarks 32.768kHz EPSON TOYOCOM MC-306 18 18 OPEN 560k 2.7 to 5.5 1.1 3.0 Applicable CL value=12.5pF SMD type The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in the following cases (see Figure 4):
Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed
Till the oscillation gets stabilized after the HOLD mode is reset with EXTOSC (OCR register, bit 6) set to 1 Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern. Figure 1 CF Oscillator Circuit Figure 2 Crystal Oscillator Circuit Rf Rd2 XT1 XT2 C4 X’talC3 Rd1 CF1 CF2 C2CFC1

Summary

8-bit 1-chip Microcontroller with USB-host controller

Description