LC87F1G64A SANYO | Alldatasheet

Document overview

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Technical content

Features

„Flash ROM

  • Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
  • Block-erasable in 128 byte units
  • 65536 × 8 bits „RAM
  • 3072 × 9 bits „Minimum Bus Cycle
  • 83.3ns (CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. „Minimum Instruction Cycle Time
  • 250ns (CF=12MHz) CMOS IC FROM 64K byte, RAM 3K byte on-chip 8-bit 1-chip Microcontroller with Full-Speed USB * This production is produced and sold by SANYO under license of the Silicon Storage Technology Inc. Specifications and information herein are subject to change without notice. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated val ues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.

No.A0477-2/29 „Ports

  • I/O ports Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07)
  • U S B p o r t s 2 ( D + , D - )
  • Dedicated oscillator ports 2 (CF1, CF2)
  • Input-only port (also used for oscillation) 1 (XT1)
  • Reset pins 1 ( RES)
  • Power pins 6 (V SS1 to 3, VDD1 to 3) „Timers
  • Timer 0: 16-bit timer/counter with two capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit counter (with two 16-bit capture registers)
  • Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an-8bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
  • Timer 4: 8-bit timer with a 6-bit prescaler
  • Timer 5: 8-bit timer with a 6-bit prescaler
  • Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
  • Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
  • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes „SIO
  • SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units)
  • SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
  • SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 3072 bytes, specifiable in 1 byte units, suspension and resumption of data transmission possible in 1 byte or 2 bytes units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in

No.A0477-3/29 „Full Duplex UART 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC „AD Converter: 8 bits × 12 channels „PWM: Multifrequency 12-bit PWM × 2 channels „USB Interface (function controller)

  • Compliant with USB 2.0 Full-Speed
  • Supports a maximum of 8 user-defined endpoints. Endpoint EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 Control { - - - - - - - - Transfer Type Max. payload 64 64 64 64 64 1023 1023 64 64 „Audio Interface 1) Sampling frequency (fs): 32kHz, 44.1kHz, 48kHz 2) PLL clock frequency: 12.288MHz, 16.9344MHz, 18.432MHz 3) Supported master clocks Bit Clock Master Clock 384fs 192fs 48fs 96fs 384fs 256fs 64fs 128fs 4) Data lengths of 16, 18, 20, 24 bits selectable 5) LSB first/MSB first mode selectable 6) Left Justified/Right Justified selectable „Watchdog Timer
  • External RC watchdog timer
  • Interrupt and reset signals selectable „Clock Output Function 1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) Able to output oscillation clock of sub clock.

No.A0477-4/29 „Interrupts

  • 32 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4/USB bus active 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/USB bus reset/USB suspend/UART1 receive 8 0003BH H or L SIO1/USB endpoint/USB-SOF/SIO4/UART1 transmit/AIF 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5
  • Priority Level: X > H > L
  • Of interrupts of the same level, the one with the smallest vector address takes precedence. „Subroutine Stack Levels: 1536 levels (the stack is allocated in RAM.) „High-speed Multiplication/Division Instructions
  • 16 bits × 8 bits (5 tCYC execution time)
  • 24 bits × 16 bits (12 tCYC execution time)
  • 16 bits ÷ 8 bits (8 tCYC execution time)
  • 24 bits ÷ 16 bits (12 tCYC execution time) „Oscillation Circuits
  • RC oscillation circuit (internal): For system clock
  • CF oscillation circuit: For system clock
  • Crystal oscillation circuit: For system clock, time-of-day clock
  • PLL circuit (internal): For USB interface (see Fig.5), audio interface (see Fig.6) „Standby Function
  • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.
  • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator , CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB interface circuit
  • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB interface circuit

No.A0477-5/29 „ROM Correction Function

  • Executes the correction program on detection of a match with the program counter value.
  • Correction program area size: 128 bytes „Package Form
  • TQFP48J(7×7): Lead-free type
  • QIP48E(14×14): Lead-free type
  • TQFP64J(10×10): Lead-free type „Development Tools
  • On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1G64A „Flash ROM Programming Boards Package Programming boards QIP48E(14×14) W87F55256Q TQFP48J(7×7) W87F55256SQ TQFP64J(10×10) W87F15256TQ „Recommended EPROM programmer Maker Model Supported version Device Flash Support Group, Inc. (Single) AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) After 02.61 LC87F1G64A FAST SANYO SKK (SANYO FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F1G64 Package Dimensions Package Dimensions unit : mm (typ) unit : mm (typ) 3288 3156A SANYO : TQFP48J(7X7) 7.0 9.0 7.0 9.0 0.125 0.5 0.20.5 (0.75)(1.0) 1.2max 0.1 11 2 2536 1348 2437 SANYO : QIP48E(14X14) 14.0 17.2 14.0 17.2 0.150.35 0.8 1.0 (1.5) 1 12 2536 48(2.7) 3.0max 0.1

No.A0477-6/29 Package Dimensions unit : mm (typ) 3310 Pin Assignments SANYO: TQFP48J(7×7) “Lead-free Type” SANYO: QIP48E(14×14) “Lead-free Type” P27/INT5/LRCK P26/INT5/BCLK P25/INT5/SDAT P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4/URX1 P20/INT4/INT6/UTX1 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4/DBGP2 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCL K P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 LC87F1G64A Top view SANYO : TQFP64J(10X10) 12.0 12.0 0.1

1.2 MAX

0.5 0.18 10.0 10.0 0.1250.5 (1.25) (1.0) 11 6 3348

No.A0477-7/29 SANYO: TQFP64J(10×10) “Lead-free Type” NC NC VDD3 VSS3 P34/UFILT P33/AFILT P32/ACF2 P31/ACF1 P30/MCL K P70/INT0/T0LCP/AN8/DPUP P71/INT1/T0HCP/AN9 P72/INT2/T0IN NC NC NC NC P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 NC NC NC NC P27/INT5/LRCK P26/INT5/BCLK P25/INT5/SDAT P24/INT5/INT7/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4/URX1 P20/INT4/INT6/UTX1 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4/DBGP2 NC NC NC NC P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LC87F1G64A Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

No.A0477-8/29 TQFP48J/ QIP48E NAME TQFP48J/ QIP48E NAME

1 P73/INT3/T0IN 25 P04/AN4/DBGP2

2 RES 26 P05/AN5/CKO

3 XT1/AN10 27 P06/AN6/T6O

4 XT2/AN11 28 P07/AN7/T7O

5 V SS1 29 P20/INT4/INT6/UTX1

6 CF1 30 P21/INT4/URX1

7 CF2 31 P22/INT4/SO4/ RD

8 V DD1 32 P23/INT4/SI4/ WR

9 P10/SO0 33 P24/INT5/INT7/SCK4

10 P11/SI0/SB0 34 P25/INT5/SDAT

11 P12/SCK0 35 P26/INT5/BCLK

12 P13/SO1 36 P27/INT5/LRCK

13 P14/SI1/SB1 37 D-

14 P15/SCK1 38 D+

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1 41 P34/UFILT

18 PWM0 42 P33/AFILT

19 V DD2 43 P32/ACF2

20 V SS2 44 P31/ACF1

21 P00/AN0 45 P30/MCLK

22 P01/AN1 46 P70/INT0/T0LCP/AN8/DPUP

23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9

24 P03/AN3/DBGP1

48 P72/INT2/T0IN

No.A0477-9/29 TQFP64J NAME TQFP64J NAME

1 NC 33 NC

2 NC 34 NC

3 P73/INT3/T0IN 35 P04/AN4/DBGP2

4 RES 36 P05/AN5/CKO

5 XT1/AN10 37 P06/AN6/T6O

6 XT2/AN11 38 P07/AN7/T7O

7 V SS1 39 P20/INT4/INT6/UTX1

8 CF1 40 P21/INT4/URX1

9 CF2 41 P22/INT4/SO4/ RD

10 V DD1 42 P23/INT4/SI4/ WR

11 P10/SO0 43 P24/INT5/INT7/SCK4

12 P11/SI0/SB0 44 P25/INT5/SDAT

13 P12/SCK0 45 P26/INT5/BCLK

14 P13/SO1 46 P27/INT5/LRCK

15 NC 47 NC

16 NC 48 NC

17 NC 49 NC

18 NC 50 NC

19 P14/SI1/SB1 51 D-

20 P15/SCK1 52 D+

21 P16/T1PWML 53 V DD3

22 P17/T1PWMH/BUZ 54 V SS3

23 PWM1 55 P34/UFILT

24 PWM0 56 P33/AFILT

25 V DD2 57 P32/ACF2

26 V SS2 58 P31/ACF1

27 P00/AN0 59 P30/MCLK

28 P01/AN1 60 P70/INT0/T0LCP/AN8/DPUP

29 P02/AN2/DBGP0 61 P71/INT1/T0HCP/AN9

30 P03/AN3/DBGP1 62 P72/INT2/T0IN

31 NC 63 NC

No.A0477-10/29 System Block Diagram Interrupt control FROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Base timer Timer 4 PWM1 INT0 to 7 Noise filter SIO0 Port 2 USB PLL Port 7 Port 3 Audio interface SIO1 Timer 0 Timer 1 PWM0 Timer 5 Timer 6 Timer 7 UART1 SIO4 On-chip debugger USB interface ADC

No.A0477-11/29 Pin Description Pin Name I/O Description Option VSS1, VSS2, VSS3 - -power supply pin No VDD1, VDD2 - +power supply pin No VDD3 - USB reference voltage pin Yes Port 0 P00 to P07 I/O • 8-bit I/O port

  • I/O specifiable in 4-bit units
  • Pull-up resistors can be turned on and off in 4-bit units.
  • HOLD reset input
  • Port 0 interrupt input
  • Pins functions AD converter input port: AN0 to AN7 (P00 to P07) On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04) P01: Audio interface SDAT input P05: System Clock Output/Audio interface SDAT input P06: Timer 6 toggle outputs P07: Timer 7 toggle outputs Yes Port 1 P10 to P17 I/O • 8-bit I/O port
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Yes Port 2 • 8-bit I/O port
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P20: UART1 transmit/INT6 input/timer 0L capture 1 input P21: UART1 receive/Audio interface SDAT input P22: SIO4 date I/O/parallel interface RD output P23: SIO4 date I/O/parallel interface WR output P24: SIO4 clock I/O/INT7 input/timer 0H capture 1 input P25: Audio interface SDAT I/O P26: Audio interface BCLK I/O P27: Audio interface LRCK I/O Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT4 enable enable enable disable disable INT5 enable enable enable disable disable INT6 enable enable enable disable disable INT7 enable enable enable disable disable P20 to P27 I/O Yes Continued on next page.

No.A0477-12/29 Continued from preceding page. Pin Name I/O Description Option Port 3 P30 to P34 I/O • 5-bit I/O port

  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P30: Audio interface master clock I/O P31: Audio interface oscillator input P32: Audio interface oscillator output P33: Audio interface PLL filter pin (see Fig.6) P34: USB interface PLL filter pin (see Fig.5) Yes Port 7 • 4-bit I/O port
  • I/O specifiable in 1-bit units
  • Pull-up resistors can be turned on and off in 1-bit units.
  • Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/ D+ 1.5kΩ pull-up resistor connect pin P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input AD converter input port: AN8(P70), AN9(P71) Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable P70 to P73 I/O No PWM0 PWM1 I/O • PWM0 and PWM1 output port
  • General-purpose input port No D- I/O • USB data I/O pin D-
  • General-purpose I/O port No D+ I/O • USB data I/O pin D+
  • General-purpose I/O port No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin
  • Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. No XT2 I/O 32.768kHz crystal oscillator output pin
  • Pin functions General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 Input Ceramic resonator input pin No CF2 Output Ceramic resonator output pin No

No.A0477-13/29 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No D+, D- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal oscillator output No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI LSI VSS1V SS2V SS3 VDD1 VDD2 VDD3 Power supply For backup

No.A0477-14/29 USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of reference voltage circuit can be switched by the option select. The procedure for marking the option selection is described below. (1) (2) (3) (4) USB Regulator USE USE USE NONUSE USB Regulator at HOLD mode USE NONUSE NONUSE NONUSE Option select USB Regulator at HALT mode USE NONUSE USE NONUSE Normal state active active active inactive HOLD mode active inactive inactive inactive Reference voltage circuit state HALT mode active inactive active inactive

  • When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1.
  • Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
  • When the reference voltage circuit is activated, the current drain increase by approximately 100µA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V
  • Inactivating the reference voltage circuit (selection (4)).
  • Connecting VDD3 to VDD1 and VDD2. Example 2: VDD1=VDD2=5.0V
  • Activating the reference voltage circuit (selection (1)).
  • Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply 3.3V For backup LSI UFILT To USB connector 27 to 33Ω 5pF 2.2µF 1.5kΩ P70 VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI UFILT 2.2µF To USB connector27 to 33Ω 5pF 1.5kΩ P70 2.2µF 0.1µF

No.A0477-15/29 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 V DD1=VDD2=VDD3 -0.3 +6.5 Input voltage V I(1) XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1, XT2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

  • Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 Per 1 applicable pin -20 Peak output current IOPH(3) Ports 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
  • Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 Average output current (Note 1-1) IOMH(3) Ports 3 P71 to P73
  • When CMOS output type is selected
  • Per 1 applicable pin ΣIOAH(1) Ports 0, 2 Total of all applicable pins -25 ΣIOAH(2) Ports 1 PWM0, PWM1 Total of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins -45 ΣIOAH(4) Ports 3 P71 to P73 Total of all applicable pins -10 High level output current Total output current ΣIOAH(5) D+, D- Total of all applicable pins -25 IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Ports 3, 7, XT2 Per 1 applicable pin 10 IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 Average output current (Note 1-1) IOML(3) Ports 3, 7, XT2 Per 1 applicable pin 7.5 ΣIOAL(1) Ports 0, 2 Total of all applicable pins 45 ΣIOAL(2) Ports 1 PWM0, PWM1 Total of all applicable pins 45 ΣIOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins 80 ΣIOAL(4) Ports 3, 7, XT2 Total of all applicable pins 15 Low level output current Total output current ΣIOAL(5) D+, D- Total of all applicable pins 25 mA QIP48E(14×14) 330 TQFP48J(7×7) 190 Allowable power Dissipation Pd max TQFP64J(10×10) Ta=-20to+70°C 280 mW Operating ambient Temperature Topr -20 +70 Storage ambient temperature Tstg -55 +125 Note 1-1: The mean output current is a mean value measured over 100ms.

No.A0477-16/29 Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit 0.245µs≤tCYC≤200µs 3.0 5.5 Operating supply voltage (Note 2-1) VDD(1) V DD1=VDD2=VDD3 0.490µs≤tCYC≤200µs Except for onboard programming 2.7 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 VIH(1) Ports 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 VDD VIH(2) Port 70 watchdog timer side 2.7 to 5.5 0.9V DD V DD High level input voltage VIH(3) XT1, XT2, CF1, RES 2.7 to 5.5 0.75V DD V DD VIL(1) 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) Ports 1, 2 P71 to P73 P70 port input/ interrupt side 2.7 to 4.0 V SS 0.2V DD VIL(3) 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) Ports 0, 3 PWM0, PWM1 2.7 to 4.0 V SS 0.2V DD VIL(5) Port 70 watchdog timer side 2.7 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(6) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25VDD V 3.0 to 5.5 0.245 200 Instruction cycle time (Note 2-2) tCYC Except for onboard programming 2.7 to 5.5 0.490 200 µs

  • CF2 pin open
  • System clock frequency division ratio=1/1
  • External system clock duty =50±5% 3.0 to 5.5 0.1 12 External system clock frequency FEXCF(1) CF1
  • CF2 pin open
  • System clock frequency division ratio=1/1
  • External system clock duty =50±5% 2.7 to 5.5 0.1 6 MHz FmCF(1) CF1, CF2 12 MHz ceramic oscillation See Fig. 1. 3.0 to 5.5 12 FmCF(2) CF1, CF2 6 MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 6 MHz Oscillation frequency range (Note 2-3) FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.

No.A0477-17/29 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, D- Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 IIH(2) XT1, XT2 For input port specification VIN=VDD 2.7 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 D+, D- Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 -1 IIL(2) XT1, XT2 For input port specification VIN=VSS 2.7 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 2.7 to 5.5 -15 µA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) Ports 0, 1, 2, 3 P71 to P73 IOH=-0.2mA 2.7 to 5.5 V DD-0.4 VOH(4) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 VOH(5) P30 (when using MCLK output function) P73 (when using clock output function) IOH=-1mA 2.7 to 5.5 V DD-0.4 VOH(6) I OH=-10mA 4.5 to 5.5 V DD-1.5 VOH(7) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 High level output voltage VOH(8) PWM0, PWM1 P05 (CK0 when using system clock output function) IOH=-1mA 2.7 to 5.5 V DD-0.4 VOL(1) I OL=30mA 4.5 to 5.5 1.5 VOL(2) I OL=5mA 3.0 to 5.5 0.4 VOL(3) P00, P01 IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) I OL=10mA 4.5 to 5.5 1.5 VOL(5) I OL=1.6mA 3.0 to 5.5 0.4 VOL(6) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=1mA 2.7 to 5.5 0.4 VOL(7) I OL=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(8) Ports 3, 7 IOL=1mA 2.7 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80 Pull-up resistance Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 2.7 to 5.5 18 50 150 kΩ Hysteresis voltage VHYS RES Ports 1, 2, 7 2.7 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF

No.A0477-18/29 Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig.9. tSCKHA(1a) • Continuous data transmission/ reception mode

  • USB, SIO4 nor AIF are not in use simultaneous.
  • See Fig.9.
  • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode
  • USB is in use simultaneous.
  • SIO4 nor AIF are not in use simultaneous.
  • See Fig.9.
  • (Note 4-1-2) Input clock High level pulse width tSCKHA(1c) SCK0(P12)
  • Continuous data transmission/ reception mode
  • USB, SIO4 and AIF are in use simultaneous.
  • See Fig.9.
  • (Note 4-1-2) 2.7 to 5.5 Frequency tSCK(2) tCYC Low level pulse width tSCKL(2) tSCKH(2)
  • CMOS output selected
  • See Fig.9. tSCK tSCKHA(2a) • Continuous data transmission/ reception mode
  • USB, SIO4 nor AIF are not in use simultaneous.
  • CMOS output selected
  • See Fig.9. tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCKHA(2b) • Continuous data transmission/ reception mode
  • USB is in use simultaneous.
  • SIO4 nor AIF are not in use simultaneous.
  • CMOS output selected
  • See Fig.9. tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC Serial clock Output clock High level pulse width tSCKHA(2c) SCK0(P12)
  • Continuous data transmission/ reception mode
  • USB, SIO4 and AIF are in use simultaneous.
  • CMOS output selected
  • See Fig.9. 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC tCYC Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0477-19/29 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Data setup time tsDI(1) 2.7 to 5.5 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)

  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig.9. 2.7 to 5.5 0.03 tdD0(1)
  • Continuous data transmission/reception mode
  • (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 Input clock tdD0(2)
  • Synchronous 8-bit mode 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.9. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig.9. 2.7 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected
  • See Fig.9. 2.7 to 5.5 tSCK Data setup time tsDI(2) 2.7 to 5.5 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig.9. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
  • Must be specified with respect to falling edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig.9. 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A0477-20/29 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(5) Low level pulse width tSCKL(5) 1 tSCKH(5) See Fig.9. tSCKHA(5a) • USB, AIF nor continuous data Transmission/reception mode Of SIO0 are not in use simultaneous.

  • See Fig.9.
  • (Note 4-3-2) tSCKHA(5b) • USB is in use simultaneous.
  • AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
  • See Fig.9.
  • (Note 4-3-2) Input clock High level pulse width tSCKHA(5c) SCK4(P24)
  • USB and continuous data transmission/ reception mode of SIO0 are in use simultaneous.
  • AIF is not in use simultaneous.
  • See Fig.9.
  • (Note 4-3-2) 2.7 to 5.5 Frequency tSCK(6) tCYC Low level pulse width tSCKL(6) tSCKH(6)
  • CMOS output selected
  • See Fig.9. tSCK tSCKHA(6a) • USB, AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
  • CMOS output selected
  • See Fig.9. tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tSCKHA(6b) • USB is in use simultaneous.
  • AIF nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
  • CMOS output selected
  • See Fig.9. tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC Serial clock Output clock High level pulse width tSCKHA(6c) SCK4(P24)
  • USB and continuous data transmission/reception mode of SIO0 are in use simultaneous.
  • AIF is not in use simultaneous.
  • CMOS output selected
  • See Fig.9. 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC tCYC Data setup time tsDI(3) 2.7 to 5.5 0.03 Serial input Data hold time thDI(3) SO4(P22), SI4(P23)
  • Must be specified with respect to rising edge of SIOCLK.
  • See Fig.9. 2.7 to 5.5 0.03 µs Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0477-21/29 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Serial output Output delay time tdD0(5) SO4(P22), SI4(P23)

  • Must be specified with respect to rising edge of SIOCLK.
  • Must be specified as the time to the beginning of output state change in open drain output mode.
  • See Fig.9. 2.7 to 5.5 (1/3)tCYC +0.05 µs Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tP1H(1) tP1L(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27), INT6(P20), INT7(P24)
  • Interrupt source flag can be set.
  • Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
  • Interrupt source flag can be set.
  • Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tCYC High/low level pulse width tPIL(5) RES Resetting is enabled. 2.7 to 5.5 200 µs AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.5 to 5.5 15.68 (tCYC= 0.49µs) 97.92 (tCYC= 3.06µs) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) 3.0 to 5.5 23.52 (tCYC= 0.735µs) 97.92 (tCYC= 3.06µs) 4.5 to 5.5 18.82 (tCYC= 0. 294µs) 97.92 (tCYC= 1.53µs) Conversion time TCAD AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 3.0 to 5.5 47.04 (tCYC= 0. 735µs) 97.92 (tCYC= 1.53µs) µs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1 Analog port input current IAINL AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 µA Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.

No.A0477-22/29 Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDOP(1) 4.5 to 5.5 9.9 24 IDDOP(2)

  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal RC oscillation stopped
  • 1/1 frequency division ration 3.0 to 3.6 5.6 14 IDDOP(3) 4.5 to 5.5 13 32 IDDOP(4)
  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation mode
  • Internal RC oscillation stopped
  • 1/1 frequency division ration 3.0 to 3.6 7.3 18 IDDOP(5) 4.5 to 5.5 6.4 15 IDDOP(6) 3.0 to 3.6 3.7 8.7 IDDOP(7)
  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ration 2.7 to 3.0 3.0 6.7 IDDOP(8) 4.5 to 5.5 0.67 3.2 IDDOP(9) 3.0 to 3.6 0.35 1.6 IDDOP(10)
  • FmCF=0MHz (oscillation stopped)
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation
  • 1/2 frequency division ration 2.7 to 3.0 0.30 1.3 mA IDDOP(11) 4.5 to 5.5 41 160 IDDOP(12) 3.0 to 3.6 17 60 Normal mode consumption current (Note 7-1) IDDOP(13) VDD1 =VDD2 =VDD3
  • FmCF=0MHz (oscillation stopped)
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ration 2.7 to 3.0 14 43 µA IDDHALT(1) 4.5 to 5.5 4.9 12 IDDHALT(2)
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation stopped
  • Internal RC oscillation stopped
  • 1/1 frequency division ration 3.0 to 3.6 2.7 6.5 IDDHALT(3) 4.5 to 5.5 7.3 18 IDDHALT(4)
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 12MHz side
  • Internal PLL oscillation mode
  • Internal RC oscillation stopped
  • 1/1 frequency division ration 3.0 to 3.6 4.0 9.6 IDDHALT(5) 4.5 to 5.5 3.0 7.2 IDDHALT(6) 3.0 to 3.6 1.6 3.9 HALT mode consumption current (Note 7-1) IDDHALT(7) VDD1 =VDD2 =VDD3
  • HALT mode
  • FmCF=12MHz ceramic oscillation mode
  • FsX’tal=32.768kHz crystal oscillation mode
  • System clock set to 6MHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ration 2.7 to 3.0 1.3 3.0 mA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A0477-23/29 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDHALT(8) 4.5 to 5.5 0.37 1.8 IDDHALT(9) 3.0 to 3.6 0.18 0.83 IDDHALT(10)

  • HALT mode
  • FmCF=0MHz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to internal RC oscillation
  • 1/2 frequency division ration 2.7 to 3.0 0.15 0.62 mA IDDHALT(11) 4.5 to 5.5 26 110 IDDHALT(12) 3.0 to 3.6 8.2 33 HALT mode consumption current (Note 7-1) IDDHALT(13) VDD1 =VDD2 =VDD3
  • HALT mode
  • FmCF=0MHz (oscillation stopped)
  • FsX'tal=32.768kHz crystal oscillation mode
  • System clock set to 32.768kHz side
  • Internal RC oscillation stopped
  • 1/2 frequency division ration 2.7 to 3.0 5.8 22 IDDHOLD(1) 4.5 to 5.5 0.14 24 IDDHOLD(2) 3.0 to 3.6 0.04 15 HOLD mode consumption current IDDHOLD(3) VDD1 HOLD mode
  • CF1=VDD or open (External clock mode) 2.7 to 3.0 0.03 12 IDDHOLD(4) 4.5 to 5.5 21 90 IDDHOLD(5) 3.0 to 3.6 5.1 24 Timer HOLD mode consumption current IDDHOLD(6) VDD1 Timer HOLD mode
  • CF1=VDD or open (External clock mode)
  • FsX’tal=32.768kHz crystal oscillation mode 2.7 to 3.0 3.3 14 µA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta = 0°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Conditions min typ max unit High level output V OH(USB) • 15k Ω±5% to GND 2.8 3.6 V Low level output V OL(USB) • 1.5k Ω±5% to 3.6 V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • |(D+)-(D-)| 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R • R S=27 to 33Ω,CL=50pF
  • VDD3=3.0 to 3.6V 4 20 ns USB data fall time t F • R S=27 to 33Ω,CL=50pF
  • VDD3=3.0 to 3.6V 4 20 ns F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2= VSS3 =0V Specification Parameter Symbol Pin Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • 128-byte programming
  • Erasing current included 3.0 to 5.5 25 40 mA Programming time tFW(1) • 128-byte programming
  • Erasing current included
  • Time for setting up 128-byte data is excluded. 3.0 to 5.5 22.5 45 ms

No.A0477-25/29 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Time Operating VDD lower limit Power Supply RES Internal RC oscillation CF oscillation (XT1, XT2) Crystal oscillation (XT1, XT2) Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD GND Internal RC oscillation CF oscillation (XT1, XT2) Crystal Oscillation (XT1, XT2) Operating mode HOLD reset signal HOLD reset signal valid tmsCF tmsX’tal HOLD HALT

No.A0477-29/29 PS This catalog provides information as of December, 2006. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO Semiconductor pr oducts described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify s ymptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high- quality high-reliability products. However, any and all semiconductor products fail with some probabi lity. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property . When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor produc ts (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording , or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circui t parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semicondu ctor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.