LC87F1964A

LC87F1964A SANYO | Alldatasheet

Document overview

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Technical content

Features

Flash ROM

Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
Block-erasable in 128-byte units
Writable in 2-byte units
65536 × 8 bits RAM
5120 × 9 bits Minimum Bus Cycle
83.3ns (CF=12MHz) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time
250ns (CF=12MHz) CMOS IC FROM 64K byte, RAM 5K byte on-chip 8-bit 1-chip Microcontroller With USB-host Controller * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No.A0496-2/28 Ports

I/O ports Ports whose I/O direction can be designated in 1 bit units 28 (P10 to P17, P20 to P27, P30 to P34, P70 to P73, PWM0, PWM1, XT2) Ports whose I/O direction can be designated in 4 bit units 8 (P00 to P07)
USB ports 2 (UHD+, UHD −)
Dedicated oscillator ports 2 (CF1, CF2)
Input-only port (also used for oscillation) 1 (XT1)
Reset pins 1 ( RES)
Power pins 6 (V SS1 to 3, VDD1 to 3) Timers
Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an-8bit prescaler × 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes SIO
SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 512/3 tCYC 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units)
SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
SIO4: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1-byte units, suspension and resumption of data transmission possible in 1-byte or 2-bytes units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Continued on next page.

No.A0496-3/28 Continued from preceding page.

SIO9: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Transfer clock cycle: 4/3 to 1020/3 tCYC 3) Automatic continuous data transmission (1 to 4096 bytes, specifiable in 1-byte units, suspension and resumption of data transmission possible in 1-byte or 2-bytes units) 4) Auto-start-on-falling-edge function 5) Clock polarity selectable 6) CRC16 calculator circuit built in Full duplex UART
UART1 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC AD Converter : 8 bits × 12 channels PWM: Multifrequency 12-bit PWM × 2 channels USB interface (host controller)
Full-Speed is supported
Transfer type: Control, Bulk, Interrupt, or Isochronous transfer possible Watchdog Timer
External RC watchdog timer
Interrupt and reset signals selectable Clock Output Function
Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
Able to output oscillation clock of sub clock. Interrupts
32 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/ INT4/UHC bus active 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H/UHC device attach/UHC device detach/UHC resume 6 0002BH H or L T1L/T1H/SIO9 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/SIO4/UART1 transmit 9 00043H H or L ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL 10 0004BH H or L Port 0/PWM0/PWM1/UHC-SOF
Priority levels X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence.

No.A0496-4/28 Subroutine Stack Levels : 2560 levels (the stack is allocated in RAM) High-speed Multiplication/Division Instructions

16 bits × 8 bits (5 tCYC execution time)
24 bits × 16 bits (12 tCYC execution time)
16 bits ÷ 8 bits (8 tCYC execution time)
24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits
RC oscillation circuit (internal): For system clock
CF oscillation circuit: For system clock, USB interface
Crystal oscillation circuit: For system clock, time-of-day clock
PLL circuit (internal): For USB interface (see Fig.5) Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB host controller circuit
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB host controller circuit Package Form
SQFP48(7×7): Lead-free type
QIP48E(14×14): Lead-free type Development Tools
On-chip debugger: TCB87 type-B + LC87F1964A Flash ROM programming boards Package Programming boards QIP48E(14×14) W87F55256Q SQFP48(7×7) W87F55256SQ Recommended EPROM programmer Maker Model Supported version Device Flash Support Group, Inc. (Single) AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) After Rev02.65 LC87F1964A SANYO SKK (SANYO FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F1964

No.A0496-5/28 Package Dimensions unit : mm (typ) 3163B Package Dimensions unit : mm (typ) 3156A SANYO : QIP48E(14X14) 14.0 17.2 14.0 17.2 0.150.35 0.8 1.0 (1.5) 1 12 2536 48(2.7) 3.0max 0.1 SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536

No.A0496-6/28 Pin Assignments SANYO: SQFP48(7×7) “Lead-free Type” SANYO: QIP48E(14×14) “Lead-free Type” Top view P27/INT5/SCK9 P26/INT5/SI9/WR9 P25/INT5/SO9/RD9 P24/INT5/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4 P20/INT4 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4/DBGP2 P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 25UHD- UHD+ VDD3 VSS3 P34/UFILT P33 P32 P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 LC87F1964A

No.A0496-7/28 SQFP48/QIP48 NAME SQFP48/QIP48 NAME

1 P73/INT3/T0IN 25 P04/AN4/DBGP2

2 RES 26 P05/AN5/CKO

3 XT1/AN10 27 P06/AN6/T6O

4 XT2/AN11 28 P07/AN7/T7O

5 V SS1 29 P20/INT4

6 CF1 30 P21/INT4

7 CF2 31 P22/INT4/SO4/ RD

8 V DD1 32 P23/INT4/SI4/ WR

9 P10/SO0 33 P24/INT5/SCK4

10 P11/SI0/SB0 34 P25/INT5/SO9/ RD9

11 P12/SCK0 35 P26/INT5/SI9/ WR9

12 P13/SO1 36 P27/INT5/SCK9

13 P14/SI1/SB1 37 UHD-

14 P15/SCK1 38 UHD+

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1 41 P34/UFILT

18 PWM0 42 P33

19 V DD2 43 P32

20 V SS2 44 P31/URX1

21 P00/AN0 45 P30/UTX1

22 P01/AN1 46 P70/INT0/T0LCP/AN8

23 P02/AN2/DBGP0 47 P71/INT1/T0HCP/AN9

24 P03/AN3/DBGP1

48 P72/INT2/T0IN

No.A0496-8/28 System Block Diagram Interrupt control FROM Standby control Clock generator CF X’tal RC IR PLA PC Bus interface Port 0 Port 1 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Base timer PWM1 INT0 to 5 Noise filter SIO0 Port 2 USB PLL Port 7 Port 3 ADC SIO1 Timer 0 Timer 1 PWM0 Timer 6 Timer 7 UART1 SIO4 On-chip debugger USB host SIO9

No.A0496-9/28 Pin Description Pin Name I/O Description Option VSS1, VSS2, VSS3 -power supply pin No VDD1, VDD2 +power supply pin No VDD3 USB reference voltage pin Yes Port 0 P00 to P07 I/O • 8-bit I/O port

I/O specifiable in 4-bit units
Pull-up resistors can be turned on and off in 4-bit units.
HOLD reset input
Port 0 interrupt input
Pins functions AD converter input port: AN0 to AN7 (P00 to P07) On-chip debugger pins: DBGP0 to DBGP2 (P02 to P04) P05: System Clock Output P06: Timer 6 toggle outputs P07: Timer 7 toggle outputs Yes Port 1 P10 to P17 I/O • 8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output/beeper output Yes Port 2 • 8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P20 to P23: INT4 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/ timer 0L capture input/ timer 0H capture input P22: SIO4 date I/O/parallel interface RD output P23: SIO4 date I/O/parallel interface WR output P24: SIO4 clock I/O P25: SIO9 date I/O/parallel interface RD9 output P26: SIO9 date I/O/parallel interface WR9 output P27: SIO9 clock I/O Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT4 enable enable enable disable disable INT5 enable enable enable disable disable P20 to P27 I/O Yes Continued on next page.

No.A0496-10/28 Continued from preceding page. Pin Name I/O Description Option Port 3 P30 to P34 I/O • 5-bit I/O port

I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P30: UART1 transmit P31: UART1 receive P34: USB interface PLL filter pin (see Fig.5) Yes Port 7 • 4-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units.
Pin functions P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/ High speed clock counter input P73: INT3 input (with noise filter) /timer 0 event input/ timer 0H capture input AD converter input port: AN8(P70), AN9(P71)Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable P70 to P73 I/O No PWM0 PWM1 I/O • PWM0 and PWM1 output port
General-purpose input port No UHD- I/O • USB data I/O pin UHD-
General-purpose I/O port No UHD+ I/O • USB data I/O pin UHD +
General-purpose I/O port No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin
Pin functions General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used. No XT2 I/O • 32.768kHz crystal oscillator output pin
Pin functions General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used. No CF1 Input Ceramic resonator input pin No CF2 Output Ceramic resonator output pin No

No.A0496-11/28 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type Output type Pull-up resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No UHD+, UHD- - No CMOS No XT1 - No Input only No XT2 - No 32.768kHz crystal oscillator output No Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07). Power Pin Treatment Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. Example 1: When the microcontroller is in the backup state in the HOLD mode, the power to sustain the high level of output ports is supplied by their backup capacitors. Example 2: The high level output at ports is not sustained and unstable in the HOLD backup mode. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply For backup LSI LSI VSS1 VSS2V SS3 VDD1 VDD2 VDD3 Power supply For backup

No.A0496-12/28 USB Reference Power Option When a voltage 4.5 to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the reference voltage for USB port output is generated. The active/inactive state of the reference voltage circuit can be switched by option selection. The procedure for marking the option selection is described below. (1) (2) (3) (4) USB Regulator USE USE USE NONUSE USB Regulator in HOLD mode USE NONUSE NONUSE NONUSE Option selection USB Regulator in HALT mode USE NONUSE USE NONUSE Normal state active active active inactive HOLD mode active inactive inactive inactive Reference voltage circuit state HALT mode active inactive active inactive

When the USB reference voltage circuit is made inactive, the level of the reference voltage for USB port output is equal to VDD1.
Selection (2) or (3) can be used to set the reference voltage circuit inactive in HOLD or HALT mode.
When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared with when the reference voltage circuit is inactive. Example 1: VDD1=VDD2=3.3V
Inactivating the reference voltage circuit (selection (4)).
Connecting VDD3 to VDD1 and VDD2. Example 2: VDD1=VDD2=5.0V
Activating the reference voltage circuit (selection (1)).
Isolating VDD3 from VDD1 and VDD2, and connecting capacitor between VDD3 and VSS. VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power supply 3.3V For backup LSI UHD+ UHD- UFILT 15kΩ To USB connector 33Ω 5pF VSS1 VSS2 V SS3 VDD1 VDD2 VDD3 Power supply For backup LSI UHD+ UHD- UFILT 2.2µF 15kΩ To USB connector 33Ω 5pF 2.2µF 0.1µF

No.A0496-13/28 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 VDD1=VDD2=VDD3 -0.3 +6.5 Input voltage V I(1) XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2, 3, 7 PWM0, PWM1 XT2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2 • When CMOS output type is selected

Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 Per 1 applicable pin -20 Peak output current IOPH(3) Ports 3 P71 to P73
When CMOS output type is selected
Per 1 applicable pin IOMH(1) Ports 0, 1, 2 • When CMOS output type is selected
Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 Average output current (Note 1-1) IOMH(3) Ports 3 P71 to P73
When CMOS output type is selected
Per 1 applicable pin ΣIOAH(1) Ports 0, 2 Total of all applicable pins -25 ΣIOAH(2) Ports 1 PWM0, PWM1 Total of all applicable pins -25 ΣIOAH(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins -45 ΣIOAH(4) Ports 3 P71 to P73 Total of all applicable pins -10 High level output current Total output current ΣIOAH(5) UHD+, UHD- Total of all applicable pins -25 IOPL(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOPL(2) P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Ports 3, 7 XT2 Per 1 applicable pin 10 IOML(1) P02 to P07 Ports 1, 2 PWM0, PWM1 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 Average output current (Note 1-1) IOML(3) Ports 3, 7 XT2 Per 1 applicable pin 7.5 ΣIOAL(1) Ports 0, 2 Total of all applicable pins 45 ΣIOAL(2) Ports 1 PWM0, PWM1 Total of all applicable pins 45 ΣIOAL(3) Ports 0, 1, 2 PWM0, PWM1 Total of all applicable pins 80 ΣIOAL(4) Ports 3, 7 XT2 Total of all applicable pins 15 Low level output current Total output current ΣIOAL(5) UHD+, UHD- Total of all applicable pins 25 mA QIP48E(14×14) 400Allowable power Dissipation Pd max SQFP48(7×7) Ta=-30 to +70°C 190 mW Operating ambient Temperature Topr -30 +70 Storage ambient temperature Tstg -55 +125 Note 1-1: The mean output current is a mean value measured over 100ms.

No.A0496-14/28 Allowable Operating Range at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit 0.245µs ≤tCYC ≤ 200µs 3.0 5.5Operating supply voltage (Note2-1) VDD(1) V DD1=VDD2=VDD3 0.490µs ≤ tCYC ≤ 200µs Except for onboard programming 2.7 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 VIH(1) Port 0, 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.7 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 70 watchdog timer side 2.7 to 5.5 0.9V DD V DD High level input voltage VIH(3) XT1, XT2, CF1, RES 2.7 to 5.5 0.75VDD V DD VIL(1) 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) Port 1, 2, 3 P71 to P73 P70 port input/ interrupt side 2.7 to 4.0 V SS 0.2V DD VIL(3) 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(4) Port 0 PWM0, PWM1 2.7 to 4.0 V SS 0.2V DD VIL(5) Port 70 watchdog timer side 2.7 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(6) XT1, XT2, CF1, RES 2.7 to 5.5 V SS 0.25V DD V 3.0 to 5.5 0.245 200Instruction cycle time (Note 2-2) tCYC Except for onboard programming 2.7 to 5.5 0.490 200 µs

CF2 pin open
System clock frequency division ratio=1/1
External system clock duty= 50±5% 3.0 to 5.5 0.1 12 External system clock frequency FEXCF(1) CF1
CF2 pin open
System clock frequency division ratio=1/1
External system clock duty= 50±5% 2.7 to 5.5 0.1 6 MHz FmCF(1) CF1, CF2 12MHz ceramic oscillation See Fig. 1. 3.0 to 5.5 12 FmCF(2) CF1, CF2 6MHz ceramic oscillation See Fig. 1. 2.7 to 5.5 6 MHz Oscillation frequency range (Note 2-3) FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-3: See Tables 1 and 2 for the oscillation constants.

No.A0496-15/28 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.7 to 5.5 1 IIH(2) XT1, XT2 For input port specification VIN=VDD 2.7 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 2.7 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 UHD+, UHD- Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.7 to 5.5 -1 IIL(2) XT1, XT2 For input port specification VIN=VSS 2.7 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 2.7 to 5.5 -15 µA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(3) Ports 0, 1, 2, 3 P71 to P73 IOH=-0.2mA 2.7 to 5.5 VDD-0.4 VOH(4) I OH=-10mA 4.5 to 5.5 VDD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 VDD-0.4 High level output voltage VOH(6) PWM0, PWM1 P05 (CK0 when using system clock output function) IOH=-1mA 2.7 to 5.5 VDD-0.4 VOL(1) I OL=30mA 4.5 to 5.5 1.5 VOL(2) I OL=5mA 3.0 to 5.5 0.4 VOL(3) P00, P01 IOL=2.5mA 2.7 to 5.5 0.4 VOL(4) I OL=10mA 4.5 to 5.5 1.5 VOL(5) I OL=1.6mA 3.0 to 5.5 0.4 VOL(6) Ports 0, 1, 2 PWM0, PWM1 XT2 IOL=1mA 2.7 to 5.5 0.4 VOL(7) I OL=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(8) Ports 3, 7 IOL=1mA 2.7 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80Pull-up resistance Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 2.7 to 5.5 18 50 150 kΩ Hysteresis voltage VHYS RES Port 1, 2, 3, 7 2.7 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.7 to 5.5 10 pF

No.A0496-16/28 Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) 2 Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 8. tSCKHA(1a) • Continuous data transmission/reception mode

USB, SIO4 nor SIO9 are not in use simultaneous.
See Fig. 8.
(Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode
USB is in use simultaneous.
SIO4 nor SIO9 are not in use simultaneous.
See Fig. 8.
(Note 4-1-2) Input clock High level pulse width tSCKHA(1c) SCK0(P12)
Continuous data transmission/reception mode
USB, SIO4 and SIO9 are in use simultaneous.
See Fig. 8.
(Note 4-1-2) 2.7 to 5.5 Frequency tSCK(2) 4/3 tCYC Low level pulse width tSCKL(2) 1/2 tSCKH(2)
CMOS output selected
See Fig. 8. tSCK tSCKHA(2a) • Continuous data transmission/reception mode
USB, SIO4 nor SIO9 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCKHA(2b) • Continuous data transmission/reception mode
USB is in use simultaneous.
SIO4 nor SIO9 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC Serial clock Output clock High level pulse width tSCKHA(2c) SCK0(P12)
Continuous data transmission/reception mode
USB, SIO4 and SIO9 are in use simultaneous.
CMOS output selected
See Fig. 8. 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC tCYC Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0496-17/28 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Data setup time tsDI(1) 2.7 to 5.5 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)

Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 tdD0(1)
Continuous data transmission/reception mode
(Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 Input clock tdD0(2)
Synchronous 8-bit mode
(Note 4-1-3) 2.7 to 5.5 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 8. 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) 2 Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig. 8. 2.7 to 5.5 Frequency tSCK(4) 2 tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected
See Fig. 8. 2.7 to 5.5 tSCK Data setup time tsDI(2) 2.7 to 5.5 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A0496-18/28 3. SIO4 Serial I/O Characteristics (Note 4-3-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(5) 2 Low level pulse width tSCKL(5) 1 tSCKH(5) See Fig. 8. tSCKHA(5a) • USB, SIO9 nor continuous data transmission/eception mode of SIO0 are not in use simultaneous.

See Fig. 8.
(Note 4-3-2) tSCKHA(5b) • USB is in use simultaneous.
SIO9 nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
See Fig. 8.
(Note 4-3-2) Input clock High level pulse width tSCKHA(5c) SCK4(P24)
USB, SIO9 and continuous data transmission/eception mode of SIO0 are in use simultaneous.
See Fig. 8.
(Note 4-3-2) 2.7 to 5.5 Frequency tSCK(6) 4/3 tCYC Low level pulse width tSCKL(6) tSCKH(6)
CMOS output selected
See Fig. 8. tSCK tSCKHA(6a) • USB, SIO9 nor continuous data transmission/eception mode of SIO0 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tSCKHA(6b) • USB is in use simultaneous.
SIO9 nor continuous data transmission/eception mode of SIO0 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC Serial clock Output clock High level pulse width tSCKHA(6c) SCK4(P24)
USB, SIO9 and continuous data transmission/eception mode of SIO0 are in use simultaneous.
CMOS output selected
See Fig. 8. 2.7 to 5.5 tSCKH(6) +(5/3) tCYC tSCKH(6) +(34/3) tCYC tCYC Data setup time tsDI(3) 2.7 to 5.5 0.03 Serial input Data hold time thDI(3) SO4(P22), SI4(P23)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 µs Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input in continuous trans/rec mode, a time from SI4RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0496-19/28 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Serial output Output delay time tdD0(5) SO4(P22), SI4(P23)

Must be specified with respect to rising edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 µs 4. SIO9 Serial I/O Characteristics (Note 4-4-1) Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(7) 2 Low level pulse width tSCKL(7) 1 tSCKH(7) See Fig. 8. tSCKHA(7a) • USB, SIO4 nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
See Fig. 8.
(Note 4-4-2) tSCKHA(7b) • USB is in use simultaneous.
SIO4 nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
See Fig. 8.
(Note 4-4-2) Serial clock Input clock High level pulse width tSCKHA(7c) SCK9(P27)
USB, SIO4 and continuous data transmission/reception mode of SIO0 are in use simultaneous.
See Fig. 8.
(Note 4-4-2) 2.7 to 5.5 tCYC Note 4-4-1: These specifications are theoretical values. Add margin depending on its use. Note 4-4-2: To use serial-clock-input in continuous trans/rec mode, a time from SI9RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Continued on next page.

No.A0496-20/28 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit Frequency tSCK(8) 4/3 tCYC Low level pulse width tSCKL(8) tSCKH(8)

CMOS output selected
See Fig. 8. tSCK tSCKHA(8a) • USB, SIO4 nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(8) +(5/3) tCYC tSCKH(8) +(10/3) tCYC tSCKHA(8b) • USB is in use simultaneous.
SIO4 nor continuous data transmission/reception mode of SIO0 are not in use simultaneous.
CMOS output selected
See Fig. 8. tSCKH(8) +(5/3) tCYC tSCKH(8) +(19/3) tCYC Serial clock Output clock High level pulse width tSCKHA(8c) SCK9(P27)
USB, SIO4 and continuous data transmission/reception mode of SIO0 are in use simultaneous.
CMOS output selected
See Fig. 8. 2.7 to 5.5 tSCKH(8) +(5/3) tCYC tSCKH(8) +(37/3) tCYC tCYC Data setup time tsDI(4) 2.7 to 5.5 0.03 Serial input Data hold time thDI(4) SO9(P25), SI9(P26)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 8. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(6) SO9(P25), SI9(P26)
Must be specified with respect to rising edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 8. 2.7 to 5.5 (1/3)tCYC +0.05 µs

No.A0496-21/28 Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tP1H(1) tP1L(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27)

Interrupt source flag can be set.
Event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.7 to 5.5 256 tCYC High/low level pulse width tPIL(5) RES Resetting is enabled. 2.7 to 5.5 200 µs AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.5 to 5.5 15.68 (tCYC= 0.49µs) 97.92 (tCYC= 3.06µs) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) 3.0 to 5.5 23.52 (tCYC= 0.735µs) 97.92 (tCYC= 3.06µs) 4.5 to 5.5 18.82 (tCYC= 0. 294µs) 97.92 (tCYC= 1.53µs) Conversion time TCAD AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) 3.0 to 5.5 47.04 (tCYC= 0. 735µs) 97.92 (tCYC= 1.53µs) µs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 µA Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.

No.A0496-22/28 Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDOP(1) 4.5 to 5.5 9.3 23 IDDOP(2)

FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 12MHzside
Internal PLL oscillation stopped
Internal RC oscillation stopped
1/1 frequency division ration 3.0 to 3.6 5.3 13 IDDOP(3) 4.5 to 5.5 12 28 IDDOP(4)
FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation mode
Internal RC oscillation stopped
1/1 frequency division ration 3.0 to 3.6 6.4 16 IDDOP(5) 4.5 to 5.5 6.1 15 IDDOP(6) 3.0 to 3.6 3.5 8.2 IDDOP(7)
FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 6MHz side
Internal RC oscillation stopped
1/2 frequency division ration 2.7 to 3.0 2.9 6.4 IDDOP(8) 4.5 to 5.5 0.68 3.3 IDDOP(9) 3.0 to 3.6 0.36 1.6 IDDOP(10)
FmCF=0MHz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation
1/2 frequency division ration 2.7 to 3.0 0.30 1.2 mA IDDOP(11) 4.5 to 5.5 40 160 IDDOP(12) 3.0 to 3.6 17 64 Normal mode consumption current (Note 7-1) IDDOP(13)
FmCF=0MHz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal RC oscillation stopped
1/2 frequency division ration 2.7 to 3.0 13 46 µA IDDHALT(1) 4.5 to 5.5 4.2 10 IDDHALT(2)
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation stopped
Internal RC oscillation stopped
1/1 frequency division ration 3.0 to 3.6 2.3 5.5 IDDHALT(3) 4.5 to 5.5 6.1 15 IDDHALT(4)
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 12MHz side
Internal PLL oscillation mode
Internal RC oscillation stopped
1/1 frequency division ration 3.0 to 3.6 3.3 7.9 IDDHALT(5) 4.5 to 5.5 2.6 6.4 IDDHALT(6) 3.0 to 3.6 1.4 3.3 HALT mode consumption current (Note 7-1) IDDHALT(7) VDD1 =VDD2 =VDD3
HALT mode
FmCF=12MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 6MHz side
Internal RC oscillation stopped
1/2 frequency division ration 2.7 to 3.0 1.2 2.6 mA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A0496-23/28 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDHALT(8) 4.5 to 5.5 0.37 1.8 IDDHALT(9) 3.0 to 3.6 0.18 0.84 IDDHALT(10)

HALT mode
FmCF=0MHz (oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation
1/2 frequency division ration 2.7 to 3.0 0.15 0.63 mA IDDHALT(11) 4.5 to 5.5 25 102 IDDHALT(12) 3.0 to 3.6 7.6 32 HALT mode consumption current (Note 7-1) IDDHALT(13) VDD1 =VDD2 =VDD3
HALT mode
FmCF=0MHz (oscillation stopped)
FsX'tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal RC oscillation stopped
1/2 frequency division ration 2.7 to 3.0 5.4 20 IDDHOLD(1) 4.5 to 5.5 0.10 24 IDDHOLD(2) 3.0 to 3.6 0.04 15 HOLD mode consumption current IDDHOLD(3) HOLD mode
CF1=VDD or open (External clock mode) 2.7 to 3.0 0.03 12 IDDHOLD(4) 4.5 to 5.5 21 88 IDDHOLD(5) 3.0 to 3.6 5.0 23 Timer HOLD mode consumption current IDDHOLD(6) VDD1 Timer HOLD mode
CF1=VDD or open (External clock mode)
FsX’tal=32.768kHz crystal oscillation mode 2.7 to 3.0 3.2 14 µA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. USB Characteristics and Timing at Ta=0 to +70°C, VSS1=VSS2=VSS3=0V Specification Parameter Symbol Conditions min typ max unit High level output V OH(USB) • 15 k Ω±5% to GND 2.8 3.6 V Low level output V OL(USB) • 1.5 k Ω±5% to 3.6 V 0.0 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • |(UHD+)-(UHD-)| 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R • R S=33Ω,CL=50pF 4 20 ns USB data fall time t F • R S=33Ω,CL=50pF 4 20 ns F-ROM Programming Characteristics at Ta = -10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • Without CPU current 3.0 to 5.5 5 10 mA tFW(1) • Erasing 20 30 ms Programming time tFW(2)
Programming 3.0 to 5.5 40 60 µs

No.A0496-25/28 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times Internal RC oscillation CF oscillation (XT1, XT2) Crystal Oscillation (XT1, XT2) State HOLD reset signal HOLD reset signal absen HOLD reset signal valid tmsCF tmsX’tal HOLD HALT Power supply RES Internal RC oscillation CF oscillation (XT1, XT2) Crystal oscillation (XT1, XT2) State Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD Operating VDD lower limit GND

No.A0496-28/28 PS This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qu ality high-reliability pr oducts, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damag e to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor Co .,Ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd.

Summary

CMOS IC FROM 64K byte, RAM 5K byte on-chip 8-bit 1-chip Microcontroller With USB-host Controller

Description