LC87F1364A

LC87F1364A SANYO | Alldatasheet

Document overview

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Technical content

Features

„Flash ROM

• Block-erasable in 128-byte units
• 65536 × 8 bits „Minimum Bus Cycle Time
• 166ns (CF = 6MHz) Note: The bus cycle time here refers to the ROM read speed. „Minimum Instruction Cycle Time (tCYC)
• 500ns (CF = 6MHz) CMOS IC FROM 64K byte, RAM 1K byte on-chip 8-bit 1-chip Microcontroller with Low-speed USB * This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by SANYO Semiconductor Co., Ltd. Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No.A0137-2/22 „Ports

• I/O ports Ports whose I/O direction can be designated in 1 bit units 9 (P1n, P70) Ports whose I/O direction can be designated in 4 bit units 8 (P0n)
• USB ports 2 (D+, D-)
• Dedicated oscillator ports 2 (XT1, XT2)
• Reset pins 1 ( RES)
• Power pins 1 (V SS1, VDD1) „Timers
• Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture registers) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer that supports PWM/toggle output capabilities) Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) × 2 channels Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer with an 8-bit prescaler (with toggle output) (The lower-order 8 bits can be used as a timer with toggle output.) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (The lower-order 8 bits can be used as PWM.)
• Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler
• Timer 7: 8-bit timer with a 6-bit prescaler „SIO
• SIO0: Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3tCYC) 3) Automatic continuous data transmission (1 to 256 bits)
• SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) „Full Duplex UART
• UART1 1) Data length: 7/8/9 bits selectable 2) Stop bits: 1 bit (2 bits in continuous transmission mode) 3) Baud rate: 16/3 to 8192/3 tCYC „AD Converter: 8 bits × 9 channels „PWM: Multifrequency 12-bit PWM × 2 channels

No.A0137-3/22 „USB Controller

• USB Specification rev. 1.1 (Low-Speed) compatible
• Supports a maximum of 2 user-defined endpoints. Endpoint EP0 EP1 EP2 Control enable enable - Transfer Type Interrupt - enable enable Max. payload 8 8 8 „Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable „Interrupts
• 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/USB bus active 4 0001BH H or L INT3/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/USB bus re set/USB suspend/UART1 receive 8 0003BH H or L SIO1/USBERR/USBPOV/USBEN P/USBNAK/ USBSTL/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/PWM0/PWM1/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence. „Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.) „High-speed Multiplication/Division Instructions
• 16 bits × 8 bits (5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits (8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time) „Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit: For system clock, USB interface
• Crystal oscillation circuit: For system clock, time-of-day clock
• PLL circuit (internal): For system clock, USB interface

No.A0137-4/22 „Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The PLL base clock generator, CF, RC and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an bus active interrupt source established in the USB interface circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The PLL base clock generator, CF and RC oscillator automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an bus active interrupt source established in the USB interface circuit „Package Form
• MFP24S(300mil): Lead-free type „Development Tools
• On-chip debugger: TCB87 type-A or TCB87 type-B + LC87F1364A „Flash ROM Programming Boards Package Programming boards MFP24S(300mil) W87F5300M „Recommended EPROM Programmer Maker Model Supported version Device Flash Support Group, Inc. (Single) AF9708/AF9709/AF9709B (including product of Ando Electric Co.,Ltd) After 02.40 LC87F1364A SANYO SKK(SANYO FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F1364

No.A0137-5/22 Package Dimensions unit : mm (typ) 3112B Pin Assignment P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P70/INT0/T0LCP/AN8/DPUP RES P17/FILT VSS1 XT1/CF1 XT2/CF2 VDD1 P04/AN4/DBGP2 P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1/URX1 P00/AN0/UTX1 P16/PWM1 P15/SCK1/INT3/T0IN/PWM0 P14/SI1/SB1/INT2/T0IN P13/SO1/INT1/T0HCP P12/SCK0 P11/SI0/SB0 P10/SO0 MFP24S Top view SANYO : MFP24S(300mil) 1 12 1324 12.5 0.63 7.6 5.4 0.151.0 0.35 (0.75) 1.7max 0.1 (1.5)

No.A0137-6/22 MFP NAME

1 P05/AN5/CKO

2 P06/AN6/T6O

3 P07/AN7/T7O

4 P70/INT0/T0LCP/AN8/DPUP

7 RES

8 P17/FILT

9 V SS1

10 XT1/CF1

11 XT2/CF2

12 V DD1

13 P10/SO0

14 P11/SI0/SB0

15 P12/SCK0

16 P13/SO1/INT1/T0HCP

17 P14/SI1/SB1/INT2/T0IN

18 P15/SCK1/INT3/T0IN/PWM0

19 P16/PWM1

20 P00/AN0/UTX1

21 P01/AN1/URX1

22 P02/AN2/DBGP0

23 P03/AN3/DBGP1

24 P04/AN4/DBGP2

No.A0137-7/22 System Block Diagram Interrupt control Flash-ROM Standby control Clock generator RC CF/X’tal PLL IR PLA PC Timer 7 Bus interface Port 0 Port 1 Port 7 ACC B register C register ALU PSW RAR RAM Stack pointer Watchdog timer Timer 4 PWM0 INT0 to 3 Noise rejection filter SIO0 UART1 ADC SIO1 Timer 0 Timer 1 Timer 5 Timer 6 Base timer PWM1 USB interface On-Chip-Debugger

No.A0137-8/22 Pin Description Pin Name I/O Description Option VSS1 - - power supply pin No VDD1 - + power supply pin No Port 0 P00 to P07 I/O • 8-bit I/O port

• I/O specifiable in 4 bit units
• Pull-up resistors can be turned on and off in 4 bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions P00: AN0 (ADC input)/UART1 transmit P01: AN1 (ADC input)/UART1 receive P02: AN2 (ADC input)/For On-Chip-Debugger P03: AN3 (ADC input)/For On-Chip-Debugger P04: AN4 (ADC input)/For On-Chip-Debugger P05: AN5 (ADC input)/System Clock Output P06: AN6 (ADC input)/timer 6 toggle outputs P07: AN7 (ADC input)/timer 7 toggle outputs Yes Port 1 P10 to P17 I/O • 8-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output/INT1 input/HOLD reset input/timer OH capture input P14: SIO1 data input/bus I/O/INT2 input/ HOLD reset input/timer 0 event input/timer OL capture input P15: SIO1 clock I/O/INT3 input (with noise filter)/timer 0 event input/timer OH capture input /PWM 0 output P16: Timer 1 PWML output/PWM 1 output P17: Timer 1 PWMH output/beeper output/Internal PLL filter pin Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable Yes Port 7 • 1-bit I/O port
• I/O specifiable in 1 bit units
• Pull-up resistors can be turned on and off in 1 bit units.
• Shared pins P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output/AN8 (ADC input) / D- 1.5kΩ pull-up resistor connect pin Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable P70 I/O No RES I Reset pin No XT1 I Ceramic oscillator input pin/32.768kHz crystal oscillator input pin No XT2 I/O Ceramic oscillator input pin/32.76 8kHz crystal oscillator output pin No D- I/O USB data I/O pin D- No D+ I/O USB data I/O pin D+ No

No.A0137-9/22 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type Output type Pull-up resistor

1 CMOS Programmable (Note 1) P00 to P07 1 bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17 1 bit

2 Nch-open drain Programmable

P70 - No Nch-open drain Programmable XT1 - No Input only No XT2 - No 32.768kHz crystal oscillator output No Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). USB Reference Power Option When a voltage 4.5V to 5.5V is supplied to VDD1 and the internal USB reference voltage circuit is activated, the H output level of the USB Port is 3.0V to 3.6V (the H output level of the ports except the USB Port is the VDD1 voltage level, however). The active/inactive state of the reference voltage circuit can be determined by option settings. According to the voltage to be supplied to VDD1, make option settings as shown below. VDD1 voltage (V) 4.5 to 5.5 3.0 to 3.6 USB Regulator USE USE USE NONUSE USB Regulator in HOLD mode USE NONUSE NONUSE NONUSE Option setting USB Regulator in HALT mode USE NONUSE USE NONUSE Normal state active active active inactive HOLD mode active inactive inactive inactive Reference voltage circuit state HALT mode active inactive active inactive (1) (2) (3) (4)

• When the USB reference voltage circuit is made inactive, the H output level of the USB Port becomes the VDD1 voltage level.
• Use the setting (2) or (3) to make the reference voltage circuit inactive in HOLD or HALT mode.
• When the reference voltage circuit is activated, the current drain increases by approximately 100µA compared with when the reference voltage circuit is inactive.

No.A0137-10/22 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1 V DD1 -0.3 +6.5 Input voltage V I(1) XT1, XT2 -0.3 V DD+0.3 Input/output voltage VIO(1) Ports 0, 1, 7 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1 • When CMOS output type is selected

• Per 1 applicable pin -10 Peak output current IOPH(2) PWM0, PWM1 Per 1 applicable pin -20 IOMH(1) Ports 0, 1 • When CMOS output type is selected
• Per 1 applicable pin -7.5 Average output current (Note 2) IOMH(2) PWM0, PWM1 Per 1 applicable pin -15 High level output current Total output current ΣIOAH(1) Ports 0, 1 PWM0, PWM1 D+, D- Total of all applicable pins -50 IOPL(1) P00 to P05 Ports 1, P70 PWM0, PWM1 Per 1 applicable pin Peak output current IOPL(2) P06, 07 Per 1 applicable pin 30 IOML(1) P00 to P05 Ports 1, P70 PWM0, PWM1 Per 1 applicable pin Average output current (Note 2) IOML(2) P06, 07 Per 1 applicable pin 20 Low level output current Total output current ΣIOAL(1) Ports 0, 1, P70 PWM0, PWM1 D+, D- Total of all applicable pins 75 mA Allowable power Dissipation Pd max MFP24S Ta=-20 to +70 °C mW Operating ambient Temperature Topr -20 +70 Storage ambient temperature Tstg -55 +125 Note 2: The mean output current is a mean value measured over 100ms.

No.A0137-11/22 Allowable Operating Conditions at Ta = -20°C to +70°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit VDD(1) 0.490µs ≤ tCYC ≤ 200µs Except for onboard programming (Note 3) 2.5 5.5Operating supply voltage VDD(2) VDD1 0.490µs ≤ tCYC ≤ 200µs internal PLL oscillation 4.5 5.5 Memory sustaining supply voltage VHD V DD1 RAM and register contents sustained in HOLD mode. 2.0 5.5 VIH(1) Port 1 P70 port input /interrupt side 2.5 to 5.5 0.3VDD +0.7 VDD VIH(2) Port 70 watchdog timer side 2.5 to 5.5 0.9V DD V DD High level input voltage VIH(3) XT1, XT2, RES 2.5 to 5.5 0.75V DD V DD 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(1) Port 1 P70 port input /interrupt side 2.5 to 4.0 V SS 0.2VDD 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(2) Port 0 2.5 to 4.0 V SS 0.2VDD VIL(3) Port 70 watchdog timer side 2.5 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(4) XT1, XT2, RES 2.5 to 5.5 V SS 0.25VDD V Instruction cycle time (Note 4) tCYC 2.5 to 5.5 0.490 200 µs

• XT2 pin open
• System clock frequency division ratio=1/1
• External system clock duty =50±5% 2.5 to 5.5 0.1 6 External system clock frequency FEXCF(1) XT1
• XT2 pin open
• System clock frequency division ratio=1/2 2.5 to 5.5 0.1 12 MHz FmCF XT1, XT2 6MHz ceramic oscillation See Fig. 1. 2.5 to 5.5 6 MHz Oscillation frequency range (Note 5) FsX’tal XT1, XT2 32.768kHz crystal oscillation Note 3: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode. Note 4: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 5: See Tables 1 and 2 for the oscillation constants.

No.A0137-12/22 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1 Port 70 RES Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.5 to 5.5 1 High level input current IIH(2) XT1, XT2 V IN=VDD 2.5 to 5.5 1 IIL(1) Ports 0, 1 Port 70 RES Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.5 to 5.5 -1 Low level input current IIL(2) XT1, XT2 V IN=VSS 2.5 to 5.5 -1 µA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 V DD-0.4 VOH(3) Ports 0, 1 IOH=-0.2mA 2.5 to 5.5 V DD-0.4 VOH(4) I OH=-10mA 4.5 to 5.5 V DD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 V DD-0.4 High level output voltage VOH(6) PWM0, PWM1 P05 (CK0 when using system clock output function) IOH=-1mA 2.5 to 5.5 V DD-0.4 VOL(1) I OL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.6mA 3.0 to 5.5 0.4 VOL(3) Ports 0, 1 Port 70 PWM0, PWM1 IOL=1mA 2.5 to 5.5 0.4 VOL(4) I OL=30mA 4.5 to 5.5 1.5 VOL(5) I OL=5mA 3.0 to 5.5 0.4 Low level output voltage VOL(6) P06, P07 IOL=2.5mA 2.5 to 5.5 0.4 V Rpu(1) 4.5 to 5.5 15 35 80Pull-up resistance Rpu(2) Ports 0, 1 Port 70 VOH=0.9VDD 2.5 to 5.5 18 50 150 kΩ Hysteresis voltage VHYS RES Port 1 Port 70 2.5 to 5.5 0.1VDD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS F=1MHz Ta=25°C 2.5 to 5.5 10 pF

No.A0137-13/22 Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin /Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 6. tSCKHA(1a) • Continuous data transmission/reception mode

• USB is not in use simultaneous.
• See Fig. 6.
• (Note 4-1-2) Input clock High level pulse width tSCKHA(1b) SCK0(P12)
• Continuous data transmission /reception mode
• USB is in use simultaneous.
• See Fig.6.
• (Note 4-1-2) 2.7 to 5.5 Frequency tSCK(2) tCYC Low level pulse width tSCKL(2) tSCKH(2)
• CMOS output selected
• See Fig.6. tSCK tSCKHA(2a) • Continuous data transmission /reception mode
• USB is not in use simultaneous.
• CMOS output selected
• See Fig.6. tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC Serial clock Output clock High level pulse width tSCKHA(2b) SCK0(P12)
• Continuous data transmission /reception mode
• USB is in use simultaneous.
• CMOS output selected
• See Fig.6. 2.7 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC tCYC Data setup time tsDI(1) 2.7 to 5.5 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig.6. 2.7 to 5.5 0.03 tdD0(1) • Continuous data transmission /reception mode
• (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 Input clock tdD0(2) • Synchronous 8-bit mode
• (Note 4-1-3) 2.7 to 5.5 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig.6.

No.A0137-14/22 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin /Remarks CondiPtions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig.6. 2.7 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected

• See Fig.6. 2.7 to 5.5 tSCK Data setup time tsDI(2) 2.7 to 5.5 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig.6. 2.7 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
• Must be specified with respect to falling edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig.6. 2.7 to 5.5 (1/3)tCYC +0.05 µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.A0137-15/22 Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tP1H(1) tP1L(1) INT0(P70), INT1(P13), INT2(P14),

• Interrupt source flag can be set.
• Event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 tPIH(2) tPIL(2) INT3(P15) when noise filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.5 to 5.5 2 tPIH(3) tPIL(3) INT3(P15) when noise filter time constant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.5 to 5.5 64 tPIH(4) tPIL(4) INT3(P15) when noise filter time constant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 2.5 to 5.5 256 tCYC High/low level pulse width tPIL(5) RES Resetting is enabled. 2.5 to 5.5 200 µs AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6) 3.0 to 5.5 ±1.5 LSB 4.5 to 5.5 15.68 (tCYC= 0.49µs) 97.92 (tCYC= 3.06µs) AD conversion time = 32×tCYC (when ADCR2=0) (Note 7) 3.0 to 5.5 31.36 (tCYC= 0.98µs) 97.92 (tCYC= 3.06µs) 4.5 to 5.5 31.36 (tCYC= 0. 49µs) 97.92 (tCYC= 1.53µs) Conversion time TCAD AD conversion time = 64×tCYC (when ADCR2=1) (Note 7) 3.0 to 5.5 31.36 (tCYC= 0. 49µs) 97.92 (tCYC= 1.53µs) µs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07), AN8(P70) VAIN=VSS 3.0 to 5.5 -1 µA Note 6: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. Note 7: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.

No.A0137-16/22 Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = 0V Specification Parameter Symbol Pin /Remarks Conditions VDD[V] min typ Max unit IDDOP(1) 4.5 to 5.5 5.3 13 IDDOP(2)

• FmCF=6MHz ceramic oscillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ration 2.5 to 4.5 3.5 9.6 IDDOP(3) • FsX’tal=32.768kHz crystal oscillation mode
• System clock set to PLL clock side
• Internal RC oscillation stopped
• 1/1 frequency division ration 4.5 to 5.5 6.7 17 IDDOP(4) 4.5 to 5.5 0.67 3.1 IDDOP(5)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Internal PLL oscillation stopped
• 1/2 frequency division ration 2.5 to 4.5 0.43 2.3 mA IDDOP(6) 4.5 to 5.5 120 380 Normal mode consumption current (Note 8) IDDOP(7)
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• Internal PLL oscillation stopped
• 1/2 frequency division ration 2.5 to 4.5 79 290 µA IDDHALT(1) 4.5 to 5.5 2.0 5.4 IDDHALT(2)
• HALT mode
• FmCF=6MHz ceramic scillation mode
• System clock set to 6MHz side
• Internal RC oscillation stopped
• 1/1 frequency division ration 2.5 to 4.5 1.2 3.6 IDDHALT(3) • HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to PLL clock side
• Internal RC oscillation stopped
• 1/1 frequency division ration 4.5 to 5.5 3.6 9.6 IDDHALT(4) 4.5 to 5.5 0.33 1.6 IDDHALT(5)
• HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Internal PLL oscillation stopped
• 1/2 frequency division ration 2.5 to 4.5 0.19 1.1 mA IDDHALT(6) 4.5 to 5.5 30 130 HALT mode consumption current (Note 8) IDDHALT(7)
• HALT mode
• FsX'tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• Internal PLL oscillation stopped
• 1/2 frequency division ration 2.5 to 4.5 12 73 IDDHOLD(1) 4.5 to 5.5 0.04 13HOLD mode consumption current IDDHOLD(2) HOLD mode
• XT1=VDD or open (External clock mode) 2.5 to 4.5 0.02 9.8 IDDHOLD(3) 4.5 to 5.5 27 120Timer HOLD mode consumption current IDDHOLD(4) VDD1 Timer HOLD mode
• FsX’tal=32.768kHz crystal oscillation mode 2.5 to 4.5 9.6 66 µA Note 8: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.

No.A0137-17/22 USB Characteristics and Timing at Ta = -20°C to +70°C, VSS1 = 0V Specification Parameter Symbol Conditions min typ max unit High level output V OH(USB) • 15k Ω±5% to GND 2.8 3.6 V Low level output V OL • 1.5k Ω±5% to 3.6V 0.3 V Output signal crossover voltage V CRS 1.3 2.0 V Differential input sensitivity V DI • ⏐(D+)-(D-)⏐ 0.2 V Differential input common mode range V CM 0.8 2.5 V High level input V IH(USB) 2.0 V Low level input V IL(USB) 0.8 V USB data rise time t R 75 300 ns USB data fall time t F 75 300 ns Rise/fall time t RFM • t R/tF 80 125 % F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = 0V Specification Parameter Symbol Pin Conditions VDD[V] min typ max unit Onboard programming current IDDFW(1) V DD1 • 128-byte programming

• Erasing current included 3.0 to 5.5 25 40 mA Programming time tFW(1) • 128-byte programming
• Erasing current included
• Time for setting up 128-byte data excluded. 3.0 to 5.5 22.5 45 mS

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