LC877680B

LC877696B SANYO | Alldatasheet

Document overview

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Technical content

Features

„ROM

• 98304 × 8bits (LC877696B)
• 81920 × 8bits (LC877680B)
• 65536 × 8bits (LC877664B)
• 49152 × 8bits (LC877648B) „RAM
• 4096 × 9 bits „Minimum Bus Cycle Time
• 83.3ns (12MHz) V DD=3.0 to 5.5V (target value)
• 125ns (8MHz) V DD=2.5 to 5.5V (target value)
• 250ns (4MHz) V DD=2.2 to 5.5V (target value)
• 30.5μs (32.768kHz) V DD=1.7 to 5.5V (target value) Note: The bus cycle time here refers to the ROM read speed. Ordering number : EN*A0965 Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. CMOS IC Internal 96K/80K/64K/48K-byte ROM 4096-byte RAM 8-bit 1-chip Microcontroller

No.A0965-2/25 „Minimum Instruction Cycle Time (tCYC)

• 250ns (12MHz) V DD=3.0 to 5.5V (target value)
• 375ns (8MHz) V DD=2.5 to 5.5V (target value)
• 750ns (4MHz) V DD=2.2 to 5.5V (target value)
• 91.5μs(32.768kHz) V DD=1.7 to 5.5V (target value) „Ports
• Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units 23 (P1n, P30 to P31, P70 to P73, P8n, XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input port 1 (XT1)
• LCD ports Segment output 32 (S00 to S31) Common output 4 (COM0 to COM3) Bias terminals for LCD driver 3 (V1 to V3) Other functions Input/output ports 32 (PAn, PBn, PCn, PDn,) Input ports 7 (PLn)
• Dedicated oscillator ports 2 (CF1, CF2)
• Reset pins 1 ( RES
• Power pins 6 (V SS1 to VSS3, VDD1 to VDD3) „LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports „Small Signal Detection (MIC signals etc) 1) Counts pulses with the level which is greater than a preset value 2) 2-bit counter „Timers
• Timer 0: 16-bit timer/counter with capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) + 8-bit counter (with 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with 16-bit capture registers) Mode 3: 16-bit counter (with 16-bit capture registers)
• Timer 1: 16-bit timer that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit timer with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes
• Day and time counter 1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter.

No.A0965-3/25 „High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. „SIO

• SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) „UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator „AD Converter: 12 bits × 12 channels „PWM: Multi frequency 12-bit PWM × 2 channels „Infrared Remote Control Receiver Circuit 1) Noise reduction function (Time constant of noise reduction filter: approx. 120μs, when selecting a 32.768kHz crystal oscillator as a reference clock.) 2) X’tal HOLD mode cancellation function „Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable „Clock Output Function 1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32,or 1/64 as system clock. 2) Can output the source oscillation clock for the sub clock.

No.A0965-4/25 „Interrupts Source Flags

• 23 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/remote control receiver 4 0001BH H or L INT3/base timer 0/base timer 1 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/MIC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0/T4/T5
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address „Subroutine Stack Levels: 2048 levels maximum (The stack is allocated in RAM.) „High-speed Multiplication/Division Instructions
• 16 bits × 8 bits (5 tCYC execution time)
• 24 bits × 16 bits (12 tCYC execution time)
• 16 bits ÷ 8 bits (8 tCYC execution time)
• 24 bits ÷ 16 bits (12 tCYC execution time) „Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit: For system clock, with internal Rf and external Rd
• Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd
• Multifrequency RC oscillation circuit (internal): For system clock 1) Adjustable in ±4% (typ) increments from the selected center frequency. 2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference. „System Clock Divider Function
• Can run on low current. and 76.8μs (at a main clock rate of 10MHz). „System Clock Multiplier Function
• Allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system clock.

No.A0965-5/25 „Standby Function

• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation.) 1) Oscillation is not stopped automatically. 2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X’tal, and multifrequency RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2, pins to the specified level (3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote controller circuit. 1) The CF, RC, and multifrequency RC oscillators automatically stop operation 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the infrared remote control receiver circuit „On-chip Debugger function
• Supports software debugging with the IC mounted on the target board. „Package Form
• QFP80(14×14): Lead-free type
• TQFP80J(12×12): Lead-free type „Development Tools
• On-chip debugger: TCB87-TypeB + LC87F76C8A „Flash ROM Programming Board Package Programming Board QFP80(14×14) W87F71256QF TQFP80J(12×12) W87F71256SQ „Same Package and Pin Assignment as Flash ROM Version 1) LC877600 series options can be specified by using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the size of the available ROM/RAM spaces is the same as that of the mask ROM version.

No.A0965-6/25 Package Dimensions unit : mm (typ) 3255 Package Dimensions unit : mm (typ) 3290 SANYO : QFP80(14X14) 14.0 14.0 17.2 17.2 0.15 0.1 3.0max 0.250.65 (0.83)(2.7) 0.8 1 20 4160 12 0 4160 (1.25) 0.20.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0)0.1 1.2max SANYO : TQFP80J(12X12)

No.A0965-7/25 Pin Assignment SANYO: QFP80(14×14) “Lead-free Type” SANYO: TQFP80J(12×12) “Lead-free Type” V1/PL4 V2/PL5 V3/PL6 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/MICIN/AN7 P70/INT0/T0LCP/AN8 VSS2 VDD2 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN P72/INT2/T0IN/NKIN P71/INT1/T0HCP/AN9 COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/ PWM4 VSS3 VDD3 P31/ PWM5 P00/UTX1 P01/URX1 P02 P03 P04 P05/CKO P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 LC877696B LC877680B LC877664B LC877648B Top view

No.A0965-8/25 System Block Diagram Interrupt control Standby control IR PLA Flash ROM Clock generator CF RC X’tal PC Bus interface Port 0 Port 1 SIO0 SIO1 Timer 0 (High speed clock counter) Timer 1 Timer 4 Timer 5 Timer 6 Port 3 Port 7 Port 8 INT0 to INT3 Noise rejection filter Small signal detector ACC B register C register PSW RAR RAM Stack pointer Watchdog timer ALU ADC Infrared remote control receiver Timer 7 LCD controller VMRC UART1 Base timer Day and time counter PWM4/PWM5

No.A0965-9/25 Pin Description Pin Name I/O Description Option VSS1 VSS2 VSS3 - - power supply pin No VDD1 VDD2 VDD3 - + power supply pin No PORT0 P00 to P07 I/O • 8-bit I/O port

• I/O specifiable in 4-bit units
• Pull-up resistors can be turned on and off in 4-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins P00: UART1 transmit P01: UART1 receive P05: Clock output (system clock/subclock selectable) P06: Timer 6 toggle output P07: Timer 7 toggle output Yes PORT1 P10 to P17 I/O • 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1PWMH output/beeper output Yes PORT3 P30 to P31 I/O • 2-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins P30: PWM4 output P31: PWM5 output Yes PORT7 P70 to P73 I/O • 4-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 enable enable disable enable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable No Continued on next page.

No.A0965-10/25 Continued from preceding page. Pin Name I/O Description Option PORT8 P80 to P87 I/O • 8-bit I/O port

• I/O specifiable in 1-bit units
• Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) No S0/PA0 to S7/PA7 I/O • Segment output for LCD
• Can be used as general-purpose I/O port (PA) No S8/PB0 to S15/PB7 I/O • Segment output for LCD
• Can be used as general-purpose I/O port (PB) No S16/PC0 to S23/PC7 I/O • Segment output for LCD
• Can be used as general-purpose I/O port (PC) No S24/PD0 to S31/PD7 I/O • Segment output for LCD
• Can be used as general-purpose I/O port (PD) No COM0/PL0 to COM3/PL3 I/O • Common output for LCD
• Can be used as general-purpose input port (PL) No V1/PL4 to V3/PL6 I/O • LCD drive bias power supply
• Can be used as general-purpose input port (PL)
• Shared pins No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin
• Shared pins General-purpose input port Must be connected to VDD1 if not to be used. AD converter input port: AN10 No XT2 I/O • 32.768kHz crystal oscillator output pin
• Shared pins General-purpose I/O port Must be set for oscillation and kept open if not to be used. AD converter input port: AN11 No CF1 Input Ceramic resonator input pin No CF2 Output Ceramic resonator output pin No

No.A0965-11/25 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor

1 CMOS Programmable (Note) P00 to P07 1 bit

2 N-channel open drain No

1 CMOS Programmable P10 to P17 1 bit

2 N-channel open drain Programmable

1 CMOS Programmable P30 to P31 1 bit

P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable P80 to P87 - No N-channel open drain No S0/PA0 to S31/PD7 - No CMOS Programmable COM0/PL0 to COM3/PL3 - No Input only No V1/PL4 to V3/PL6 - No Input only No XT1 - No Input only No XT2 - No Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No Note: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins. *2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode. Power supply LSI VDD1 For backup *2 VDD2 VDD3 VSS3VSS2VSS1

No.A0965-12/25 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1,VDD2, VDD3 V DD1=VDD2=VDD3 -0.3 +6.5 Supply voltage for LCD VLCD V1/PL4, V2/PL5, V3/PL6 VDD1=VDD2=VDD3 -0.3 V DD Input voltage V I(1) • Port L

• XT1, CF1, RES -0.3 VDD+0.3 Input/output voltage VIO(1) • Ports 0, 1, 3, 7, 8
• Ports A, B, C, D
• XT2 -0.3 VDD+0.3 V IOPH(1) Ports 0, 1 • CM OS output selected
• Per applicable pin -10 IOPH(2) Port 3 • CMOS output selected
• Per applicable pin -20 IOPH(3) Ports 71 to 73 Per applicable pin -5 Peak output current IOPH(4) Ports A, B, C, D Per applicable pin -5 IOMH(1) Ports 0, 1 • CM OS output selected
• Per applicable pin -7.5 IOMH(2) Port 3 • CMOS output selected
• Per applicable pin -15 IOMH(3) Ports 71 to 73 Per applicable pin -3 Average output current (Note 1-1) IOMH(4) Ports A, B, C, D Per applicable pin -3 ΣIOAH(1) Ports 0, 1, 31 Total of currents at all applicable pins -25 ΣIOAH(2) Port 30 Total of currents at all applicable pins -15 ΣIOAH(3) Ports 0, 1, 3 Total of currents at all applicable pins -40 ΣIOAH(4) Ports 71 to 73 Total of currents at all applicable pins ΣIOAH(5) Ports A, B Total of currents at all applicable pins -25 ΣIOAH(6) Ports C, D Total of currents at all applicable pins -25 High level output current Total output current ΣIOAH(7) Ports A, B, C, D Total of currents at all applicable pins -45 IOPL(1) Ports 0, 1 Per applicable pin 20 IOPL(2) Port 3 Per applicable pin 30 IOPL(3) • Ports 7, 8
• XT2 Per applicable pin 10 Peak output current IOPL(4) Ports A, B, C, D Per applicable pin 10 IOML(1) Ports 0, 1 Per applicable pin 15 IOML(2) Port 3 Per applicable pin 20 IOML(3) • Ports 7, 8
• XT2 Per applicable pin 7.5 Low level output current Average output current (Note 1-1) IOML(4) Ports A, B, C, D Per applicable pin 7.5 mA Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms. Continued on next page.

No.A0965-13/25 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit ΣIOAL(1) Ports 0, 1, 31 Total of currents at all applicable pins ΣIOAL(2) Port 30 Total of currents at all applicable pins ΣIOAL(3) Ports 0, 1, 3 Total of currents at all applicable pins ΣIOAL(4) • Ports 7, 8

• XT2 Total of currents at all applicable pins ΣIOAL(5) Ports A, B Total of currents at all applicable pins ΣIOAL(6) Ports C, D Total of currents at all applicable pins Low level output current Total output current ΣIOAL(7) Ports A, B, C, D Total of currents at all applicable pins mA QFP80(14×14) 289.51Maximum power dissipation Pd max TQFP80J(12×12) Ta=-40 to +85°C 236.74 mW Operating ambient temperature Topr -40 +85 Storage ambient temperature Tstg -55 +125 Note 1-1: Average output current refers to the average of output currents measured for a period of 100 ms. Allowable Operating Range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit VDD(1) 0.237 μs≤tCYC≤200μs 3.0 5.5 VDD(2) 0.356 μs≤tCYC≤200μs 2.5 5.5 VDD(3) 0.712 μs≤tCYC≤200μs 2.2 5.5 Operating supply voltage VDD(4) VDD1=VDD2=VDD3 10μs≤tCYC≤200μs 1.7 5.5 Memory sustaining supply voltage VHD V DD1 RAM and register contents sustained in HOLD mode 1.5 5.5 VIH(1) • Ports 0, 3, 8
• Ports A, B, C, D
• Port L Output disabled 1.7 to 5.5 0.3VDD +0.7 V DD VIH(2) • Port 1
• Ports 71 to 73
• Port 70 port input/ interrupt side
• Output disabled
• When INT1VTSL=0 (P71only) 1.7 to 5.5 0.3VDD +0.7 V DD VIH(3) Port 71 interrupt side • Output disabled
• When INT1VTSL=1 1.7 to 5.5 0.85VDD V DD VIH(4) Port 87 small signal input side Output disabled 1.7 to 5.5 0.75VDD V DD VIH(5) Port 70 watchdog timer side Output disabled 1.7 to 5.5 0.9V DD V DD High level input voltage VIH(6) XT1, XT2, CF1, RES 1.7 to 5.5 0.75VDD V DD V Continued on next page.

No.A0965-14/25 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(1) • Ports 0, 3, 8

• Ports A, B, C, D
• Port L Output disabled 2.2 to 4.0 V SS 0.2V DD 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(2) • Port 1
• Ports 71 to 73
• Port 70 port input/ interrupt side
• Output disabled
• When INT1VTSL=0 (P71 only) 1.7 to 4.0 V SS 0.2V DD VIL(3) Port 71 interrupt side • Output disabled
• When INT1VTSL=1 1.7 to 5.5 V SS 0.45VDD VIL(4) Port 87 small signal input side Output disabled 1.7 to 5.5 V SS 0.25VDD VIL(5) Port 70 watchdog timer side Output disabled 1.7 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(6) XT1, XT2, CF1, RES 1.7 to 5.5 V SS 0.25VDD V 3.0 to 5.5 0.237 200 2.5 to 5.5 0.356 200 2.2 to 5.5 0.712 200 Instruction cycle time (Note 2-1) tCYC 1.7 to 5.5 10 200 μs 3.0 to 5.5 0.1 12 2.5 to 5.5 0.1 8
• CF2 pin open
• System clock frequency division ratio=1/1
• External system clock DUTY50±5% 2.2 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 External system clock frequency FEXCF(1) CF1
• CF2 pin open
• System clock frequency division ratio=1/2 2.2 to 5.5 0.2 8 FmCF(1) CF1, CF2 • 12MHz ceramic oscillation
• See figure 1. 3.0 to 5.5 12 FmCF(2) CF1, CF2 • 8MHz ceramic oscillation
• See figure 1. 2.5 to 5.5 8 FmCF(3) CF1, CF2 • 4MHz ceramic oscillation
• See figure 1. 2.2 to 5.5 4 FmVMRC(1) • Multifrequency RC source oscillation
• VMRAJ2 to 0=4, VMFAJ2 to 0=0, When VMSL4M=0 2.2 to 5.5 10 FmVMRC(2) • Multifrequency RC source oscillation
• VMRAJ2 to 0=4, VMFAJ2 to 0=0, When VMSL4M=1 2.2 to 5.5 4 MHz Oscillation frequency range (Note 2-2) FsX’tal XT1, XT2 • 32.768kHz crystal oscillation
• See figure 2. 1.7 to 5.5 32.768 kHz OpVMRC(1) When VMSL4M=0 2.2 to 5.5 8 10 12Multifrequency RC oscillation usable range OpVMRC(2) When VMSL4M=1 2.2 to 5.5 3.5 4 4.5 MHz VmADJ(1) VMRAJn 1STEP (Wide range) 2.2 to 5.5 8 24 64Multifrequency RC oscillation adjustment range VmADJ(2) VMFAJn 1STEP (Narrow range) 2.2 to 5.5 1 4 8 Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants.

No.A0965-15/25 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) • Ports 0, 1, 3, 7, 8

• Ports A, B, C, D
• Port L
• Output disabled
• Pull-up resistor off
• VIN=VDD (including output Tr's off leakage current) 1.7 to 5.5 1 IIH(2) RES V IN=VDD 1.7 to 5.5 1 IIH(3) XT1, XT2 • When configured as input ports
• VIN=VDD 1.7 to 5.5 1 IIH(4) CF1 V IN=VDD 1.7 to 5.5 15 4.5 to 5.5 4.2 8.5 15 High level input current IIH(5) Port 87 small signal input side VIN=VBIS+0.5V (VBIS denotes bias voltage) 1.7 to 4.5 1.5 5.5 10 IIL(1) • Ports 0, 1, 3, 7, 8
• Ports A, B, C, D
• Port L
• Output disabled
• Pull-up resistor off
• VIN=VSS (including output Tr's off leakage current) 1.7 to 5.5 -1 IIL(2) RES V IN=VSS 1.7 to 5.5 -1 IIL(3) XT1, XT2 • When configured as input ports
• VIN=VSS 1.7 to 5.5 -1 IIL(4) CF1 V IN=VSS 1.7 to 5.5 -15 Low level input current IIL(5) Port 87 small signal input side VIN=VBIS-0.5V (VBIS denotes bias voltage) 1.7 to 4.5 -10 -5.5 -1.5 μA VOH(1) I OH=-1mA 4.5 to 5.5 V DD-1 VOH(2) I OH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(3) CMOS output ports 0, 1 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 VOH(4) I OH=-10mA 4.5 to 5.5 VDD-1.5 VOH(5) I OH=-1.6mA 3.0 to 5.5 VDD-0.4 VOH(6) CMOS output ports 30, 31 IOH=-1mA 2.2 to 5-5 VDD-0.4 VOH(7) I OH=-0.4mA 3.0 to 5.5 VDD-0.4 VOH(8) Ports 71 to 73 IOH=-0.2mA 2.2 to 5.5 VDD-0.4 VOH(9) I OH=-1mA 4.5 to 5.5 VDD-1 VOH(10) I OH=-0.4mA 3.0 to 5.5 VDD-0.4 High level output voltage VOH(11) Ports A, B, C, D IOH=-0.2mA 2.2 to 5.5 VDD-0.4 VOL(1) I OL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.6mA 3.0 to 5.5 0.4 VOL(3)
• Ports 0, 1
• Port 3 (PWM4, 5 function output mode) IOL=1mA 2.2 to 5.5 0.4 VOL(4) I OL=30mA 4.5 to 5.5 1.5 VOL(5) I OL=5mA 3.0 to 5.5 0.4 VOL(6) Port 3 (Port function output mode) IOL=2.5mA 2.2 to 5.5 0.4 VOL(7) I OL=1.6mA 3.0 to 5.5 0.4 VOL(8)
• Ports 7, 8
• XT2 IOL=1mA 2.2 to 5.5 0.4 VOL(9) I OH=1.6mA 3.0 to 5.5 0.4 Low level output voltage VOL(10) Ports A, B, C, D IOL=1mA 2.2 to 5.5 0.4 VODLS S0 to S31 • I O=0mA
• VLCD, 2/3VLCD 1/3VLCD level output
• See Fig. 8. 2.2 to 5.5 0 ±0.2 LCD output voltage deviation VODLC COM0 to COM3 • I O=0mA
• VLCD, 2/3VLCD 1/2VLCD, 1/3VLCD level output
• See Fig. 8. 2.2 to 5.5 0 ±0.2 V RLCD(1) Resistance per one bias resister See Fig. 8. 2.2 to 5.5 60 LCD bias resistor RLCD(2) • Resistance per one bias resister
• 1/2 resistance mode See Fig. 8. 2.2 to 5.5 30 kΩ Continued on next page.

No.A0965-16/25 Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Rpu(1) 4.5 to 5.5 15 35 80Pull-up MOS Tr. resistance Rpu(2)

• Ports 0, 1, 3, 7
• Ports A, B, C, D VOH=0.9VDD 2.2 to 4.5 18 50 150 kΩ VHYS(1) • Ports 1, 7
• RES 2.2 to 5.5 0.1VDD Hysteresis voltage VHYS(2) Port 87 small signal input side 2.2 to 5.5 0.1VDD V Pin capacitance CP All pins • V IN=VSS for pins other than that under test
• f=1MHz
• Ta=25°C 1.7 to 5.5 10 pF Input sensitivity Vsen Port 87 small signal input side 2.2 to 5.5 0.12VDD Vp-p Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 6. Input clock High level pulse width tSCKHA(1) SCK0(P12)
• Continuous data transmission/reception mode
• See Fig. 6.
• (Note 4-1-2) 2.2 to 5.5 Frequency tSCK(2) tCYC Low level pulse width tSCKL(2) tSCKH(2)
• CMOS output selected
• See Fig. 6. tSCK Serial clock Output clock High level pulse width tSCKHA(2) SCK0(P12)
• Continuous data transmission/reception mode
• CMOS output selected
• See Fig. 6. 2.2 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC Data setup time tsDI(1) 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)
• Must be specified with respect to rising edge of SIOCLK
• See Fig. 6. 2.2 to 5.5 0.03 tdDO(1)
• Continuous data transmission/reception mode
• (Note 4-1-3) (1/3)tCYC +0.05 Input clock tdDO(2)
• Synchronous 8-bit mode
• (Note 4-1-3) 1tCYC +0.05 Serial output Output clock Output delay time tdDO(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.2 to 5.5 (1/3)tCYC +0.05 μs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous transmission/reception mode, a time from SI0RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.

No.A0965-17/25 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig.6. 2.2 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected

• See Fig. 6. 2.2 to 5.5 tSCK Data setup time tsDI(2) 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
• Must be specified with respect to rising edge of SIOCLK.
• See Fig. 6. 2.2 to 5.5 0.03 Serial output Output delay time tdDO(4) SO1(P13), SB1(P14)
• Must be specified with respect to falling edge of SIOCLK.
• Must be specified as the time to the beginning of output state change in open drain output mode.
• See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 μs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72)
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.7 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.7 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.7 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
• Interrupt source flag can be set.
• Event inputs for timer 0 are enabled. 1.7 to 5.5 256 tPIH(5) tPIL(5) MICIN(P87) The pulses can be counted by the small signal sensor/counter. 1.7 to 5.5 1 tCYC tPIH(6) tPIL(6) RMIN(P73) The pulses can be recognized as signals by the infrared remote control receiver circuit. 2.2 to 5.5 3 RMCK (Note5-1) High/low level pulse width tPIL(7) RES Resetting is enabled. 1.7 to 5.5 2000 μs Note 5-1: RMCK denotes the frequency of the base clock (1tCYC to 128tCYC/subclock source oscillation frequency) for the infrared remote control receiver circuit

No.A0965-18/25 AD Converter Characteristics at VSS1 = VSS2 = 0V <12-bit AD conversion mode at Ta = -30°C to +85°C> (To be determined after evaluation) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 12 bit (Note 6-1) 3.0 to 5.5 ±16Absolute accuracy ET (Note 6-1) Ta=-10 to 50°C 4.0 to 5.5 32 115 LSB 3.0 to 5.5 64 115See "Conversion time calculation method". (Note 6-2) 3.0 to 5.5 V SS V DD Conversion time TCAD See "Conversion time calculation method". (Note 6-2) Ta=-10 to 50°C 3.0 to 5.5 1 μs Analog input voltage range VAIN 3.0 to 5.5 -1 V IAINH VAIN=V DD 3.0 to 5.5 12 Analog port input current IAINL AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1) AN11(XT2) VAIN=VSS -1 μA <8-bit AD conversion mode at Ta =-30 to +85°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 2.0 to 5.5 8 bit ET(1) Specified with tCAD(1) (Note 6-1) 3.0 to 5.5 ±1.5Absolute accuracy ET(2) Specified with tCAD(2) (Note 6-1) 2.0 to 5.5 ±4.0 LSB 4.0 to 5.5 20 90tCAD(1) See "Conversion time calculation method". (Note 6-2) 3.0 to 5.5 40 90 μs Ta=-10 to +55°C See "Conversion time calculation method". (Note 6-2) Conversion time tCAD(2) See "Conversion time calculation ms Analog input voltage range VAIN 2.0 to 5.5 V SS V DD V IAINH VAIN=V DD 2.0 to 5.5 1Analog port input current IAINL AN0(P10) to AN7(P17), AN8(P70), AN9(Internal reference voltage) VAIN=VSS 2.0 to 5.5 -1 μA <Conversion time calculation method> 12-bit AD conversion mode: TCAD (conversion time) = ((52/(division ratio)) + 2) × (1/3)×tCYC 8-bit AD conversion mode: TCAD (conversion time) = ((32/(division ratio)) + 2) × (1/3)×tCYC <Recommended Operating Conditions> Conversion Time (TCAD) External oscillator FmCF[MHz] Supply Voltage Range VDD[V] System Clock Division (SYSDIV) Cycle Time tCYC AD Frequency Division Ratio (ADDIV) 12-bit AD 8-bit AD 4.0 to 5.5 1/1 250ns 1/8 34.8 μs 21.5 μs 12MHz 3.0 to 5.5 1/1 250ns 1/16 69.5 μs 42.8 μs 2.0 to 5.5 1/1 91.5 μs 1/8 - 7.86ms 32.768kHz 3.0 to 5.5 1/1 250 μs 1/8 - 7.86ms Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. The absolute accuracy refers to the accuracy that is measured while there is no change in the I/O state of the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital-conversion-value corresponding to the analog input value is loaded in the required register. The conversion time becomes twice the normal value in the following cases:

• The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system reset.
• The AD conversion is carried out for the first time after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode.

No.A0965-19/25 Consumption Current Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V (To be determined after evaluation) Specification Parameter Symbol Pin/Rema rks Conditions VDD[V] min typ max unit IDDOP(1) 4.5 to 5.5 8.0 17.2 IDDOP(2)

• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio 3.0 to 3.6 4.1 9.8 IDDOP(3) 4.5 to 5.5 5.5 12.6 IDDOP(4) 3.0 to 3.6 2.8 7.1 IDDOP(5)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio 2.5 to 3.0 2.3 5.7 IDDOP(6) 4.5 to 5.5 3.0 7.2 IDDOP(7) 3.0 to 3.6 1.5 3.8 IDDOP(8)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 2.2 to 3.0 1.2 3.0 IDDOP(9) 4.5 to 5.5 0.6 1.5 IDDOP(10) 3.0 to 3.6 0.3 0.7 IDDOP(11)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 2.2 to 3.0 0.2 0.6 IDDOP(12) 4.5 to 5.5 6.9 15.8 IDDOP(13)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 10MHz multifrequency RC oscillation
• 1/1 frequency division ratio 3.0 to 3.6 1.4 8.3 IDDOP(14) 4.5 to 5.5 3.4 7.2 IDDOP(15) 3.0 to 3.6 1.4 5.0 IDDOP(16)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 4MHz multifrequency RC oscillation
• 1/1 frequency division ratio 2.2 to 3.0 1.1 4.1 mA IDDOP(17) 4.5 to 5.5 27.6 126.3 IDDOP(18) 3.0 to 3.6 9.2 74.2 Normal mode consumption current (Note 7-1) IDDOP(19) VDD1 =VDD2 =VDD3
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 1.7 to 3.0 6.9 63.8 μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.A0965-20/25 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDHALT(1) 4.5 to 5.5 2.7 6.2 IDDHALT(2) HALT mode

• FmCF=12MHz ceramic oscillation
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side.
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio 3.0 to 3.6 1.2 3.2 IDDHALT(3) 4.5 to 5.5 2.0 12.6 IDDHALT(4) 3.0 to 3.6 0.9 7.1 IDDHALT(5) HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio 2.5 to 3.0 0.7 5.7 IDDHALT(6) 4.5 to 5.5 1.2 3.3 IDDHALT(7) 3.0 to 3.6 0.5 1.5 IDDHALT(8) HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 2.2 to 3.0 0.4 1.1 IDDHALT(9) 4.5 to 5.5 0.3 0.8 IDDHALT(10) 3.0 to 3.6 0.13 0.4 IDDHALT(11) HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 2.2 to 3.0 0.10 0.3 IDDHALT(12) 4.5 to 5.5 2.6 6.0 IDDHALT(13) HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 10MHz multifrequency RC oscillation
• 1/1 frequency division ratio 3.0 to 3.6 1.2 3.1 IDDHALT(14) 4.5 to 5.5 1.3 3.1 IDDHALT(15) 3.0 to 3.6 0.6 1.5 IDDHALT(16) HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 4MHz multifrequency RC oscillation
• 1/1 frequency division ratio 2.2 to 3.0 0.5 1.2 mA IDDHALT(17) 4.5 to 5.5 20.2 114.6 IDDHALT(18) 3.0 to 3.6 5.1 67.1 HALT mode consumption current (Note 7-1) IDDHALT(19) VDD1 =VDD2 =VDD3 HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio 1.7 to 3.0 3.5 57.9 IDDHOLD(1) 4.5 to 5.5 0.14 35 IDDHOLD(2) 3.0 to 3.6 0.03 28 HOLD mode consumption current IDDHOLD(3) VDD1 HOLD mode
• CF1=VDD or open (external clock mode) 1.7 to 3.0 0.03 26 IDDHOLD(4) 4.5 to 5.5 17.5 125.3 IDDHOLD(5) 3.0 to 3.6 3.8 60 Clock HOLD mode consumption current IDDHOLD(6) VDD1 Clock HOLD mode
• CF1=VDD or open (external clock mode)
• FmX’tal=32.768kHz crystal oscillation mode 1.7 to 3.0 2.4 50 μA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.

No.A0965-21/25 UART (Full Duplex) Operating Conditions at Ta = -20 to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Transfer rate UBR UTX(P00), URX(P01) 2.2 to 5.5 16/3 8192/3 tCYC Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission mode) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H) Example of 8-bit Data Reception Mode Processing (Receive Data=55H) * When using UART, set P0LDDR (P0DDR: BIT0) to “0” Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator Circuit Constant Oscillation Stabilization Time Nominal Frequency Vendor Name Oscillator Name [pF] [pF] Rf1 [Ω] Rd1 [Ω] Operating Voltage Range [V] typ [ms] max [ms] Remarks 12MHz MURATA CSTCE120G52-R0 (10) (10) OPEN 330 3.0 to 5.5 0.05 0.15 Built-in C1, C2 CSTLS8M00G53-B0 (15) (15) OPEN 680 2.5 to 5.5 0.05 0.15 8MHz MURATA CSTCE8M00G52-R0 (10) (10) OPEN 330 2.5 to 5.5 0.05 0.15 Built-in C1, C2 4MHz MURATA CSTCR4M00G53-R0 (15) (15) OPEN 1k 2.5 to 5.5 0.05 0.15 Built-in C1, C2 The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4). Transmit data (LSB first) Start of transmission End of transmission UBR Start bit Stop bit UBR Receive data (LSB first) Start of reception End of reception Start bit Stop bit

No.A0965-23/25 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times Operating VDD lower limit Power supply RES Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD Internal RC oscillation CF1, CF2 XT1, XT2 State HOLD reset signal HOLD release signal VALID tmsCF tmsX’tal HOLD HALT HOLD reset signal absent

No.A0965-25/25 Figure 8 LCD Bias Resistors PS VLCD SW: ON when VLCD=VDD 2/3VLCD 1/2VLCD 1/3VLCD SW : ON/OFF (programmable) VDD GND RLCD RLCD RLCD RLCD RLCD RLCD RLCD RLCD RLCD RLCD This catalog provides information as of September, 2007. Specifications and information herein are subject to change without notice. SANYO Semiconductor Co.,Ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. When designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. Such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equi pment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor C o.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd.