LC875G24A

LC875G32A SANYO | Alldatasheet

Document overview

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PDF pages: 23

Technical content

Features

ROM

32768 × 8 bits (LC875G32A)
24576 × 8 bits (LC875G24A)
16384 × 8 bits (LC875G16A)
8192 × 8 bits (LC875G08A) RAM
1024 × 9 bits (LC875G32A/24A/16A/08A) Minimum Bus Cycle
100ns (10MHz) Note: The bus cycle time here refers to the ROM read speed. CMOS IC ROM 32K/24K/16K/8K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller Specifications of any and all SANYO Semiconductor Co.,L td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer 's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer 'sp r o d u c t so r equipment. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.

No.8299-2/23 Minimum Instruction Cycle Time

300ns (10MHz) Ports
Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units 30 (P1n,P2n,P30 to P36,P70 to P73,PWM0,PWM1,XT2) Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
Normal withstand voltage input port 1 (XT1)
Dedicated oscillator ports 2 (CF1, CF2)
Reset pins 1 (RES )
Power pins 6 (V SS1 to 3, VDD1 to 3) Timers
Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2-channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register)
Timer 1 : 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + with an 8-bit prescaler 8-bit timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2-channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8-bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8-bits can be used as PWM.)
Timer 4: 8-bit timer with a 6-bit prescaler
Timer 5: 8-bit timer with a 6-bit prescaler
Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time-schemes High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real time. SIO
SIO 0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1 byte units)
SIO 1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) UART
Full duplex
7/8/9 bit data bits selectable
1stop bit (2-bit in continuous data transmission)
Built-in baudrate generator

No.8299-3/23 AD Converter : 12-bits/8-bits×12-channels

12-bits/8-bits AD converter selectable
Automatic reference voltage generation controllable PWM : Multifrequency 12-bit PWM×2-channels Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Watchdog Timer
External RC watchdog timer
Interrupt and reset signals selectable Interrupts
22 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level Interrupt Source 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1
Priority Level: X > H > L
Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 512 levels (the stack is allocated in RAM.) High-speed Multiplication/Division Instructions
16-bits×8-bits (5 tCYC execution time)
24-bits×16-bits (12 tCYC execution time)
16-bits÷8-bits (8 tCYC execution time)
24-bits÷16-bits (12 tCYC execution time) Oscillation Circuits
RC oscillation circuit (internal): For system clock
CF oscillation circuit: For system clock, with internal Rf
Crystal oscillation circuit: For low-spee d system clock, with internal Rf
Frequency variable RC oscillation circuit (internal): For system clock System Clock Divider Function
Can run on low current. (at a main clock rate of 10MHz).

No.8299-4/23 Standby Function

HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by a system reset or occurrence of an interrupt.
HOLD mode : Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port 0.
X'tal HOLD mode : Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are four ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (3) Having an interrupt source established at port. (4) Having an interrupt source established in the base timer circuit. Package Form
QIP48E(14×14): “Lead-free type”
SQFP48(7×7): “Lead-free type” Development Tools
Evaluation chip: LC87EV690
Emulator: EVA62S+ECB876600D+SUB875G00+POD48QFP ICE-B877300+SUB875G00+POD48QFP
Onchip debugger: TCB87 TypeA+LC87F5G32A TCB87 TypeB+LC87F5G32A Flash ROM Version
LC87F5G32A

No.8299-5/23 Package Dimensions Package Dimensions unit : mm (typ) unit : mm (typ) 3156A 3163B Pin Assignment SANYO: QIP48E(14×14) "Lead-free Type" SANYO: SQFP48(7×7) "Lead-free Type" Top view P73/INT3/T0IN RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P07/T7O/AN7 P06/T6O/AN6 P05/CKO/AN5 P04/AN4 P36 P35 VDD3 VSS3 P34 P33 P32 P31 P30 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 LC875G32A LC875G24A LC875G16A LC875G08A SANYO : QIP48E(14X14) 14.0 17.2 14.0 17.2 0.150.35 0.8 1.0 (1.5) 1 12 2536 48(2.7) 3.0max 0.1 SANYO : SQFP48(7X7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5)0.1 1.7max 0.180.5 (0.75) 11 2 2536

No.8299-6/23 SQFP/QIP NAME SQFP/QIP NAME

1 P73/INT3/T0IN 25 P04/AN4

2 RES 26 P05/CKO/AN5

3 XT1/AN10 27 P06/T6O/AN6

4 XT2/AN11 28 P07/T7O/AN7

5 V SS1 29 P20/UTX/INT4/T1IN

6 CF1 30 P21/URX/INT4/T1IN

7 CF2 31 P22/INT4/T1IN

8 V DD1 32 P23/INT4/T1IN

9 P10/SO0 33 P24/INT5/T1IN

10 P11/SI0/SB0 34 P25/INT5/T1IN

11 P12/SCK0 35 P26/INT5/T1IN

12 P13/SO1 36 P27/INT5/T1IN

13 P14/SI1/SB1 37 P36

14 P15/SCK1 38 P35

15 P16/T1PWML 39 V DD3

16 P17/T1PWMH/BUZ 40 V SS3

17 PWM1 41 P34

18 PWM0 42 P33

19 V DD2 43 P32

20 V SS2 44 P31

21 P00/AN0 45 P30

22 P01/AN1 46 P70/INT0/T0LCP/AN8

23 P02/AN2 47 P71/INT1/T0HCP/AN9

24 P03/AN3

48 P72/INT2/T0IN

No.8299-7/23 System Block Diagram Interrupt control Standby control IR PLA Bus interface Port 0 Port 1 SIO0 SIO1 Timer 0 Timer 1 Timer 4 Timer 5 Port 3 Port 7 ADC ALU ROM PC ACC B register C register PSW RAR RAM Stack pointer Watchdog timer PWM0 Port 2 Base timer Timer 6 INT0-2, INT4,5 INT3(Noise filter) Timer 7 PWM1 Clock generator CF RC X’tal MRC UART1

No.8299-8/23 Pin Description Pin Name I/O Description Option VSS1 VSS2 VSS3 - - Power supply pin No VDD1 VDD2 VDD3 - + Power supply pin No Port 0 P00 to P07 I/O • 8-bit I/O port

I/O specifiable in 4-bit units
Pull-up resistors can be turned on and off in 4-bit units
HOLD reset input
Port 0 interrupt input
Shared pins P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output AD converter input port: AN0 (P00) to AN7 (P07) Yes Port 1 P10 to P17 I/O • 8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units
Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output/beeper output Yes Port 2 • 8-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units
Pin functions P20: UART transmit P21: UART receive P20 to P23: INT4 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input P24 to P27: INT5 input/HOLD reset input/timer 1 event input/ timer 0L capture input/timer 0H capture input Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT4 INT5 enable enable enable enable enable enable disable disable disable disable P20 to P27 I/O Yes Continued on next page.

No.8299-9/23 Continued from preceding page. Pin Name I/O Description Option Port 3 P30 to P36 I/O • 7-bit I/O port

I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units Yes Port 7 • 4-bit I/O port
I/O specifiable in 1-bit units
Pull-up resistors can be turned on and off in 1-bit units
Shared pins AD converter input port : AN8 (P70), AN9 (P71) P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer 0H capture input P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input Interrupt acknowledge type Rising Falling Rising & Falling H level L level INT0 INT1 INT2 INT3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable P70 to P73 I/O No PWM0, PWM1 I/O • PWM0 and PWM1 output ports
General-purpose I/O available No RES Input Reset pin No XT1 Input • 32.768kHz crystal oscillator input pin
Shared pins General-purpose input port AD converter input port: AN10 Must be connected to VDD1 if not to be used No XT2 I/O • 32.768kHz crystal oscillator output pin
Shared pins General-purpose I/O port AD converter input port: AN11 Must be set for oscillation and kept open if not to be used No CF1 Input Ceramic resonator input pin No CF2 Output Ceramic resonator output pin No

No.8299-10/23 Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected in Units of Option Type Output Type Pull-up Resistor

1 CMOS Programmable (Note 1) P00 to P07 1-bit

2 Nch-open drain No

1 CMOS Programmable P10 to P17 1-bit

2 Nch-open drain Programmable

1 CMOS Programmable P20 to P27 1-bit

1 CMOS Programmable P30 to P36 1-bit

P70 - No Nch-open drain Programmable P71 to P73 - No CMOS Programmable PWM0, PWM1 - No CMOS No XT1 - No Output for 32.768kHz crystal oscillator (Input only) No XT2 - No Input for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) No Note 1: Programmable pull-up resistor of Port 0 is specified in nibble units (P00 to P03, P04 to P07). Note: To reduce VDD signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3 should connect to each other and they should also be grounded. Example 1: During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor. Example 2: During backup in hold mode, output is not held high and its value in unsettled. LSI VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 Power Supply Back-up capacitor VSS1V SS2V SS3 VDD1 VDD2 VDD3 Power Supply Back-up capacitor LSI

No.8299-11/23 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Maximum supply voltage VDD max V DD1, VDD2, VDD3 VDD1=VDD2=VDD3 -0.3 +6.5 Input voltage VI XT1, CF1 -0.3 V DD+0.3 Input/output voltage VIO Ports 0, 1, 2, Port 3, 7, PWM0, PWM1, XT2 -0.3 V DD+0.3 V IOPH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -10 IOPH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin -20 Peak output current IOPH(3) Ports P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3 CMOS output select Per 1 applicable pin -7.5 IOMH(2) PWM0, PWM1 CMOS output select Per 1 applicable pin -15 Mean output current (Note 1-1) IOMH(3) Ports P71 to P73 Per 1 applicable pin -3 ΣIOAH(1) Ports P71 to P73 Total of all applicable pins -10 ΣIOAH(2) Port 0 Total of all applicable pins -25 ΣIOAH(3) Port 1, PWM0, PWM1 Total of all applicable pins -25 ΣIOAH(4) Ports 0, 1 PWM0, PWM1 Total of all applicable pins -45 ΣIOAH(5) Ports 2, P35, P36 Total of all applicable pins -25 ΣIOAH(6) Ports P30 to P34 Total of all applicable pins -25 High level output current Total output current ΣIOAH(7) Ports 2, 3 Total of all applicable pins -45 IOPL(1) Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Per 1 applicable pin IOPL(2) Ports P00, P01 Per 1 applicable pin 30 Peak output current IOPL(3) Port 7, XT2 Per 1 applicable pin 10 IOML(1) Ports P02 to P07 Ports 1, 2, 3 PWM0, PWM1 Per 1 applicable pin IOML(2) Ports P00, P01 Per 1 applicable pin 20 Mean output current (Note 1-1) IOML(3) Port 7, XT2 Per 1 applicable pin 7.5 ΣIOAL(1) Port 7, XT2 Total of all applicable pins 15 ΣIOAL(2) Port 0 Total of all applicable pins 45 ΣIOAL(3) Port 1, PWM0, PWM1 Total of all applicable pins 45 ΣIOAL(4) Ports 0, 1 PWM0, PWM1 Total of all applicable pins 80 ΣIOAL(5) Ports 2, P35, P36 Total of all applicable pins 45 ΣIOAL(6) Ports P30 to P34 Total of all applicable pins 45 Low level output current Total output current ΣIOAL(7) Ports 2, 3 Total of all applicable pins 60 mA SQFP48(7×7) 190Power dissipation Pd max QIP48E(14×14) Ta= -30 to +70°C 390 mW Operating ambient temperature Topr -30 +70 Storage ambient temperature Tstg -55 +125 Note 1-1: The mean output current is a mean value measured over 100ms.

No.8299-12/23 Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit VDD(1) 0.294 µs ≤ tCYC ≤ 200µs 4.0 5.5 VDD(2) 0.367 µs ≤ tCYC ≤ 200µs 3.0 5.5 Operating supply voltage VDD(3) VDD1=VDD2=VDD3 0.588µs ≤ tCYC ≤ 200µs 2.5 5.5 Memory sustaining supply voltage VHD V DD1=VDD2=VDD3 RAM and register contents sustained in HOLD mode. 2.0 5.5 VIH(1) Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.5 to 5.5 0.3VDD +0.7 V DD VIH(2) Port 0 2.5 to 5.5 0.3VDD +0.7 V DD VIH(3) Port 70 watchdog timer side 2.5 to 5.5 0.9V DD V DD High level input voltage VIH(4) XT1, XT2, CF1, RES 2.5 to 5.5 0.75V DD V DD 4.0 to 5.5 V SS 0.1VDD +0.4 VIL(1) Ports 1, 2, 3 P71 to P73 P70 port input/ interrupt side PWM0, PWM1 2.5 to 4.0 V SS 0.2V DD 4.0 to 5.5 V SS 0.15VDD +0.4 VIL(2) Port 0 2.5 to 4.0 V SS 0.2VDD VIL(3) Port 70 watchdog timer side 2.5 to 5.5 V SS 0.8VDD -1.0 Low level input voltage VIL(4) XT1, XT2, CF1, RES 2.5 to 5.5 V SS 0.25V DD V 4.0 to 5.5 0.294 200 3.0 to 5.5 0.367 200 Instruction cycle time tCYC (Note 2-1) 2.5 to 5.5 0.588 200 µs 4.5 to 5.5 0.1 10

CF2 pin open
System clock frequency division ratio=1/1
External system clock duty =50±5% 2.5 to 5.5 0.1 5 4.5 to 5.5 0.2 20.4 External system clock frequency FEXCF CF1
CF2 pin open
System clock frequency division ratio=1/2 2.5 to 5.5 0.2 10 FmCF(1) CF1, CF2 10MHz ceramic oscillation See Fig 1. 4.0 to 5.5 10 FmCF(2) CF1, CF2 8MHz ceramic oscillation See Fig 1. 3.0 to 5.5 8 FmCF(3) CF1, CF2 5MHz ceramic oscillation See Fig 1. 2.5 to 5.5 5 FmMRC Frequency variable RC oscillation source oscillation 2.5 to 5.5 16 MHzOscillation frequency range (Note 2-2) FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig 2. 2.5 to 5.5 32.768 kHz Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants.

No.8299-13/23 Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IIH(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) 2.5 to 5.5 1 IIH(2) XT1, XT2 For input port specification VIN=VDD 2.5 to 5.5 1 High level input current IIH(3) CF1 V IN=VDD 2.5 to 5.5 15 IIL(1) Ports 0, 1, 2, 3 Port 7 RES PWM0, PWM1 Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) 2.5 to 5.5 -1 IIL(2) XT1, XT2 For input port specification VIN=VSS 2.5 to 5.5 -1 Low level input current IIL(3) CF1 V IN=VSS 2.5 to 5.5 -15 µA VOH(1) I OH= -1mA 4.5 to 5.5 V DD-1 VOH(2) Ports 0, 1, 2, 3 IOH= -0.1mA 2.5 to 5.5 V DD-0.5 VOH(3) P71 to P73 I OH= -0.4mA 4.5 to 5.5 V DD-1 VOH(4) I OH= -6mA 4.5 to 5.5 V DD-1 VOH(5) I OH= -1.6mA 4.5 to 5.5 V DD-0.4 High level output voltage VOH(6) PWM0, PWM1, P05 (System clock output function used) IOH= -1mA 2.5 to 5.5 V DD-0.4 VOL(1) I OL=10mA 4.5 to 5.5 1.5 VOL(2) I OL=1.6mA 4.5 to 5.5 0.4 VOL(3) Ports 0, 1, 2, 3 PWM0, PWM1, XT2 IOL=1mA 2.5 to 5.5 0.4 VOL(4) P00, P01 I OL=30mA 4.5 to 5.5 1.5 Low level output voltage VOL(5) Port 7 I OL=1mA 2.5 to 5.5 0.4 V Rpu(1) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 4.5 to 5.5 15 35 80Pull-up resistance Rpu(2) Ports 0, 1, 2, 3 Port 7 VOH=0.9VDD 2.5 to 4.5 18 50 150 kΩ Hysteresis voltage VHYS RES Ports 1, 2, 7 2.5 to 5.5 0.1V DD V Pin capacitance CP All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25°C 2.5 to 5.5 10 pF

No.8299-14/23 Serial Input/Output Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(1) Low level pulse width tSCKL(1) 1 tSCKH(1) See Fig. 6. Input clock High level pulse width tSCKHA(1) SCK0(P12)

Continuous data transmission/reception mode
See Fig. 6.
(Note 4-1-2) 2.5 to 5.5 Frequency tSCK(2) tCYC Low level pulse width tSCKL(2) tSCKH(2)
CMOS output selected
See Fig. 6. tSCK Serial clock Output clock High level pulse width tSCKHA(2) SCK0(P12)
Continuous data transmission/reception mode
CMOS output selected
See Fig. 6. 2.5 to 5.5 tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tCYC Data setup time tsDI(1) 2.5 to 5.5 0.03 Serial input Data hold time thDI(1) SB0(P11), SI0(P11)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 6. 2.5 to 5.5 0.03 tdD0(1)
Continuous data transmission/reception mode
(Note 4-1-3) 2.5 to 5.5 (1/3)tCYC +0.05 Input clock tdD0(2)
Synchronous 8-bit mode
(Note 4-1-3) 2.5 to 5.5 1tCYC +0.05 Serial output Output clock Output delay time tdD0(3) SO0(P10), SB0(P11) (Note 4-1-3) 2.5 to 5.5 (1/3)tCYC +0.05 µs Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.

No.8299-15/23 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Frequency tSCK(3) Low level pulse width tSCKL(3) 1 Input clock High level pulse width tSCKH(3) SCK1(P15) See Fig. 6. 2.5 to 5.5 Frequency tSCK(4) tCYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) • CMOS output selected

See Fig. 6. 2.5 to 5.5 tSCK Data setup time tsDI(2) 2.5 to 5.5 0.03 Serial input Data hold time thDI(2) SB1(P14), SI1(P14)
Must be specified with respect to rising edge of SIOCLK.
See Fig. 6. 2.5 to 5.5 0.03 Serial output Output delay time tdD0(4) SO1(P13), SB1(P14)
Must be specified with respect to falling edge of SIOCLK.
Must be specified as the time to the beginning of output state change in open drain output mode.
See Fig. 6. 2.5 to 5.5 (1/3)tCYC +0.05 µs Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.

No.8299-16/23 Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72), INT4(P20 to P23), INT5(P24 to P27)

Interrupt source flag can be set.
Event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 tPIH(2) tPIL(2) INT3(P73) when noise filter time constant is 1/1
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.5 to 5.5 2 tPIH(3) tPIL(3) INT3(P73) when noise filter time constant is 1/32
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.5 to 5.5 64 tPIH(4) tPIL(4) INT3(P73) when noise filter time constant is 1/128
Interrupt source flag can be set.
Event inputs for timer 0 are enabled. 2.5 to 5.5 256 tCYC High/low level pulse width tPIL(5) RES Resetting is enabled. 2.5 to 5.5 200 µs AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V <12-bits AD Converter Mode / Ta= -10°C to +50°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 4.75 to 5.25 12 bit Absolute accuracy ET (Note 6-1) 4.75 to 5.25 T.B.D LSB Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 4.75 to 5.25 38.5 90 µs Analog input voltage range VAIN 4.75 to 5.25 V SS V DD V IAINH VAIN=V DD 4.75 to 5.25 1Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) VAIN=VSS 4.75 to 5.25 -1 µA <8-bits AD Converter Mode / Ta= -30°C to +70°C> Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Resolution N 3.0 to 5.5 8 bit Absolute accuracy ET (Note 6-1) 3.0 to 5.5 ±1.5 LSB 4.5 to 5.5 22.5 90Conversion time TCAD See conversion time calculation formulas. (Note 6-2) 3.0 to 5.5 45 90 µs Analog input voltage range VAIN 3.0 to 5.5 V SS V DD V IAINH VAIN=V DD 3.0 to 5.5 1Analog port input current IAINL AN0(P00) to AN7(P07) AN8(P70) AN9(P71) AN10(XT1) AN11(XT2) VAIN=VSS 3.0 to 5.5 -1 µA Conversion time calculation formulas: 12-bits AD Converter Mode: TCAD (Conversion time) = ((52/(division ratio))+2) × (1/3) × tCYC 8-bits AD Converter Mode: TCAD (Conversion time) = ((32/(division ratio))+2) × (1/3) × tCYC Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when :
The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.

No.8299-17/23 Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit IDDOP(1) • FmCF=10MHz ceramic oscillation mode

FsX’tal=32.768kHz crystal oscillation mode
System clock set to 10MHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/1 frequency division ratio 4.0 to 5.5 7 12.5 IDDOP(2) • CF1=20MHz external clock
FsX’tal=32.768kHz crystal oscillation mode
System clock set to CF1 side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/2 frequency division ratio 4.0 to 5.5 8 15 IDDOP(3) 4.5 to 5.5 3.7 6.8 IDDOP(4)
FmCF=5MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 5MHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/1 frequency division ratio 2.5 to 4.5 1.9 5.2 IDDOP(5) 4.5 to 5.5 0.6 1.9 IDDOP(6)
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation
Frequency variable RC oscillation stopped
1/2 frequency division ratio 2.5 to 4.5 0.3 1.4 IDDOP(7) 4.5 to 5.5 1.3 4.2 IDDOP(8)
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
Internal RC oscillation stopped
System clock set to 1MHz with frequency variable RC oscillation
1/2 frequency division ratio 2.5 to 4.5 0.7 3.2 mA IDDOP(9) 4.5 to 5.5 26 85 Normal mode consumption current (Note 7-1) IDDOP(10) VDD1 =VDD2 =VDD3
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/2 frequency division ratio 2.5 to 4.5 11 65 µA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. Continued on next page.

No.8299-18/23 Continued from preceding page. Specification Parameter Symbol Pin/ Remarks Conditions VDD[V] min typ max unit IDDHALT(1) • HALT mode

FmCF=10MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 10MHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/1 frequency division ratio 4.0 to 5.5 2.4 4.9 IDDHALT(2) • HALT mode
CF1=20MHz external clock
FsX’tal=32.768kHz crystal oscillation mode
System clock set to CF1 side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/2 frequency division ratio 4.0 to 5.5 3.4 7.7 IDDHALT(3) 4.5 to 5.5 1.5 3.1 IDDHALT(4)
HALT mode
FmCF=5MHz ceramic oscillation mode
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 5MHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/1 frequency division ratio 2.5 to 4.5 0.7 2.2 IDDHALT(5) 4.5 to 5.5 0.3 1.1 IDDHALT(6)
HALT mode
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to internal RC oscillation
Frequency variable RC oscillation stopped
1/2 frequency division ratio 2.5 to 4.5 0.15 0.8 IDDHALT(7) 4.5 to 5.5 1.1 3.6 IDDHALT(8)
HALT mode
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
Internal RC oscillation stopped
System clock set to 1MHz with frequency variable RC oscillation
1/2 frequency division ratio 2.5 to 4.5 0.6 2.7 mA IDDHALT(9) 4.5 to 5.5 18 60 HALT mode consumption current (Note 7-1) IDDHALT(10) VDD1 =VDD2 =VDD3
HALT mode
FmCF=0Hz (oscillation stopped)
FsX’tal=32.768kHz crystal oscillation mode
System clock set to 32.768kHz side
Internal RC oscillation stopped
Frequency variable RC oscillation stopped
1/2 frequency division ratio 2.5 to 4.5 7 40 IDDHOLD(1) 4.5 to 5.5 0.015 17HOLD mode consumption current IDDHOLD(2) VDD1 HOLD mode
CF1=VDD or open (External clock mode) 2.5 to 4.5 0.01 12 IDDHOLD(3) 4.5 to 5.5 16 55Timer HOLD mode consumption current IDDHOLD(4) VDD1 Timer HOLD mode
CF1=VDD or open (External clock mode)
FsX’tal=32.768kHz crystal oscillation mode 2.5 to 4.5 10 36 µA Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.

No.8299-19/23 UART (Full duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] min typ max unit Transfer rate UBR P20, P21 2.5 to 5.5 16/3 8192/3 tCYC Data length: 7, 8, and 9 bits (LSB first) Stop bits: 1-bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H) Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H) Start bit Stop bit Transmit data (LSB first) Start of transmission End of transmission UBR Stop bit Receive data (LSB first) UBR Start of reception Start bit End of reception

No.8299-21/23 Reset Time and Oscillation Stabilization Time HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times Operating VDD lower limit Power Supply RES Internal RC oscillation CF1, CF2 XT1, XT2 Operating mode Reset time tmsCF tmsX’tal Unpredictable Reset Instruction execution VDD Internal RC oscillation CF1, CF2 XT1, XT2 State HOLD reset signal HOLD release signal VALID tmsCF tmsX’tal HOLD HALT HOLD reset signal absent

No.8299-23/23 PS This catalog provides information as of January, 2007. Specifications and information herein are subject to change without notice. SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-qu ality high-reliability pr oducts, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damag e to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. Information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. In the event that any or all SANYO Semiconductor Co .,Ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd.

Summary

ROM 32K/24K/16K/8K byte, RAM 1024 byte on-chip 8-bit 1-chip Microcontroller

Description