LC875048B

LC875064B SANYO | Alldatasheet

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Features

(1) Read Only Memory (ROM) - 65535 × 8 bits (LC875064B) - 57343 × 8 bits (LC875056B) - 49151 × 8 bits (LC875048B) 8-Bit Single Chip Microcontroller with 64/56/48K-Byte EPROM and 2048-Byte RAM On Chip LC875064B/56B/48B Ordering number : ENN*6714 CMOS IC

No.6714-2/26 (2) Random Access Memory (RAM) - 2048 × 8 bits (LC875064B/56B/48B) (3) Bus Cycle Time - 100ns (10MHz) Note: The bus cycle time indicates ROM read time. (4) Minimum Instruction Cycle Time : 300ns (10MHz) (5) Ports - Input/output ports Each bit data direction programmable 51 (P1n, P2n, P70 to P73, P80 to P82, PA2 to PA5, PBn, PCn) Nibble data direction programmable 8 (P0n) - Input ports 2 (XT1,XT2) - PWM Output ports 2 (PWM0,PWM1) - Oscillator pins 2 (CF1,CF2) - Reset pin 1 ( RES ) - Power supply 6 (VSS1 to 3,VDD1 to 3) (6) Timers - Timer0: 16 bit timer/counter with capture register Mode 0: 2 channel 8 bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8 bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register - Timer1: PWM/16 bit timer/counter (with toggle output) Mode 0: 8 bit timer (with toggle output) + 8 bit timer counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM output. - Base timer 1. The clock signal can be selected from any of the following: sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output for timer 0. 2. Interrupts can be selected to occur at one of five different times. (7) SIO - SIO0: 8 bit synchronous serial interface 1. LSB first/MSB first function available 2. Internal 8-bit baud-rate generator (maximum transmit clock period 4/3 T CYC) 3. Continuous automatic data communications (1 - 256 bits) - SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 - 512 T CYC) Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 - 2048 T CYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 - 512 T CYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) (8) AD converter - 8-bits × 3-channels (9) PWM - 2 channel synchronous variable 12 bit PWM (10) Parallel interface - RS, RD , WR , CS0 - CS2 Outputs (reversible polarity) - read/write possible in 1 TCYC

No.6714-3/26 (11) Remote control receiver circuit (connected to P73/INT3/T0IN terminal) - Noise rejection function (noise rejection filter time constant can selected from 1/32/128 TCYC) (12) Watchdog timer - The watchdog timer period set by external RC. - Watchdog timer can be set to produce interrupt, system reset (13) Interrupts - 16-source, 10-vectored interrupts: 1. Three level (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower level interrupt request is refused. 2. If interrupt requests to two or more vector addresses occur at once, the higher level interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence. No. Vector Selectable Level Interrupt signal 1 00003H X or L INT0 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0 8 0003BH H or L SIO1 9 00043H H or L ADC 10 0004BH H or L Port 0/PWM0, 1  Priority Level: X > H > L  For equal priority levels, vector with lowest address takes precedence. (14) Subroutine stack levels - 1024 levels max. Stack is located in RAM (15) Multiplication and division - 16 bit × 8 bit (executed in 5 cycles) - 24 bit × 16 bit (12 cycles ) - 16 bit ÷ 8 bit (8 cycles) - 24 bit ÷ 16 bit (12 cycles) (16) Oscillation circuits - On-chip RC oscillation circuit used for system clock - On-chip CF oscillation circuit used for system clock - On-chip Crystal oscillation circuit used for system clock and time-base clock (17) Standby function - HALT mode HALT mode is used to reduce power consumption. Program execution is stopped. Peripheral circuits still operate. 1. Oscillation circuits are not stopped automatically 2. Release on system reset - HOLD mode HOLD mode is used to reduce the power dissipation. Both program execution and peripheral circuits are stopped. 1. CF, RC and crystal oscillation circuits stop automatically 2. Release occurs on any of the following conditions input to the reset pin goes low a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 an interrupt condition arises at port 0

No.6714-4/26 - X’tal HOLD mode X’tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1. CF and RC oscillation circuits stop automatically 2. Crystal oscillator is maintained in its state at HOLD mode inception. 3. Release occurs on any of the following conditions input to the reset pin goes low a specified level is input to at least one of INT0, INT1, INT2, INT4, INT5 an interrupt condition arises at port 0 an interrupt condition arises at the base-timer (18) Factory shipment - delivery form QIP64E - delivery form DIP64S (19) Development Tools - Evaluation chip : LC876098 - Emulator : EVA87000 + ECB875000 (Evaluation chip board) + POD875000 (POD)

No.6714-5/26 Pin Assignment Package Dimension (unit : mm) 3159 SANYO : QIP-64E PB2/D2 PB3/D3 PB4/D4 PB5/D5 PB6/D6 PB7/D7 P27/INT5/T1IN P26/INT5/T1IN P25/INT5/T1IN P24/INT5/T1IN P23/INT4/T1IN P22/INT4/T1IN P21/INT4/T1IN P20/INT4/T1IN P07 P06 P70/INT0/T0LCP P71/INT1/T0HCP P72/INT2/T0IN P73/INT3/T0IN RES# XT1 XT2 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P10/SO0 P11/SI0/SB0 PA5/RS PA4/RD# PA3/WR# PA2/CS0# PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 VDD3 VSS3 PB0/D0 PB1/D1 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWM L P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05 LC875064B/56B/48B QIP 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

No.6714-6/26 QIP NAME QIP NAME

1 P12/SCK0 33 PB1/D1

2 P13/SO1 34 PB0/D0

3 P14/SI1/SB1 35 VSS3

4 P15/SCK1 36 VDD3

5 P16/T1PWML 37 PC7/A7

6 P17/T1PWMH/BUZ 38 PC6/A6

7 PWM1 39 PC5/A5

8 PWM0 40 PC4/A4

9 VDD2 41 PC3/A3

10 VSS2 42 PC2/A2

11 P00 43 PC1/A1

12 P01 44 PC0/A0

13 P02 45 PA2/CS0#

14 P03 46 PA3/WR#

15 P04 47 PA4/RD#

16 P05 48 PA5/RS

17 P06 49 P70/INT0/T0LCP

18 P07 50 P71/INT1/T0HCP

19 P20/INT4/T1IN 51 P72/INT2/T0IN

20 P21/INT4/T1IN 52 P73/INT3/T0IN

21 P22/INT4/T1IN 53 RES#

22 P23/INT4/T1IN 54 XT1

23 P24/INT5/T1IN 55 XT2

24 P25/INT5/T1IN 56 VSS1

25 P26/INT5/T1IN 57 CF1

26 P27/INT5/T1IN 58 CF2

27 PB7/D7 59 VDD1

28 PB6/D6 60 P80/AN0

29 PB5/D5 61 P81/AN1

30 PB4/D4 62 P82/AN2

31 PB3/D3 63 P10/SO0

32 PB2/D2

64 P11/SI0/SB0

No.6714-7/26 System Block Diagram Interrupt control CF Standby control RC Xtal Clock Generator IR PLA ROM PC SIO0 SIO1 Timer 0 Timer 1 Bus Interface Port 1 Port 0 Port 7 Port 8 ADC P o r t 2 I N T 4,,5 Parallel interface Port A Port B Port C ACC B Register C Register PSW RAR RAM Stack Pointer Watch Dog Timer PWM0 PWM1 Base Timer ALU INT0-3 Noise Rejection Filter

No.6714-8/26 Pin Assignment Pin Name I/O Pin Function Option VSS1 VSS2 VSS3 - Negative power supply No VDD1 VDD2 VDD3 - Positive power supply No Port 0 P00 - P07 I/O 8-bit Input/output port Data direction can be specified in nibble units Use of pull-up resistor can be specified in nibble units HOLD-release input Input for port 0 interrupt Yes Port 1 P10 - P17 I/O 8-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions P10: SIO0 data output P11: SIO0 data input/bus input/output P12: SIO0 clock input/output P13: SIO1 data output P14: SIO1 data input/bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output Yes Port 2 8-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions P20-P23: INT4 input/HOLD release input/timer 1 event input /Timer 0L capture input/Timer 0H capture input P24-P27: INT5 input/HOLD release input/timer 1 event input /Timer 0L capture input /Timer 0H capture input Interrupt receiver format Rising Falling Rising/ falling H level L level INT4 INT5 Yes Yes Yes Yes Yes Yes No No No No P20 - P27 I/O Yes (Continued)

No.6714-9/26 Name I/O Function description Option Port 7 4-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions P70: INT0 input/HOLD release input/Timer0L capture input /Output for watchdog timer P71: INT1 input/HOLD release input/Timer0H capture input P72: INT2 input/HOLD release input/timer 0 event input /Timer0L capture input P73: INT3 input(noise rejection filter attached input) /timer 0 event input/Timer0H capture input Interrupt receiver format Rising Falling Rising/ falling H level L level INT0 INT1 INT2 INT3 Yes Yes Yes Yes Yes Yes Yes Yes No No Yes Yes Yes Yes No No Yes Yes No No P70 - P73 I/O No Port 8 P80 - P82 I/O 3-bit Input/output port Data direction can be specified for each bit Other functions P80-P82: AD input port No Port A PA2 - PA5 I/O 4-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions PA2: Parallel interface output CS0 PA3: Parallel interface output WR PA4: Parallel interface output RD PA5: Parallel interface output RS Yes Port B PB0 - PB7 I/O 8-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions PB0-PB7: Parallel interface data input/output; address output Yes Port C PC0 - PC7 I/O 8-bit Input/output port Data direction can be specified for each bit Use of pull-up resistor can be specified for each bit Other functions PC0-PC7: Parallel interface address output Yes PWM0 O PWM0 output port No PWM1 O PWM1 output port No RES I Reset terminal No XT1 I Input for 32.768kHz crystal oscillation Other function Input port When not in use, connect to VDD1. No XT2 I/O Output for 32.768kHz crystal oscillation Other function General purpose input port When not in use, set to oscillation mode and leave open circuit No CF1 I Input terminal for ceramic oscillator No CF2 O Output terminal for ceramic oscillator No

No.6714-10/26 Port Output Configuration Output configuration and pull-up resistor options are shown in the following table. Input is possible even when port is set to output mode. Terminal Option applies to: Option Output Format Pull-up resistor

1 CMOS Programmable (Note 1) P00-P07 1 bit units

2 Nch-open drain None

1 CMOS Programmable P10-P17

2 Nch-open drain Programmable

1 CMOS Programmable PA2-PA5

PB0-PB7(*) PC0-PC7 each bit P70 - None Nch-open drain Programmable P71-P73 - None CMOS Programmable P80-P82 - None Nch-open drain None PWM0, PWM1 - None CMOS None XT1 - None Input only None XT2 - None Output for 32.768kHz crystal oscillation None Note 1 Programmable pull-up resisters of Port 0 can be attatched in nibble units (P00-03, P04-07). (*) When in parallel interface mode, PB0-PB7 output format is CMOS, regardless of any selected option. Note: Connect as follows to reduce noise on VDD and increase the back-up time. VSS1, VSS2 and VSS3 must be connected together and grounded. Example 1 : In hold mode, during backup, port output ‘H’ level is supplied from the back-up capacitor. Example 2 : During backup in hold mode output is not held high and its value in unsettled. Power Supply LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Back-up capacitor LSI VDD1 VDD2 VDD3 VSS1 VSS2 VSS3 Power Supply Back-up capacitor

No.6714-11/26 1. Absolute Maximum Ratings at Ta=25°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Supply voltage VDDMAX VDD1, VDD2, VDD3 VDD1=VDD2 =VDD3 -0.3 +7.0 Input voltage VI(1) XT1, XT2, CF1 -0.3 VDD+0.3 Output voltage VO(1) PWM0, PWM1 -0.3 VDD+0.3 Input/output voltage VIO(1) Ports 0, 1, 2 Ports 7, 8 Ports A, B, C PWM0, PWM1 -0.3 VDD+0.3 V IOPH(1) Ports 0, 1, 2 Ports A, B, C PWM0, PWM1 CMOS output For each pin. -10 Peak output current IOPH(2) Port 7 For each pin. -5 ΣIOAH(1) Port 7 The total of all pins. -5 ΣIOAH(2) Port 8 The total of all pins. -5 ΣIOAH(3) Port 1 PWM0, PWM1 The total of all pins. -20 ΣIOAH(4) Port 0 The total of all pins. -20 ΣIOAH(5) Ports 2, B The total of all pins. -20 High level output current Total output current ΣIOAH(6) Ports A, C The total of all pins. -20 IOPL(1) P02-P07 Ports 1, 2 Ports A, B, C PWM0, PWM1 For each pin. 20 IOPL(2) P00, P01 For each pin. 30 Peak output current IOPL(3) Ports 7, 8 For each pin. 15 ΣIOAL(1) Port 7 The total of all pins. 5 ΣIOAL(2) Port 8 The total of all pins. 5 ΣIOAL(3) Port 1 PWM0, PWM1 The total of all pins. 40 ΣIOAL(4) Port 0 The total of all pins. 70 ΣIOAL(5) Ports 2, B The total of all pins. 40 Low level output current Total output current ΣIOAL(6) Ports A, C The total of all pins. 40 mA Maximun power dissipation Pdmax QFP64E Ta=-30 to +70°C 430 mW Operating temperature range Topg -20 70 Storage temperature range Tstg -65 150

No.6714-12/26 2. Recommended Operating Range at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit 0.294µs ≤ tCYC ≤ 200µs 4.5 6.0 Operating supply voltage range VDD(1) VDD1=VDD2 =VDD3 0.588µs ≤ t CYC ≤ 200µs 2.5 6.0 HOLD voltage VHD VDD1=VDD2 =VDD3 RAM and the register data are kept in HOLD mode. 2.0 6.0 VIH(1) Ports 1, 2 P71-P73 P70 port input /interrupt 2.5 - 6.0 0.3VDD +0.7 VDD VIH(2) Ports 0, 8 Ports A, B, C 2.5 - 6.0 0.3VDD +0.7 VDD VIH(3) Port 70 Watchdog timer input 2.5 - 6.0 0.9VDD VDD Input high voltage VIH(4) XT1, XT2, CF1, RES 2.5 - 6.0 0.75VDD VDD VIL(1) Ports 1, 2 P71-P73 P70 port input /interrupt 2.5 - 6.0 VSS 0.1VDD +0.4 VIL(2) Ports 0, 8 Ports A, B, C 2.5 - 6.0 VSS 0.15VDD +0.4 VIL(5) Port 70 Watchdog timer input 2.5 - 6.0 VSS 0.8VDD -1.0 Input low voltage VIL(6) XT1, XT2, CF1, RES 2.5 - 6.0 VSS 0.25VDD V 4.5 - 6.0 0.294 200 Operation cycle time tCYC 2.5 - 6.0 0.588 200 µs 4.5 - 6.0 0.1 10 CF2 open circuit system clock divider set to 1/1 external clock DUTY=50±5% 2.5 - 6.0 0.1 5 4.5 - 6.0 0.2 20.4 External system clock frequency FEXCF(1) CF1 CF2 open circuit system clock divider set to 1/2 2.5 - 6.0 0.1 10 MHz (Note 1) The oscillation constant is shown in Tables 1 and 2.

No.6714-13/26 3. Electrical Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit IIH(1) Ports 0, 1, 2 Ports 7, 8 Ports A, B, C RES PWM0, PWM1 Output disable Pull-up resistor off VIN=VDD (including off state leak current of output Tr.) 2.5 - 6.0 1 IIH(2) XT1, XT2 When specified as an input port. VIN=VDD 2.5 - 6.0 1 Input high current IIH(3) CF1 VIN=VDD 2.5 - 6.0 15 IIL(1) Ports 0, 1, 2 Ports 7, 8 Ports A, B, C  RES PWM0, PWM1 Output disable Pull-up resistor off VIN=VSS (including off state leak current of output Tr.) 2.5 - 6.0 -1 IIL(2) XT1, XT2 When specified as an input port VIN=VSS 2.5 - 6.0 -1 Input low current IIL(3) CF1 VIN=VSS 2.5 - 6.0 -15 µA VOH(1) IOH=-1.0mA 4.5 - 6.0 VDD-1 VOH(2) Ports 0, 1, 2 Ports B, C PWM0, PWM1 IOH=-0.1mA 2.5 - 6.0 VDD-0.5 VOH(3) IOH=-5.0mA 4.5 - 6.0 VDD-1 VOH(4) Port A IOH=-0.4mA 2.5 - 6.0 VDD-0.5 Output high current VOH(5) Port 7 IOH=-0.4mA 2.5 - 6.0 VDD-1 V (Continued)

No.6714-14/26 Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit VOL(1) Ports 0, 1, 2 Ports B, C IOL=10mA 4.5 - 6.0 1.5 VOL(2) VOL(3) PWM0, PWM1 VOL(4) P00, P01 IOL=30mA 4.5 - 6.0 1.5 VOL(5) IOL=1mA 4.5 - 6.0 0.4 VOL(6) Ports 7, 8 VOL(7) IOL=15mA 4.5 - 6.0 1.5 Output low current VOL(8) Port A IOL=2mA 2.5 - 6.0 0.4 V Pull-up resistor Rpu Ports 0, 1, 2 Port 7 Ports A, B, C VOH=0.9VDD 2.5 - 6.0 15 40 70 kΩ Hysteresis voltage VHIS Ports 1, 2 Port 7  RES 2.5 - 6.0 0.1VDD V Pin capacitance CP All pins Every other terminal connected to VSS. f=1MHz Ta=25°C 2.5 - 6.0 10 pF

No.6714-15/26 4. Serial Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Cycle t SCK(1) tSCKL(1)

1 Low level

tSCKLA(1) tSCKH(1)

1 High level

tSCKHA(1) SCK0(P12) Refer to figure 6 2.5 - 6.0 3(SIO0) Cycle t SCK(2) Low level pulse width tSCKL(2) 1 Input clock High level pulse width tSCKH(2) SCK1(P15) Refer to figure 6 2.5 - 6.0 Cycle t SCK(3) tCYC tSCKL(3) Use pull-up resistor (1k Ω ) when output is open drain. Refer to figure 6 Low level pulse width tSCKLA(2) SCK0(P12) SIO0 tSCKH(3) 1/2 High level pulse width tSCKHA(2) SCK0(P12) SCK0(P12) SIO0 2.5 - 6.0 tSCK Cycle t SCK(4) 2 t CYC Low level pulse width tSCKL(4) 1/2 Serial clock Output clock High level pulse width tSCKH(4) SCK1(P15) CMOS output option Refer to figure 6 2.5 - 6.0 tSCK 4.5 - 6.0 0.03 Data set-up time tsDI 2.5 - 6.0 0.03 4.5 - 6.0 0.03 Serial input Data hold time thDI SB0(P11), SB1(P14), SI0, SI1 Data set-up to SI0CLK Refer to figure 6 2.5 - 6.0 0.03 4.5 - 6.0 1/3tCYC +0.05 Serial output Output delay time tdD0 SO0(P10), SO1(P13), SB0(O11), SB1(P14) Data set-up to SI0CLK When port is open drain: Time delay from SI0CLK trailing edge to the SO data change. Refer to figure 6 2.5 - 6.0 1/3tCYC +0.05 µs

No.6714-16/26 5. Parallel Input/Output Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Please refer to figures 8 and 9 for parallel output timing waveforms. Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Write cycle, Read cycle tC(1) 2.5 - 6.0 1 tCYC tsA(1)  WR (PA3), PB0-PB7  RD (PA4), PC0-PC7 2.5 - 6.0 1/3tCYC -30ns Address set-up time tsA(2) RD (PA4), PC0-PC7 From address set-up until control signal changes 2.5 - 6.0 2/3tCYC -30ns thA(1) RD (PA4), PC0-PC7 From change of RD until address change 2.5 - 6.0 1/6tCYC tCYC & ns Address hold time thA(2) WR (PA3), PC0-PC7 From change of WR until address change 2.5 - 6.0 5 ns tsRS(1) WR (PA3), RS(PA5), CS (PAX) From change of RS, CS until change in WR 2.5 - 6.0 1/6tCYC -15ns tsRS(2) RD (PA4), RS(PA5) 2.5 - 6.0 1/6tCYC -15ns RS set-up tie tsRS(3) RD (PA4), RS(PA5) from change of RS until change in RD 2.5 - 6.0 1/3tCYC -15ns tsCS(1) RD (PA4), CS (PAX) From change in CS until change in RD 2.5 - 6.0 1/3tCYC -15ns CS set-up time tsCS(2) WR (PA3), CS (PAX) From change in CS until change in WR 2.5 - 6.0 2/3tCYC -15ns tCYC & ns thRS(1) WR (PA3), RS(PA5) From change in WR until change in RS 2.5 - 6.0 0 ns thRS(2) RD (PA4), RS(PA5), CS (PAX) 2.5 - 6.0 1/6tCYC tCYC & ns RS hold time thRS(3) RD (PA4), RS(PA5), CS (PAX) From change in RD until change in RS, CS 2.5 - 6.0 0 ns thCS(1) RD (PA4), RS(PA5) From change in RD until change in CS 2.5 - 6.0 1/6tCYC tCYC & ns CS hold time thCS(2) WR (PA3), RS(PA5) From change in WR until change in CS 2.5 - 6.0 0 ns tWRH(1) WR (PA3) 2.5 - 6.0 1/6tCYC -5ns tCYC WR ’H’ pulse width tWRH(2) WR (PA3) 2.5 - 6.0 2/3tCYC -5ns tCYC tWRL(1) WR (PA3) 2.5 - 6.0 1/6tCYC -5ns tCYC WR ’L’ pulse width tWRL(2) WR (PA3) 2.5 - 6.0 1/3tCYC -5ns tCYC tCYC & ns (Continued)

No.6714-17/26 Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit tRDH(1) RD (PA4) 2.5 - 6.0 1/6tCYC -5ns tCYC RD ’H’ pulse width tRDH(2) RD (PA4) 2.5 - 6.0 1/3tCYC -5ns tCYC tRDL(1) RD (PA4) 2.5 - 6.0 1/3tCYC -5ns tCYC RD ’L’ pulse width tRDL(2) RD (PA4) 2.5 - 6.0 1/2tCYC -5ns tCYC tdDT(1) RD (PA4), PB0-PB7 2.5 - 6.0 1/6tCYC -15ns Data write permission delay tdDT(2) RD (PA4), PB0-PB7 Time for permission, from RD leading edge until input data set-up (Note 1) 2.5 - 6.0 1/3tCYC -15ns tCYC & ns Input data set-up time tsDTR(1) RD (PA4), PB0-PB7 From input data set- up to RD leading edge. (Note 2) 2.5 - 6.0 40 ns Input data hold time thDTR(1) RD (PA4), PB0-PB7 From RD leading edge until input data hold 2.5 - 6.0 0 ns Output data set-up time tsDTW(1) RD (PA4), PB0-PB7 2.5 - 6.0 1/3tCYC -30ns Output data set-up time tsDTW(2) RD (PA4), PB0-PB7 From output data set- up until WR leading edge 2.5 - 6.0 1/3tCYC -30ns tCYC & ns thDTW(1) 2.5 - 6.0 0 Output data hold time thDTW(2) RD (PA4), PB0-PB7 From WR leading edge until output data hold 2.5 - 6.0 0 ns Note 1 : Time until incorrect data of Low is disappeared. Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1). 6. Pulse Input Conditions at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit tPIH(1) tPIL(1) INT0(P70), INT1(P71), INT2(P72) INT4(P20-P23) INT5(P24-P27) Interrupt acceptable Events to timer 0 and 1 can be input. 2.5 - 6.0 1 tPIH(2) tPIL(2) INT3(P73) (The noise rejection clock select to 1/1.) Interrupt acceptable Events to timer 0 can be input. 2.5 - 6.0 2 tPIH(3) tPIL(3) INT3(P73) (The noise rejection clock select to 1/32.) Interrupt acceptable Events to timer 0 can be input. 2.5 - 6.0 64 tPIH(4) tPIL(4) INT3(P73) (The noise rejection clock select to 1/128.) Interrupt acceptable Events to timer 0 can be input. 2.5 - 6.0 256 t CYC High/low level pulse width tPIL(5) RES Reset acceptable 2.5 - 6.0 200 µs

No.6714-18/26 7. AD Converter Characteristics at Ta=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit Resolution N 4.5 - 5.5 8 bit Absolute precision ET (Note 2) 4.5 - 5.5 ±1.5 LSB AD conversion time =32 × tCYC (ADCR2=0) (Note 3) 4.5 - 5.5 15.10 (tCYC= 0.588µs) 97.92 (tCYC= 3.06µs) Conversion time TCAD AD conversion time =64 × tCYC (ADCR2=1) (Note 3) 4.5 - 5.5 15.10 (tCYC= 0.294µs) 97.92 (tCYC= 1.53µs) µs Analog input voltage range VAIN 4.5 - 5.5 VSS VDD V IAINH VAIN=VDD 4.5 - 5.5 1 Analog port input current IAINL AN0(P80) - AN2(P82) VAIN=VSS 4.5 - 5.5 -1 µA (Note 2) Absolute precision not including quantizing error (±1/2 LSB). (Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.

No.6714-19/26 8. Current Dissipation Characteristics atTa=-20°C to +70°C, VSS1=VSS2=VSS3=0V Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit IDDOP(1) FmCF=10MHz for Ceramic resonator oscillation FsX’tal=32.768kHz for crystal oscillation System clock: CF oscillation Internal RC oscillation stopped. 4.5 - 6.0 15 27 IDDOP(2) 4.5 - 6.0 6 11 IDDOP(3) FmCF=5MHz for Ceramic resonator oscillation FsX’tal=32.768kHz for crystal oscillation System clock: CF oscillation Internal RC oscillation stopped. 2.5 - 4.5 3 8 IDDOP(4) 4.5 - 6.0 1 2.5 IDDOP(5) FmCF=0Hz (oscillation stops) FsX’tal=32.768kHz for crystal oscillation System clock: Internal RC oscillation 2.5 - 4.5 0.5 2 mA IDDOP(6) 4.5 - 6.0 35 70 Current flow during basic operation (Note 4) IDDOP(7) VDD FmCF=0Hz (oscillation stops) FsX’tal=32.768kHz for crystal oscillation System clock: X’tal oscillation Internal RC oscillation stopped. 2.5 - 4.5 15 45 µA (Continued)

No.6714-20/26 Ratings Parameter Symbol Pins Conditions VDD[V] min. typ. max. unit IDDHALT(1) HALT mode FmCF=10MHz for ceramic resonator oscillation FsX’tal=32.768kHz for crystal oscillation System clock: CF oscillation Internal RC oscillation stopped. 4.5 - 6.0 5 11 IDDHALT(2) 4.5 - 6.0 3 5 IDDHALT(3) HALT mode FmCF=5MHz for Ceramic resonator oscillation FsX’tal=32.768kHz for crystal oscillation System clock: CF oscillation Internal RC oscillation stopped. 2.5 - 4.5 1.0 2.5 mA IDDHALT(4) 4.5 - 6.0 400 1300 IDDHALT(5) HALT mode FmCF=0Hz (oscillation stops) FsX’tal=32.768kHz for crystal oscillation System clock: Internal RC oscillation 2.5 - 4.5 250 800 IDDHALT(6) 4.5 - 6.0 23 60 Current flow: HALT mode (Note 4) IDDHALT(7) VDD HALT mode FmCF=0Hz (oscillation stops) FsX’tal=32.768kHz for crystal oscillation System clock: X’tal oscillation Internal RC oscillation stopped. 2.5 - 4.5 8 30 µA IDDHOLD(1) 4.5 - 6.0 0.01 30 Current flow: HOLD mode (Note 4) IDDHOLD(2) VDD1 HOLD mode 2.5 - 4.5 0.01 30 µA 4.5 - 6.0 45 100 Current flow: Date/time clock HOLD mode IDDHOLD(2) VDD1 Date/time clock HOLD mode CF1=VDD or open circuit (when using external clock) FmX’tal=32.768kHz for crystal oscillation 2.5 - 4.5 6 36 µA (Note 4) The currents of output transistors and pull-up MOS transistors are ignored.

No.6714-22/26 Reset time and oscillation stable time HOLD release signal and oscillation stable time Figure 4 Oscillation stabilizing time Power Supply RES# Internal RC Resonator oscillation CF1,CF2 XT1,XT2 Operation mode Reset time tmsCF tmsXtal Unfixed Reset Instruction execution mode VDD VDD limit GND Internal RC Resonator oscillation CF1,CF2 XT1,XT2 Operation mode HOLD release signal Without HOLD Release signal HOLD release signal VALID tmsCF tmsXtal HOLD HALT

No.6714-24/26  Parallel Input/Output timing waveform : Indirect Setting, Read Mode Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.  Parallel Input/Output timing waveform : Indirect Setting, Write Mode Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 8 Indirect mode: Parallel Timing Waveforms tsRS(1) ADR/DATA: CS#: RS: WR#: RD#: DATAin: tC(1) read cycle tsA(1) addr thRS(1) tWRH(1) tWRL (1) tsRS (2) tRDL (1) thRS (2) tRDH(1) tsDTR (1) tdDT(1) thDTR (1) data H ADR/DATA: CS#: RS: WR#: RD#: DATAin: tC(1) write cycle data addr tsA(1) tsRS(1) thRS (1) thDTW(1) thRS(3) tsRS(3) tsDTW (1) tWRH(1) tWRL (1) tWRL(2)

No.6714-25/26  Parallel Input/Output timing waveform : Direct Setting, Read Mode Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format.  Parallel Input/Output timing waveform : Direct Setting, Write Mode Note: Port A terminals used as RS, WR , RD and CS should be set to CMOS format. Figure 9 Direct Mode: Parallel Input/Output Timing Diagrams data H tC(1) addr tsA(1) tsCS(1) tRDH(2) tRDL(2) tdDT(2) tsDTR(1) thDTR(1) thA(1) thCS(1) ADR: CS#: DATA: WR#: RD#: DATAin: tC(1) addr tsA(2) tsCS(2) tWRL(2) tsDTW(2) thDTW(2) thA(2) thCS(2) ADR: CS#: DATA: WR#: RD#: DATAin: data tWRH(2) read cycle write cycle

No.6714-26/26 memo: PS