LC864520A | DigiCamel IC Datasheet

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LC864532A SANYO | Alldatasheet

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Ordering number: EN 5582 CMOS LSI } LC864532A/28A/24A/20A/16A/12A/08A bs 8-bit Single Chip Microcontroller Overview Package Dimensions The LC864532A/28A/24A/20A/16A/12A/08A microcontrollers Unit: mm are 8-bit single chip microcontrollers for the TV controls with the following on-chip functional blocks: 3128-DIP52S * CPU: Operable at a minimum bus cycle time of 0.5 us * On-chip ROM maximum capacity : 32K bytes [LC864532A, 28A, 24A, 20A, 16A, 12A, 08A] (LC864532A) Snoponannnaasenonnnaannaa — * On-chip RAM capacity : 256 bytes + CRT display RAM: 160% 9 bits re) CO | ag 4H * On-Screen Display controller a ~ ae Kanji (Chinese character) displaying available ad LU | * 16-bit timer/counter y * 16-bit timer/PWM < 480 “| + 4-channel x 4-bit A/D Converter f al * Two 6-bit D/A Converters | + 8-bit synchronous serial-interface circuit CE ao All of the functions above are fabricated on a single chip. z owl 4 mal [lors SANYO : DIP52S Feature (1) Read-Only Memory (ROM) : LC864532A 32768 x8 bits LC864516A 16384 x8 bits LC864528A 28672 x 8 bits LC864512A 12288 x 8 bits LC864524A 24576 x 8 bits LC864508A, 8192 x 8 bits LC864520A 20480 x 8 bits (2) Random Access Memory (RAM) : 256 x 8 bits 160 x 9 bits (for CRT display) (3) Bus cycle time / Instruction-eycle time The LC864532A/284/24A/20A/16A/12A/08A microcontrollers are constructed to read the ROM twice within one instruction cycle. It has about 1.7 times performance capability within the same instruction-cycle compared to our 4-bit microcontrollers (LC66000 series). The bus cycle time indicates the speed to read ROM. Ceramic (CF) 12M 45V1055V intemal RC 00 kHz 45Vt055V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 23098HA (II) No, 5582-1/18

LC864532A/28A/24A/20A/16A/12A/08A (4) OSD functions * Screen for display : 34 columns x 16 rows (at standard character size) * Display RAM : 160 x 9 bits (6 columns for control + 34 columns for display) x 4 rows x 9 bits * 252 kinds of user specified characters 252 kinds 12x 18 dots * Various character attributes Character colors :8 colors Character background colors :8 colors Fringe / shadow :8 colors Full screen colors :8 colors Fringe / shadow Rounding * Adjacent character attribute data changing available * Vertical display start line setting in row unit available (row overlapping available) * Horizontal display start position setting available + Eight kinds of character size Horiz. x Vert. = (1X 1), (1x2), (22), (24) * Shuttering and scrolling in row unit available * Horizontal character pitch selectable : 9 to 16 dots + Polarity of R, G,B, BL output programmable + Polarity of HS, VS input programmable (5) Ports - Input/output ports : 2 ports (16 lines) Input/output port programmable in nibble units : 1 port (8 lines) (when the N-ch open drain output is selected, the data in a bit can be inputted) Input/output port programmable in bit units : 1 port (8 lines) - Input ports : 2 ports (8 lines) (6) A/D converter - 4-channel x 4-bit A/D converter (converted with program) (7) D/A converters - Two 7-bit D/A converters (8) PWM outputs - Ten 7-bit PWMs - 10-channel x 7-bit PWM. (9) Timer - Timer 0; 16-bit timer / counter 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of Timer is 1 tCYC. - Timer 1; 16-bit timer / PWM Mode 0 Two 8-bit timers with a programmable prescaler Mode 1 8-bit timer with a programmable prescaler + 8-bit PWM Mode 2: 16-bit timer with a programmable prescaler Mode 3 Variable-bit PWM (9 to 16 bits) Tn Mode 0 and Mode 1, the resolution of Timer and PWM is 1 tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : 1 tCYC or 1/2 tCYC by program. No, 5582-2/18

LC864532A/28A/24A/20A/16A/12A/08A (10) Remote control receiver circuit (shares with the P73/INT3/TOIN pin) - Noise rejection function - Polarity switching (11) Watchdog timer External RC circuit is required Interrupt or system reset is selectable. (12) Interrupts - 12-source 9-vectored interrupts 1. External interrupt INTO 2. External interrupt INT1 3. External interrupt INT2, Timer/counter TOL (Lower 8 bits) 4. External interrupt INT3 5, Timer/counter TOH (Upper 8 bits) 6. Timer T1H, TIL. 7. Serial interface 0 (SIOO) — 8. Vertical synchronous signal interrupt (VS) , End of display row 9. Port 0 - Interrupt priority control available Three interrupt priorities are supported (low, high and the highest) and multilevel nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INTO and INT1, high or the highest priority can be set. (13) Sub-routine stack level - A maximum of 128 levels (Sets the stack inside a RAM.) (14) Multiplication/division instruction - 16 bits x 8 bits (7 instruction cycle times) - 16 bits / 8 bits (7 instruction cycle times) (15) 3 oscillation circuits - On-chip RC oscillation circuit for the system clock - On-chip CF oscillation circuit for the system clock - On-chip LC oscillation circuit for the CRT synchronization (16) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request signals or the system reset. - HOLD Mode The HOLD mode is used to stop oscillations ; the RC (internal) and the ceramic oscillations. This mode can be released by the following conditions. * Pull the reset pin (RES) to low level. + Feed the selected level to either P70/INTO or P71/INT1. + Feed the Port0 interrupt condition. (17) Factory shipments DIPS2S (18) Development Tools - Evaluation (EVA) chip : LC866098 - EPROM with a window : LC86E4564 - One time ROM version : LC86P4564 - Emulator : EVA86000 (Main) + ECB864500 (Evaluation board) + POD864500 (Pod) No, 5582-3/18

LC864532A/28A/24A/20A/16A/12A/08A System Block Diagram Lot | Stand-by control 8 PC i : oR a a Pane ee en ‘TIMER 0 PORT7 —>:= Lo noise rejection filter RAM ae - CGROM OSD control PORTO No, 5582-4/18

i kcseass2mzenreanzontent2nosa Pin Assignment Pio/soo 1 —— 52 ff} P07 Pll/sio/sBo Q 2 51 ff P06 pi2/scxo Y 3 50 1 Pos pis q 4 49 P04 pi4 q 5 4g f] P03 pis q 6 47 | P02 pie G7 460 Por Pi7/pwm 8 45 1} Poo Dvss 9 44] P73/INT3/TOIN cF1 Q 10 43 [| P72/INT2/TOIN cF2 Q 11 42 P71/INTL Dvpp Qj 12 41 [| P70/INTO P90/ANO [ 13 40 PWM PO1/AN1 Q 14 39 1 PwMs P92/AN2 [ 15 38 1} PWM7 P93/AN3 16 37 1 PWG Res Q 17 36 | PWM nel Q 18 35 1 PwM4 Le2 Q 19 34 | PWM3 FILT { 20 33 1) PwM2 AVDD Q 21 32 0 PWM1 AVsS [| 22 31 1) PwMo DAO [} 23 30 f BL DAl { 24 29 1 B VS g 25 as fl Gc FS qj) 26 27 R Top view No, 5582-5/18

LC864532A/28A/24A/20A/16A/12A/08A Pin Description * Port option is able to be specified by a bit unit Pin Description Table [fname [enna [Wo [ fst enpaen | oaee ] ovss | 9 | — | _ Negative power terminal for digital circuit | [crt | to [input | inputterminaltorceramicresonator | [ee] [peor mit resemic ister] ovop_ | 12 | — _| _ Positive power terminal for digital circuit [ [tee [ie [op eater seat ouput ening] rut | 20 | ouput | Filter terminal for PLL pT avop_| 21 | _— _| _ Positive power terminal for analog circuit [ avss | 22 | — _| _ Negative power terminal for analog circuit [ DAO cutput/ general purpose 1/0 terminal ; DAt output / general purpose VO terminal | Vertical synchronization signal input tein pT a ee [nf 27 | output |e (Fi) output teminal of RGB image ouput pT [| 28] output | Green 6) output terminal of RGB image output [| | 8 | 22 [output |i (8) output terminal of RGB image output ; BL 30 Output Fast blanking control signal Switch TV image signal and OSD image signal Pwmo ] 31to40 | Output PWMDO to 9 output terminal to PWMo 18 V withstand 8-bit Input/output port Pull-up resistor P00 to POT | 45 1052 v0 Inputioutput can be specified in nibble units provided/ not provided HOLD release input {in bit units) Interrupt input Output format CMOS/Nch-OD (in bit units) Port 4 8-bit Input/output port Output format PIOtoP17 | 1108 vO Inputoutput can be specified in bit units CMOSINch-OD Other functions (in bit units) P10 | S100 data output P11 | S100 data input / bus input / output P12 | SIOO clock input / output 4-bit input port Pull-up resistor P70 4 0 Other functions provided/ not provided P7110P73 | 4210.44 Input P70 | INTO input / HOLD release input / Neh-transistor] | (in bit units) output for watchdog timer P71 | INTI input / HOLD release input P72 | INT2 input / timer 0 event input P73 | INT3 input (noise rejection fiter attached input) /timer 0 event input Interrupt receiver format vector address [| sng | Fatng | Fina Fag INTO [enable | enable | disable [enable [ enable | 03H __| INTA INTE INT3 |__Foro | 4-bit input port PO0 10 PSS | 131016 Input Other function AID converter input port (4 lines) No, 5582-6/18

LC864532A/28A/24A/20A/16A/12A/08A * Any port option can be selected in bit units, * PortOportion _: Pull-up resistor is provided when CMOS output is selected. The pull-up resister is not provided when N-ch Open Drain is selected. * Portl option _; Programmable pull-up resister is provided when any output form is selected. * Port status daring reset Pull-up resistor status at selecting pull-up option [Porto | Input | Pull-up resistor OFF, ON after reset release [_Port7 | input | Fixed pull-up resistor provided * AVDD and AVSS are the power terminals for built-in analog circuit. DVDD and DVSS are the power terminals for built-in digital cirouit. Connect them like the following figure to reduce the mutual noise influence. LSI DYDD Power supply fa Dae - AVDD ae = | AVSS No, 5582-7/18

LC864532A/28A/24 A/20A/16A/12A/08A Specifications 1. Absolute Maximum Ratings at Ta = 25°C, Vss = 0 V Parameter symbol Unit Crom | mn [we | mo | Input voltage vit) | © P71, 72,73 03 Voot0.3 * Port 9 + RES, HS, VS Output vorage | __ vot) [rasecreur [| | os] | veotos | Inputoutput Vio(t) | Ports 0, 1, P70 03 Voot0.3 voltage DAO, 1 High- | Peak lopn(1) | Ports 0, 4 + Pull-up MOS -2 mA level | output transistor output output | current * At each pin current lopu(2) | Ports 0,4 * CMOS output 4 DAO, 4 + At each pin lopH(3) R, G, B, BL * CMOS output +5 + At each pin Total [| Siosn(t) Thetotalotarpine | | of [| carent |Ztcant@) [Roto | The totalofalpins | | =10 | output | sinnf@)_[ Porto Thetotalotalpns [| of Siow _[R.G.8,80 Thetotalotalpne [pat | Low [Peak | ontt) [Protea ipact [ateacnpin | | Ta] current lo.(3) | *R,G,B, BL At each pin 5 + PWMO to PWM9 carent | eae) [Pors.e70 | Thetotalotallpins | output | Sin@) | Pont P70 Thetotalofaipns [| Slow) [R68 aL Thettal otal pne | | | | Siouta) [rweotopwno | Thetotatotanpins | | [| 30 | Maximum power DIP52S Ta = -30 to +70°C 430 mW dissipation Operating Topr 30 +70} °C temperature range Storage Tstg 55 +150 temperature range * DVSS and AVSS must be supplied the same voltage, Vss. Vos = DVSS = AVSS DVDD and AVDD must be supplied the same voltage, Vov. Vop = DVDD = AVDD. No. 5582-8/18

LC864532A/28A/24 A/20A/16A/12A/08A Parameter symbol Unit [vom| nm [wp [mo | Oscillation Fmcr | CF1, CF2 12 MHz (ceramic 451055 | 11.76 | 12 12.24 frequency range resonator oscillation) (Note 1) Refer to Figure 1 Fmic | Let, Lo2 14.11 MHz 4.51055 14.11 (LC oscillation) Refer to Figure 2. | rmac [| RC oscitation asw55| oa | oa [20 | Oscillation stable tmsCF | CF1, CF2 12 MHz (ceramic 4.51055 0.02 0.2 ms time period resonator oscillation) (Note 2) Refer to Figure 3. Note 1: Refer to Table 1 and Table 2 for the oscillation constant. Note 2: The oscillation stable time is a period necessary for the oscillation to be stable after the power first applied, the HOLD mode released and the main-clock oscillation stop instruction released. Refer to the Figure 3 for details No. 5582-10/18

LC864532A/28A/24A/20A/16A/12A/08A 3. Electrical Characteristics at Ta = -30°C to +70°C, Vss= 0V Parameter | Symbol Unit Input high-level h(t) *Port1 DAO, 1 + Output disable 4805.5 1 HA current * Port 0 without + Pull-up MOS pull-up MOS transistor OFF transistor. Vin = Voo (including the off-leak current of the output transistor) 1in(2) * Port 7 without Vin = Voo 4.8 to5.5 1 pull-up MOS transistor. + Port 9 * RES _ + HS, VS Input low-level hy *Port1 DAO, 1 + Output disable 4505.5 current * Port 0 without + Pull-up MOS pull-up MOS transistor OFF transistor. *Viv = Ves (including the off-leak current of the output transistor) W(2) * Port 7 without Vin = Vss 4505.5 pull-up MOS transistor. + Port 9 11.(3) +RES Vin = Vss 4.51055 HS, VS Output high-level Vox(1) | CMOS output of low = 1.0 mA 4505.5 | Voo-1 v voltage ports 0,1 DAO, 1 vou) [R.6.8, BL biz-otma [ass |vorosf | Gutputlowlevet | Vet ia = 101A aswss} | | a8 | voltage Vo.(2) | Ports 0,1 DAO,1 lov =1.6 mA 45055 + The total current of the ports 0, 1 is 40 mA or less. Vor(3) | © R,G,B, BL lo =3.0 mA 4505.5 + PWMO to PWM9 =| « The current of any unmeasured pin is 3 mA orless. [waa [pm [etm [aswes] [| | oa | Pull-up MOS + Ports 0,1 Vou = 0.9Vo0 45to55| 13 38 ka, transistor + Port 7 resistance Output off-leakage lore PWMO to PWM9 Vour = 13.5 V 4505.5 5 BA current Hysteresis voltage Vuais + Ports 0,1 Output disable 4505.5 0.1Vo0 v + Port 7 + RES HS, VS Pin capacitance cP Allpins *f=1MHz 4505.5 10 pF + Unmeasured input pins are set to Ves level. *Ta=25°C No. 5582-11/18

LC864532A/28A/24A/20A/16A/12A/08A 4. Serial Input/Output Characteristics at Ta = -30°C to +70°C , Vss=0V Parameter | Symbol Pine Unt * SCLKO Low. | tCKL(1) 45to55| 4 x | level 3 | pulse g |p 3 [wath £ | High- | tCKH(1) 48to55| 4 level s pulse 3 width 3 roxeviay | + $0K0 suseapulup aston] 2 [| | Low- | tCKL(2) resistor (1 kQ) 4.5 105.5 H/2tcKc’ ¥ | level during open 3 | pulse drain output. = | width + Refer to Figure 5. a 6 | High- | tCKH() 4505.5 H/2tcKC’ level pulse width = | Data set-up tick slo * Data set-up to 45t055| 04 iy 2 | time SCKO rising ® | Data hold tCKI + Data hold from 4805.5 & | time SCKO rising + Refer to Figure 5. Output delay} tcKo(1) | Soo + Use a pull-up 4805.5 7M2tcYC}] us time resistor (1k) 40.2 g_ | (Satial clock during open B | is extemal drain output. 3 | clock) + Data set-up to @ | Outputdelay | tcKO(2) SCKO falling 48055 T/3tCYC 3 | time + Data hold from 40.2 (Serial clock SCKO falling is intemal + Refer to Figure 5 clock) No. 5582-12/18

LC864532A/28A/24A/20A/16A/12A/08A 5. Pulse Input Conditions at Ta = -30°C to +70°C, Vss =0 V Parameter Symbol Unit [veom| on | | mo] Highow-level tPIH(1) | + INTO,INTA + Interrupt acceptable | 4.5 to 5.5 tCYC pulse width tPIL(1) _| + INT2/TOIN + Timer0-countable tPIH(2) | INT3/TOIN + Interrupt acceptable | 4.5 to 5.5 2 {PIL(2) | (The noise rejection | + Timer0-countable clock is set to 1/1) tPIH(3)_ | INT3/TOIN + Interrupt acceptable | 4.5t055] 32 tPIL(3) | (The noise rejection | + Timer0-countable clock is set to 1/16) tPIH(S) | AS, VS Display position 45to55| 10 tCYC tPIL(S) controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 7. Rising/falling time tTHL =| HS Refer to Figure 7 4.51055 500 | ns tTLH pull-in range Figure 10 is 1/2 Voo. 6. A/D Converter Characteristics at Ta = -30°C to +70°C, Vss=0V. [vena min [op [mar | Conversion time 1CAD | From Vref selection | 1 bit conversion time | 4.5 to 5.5 1.96 us to when the result | = 2tCYC is produced Reference current laer (Regulate the ladder | 4.5 to 5.5 1.0 2.0 mA resistor) Analog input Var NO to ANS 451055] Vss Voo v voltage range Note 3: Absolute precision excepts quantizing error (+1/2 LSB). No. 5582-13/18

LC864532A/28A/24A/20A/16A/12A/08A 7. D/A Converter Characteristics at Ta = -30°C to +70°C, Vss=0V Parameter] Symbol Unit [vei| mm [oe [ me] [resouton [| noa fT ass fT TT tt | sole precision | TOA P| Ponts moge woe) [astossp | ae | | ase | [settingtime | spa | tote) astoss[ [io [| us | Analog input VAOUT | DAO to DA1 4.51055] Ves Voo v voltage range ropa [| nate) 451055 Note 4: Absolute precision excepts quantizing error (+1/2 LSB). Note 5: Settling time refers to the time from when the D/A conversion instruction is executed to when the analog voltage output corresponding to the digital on the specific port is generated. (No load) Note 6: D/A data = 80H 8. Current Drain Characteristics at Ta = -30°C to +70°C, Vss=0V [voor [ min | ye | max_| Current drain Inpor(1) | DVDD, AVDD + FmCF = 12 MHz 4.51055 16 28 mA during basic Ceramic resonator operation oscillation (Note 7) * FmLC = 14.11 MHz LC oscillation + System clock CF oscillation + Intemal RC oscillation stops Current drain loonacr(1) | DYDD, AVDD + HALT mode 4.51055 5 10 mA in HALT mode + FmCF = 12 MHz (Note 7) Ceramic resonator oscillation + FmLC = 0 Hz (oscillation stops) + System clock CF oscillation + Intemal RC oscillation stops looratr(2) | DYDD, AVDD + HALT mode 4.5 105.5 800 HA + FmCF = 0 MHz (oscillation stops) + FmLC =0 Hz (oscillation stops) + System clock Internal RC Current drain DYDD, AVDD *HOLD mode 4.51055 0.05 20 HA in HOLD mode +All oscillation stops. (Note 7)| looworo(2) Note 7: The currents of the output transistors and the pull-up MOS transistors are ignored. No. 5582-14/18

resonator oscillation CST12.0MTW.

Both Cl and C2 must use a K rank (+10%) and SL characteristics.

Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)

See Figures 10 and 11 for the oscillation frequency.

Table 2. LC Oscillation Guaranteed Constant (OSD clock) pins as possible with the shortest pattern length. + If you use other oscillators herein, we provide no guarantee for the characteristics.

LC864532A/28A/24A/20A/16A/12A/08A Monitor 22k O VAVAN FILT 2.2 uF T 1000 pF Figure 9 FILT Recommended Circuit (Note) *Place the parts connected to the FILT terminal as close to the FILT as possible with the shortest pattern length on the board. Voo =s.0v Veo =¢ov t WP cr azaH + 16 oh B8 eb00r wT Ta = 25°C z = 30pF iy 2 1s “= fr s © = 33pF = Lea 7a

3 C= 36pF 5 U = 4onH

$ 3 ferer - 4 © = S0pF £14 F 13 8 13 ° 1 2 3 4 5 0 1 2 3 4 5 FILT [VJ FILT[V] > Figure 10 FILT-LC Oscillation Frequency (1) Figure 11 FILT-LC Oscillation Frequency (2) Il No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. I Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD.., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. I information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and infomation herein are subject to change without notice. PS No, 5582-18/18

Product Information

LC864520A specifications and overview.

Summary

8-Bit Single-Chip Microcontroller?

Description

8-Bit Single-Chip Microcontroller?

Source title LC864520A Datasheet(PDF) - Sanyo Semicon Device

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