LC86P4448 SANYO | Alldatasheet
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Technical content
Features
(1) Option switching by PROM data The option function of the LC864400 series can be specified by the PROM data. The functions of the trial pieces can be evaluated using the mass production board. (2) Internal PROM capacity + 49152 bytes (3) Internal RAM capacity 384 bytes LC864448 49152 bytes 384 bytes Lose4444 45056 bytes 384 bytes Lo864440 40960 bytes 384 bytes LC864436 36864 bytes 384 bytes LC864432 32768 bytes 384 bytes Los64428 28672 bytes 384 bytes LC864424 24576 bytes 384 bytes LC864420 20480 bytes 384 bytes (4) Operating supply voltage 4.5V to 5.5V (5) Instruction cycle time + 0,99 us to 366 us (6) Operating temperature 30°C to 470°C (7) The pin and package compatible with the LC864400 series mask ROM devices (8) Applicable mask ROM version LC864448/L.C864444/LC864440/LC864436/LC864432 LC864428/LC864424/LC8644 20 (9) Factory shipment : DIPG4S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 22898HA (II) No. 5583-1/19
‘The LC86P4448 is proveded for the first release and small shipping of the LC864400 series. Atusing, take notice of the followings. (1) Differences between the LC86P4448 and the LC864400 series Lesera4as L¢864448/44/40/36/32/28/24/20 Operation after reset The option is specified by degrees until 3ms | The program is executed from OOH of the program releasing after going to a'H!' level to the reset terminal. | counter immediately after going to a'H' level to the The program is executed from 00H of the reset terminal, program counter. Operating supply 45V to 5.5V 27V to 55V voltage range (Vo) Refer to ‘electrical characteristics’ on the semiconductor news. The LC86P4448 uses 256 bytes addressed on FFOOH to FFFFH in the program memory as the option configuration data area. All options of the LC864400 series can be specified. (2) Option The option data is written with the option specifying program "SU86K.EXE". The option data is linked to the program area by the linkage loader "L86K.EXE". (3) ROM space The LC86P4448 and LC864400 series use 256 bytes addressed on FFOOH to FFFFH in the program memory as the option specified data area, The program memory capacity of this series is, at most, 49152 bytes addressed on 0000H to BFFFH. 49FFFFH [Character Character Character Character Character Character generatorROM | —|generatorROM | | generatorROM | | generator ROM | |generatorROM | generator ROM OFFFFH | Opion specified Option specified Option specified Option specified Option specified lOption specified OFFOOH | atea 256 bytes area 256 bytes: area 256 bytes area 256 bytes: area 256 bytes area 256 bytes OBFFFH Eee OAFFFH Rd O7FFFH Ee ey ee a es OOFFFH ee be ey ee ee ees pPeaemare) | famerisea) EPeomnaes) [frgremact) peoamaes) | Ceuertaer pues) SMa byes FSR eye: FScekbyecs| ESeekbyee:| ego byer coooH EESEEESS ESSSEES EGEEES EEEESS) ESE] BEES Lc864448 Lc864444 LC864440 LC864436 LC864432 LC864426 13FFFFH | Character Character generator ROM | | generator ROM OFFFFH | Onion specified | [pion specified 256 256 oFFooH | Moaebves area 256 bytes - | OFFFH es Rcedtbyiee] Fo BoiChytes c000H ESSE ERs Lc864424 Lc864420 No. 5583-2/19
(1) Create a programming data for LC86P4448 Programming data for EPROM of the LC86P4448 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with the file converter program EVA2HEX.EXE. The HEX file is used as the programming data for the LC86P4448 (2) How to program for the PROM The LC86P4448 can be programmed by the EPROM programmer with attachment W86EP4448D. + Recommended EPROM programmer EPROM programmer Advantest R4945, R4944, 4943 AF-G704 AVAL PKW-1100, PKW-3000 Minato electronics MODEL1890A + "27010 (Vpp = 12.5 V) Intel high speed programming” mode should be adopted. The address must be set to 13FFFH" and the (3) How to use the data security function "Data security" is the function to disable the EPROM data from being read out. The following is the process in order to execute data security function. 1, Set the jumper of attachment 'ON'. 2, Program again. The EPROM programmer will display an error. The error means that the data security functions normally. It is not trouble of the EPROM programmer or the LSI. Notes * Data security is not executed when the data of all addresses have 'FF at procedure 2 above. * Data security cannot be executed by programming the sequential operation "BLANK=>PROGRAM=>VERIFY" at procedure 2 above. * Set the jumper to 'OFF’ after executing the data security. Data security Ree Pee Data security OFF Bk Ue ae “Ree <3 Jumper Jumper “ee Pint W86EP4448D No. 5583-3/19
I p1oysoo 1 64 f] po7 Pl1/st0/sBo Q 2 63 fl poe P12/scKO J 3 62 1 pos pi3 4 61 f) po4 pi4 5 60 f) po3 pis 0 6 59 fl po2 pié 7 58 f] po P17/PWM {| 8 57 f} Poo xT1 Q 9 56 ff P25 xT2 ( 10 55 p24 Dvss q 11 54 0 p23 cri q 12 53 DP p22 cF2 q 13 52 0 pai DVDD q 14 51 p20 P90/ANO [ 15 50 DP P73/INT3/TOIN P91/AN1 Q 16 49 [1 P72/INT2/TOIN P92/AN2 Q 17 4g ff) P71/INT1 P93/AN3 Q 18 47 [1 P70/INTO p94/AN4 (19 46 [| PwM9 P9S/ANS {| 20 45 0 PwMs P96/AN6 ( 21 44) PwM7 P9T/ANT [22 43 f} pwMe RES Q 23 42 | PwMs Lel Q 24 41 PwM4 Le2 J 25 40 PWM3 FILT Q 26 39 1 PwM2 AVDD [| 27 38 D1 PwML avss [J 28 37 PwMO cvIN J 29 36 H BL vs { 30 35 DP B Hs Q 31 34 G I Q 32 33 PD R Top view No. 5583-4/19
‘Al6 to AO D710 D0 [ seanay comet] contol fe— Standby trol andby contro atoll a OE DASEC 0 5 PROM(8KB) RC 6 3 a eee LO SS —— =] Noise rejection filter a oe circuit No. 5583-5/19
+ Port option can be specified by bit units. + At port 0, 'Pull-up resistor provided’ when specifying CMOS output. 'Pull-up resistor not provided’ when specifying N-ch open drain output. * Atport 1 and 2, 'Programmable pull-up resistor provided’ when specifying either CMOS or N-ch open drain output. Pin Description Table [_Pinname [ rinwe[ vo | Function descipion [Option | PROM mods ovss [11 | — | Negative power supply tor digital cirout ee ee [xz] t0 | of ouput rin or the eystalosciation re ee | crt | ta | 1 [imputterninalforcaramicresenator | [or | 14 [0 | oututteinlfrcnraric senator | id | dvoo | 14 | — [Positive poner supply tor agit circuit re ee | Fes | 2a | 1 [Resettemins PT [tot [24 [1 [tc cectton cmaitimttomna + SSCs SCCid [toe 25 | 0 | tc oscitation circuit output terminal ee aut [26 | 0 | Fiterteminal for PLL ee ee avss | 26 | — [Negative powersupplyforanaiog dreuit_ [PT cvin [20 [1 | Video signal input terminal re ee [vs [20 | 1 |vercal emetrorizatonsnalinpatomna [sd ——SSSS—iS [ws | 21_[ 1 | Hota srcrenizatensigainptiomina |__| J tse To J image intensity utput ee ee | 85 To [aus ©) ouputtermina of RGBimage output | ast) BL 36 Fast blanking control signal AT (‘1) ‘Switch TV image signal and caption/ OSD image signal PwMo 37 to 46 PWNM0 to 9 output terminal PWM 0 to8 to PWM9 15 V withstand AB to A16 (*1) PWM 9 : "L" fixed 8-bit Input/output port Pull-up resistor POO to PO7 57 to 64 vo Input/output can be specified in nibble units Provided/not provided HOLD release input (in bit units) Interrupt input Output Format CMOSINch-OD (in bit units) 8-bit Input/output port Output Format DO to D7 ("2) Pi0toP17 | 1to8 | VO | input/output can be specified in bit units. CMOS/Nch-OD Other function (in bit units) P10 |SIO0 data output P11 |S100 data input /bus input/output P12 |SIO0 clock input/output P17 |Timer 1 (PWM) output 6-bit Input/output port Output Format P20to P25 | 51to56| I/O | input/output can be specified in bit units. CMOS/Nch-OD (in bit units) No. 5583-6/19
[Farane [Pano [10 [Rancenencipion [open Provo] 4-bit input port Pull-up resistor P70 : VPP (°3) P70 47 | vO | Other function provided/ P71 : DASEC (*4) P71toP73 | 48t050] 1 | 1P70 [NTO inputHOLD release input/Nch- not provided P72 : OE (°5) transistor output for watchdog timer (in bit units) P73 : CE (*6) P71 |INT1 input/HOLD release input P72 _|INT2 input/timer 0 event input P73 _|INT3 input (noise rejection filter attached input/timer 0 event input Interrupt receiver format vector address | rise [rat [serra INTO INT 8-bit input port P90 to P93 PO0 to POT | 15to22 Other function A0 to A3 ("1) AD converter input port (8 lines) *1 An Address input *2 Data I/O *3 Power for programming *4 Memory select input/output for data security *5 Output Enable input *6 Chip Enable input * Port state during reset Pull-up resistor status at selecting pull-up option [Fer [ret] Putep aber OFF, ON aterretiene | | Port1, 2 | input | Programmable pull-up resistor OFF [Port 7 | input | Fixed pull-up resistor provided * AVDD and AVSS are the power supply terminals for the analog operation block, DVDD and DVSS are the power supply terminals for the digital operation block. Connect them like the following figure to reduce the mutual noise influence. LsI DVDD Power supply tzz | ~ AVDD | a = | AVSS No, 5583-7/19
- Absolute Maximum Ratings at Ta = 25°C, Vss= 0 V Parameter symbol Unit [voor | min | yp [max _| Input voltage vit) | © P74, 72, 73 0.3 Voo+0.3 * Port? + RES, HS, VS, CVIN Ourput votage | vot) [aaeenneer | | [oa [| vioso | Inputoutput Violt) | Ports 0, 1, 2, P70 0.3 Vo0+0.3 voltage High- | Peak lopn(1) | Ports 0, 1,2 *Pull-up MOS mA level output transistor output output | current *Ateach pin current lopn(2)_ | Ports 0, 1, 2 *CMOS output -4 *Ateach pin lopH(3) R, G, B, BL, I *CMOS output 5 *Ateach pin Total | Bloss(t) Thetotalotanpins | | 10 | | aut | sian(@) [Pore 0,2 [the toa stare | | 0 | |_| current Tonia) [R.G.8.01 |therotaoraipines [|| as || tow [Peak | toatt) | Pons0.1,2 [ateachpin | TT 2 eel bee MET P a current lor) | *R,G,B, BL, I At each pin 5 + PWMO to PWM9 output Port 1, P70 The total of all pins [Sica [Puno topune —[Trevsalotatpne | [||| Maximum power DIP64S Ta = -30 to +70°C 720 mW dissipation Operating Topr -30 +70 | °c temperature range Storage Tstg -55 +125 temperature range * DVSS and AVSS must be supplied the same voltage, Vss. Vss = DVSS = AVSS DVDD and AVDD must be supplied the same voltage, Vop. - Vop = DVDD = AVDD. No. 5583-8/19
- Recommended Operating Range at Ta = -30°C to +70°C, Vss=0V Parameter | Symbol Pins Unit voi | min | ye [max _| supply voltage range | Voo(2) 0.97 us <tCYC < 400 us ee Hold voltage Vuo | DYDD, AVDD. RAMs and the registers 55 hold data at HOLD mode high-level vii2) | *Ports 1,2 (Schmitt) | Output disable 45105.5| 0.78 Voo Voo voltage P72, 73 HS, VS vi(3) |*P70 Output N-channel 451055) 0.75 Voo Voo port input / interrupt | transistor OFF *P71 +RES (Schmitt) via) | P70 Output N-channel 4505.5) Voo-0.5 Voo Watchdog timer _| transistor OFF input vin(S) | Port 9 45t05.5| 0.7 Voo Voo port input voltage V2) |*Porst 1,2 (Schmitt) | Output disable 451055 Voss 0.25 Voo <P72, 73 «HS, VS *Port 9 vu) |+P70 N-channel transistor OFF | 4.5 to 5.5 Ves 0.25 Vo port input / interrupt *P71 +FES (Schmitt) vi(4) P70 N-channel transistor OFF | 4.5 to 5.5 Vss 0.6 Voo Watchdog timer input v6) | Porto 451055 Vss 0.3Vo0 port input CVIN input Vevin | CVIN 5.0 | 1Vp-p-3dB] 1Vp-p] 1Vp-p+3dB] Vp-p | * amplitude * Vp-p : Peak-to-peak voltage No. 5583-9/19
Parameter Symbol [Ratings] unit [voor | min [ye [max _| Oscillation Fmcr(t) | Crt, C2 12 MHz (ceramic 451055) 11.76| 12| 12.24 frequency range resonator oscillation) (Note 1) Refer to Figure 1 FmCF (2) 12.08 MHz (ceramic | 45t055| 11.84] 1208] 12.92 resonator oscillation) Refer to Figure 1. Fmic | Let, Lz 44.41 MHz 451055 141 (LC oscillation) Refer to Figure 2. | rmec [| oseitation astoss| o4| o8| 30 | FsxXtal XT1, XT2 32.768 kHz (crystal 451055 32.768 kHz resonator oscillation) Refer to Figure 3 Oscillation tmscF(1) | Ft, cF2 12 MHz (ceramic 451055 0.02] 02 | ms stable time resonator oscillation) period Refer to Figure 4 (Note 2) tmsCF(2) 42 MHz (ceramic 451055 0.02 resonator oscillation) Refer to Figure 4 teeXtal | XT1, xT2 32.768 KHz (crystal | 4.5 t055 5.0 resonator oscillation) Refer to Figure 4. (Note 1) Refer to tables 1, 2 and 3 for oscillation constant. (Note 2) The oscillation stable time period refers to the time it takes to oscillate stably after the following conditions, 1. Applying the first supply voltage. 2, Release of the HOLD mode. 3, Release of the stopping of the main-clock oscillation, (Refer to Figure 4) No. 5583-10/19
- Electrical Characteristics at Ta =-30°C to +70°C, Vss=0V Parameter [Symbol Unit Input high-level lua(1) *Ports 1,2 * Output disable 45to5.5 1 pA current *Port 0 without +Pull-up MOS pull-up MOS. transistor OFF transistor *Vin = Yoo (including the off-leak current of the output transistor) In(2)—|* Port 7 without Vin = Voo 4.8 to5.5 1 pull-up MOS. transistor Port 9 +RES HS, VS Input low-level h(t) |*Ports 1,2 + Output disable 4505.5 + current *Port 0 without +Pull-up MOS pull-up MOS. transistor OFF transistor Vin = Vss (including the off-leak current of the output transistor) I(2)—_|* Port 7 without Vin = Ves 4505.5 -1 pull-up MOS. transistor *Port9 13) |* RES Vin =Vss 48 to5.5 1 HS, VS Output high-level Vox(1) [CMOS output of low = 1.0 mA 4505.5] Voo-t v voltage ports 0, 1,2 voltage Voul2) [Ports 0, 1,2 slo, = 1.6 mA 45 105.5 +The total current of the ports 0, 1 is 40 mA or less. Vo.(3) |*R, GB, BL, I slo. = 3.0 mA 4505.5 *PWMO0 to PWM9 | The current of any unmeasured pin is 3 mA orless. [vaw [Fe —‘inetma —faswasf | | oa | Pull-up MOS +Ports 0, 1,2 Vox = 0.9Vo0 4505.5 13 39 ka transistor *Port7 resistance Output off-leakage lore PWMO to PWM9 Vour =13.5V 4505.5 5 | pA current Hysteresis Vas +Ports 0, 1,2 Output disable 4505.5 0.1Vp0 v voltage *Port 7 +RES HS, VS No. 5583-11/19
Parameter | Symbol Unit Input clamp Voune cvin 50| 23 25 | 27 | v voltage Pin capacitance cP All pins ¢f=1 MHz 451055 10 pF *Unmeasured terminals for the input are set to Vss level *Ta = 25°C 4. Serial Input/Output Characteristics at Ta = -30°C to +70°C , Vss=0V Parameter | Symbol Uni Voo VI tCKCY(1)_}+SCKO Refer to Figure 6. asto5s| 2; |__| tcye Low- tcKL(a) |*SCLKO 1 x | level 8 | pulse | Pu = |_wiath £| High- tCKH(1) level S pulse 3 width Bs Low- tCKL(2) |*SCLKO (1 kQ) when open 1/2tCKCY x | level drain output 8] pulse + Refer to Figure 6 3 | width B 8 | High- tCKH(2) 4/2tCKCY level pulse width z= [Data set-up tick |e Slo + Data set-up toSCKO | 4.5 t05.5| 0.1 us 2 |time tising |Data hold tCKI * Data hold from SCKO o4 & time nsing ° + Refer to Figure 6 Output delay} tCKO(1) |» Soo Use a pull-up resistor | 4.5 to 5.5 7MatcYC time (1 kQ) when open 40.2 3 |(Exteral drain output. & |serial clock) + Data set-up to SCKO & Joutput delay] tcKo(2) falling 451055 4/3tYC 5 * Data hold from SCKO & |time fall 40.2 (intemal * wes Figure 6 serial clock) + Refer to Figure 6. No. 5583-12/19
- Pulse Input Conditions at Ta = -30°C to +70°C, Vss = 0 V vow | an | w [mo | High/low level {PIH(1) | *INTO, INT4 }*Interrupt acceptable | 4.5 to 5.5 1 tcYC pulse width tPIL(1) | +INT2/TOIN }* Timer0-countable tPIH(2)_ | INT3/TOIN sInterrupt acceptable | 4.5 to5.5 tPIL(2) | (The noise rejection _|« Timer0-countable clock is set to 1/1) tPIH(3)_ | INT3/TOIN }*Interrupt acceptable tPIL(3) | (The noise rejection |* Timer0-countable 45to55 32 clock is set to 1/16) wu) [RES [Reset acceptable [astoss| 200 | | | ns | tPIH(S) | HS, VS Display position 45to55} 10 icy tPIL(S) controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 8 Rising/falling time ‘THLE «| AS Refer to Figure 8. 451055 500 tTLH Horizontal FH |HS The monitor pointin | 4.5to55] 15.23 | 15.73 | 16.23 | kHz pull-in range Figure 11 is 1/2 Vo. 6. A/D Converter Characteristics at Ta = -30°C to +70°C, Vss=0V Conversion time tCAD | From Vref selection to | 1 bit conversion time | 4.5 to5.5 2 bs when the result is = 2tcYC produced Reference current lner (Regulate the ladder | 4.5to5.5 1.0 2.0 mA resistor) Analog input Van JANO to AN7 451055 | Vos Voo | V voltage range Analog portinput van=Voo faswss[ [Tt Ta cunent [vaveves fastens] 1 | [| (Note 3) Absolute precision excepts quantizing error (+1/2 LSB) No. 5583-13/19
- Current Drain Characteristics at Ta = -30°C to +70°C, Vss=0V prem fem | | ee Unit Current drain Ippop(1) DVDD, AVDD |*FmCF = 12 MHz or 45to5.5 25 38 mA during basic FmCF =12.08 MHz operation when ceramic resonator (Note 4) oscillation *FsXtal = 32.768 kHz when crystal oscillation *FmLC = 14.11 MHz LC oscillation + System clock : CF oscillation *Internal RC oscillation stops lovor(2) *FmCF = 0 Hz 45t05.5 16 (when oscillation stops) *FmLC = 0 Hz (when oscillation stops) +FeXtal = 32.768 kHz when crystal oscillation + System clock : LC oscillation +Internal RC oscillation stops Current drain Iopxait(1) | DYDD, AVDD |+HALT mode 4505.5 5 mA in HALT mode *FmCF = 12 MHzor (Note 4) FmCF =12.08 MHz when ceramic resonator oscillation *FmLC = 0 Hz (when oscillation stops) +FeXtal = 32.768 kHz when crystal oscillation + System clock : CF oscillation +Internal RC oscillation stops. Iopyatt(2) | DYDD, AVDD |+HALT mode 4505.5 1600 | pA *FmCF = 0 Hz (when oscillation stops) *FmLC = 0 Hz (when oscillation stops) +FsXtal = 32.768 kHz when crystal oscillation + System clock : Internal RC lopHatt(3) DYDD, AYDD |+FmCF = 0 Hz 45to5.5 25 100 (when oscillation stops) *FmLC =0 Hz (when oscillation stops) +FsXtal = 32.768 kHz when crystal oscillation + System clock : LC oscillation *Internal RC oscillation stops Current drain IooHo.0. =| DVDD, AVDD |+HOLD mode 4505.5 0.08 30 | pA in HOLD mode *All oscillation stops. (Note 4) (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No. 5583-14/19
- Both Cl and C2 must use K rank (+10%) and SL characteristics.
Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)
14.11 MHz LC oscillation 47 pH 33 pF | 45 pF (Trimmer)
4.7 WHi10% 33 pH 33 pH
Table 2. LC oscillation Guaranteed Constant (OSD clock)
- Both C5 and C6 must use a J rank (+5%) and CH characteristics.
Table 3. Crystal Oscillation Guaranteed Constant (sub-clock) pins as possible with the shortest possible pattern length. + If you use other oscillators herein, we provide no guarantee for the characteristics.
Requirements Prior to Mounting Notes on Handling * The construction of one-time microcontrollers in which the PROM is not programmed precludes Sanyo from fully testing them before they are shipped. The screening procedure described below is recommended in order to attain higher reliability after programming the PROM. * The nature of one-time microcontrollers in which the PROM is not programmed precludes us from fully testing them by writing all of the bits. Therefore, it is not possible for us to guarantee a write yield of 100%. * — Storage in moisture-proof packaging (unopened) While they are still in the moisture-proof packaging, these devices should be stored at a temperature of 30°C and a humidity of no more than 70%. * After opening the moisture-proof packaging These devices should be mounted and soldered as soon as possible after the moisture-proof packaging is opened. Once the moisture-proof packaging is opened, the devices should be stored at a temperature of 30°C and a humidity of no more than 70% for no more than 96 hours. a. Inthe case of models that are programmed by the user (models that are shipped with the PROM not programmed) DIP model Programming/verification Recommended screening procedure Exposure to high temperature without power| 150 +5°C, 24") hours Confirmation that program can be read b. Requirements prior to mounting for models that are programmed by Sanyo (models that are shipped with the PROM already programmed) DIP model I No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. I Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. I Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice. PS No, 5583-19/19