LC864266A

Online Datasheet

Read LC864266A online.

LC864266A SANYO | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 20

Technical content

Features

(1) Read-only program memory (ROM) LC864266A 65280 x 8 bits LC864265A 65280 x 8 bits (2) Read-only look up table memory (ROM) : LC864266A, 65536 x 8 bits LC864265A 32768 x 8 bits (3) Random access memory (RAM) 512 x 8 bits 640 x 9 bits (for CRT display) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 20898HA (II) No. 5552-1/20

LC864266A, 864265A (4) OSD functions * Screen for display: 34 columns x 16 rows (standard character size) * Display for RAM. 640 x 9 bits (6 columns for control + 34 columns for display) x 16 rows x 9 bits * 377 kinds of user specified characters Caption/Text mode (9 x 9 dots) x 125 kinds OSD mode : (12x 18 dots) x 127 characters (127 characters can also be used in Caption/Text mode) * Various character attributes Character colors : 16 colors Character background colors: 16 colors Fringe / shadow colors : 16 colors Full screen colors : 16 colors Fringe / shadow Rounding Underline Italic character (slanting) * Close-character attribute data changing available + Vertical display start line setting in row units available (Row overlapping available) * Horizontal display start position available + Display mode specification by row (Display mode mixable) caption mode / text mode / OSD mode + Eight kinds of character size Horiz. x Vert. =(1X1), (1x2), (22), (2% 4) * Shuttering and scrolling in row units available * Horizontal character pitch selectable : 9 to 16 dots + Polarity of R. G, B, I, BL output programmable + Polarity of HS, VS input programmable (5) Data slicer clock switching function Clock source is selective from LC oscillation or ceramic resonator (or Xtal) oscillation. (6) Bus cycle time / Instruction cycle time The LC864132B/24B/20B/16B/12B microcontrollers are designed to read the ROM twice within one instruction cycle. It has about 1.7 times performance capability within the same instruction-cycle compared to our 4-bit microcontrollers (LC66000 series). The bus cycle time indicates the speed to read ROM. (7) Ports - Input/output port : 2 ports (16 lines) Input/output port programmable in nibble unit : 1 port (8 lines) (When the N-ch open drain output is selected, the data in a bit can be inputted) Input/output port programmable in a bit : l port (8 lines) - Input port : 2 ports (8 lines) No, 5552-2/20

LC864266A, 864265A (8) A/D converter - 4-channel x 5-bit AD converter (converted with program) (9) PWM output - 10-channel x 7-bit PWM (10) Timer - Timer 0: 16-bit timer / counter 2-bit prescaler + 8-bit built-in programmable prescaler Mode 0: Two 8-bit timers with a programmable prescaler Mode 1: 8-bit timer with a programmable prescaler + 8-bit counter Mode 2: 16-bit timer with a programmable prescaler Mode 3: 16-bit counter The resolution of timer is 1 tCYC. - Timer 1: 16-bit timer / PWM Mode 0: Two 8-bit timers Mode 1: 8-bit timer + 8-bit PWM Mode 2: 16-bit timer Mode 3: Variable-bit PWM (9 to 16 bits) Tn Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : tCYC or 1/2tCYC by program. (11) Remote control receiver circuit (shares with the P73/INT3/TOIN terminal) - Noise rejection function - Polarity switching (12) Watchdog timer External RC circuit is required Interrupt or system reset is selectable (13) Interrupts = 11-source 9-vectored interrupts 1, External Interrupt INTO 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter TOL (Lower 8 bits) 4, External Interrupt INT3 5, Timer/counter TOH (Upper 8 bits) 6, Timer T1H, TIL. 7. Serial interface 0 (STOO) 8, Data slicer _ 9. Vertical synchronous signal interrupt (VS) - Interrupt priority control available Three interrupt priorities are supported (low, high and the highest) and multilevel nesting is possible. Low or high priority can be assigned to the interrupts from 3 to 10 listed above. For the external interrupt INTO and INT1, high or the highest priority can be set. (14) Sub-routine stack level - A maximum of 128 levels (Sets the stack inside a RAM.) No, 5552-3/20

LC864266A, 864265A (15) Multiplication/division instruction - 16bits x 8 bits (7 instruction cycle times) - 16bits /8 bits (7 instruction cycle times) (16) Three oscillation circuits - On-chip RC oscillation circuit for the system clock - On-chip ceramic resonator oscillation circuit for the system clock - On-chip LC oscillation circuit for the CRT synchronization (17) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This mode can be released by the interrupt request signals or the system reset. - HOLD mode The HOLD mode is used to stop oscillations ; the RC (internal) and the ceramic oscillations. This mode can be released by the following conditions. * Pull the reset terminal (RES) to low level. + Feed the selected level to either P70/INTO or P71/INT1. (18) Factory shipment DIPS2S (19) Development Tools - Evaluation (EVA) chip : LC866098 - EPROM attached a window : LC86E4266 - Emulator : E¥VA86000 (Main) + ECB864200 (Evaluation board) + POD864100 (Pod) No, 5552-4/20

LC864266A, 864265A System Block Diagram Interrupt control \\ | OUR PLA ROM Standby control r i a % 3 a8 Pc : H =] beets LT ee 7 comer [rere ae INTO to INT 3 i, ce {om OSD control Watch dog timer No, 5552-5/20

LC864266A, 864265A Pin Assignment piossoo YG 1 cS 520 Pav? Pl1/si0/sBo Y 2 510 PaA6 P12/scko Y 3 50 PAS pi3 | 4 49f}) Pad pi4 5 43} PA3 pis q 6 47) PA2 pie 7 46f PAL P17/PWwM | 8 45[ PAO Dvss | 9 44) P73/INT3/TOIN CFL O10 43) P72/INT2/TOIN cF2 Qa 42) P71/INT1 DVDD 12 41} P70/INTO P90/ANO 13 40 PWM PO1/ANL O44 39 PWM P92/AN2 415 38 PWM7 P93/AN3 O16 37 PwWM6 RES 17 36 PwWM5S Lcl Og 35 PWM4 Lc2 Dis 34 PWM3 FILT 39 33) PWM2 AVDD O91 32 PwM1 AVSS @q 22 310 PWMO CVIN q 23 30 BL VS 24 29 B HS 25 oasfc Iq 26 27 R Top view No. 5552-6/20

LC864266A, 864265A Pin Description + Port option can be specified in bit units except the pull-up resistor selection of port 0. Pin Description Table pvss | 9 | — Negative poner supply for ta ereu rT oven] 12 | — Festive power suppiy for aga ore | | es | 17 | mput__ | Resettomina [| LC oscillation circuit input terminal [ Sutput | _16 osetlaon dreut utputwnmina rT Fit 20 | output) iter terminal tor PLL Do avon | 21 | — | Positive power supply for analog circuit | aves | 22 | __— | _Negatve power supply for aneloy aad evn [23 [input video signal input temnina [ | ws | a imput__| Vertical synchronization signal input teminal | Pt | 26 | output [image intensity output [ || a J ouput [ed (hi) cutputterinal of RGB image output [ Je | 20 output | Btu (6) ouput terminal of RGB image output [| BL 30 Ouptut Fast blanking control signal Switch TV image signal and caption/OSD image signal Pwo 31 to. 40 Output PWMO to 9 output terminal to PWM9 15 V withstand 8-bit Input/output port Output Format P1OtoP17 | 1to8 vo Input/output can be specified in bit units. CMOS/Nch-OD Other function (in bit units) P10 | S100 data output P11 | S100 data input / bus input/output P12 | S100 clock input/output P17 | Timer 1 (PWM) output 4-bit input port Pull-up resistor P70 4 vo Other function provided/ P71toP73 | 42to 44 Input P70 | INTO inputHOLD release inputl not provided Nch-transistor output for watchdog timer (in bit units) P71 | INT1 input/HOLD release input P72 | INT2 inputtimer 0 event input P73 | INT3 input (noise rejection filter attached input/ timer 0 event input) Interrupt receiver formats / vector addresses into | enable | enabie | disable | enable | enabie_| 03H | int ire INTs Continued on next page. No. 5552-7/20

LC864266A, 864265A Continued from preceding page. [_Pinname [Pinno | vo [| Function Description Option _— a A P90 to P93 | 13to 16 Other functions AD converter input port (4 lines) PAO to PA7 | 45 to52 vo Input/output can be specified in nibble units * Any port option can be selected in bit units. * Port 0 portion : Pull-up resistor is provided when CMOS output is selected. The pull-up resister is not provided when N-ch Open Drain is selected. * Port 1 option : Programmable pull-up resister is provided when any output form is selected. * Port status during reset Terminal vo Pull-up resistor status at selecting pull-up option [Pont | input | Programmable pup resistor OFF | Pon7 | input__[ Fixed puiltup tesistorprovided * AVDD and AVSS are the power supply terminals for built-in analog circuit, while DVDD and DVSS are for built-in digital circuit. Connect them like the following figure to reduce the mutual noise-influence. LSI DVDD Power ae = | ™ pea AVDD AVSS No. 5552-8/20

LC864266A, 864265A Parameter Symbol Unit Cram me [we [ma] Oscillation FmOF (1) | CF1, F2 42 MHz (ceramic 451055| 11.76] 12 | 12.24 frequency range resonator oscillation) (Note 1) Refer to Figure 1 FmCF (2) 42.08 MHz (ceramic 11.84] 12.08] 12.92 resonator oscillation) Refer to Figure 1. Fmic | Let, Lez 44.11 MHz 451055 14.44 (LC oscillation) Refer to Figure 2. [rmac [| Rc cscitation asvoss[ oa | oa | 20 | Oscillation ‘tmsCF (1) CF1, CF2 12 MHz (ceramic 4.51055 0.02 0.2 ms stable time resonator oscillation) period Refer to Figure 3 (Note 2) tmsCF (2) 42.08 MHz (ceramic resonator oscillation) Refer to Figure 3. (Note 1) Refer to Table 1 and Table 2 for the oscillation constant (Note 2) The oscillation stable time is a period necessary for the oscillation to be stable after the power first applied, the HOLD mode released and the main-clock oscillation stop instruction released, Refer to the Figure 3 for details. No. 5552-11/20

LC864266A, 864265A 3. Electrical Characteristics at Ta =-30°C to + 70°C, Vss= 0V Parameter | Symbol Unit [veo] an] w [no | Input high-level h(t) *Port4 + Output disable 4805.5 1 HA current + PortA + Pull-up MOS transistor OFF Vin = Voo (including the off-leak current of the output transistor) 1in(2) * Port 7 without Vin = Voo 4.8 to5.5 1 pull-up MOS transistor + Port 9 “FES _ +HS,VS Input low-level hy + Port 4 + Output disable 4505.5 current + Porta + Pull-up MOS transistor OFF *Viv = Ves (including the off-leak current of the output transistor) W(2) * Port 7 without Vin = Vss 4505.5 pull-up MOS transistor + Port 9 1.(3) + RES Vin = Vso 4.51055 +HS,VS Output high-level Vox(1) | CMOS output of low = 1.0 mA 4505.5 | Voo-1 v voltage ports A, 1 vou) [8.6.8 81.1 biz-otma [astoss|voros| [| Suputlowiever | Vat i 210 mA aswss] [| 18 voltage Voul2) | Ports A, 4 lol = 1.6 mA 4.51055 + The total current of the ports A, 1 is not over 40 mA. Voi(3) | RG, B, BL! lo =3.0 mA 4505.5 + PWMO to PWM9 | « The current of any unmeasured pins is not over 3 mA. [waa [rm [etm [aswesp [| oa | Pull-up MOS + Ports A, 1 Vou = 0.9Vo0 45to55| 13 38 ka, transistor + Port 7 resistance Output off-leakage lore PWMO to PWM9 Vour = 13.5 V 4505.5 5 BA current Hysteresis voltage Vuis + Ports A, 1 Output disable 4505.5 0.1Vo0 v *Port7 RES _ +HS,VS No. 5552-12/20

LC864266A, 864265A 5. Pulse Input Conditions at Ta = -30°C to +70°C, Vsgs=0V Parameter | Symbol Unit [veom| mm |v [max] Highfow-level tPIH(1) | + INTO, INT1 ¢ Interrupt acceptable | 4.5 to 5.5 tCYC pulse width tPIL(1) | * INT2/TOIN + Timer/counter 0 pulse countable tPIH(2) | INTS/TOIN + Interrupt acceptable | 4.5 to 5.5 2 tPIL(2) | (The noise rejection | + Timer/counter 0 clock is selected to pulse countable tPIH(3) | INT3/TOIN * Interrupt acceptable {PIL(3)_| (The noise rejection | * Timer/counter 0 45to55| 32 clock is selected to pulse countable 16) PIL) Resetacceptable [aswoss| zoo] | | ns | tPIH(5) | HS, VS Display position 45055 40 t1cYC tPIL(S) controllable Each active edge of HS, VS must be more than 1tCYC. Refer to Figure 7. Rising/falling time tTHL HS Refer to Figure 7. 4.51055 500 ns tTLH Horizontal FH HS The monitor point in 45to5.5 | 15.23 | 15.73 16.23 kHz pull-in range Figure 10 is 1/2 Voo. 6. A/D Converter Characteristics at Ta = -30°C to +70°C, Vss=0V Yow | am [ve [ma] en CY OO Jassauteprecison| er | [wa _[aswss| | saa] aa | 1s | Conversion time tCAD | From selecting 1 bit conversion 4505.5 1.96 us Vref to resulting time = 2tCYC Reference current ther (Regulate the ladder 45to5.5 1.0 2.0 mA resistor) Analog input Vamsi ‘ANO to ANS 451055] Vos Voo v voltage range (Note 3) Absolute precision excepts quantizing error (+1/2 LSB). No. 5552-14/20

LC864266A, 864265A 7. Current Drain Characteristics at Ta =-30°C to +70°C , Vss=0 V Parameter | Symbai Fins Conaons ont [vei| mm [oe [ me] Current drain Iopor(1) | DYDD, AVDD + FmCF = 12 MHz 4805.5 a 32 mA during basic Ceramic resonator operation oscillation (Note 4) + FmLC = 14.11 MHz LC oscillation + System clock CF oscillation + Intermal RC oscillation stops Current drain looHacr(1) | DYDD, AVDD + HALT mode 4.51055 5 10 mA in HALT mode + FmCF = 12 MHz or (Note 4) 12.08 MHz Ceramic resonator oscillation + FmLC =0 Hz (oscillation stops) + System clock CF oscillation + Intermal RC oscillation stops. loprair(2) | DVDD, AVDD + HALT mode 4505.5 300 800 BA + FmCF = 0 MHz (oscillation stops) + FmLC =0 Hz (oscillation stops) + System clock intemal RC Current drain IooHo.o | DVDD, AVDD *HOLD mode 4505.5 0.05 20 HA in HOLD mode * All oscillation stops. (Note 4) (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No. 5552-15/20

Both Cl and C2 must use an K rank (+10%) and an SL characteristics.

Table 1. Ceramic Resonator Oscillation Guaranteed Constant (Main-clock)

14.11 MHz LC oscillation 33 pF 45 pF (Trimmer)

See Figure 11, 12 for LC oscillation characteristics.

Table 2. LC Oscillation Guaranteed Constant (OSD clock) as possible with the shortest pattern length.

LC864266A, 864265A Noise filter 1 4700 i c-video [/ }-—+—\\/\\\\ : cvIN : | 2.2uF | 560pF : * ee Coupling capacitor Figure 9 CVIN Recommended Circuit Monitor point 22kQ. ¢ VAVAY FILT + 22uF 1000pF Figure 10 FILT Recommended Circuit (Note) * Place the parts connected FILT terminal as close to the FILT as possible with the pattern length on the board, Voo =5.0V Vop = 5.0V 16 L=4.7pH + 16

= = Ls 4 5uH zp © = 33pF 3 L = 4.7HH z z Le 5.1K 5 14 © = 39pF . 14 3 3 3 3 8 43 8 13 oO 1 2 3 4 5 0 1 2 3 4 5 FILT [VJ] > FILT[V] Figure 11 FILT-LC Oscillation Frequency (1) Figure 12 FILT-LC Oscillation Frequency (2) No. 5552-19/20

LC864266A, 864265A I No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disastet/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. I Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD. its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD. its affiliates, subsidiaries and distibutors or any of their officers and employees jointly or severally. I Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties, This catalog provides information as of February, 1998. Specifications and information herein are subject to change without notice. PS No, 5552-20/20

Product Information

LC864266A specifications and overview.

Summary

8-Bit Single-Chip Microcontroller?

Description

8-Bit Single-Chip Microcontroller?

Source title LC864266A Datasheet(PDF) - Sanyo Semicon Device

Related Parts

More parts from the same family.

Browse manufacturer