LC86P4164 SANYO | Alldatasheet
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Technical content
Features
(1) Option switching by PROM data The option function of the LC864100 series can be specified by the PROM data. The functions of the trial pieces can be evaluated using the mass production board. (2) Internal PROM capacity : 65512 bytes (for program data) : 8192 x 12 bits (for character data) (3) Internal RAM capacity : 384 bytes (4) Operating supply voltage :45V to 5.5V (5) Instruction cycle time : 1.0ps to 30ps (6) Operating temperature =30°C to +70°C (7) The pin and the package compatible with the LC864100 series mask ROM devices (8) Applicable mask ROM version : LC864164/LC864156/LC864148/LC864140/LC864132 LC864124/LC864120/LC864116/LC864112 (9) Factory shipment : DIP52S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 33098HA (II) No. 5550-1/19
‘The LC86P4164 is provided for the first release and small shipping of the LC864100 series. Atusing, take notice of the followings. (1) Differences between the LC86P4164 and the LC864100 series Cee ee ramen Operation after reset The option is specified by degrees until The program is executed from OOH of the releasing 31ms after going to a'H' level tothe reset | program counter immediately after terminal, The program is executed from | going to a'H' level to the reset terminal. 00H of the program counter. Operating supply 45V to 6.0V 45V to 60V voltage range (Voo) Operating temperature =30 to +70°C =30 to +70°C range (Topr) Refer to ‘electrical characteristics’ on the semiconductor news. ‘The LC86P4164 uses the program memory area of 256 bytes from FFOOH to FFFFH to select the options. (2) Option The option data is created by the option specified program "SU86K.EXE”. The created option data is linked to the program area by the linkage loader "L86K.EXE”. (3) ROM space The LC86P4164 and LC864100 series use the program memory area of 256 bytes from FFOOH to FFFFH to select options. The program memory has 65280 bytes from 0000H to FEFFH. 19FFFFH [~ Charactr Character Character Character Character Character generator OM | | generator ROM | [generator ROM | | generater ROM | [generator ROM | [generator ROM creen Option specited | | Optenspecied | Open specited | | opfonspecitsd | [Optonspedted | option specified OFEFFH | #24256 bytes area 256 bytes aoa 256 bytes area 256 bytes area 256 bytes area 256 bytes OBFFFH "Se Ee Rey OFF Re Ry) Rae Ce ee oe i oo no nn ee ee LC864164 Lo864156 LC864148 Los64140 L0864132 LO864124 13FFFFH | Cheracter Character Cheracter generator ROM | | generatcr ROM |_| generator ROM OFFFFH | Optonspaciied | Option specifed | |Opicn specified area 256 bytes area 256 bytes area256 bytes a LC864120 Los64116 Lo864112 No, 5550-2/19
(1) Create a programming data for LC86P4164 Programming data for EPROM of the LC86P4164 is required. Debugged evaluation file (EVA file) must be converted to an INTEL-HEX formatted file (HEX file) with file converter program, SU86K.EXE. The HEX file is used as the programming data for the LC86P4164. (2) How to program for the PROM ‘The LC86P4164 can be programmed by the EPROM programmer with attachment; W86EP4164D. + Recommended EPROM programmer F045, Rous AF-9704 PKW-A100, PW. 2000 MODEL 18908 + "27010 (Vpp=12.5V) Intel high speed programming" mode should be adopted. The address must be set to "0 to 13FFFH" and a jumper (DASEC) must be set to OFF at programming. (3) How to use the data security function "Data security” is the function to disable the EPROM data from being read out. The following is the procedure in order to execute the data security function, 1, Set'ON' the jumper of attachment. 2. Program again. Then the EPROM programmer displays an error. The error means that the data security functions normally. It is not a trouble of the EPROM programmer or the LSI. Notes + Data security is not executed when the data of all address have 'FF’ at the procedure 2 above. + Data security cannot be executed by programming the sequential operation "BLANK=>PROGRAM=>VERIFY" at procedure 2 above. + Set the jumper to 'OFF after executing the data security. Data security Pe. “aa a ee 7 oe Jumper a Jumper ig “ae W86EP4164D pin4 No. 5550-3/19
pis Q 4 49 1} p04 pi4 5 4g} P03 pis 6 47) P02 pie Q 7 46 POL pi7/pwm UY gs 45 1 poo pvss Y 9 44} P73/INT3/TOIN cr1 0 10 43 } P72/INT2/TOIN or2 O a1 42) P71/INTI pvpp J 12 41 0 p70/INTO pso/ano Q 13 40 1 Pwmg po1/aN1 Q 14 39 0 PwMs po2/an2 Q i5 38 Df PWM7 p93/AN3 O 46 37 0 PwMe Res O a7 36 1 PwMS tcl Uf ig 35 D PwM4 te2 O a9 34 0 PWM3 FILT Y 969 33 1 PwWM2 AVDD 21 32 0 PWM avss ( 99 31 0 PwWMo CVIN J 93 30 ff BL VS O 24 29 1 B FS od 2s 28 fle I 0 26 270 R Top view No. 5550-4/19
Standby control contral fed OE DASEC G oF 5 G “as PROM(64KB) oe 2 2 —
5 Le ”
a el ee inn ae INTO to INT3 a osp CGROM Watch dog timer No. 5550-5/19
[Pirvane [Pawo | VO] Finclon desorpion [Onlin | __ PRON mode [ore | it | 0 | ouputteminaltoresramicresnator | OO [tor | tet | tc oscitation circuit input terminal ee | ice [19 [0 | tcosaitaton circuit output terminal ee avon | 21 | — | Positive power supply oranalogcieut || aves | 22 | — | Wagatve powersupplytoranatogcieut | | vs 24 Vertical synchronization signal input terminal HS 25 Horizontal synchronization signal input terminal [1 | 2 Jo J tmage intensity contol output ee
27 Red (R) output terminal of RGB image A4 (1)
G 28 Green (G) output terminal of RGB image AS (1) output
29 Blue (B) output terminal of RGB image A6 ("1)
BL 30 Fast blanking control signal AT (#1) Switch TV image signal and caption/ OSD image signal PWMO 31 to 40 PWM to PWM9 output terminal PWM0 to PWMB to PWM9 15V withstand AB to A16 (#1) PWM8 : “L" fixed Sn inpavounput pon Pultap resistor P00 to P07| 45to52] /O | Input/output can be specified in nibble unit Providedinot provided HOLD release input (in bit units) Interrupt input Output Format CMOS/Nch-OD (in bit units) 8-bit input/output port Output Format D0 to D7 (*2) P10 to P17 vo Input/output can be specified in bit unit. CMOS/Nch-OD Other functions (in bit unit) P10 | SIOO data output P11 | SIO0 data input /bus input/output P42 | S100 clock input/output P47 | Timer 1 (PWM) output Continued on next page. No. 5550-6/19
Continued from preceding page. PROM mode 4-bit input port Pull-up resistor P70 : VPP (*3) P70 41 Other functions provided/ P71: DASEC (#4) P71 toP73 | 42 to 44 P70 | INTO inputHOLD release input/ not revised te : = ne Nch-transistor output for watchdog (in bit units) (*6) timer P71 | INT? inpu/HOLD release input P72 | INT2 input/timer 0 event input P73 | INT3 input (noise rejection filter attached input/timer 0 event input Interrupt receiver format vector address iNTo wt [enable | enable | cisable | enabie_[ enable [oot | INTs | Porto | 4-bit input port A010 A3 (3) P90 to P93 | 13to 16 Other function AUD converter input port (4 lines) "1 An— Address input "2 Data /O "3 Power for programming *4 Memory select input/output for data security *5 Output Enable input *6 Chip Enable input © Allof port options except the 4-bit unit pull-up resistor option of Port 0 can be specified in a bit unit. * Port status during reset Pull-up resistor status at selecting pull-up option [Porto | __input__| _Pultup resistor OFF, ON after reset release [Pott | _input | _ Programmable pull-up resistor OFF L_Pot7 | input [Fixed pull-up resistor provided * AVDD and AVSS are the power supply terminals for built-in analog circuit while DVDD and DVSS are the power supply terminals for built-in digital circuit. Connect them like the following figure to reduce the mutual noise influence. LsI DvDD eed pe | “ || - AVDD Eza AVSS No, 5550-7/19
- Absolute Maximum Ratings at Ta = 25°C, Vss = 0 V Parameter | Symbol Ont vot) | min [ ye [max _| Supply voltage DvDD, AOD ovop=avoo | fos | | ero] v Input voltage vi(1) ° P71, 72,73 -0.3 Voo+0.3 * Porto * RES,HS,VS,CVIN ouput vorage | vot) [researreut{ | [os [| veotos | vote) | ewwororwme | Tf os ||| Inpuvoutput Vio(t) Ports 0, 1, P70 -0.3 Voo+0.3 voltage High- | Peak lopH(1) Ports 0, 1 * Pull-up MOS -2 mA level output transistor output output | current * Ateach pin current lopn(2) | Ports 0, 1 + CMOS output 4 + Ateach pin lorH(3) | -R,G,B, BL,I + CMOS output - + At each pin Ylow(@) | R,G,B, BL The total ofalpins | «| -15 | | tow [Peak | tontt) [rotsa1 | ateachin || TT 20 | fuput formem | -bae@ [ero | ateasnpin TT | output | current current lori) | © R,G,B, BL! Ateach pin 5 * PWMO0 to PWM9: Total [_ Bion t) Theteiaotanpins | | [Tao | curren | Pont.p70 | Thetotaotallpins _| output FS @) | Pont, Pr The tata oalipine | |_| | a0 | Sue) [Ro8.81 | teraacatrine | | | | 18 | Stout) | pwioioPwire | the caroatrine | | | | 20 | Maximum power DIP52S Ta =-30 to +70°C 430 | mw dissipation Operating Topr -30 +70 | °C temperature range Storage Tstg -55 +125 temperature range * DVSS and AVSS must be supplied the same voltage, Vss Ves = DVSS = AVSS DVDD and AVDD must be supplied the same voltage, Vop. Vop = DVDD = AVDD No. 5550-8/19
- Recommended Operating Range at Ta =-30°C to +70°C, Vss = 0V Paraneior Symba Pre ont Ceo [in| wr [mon Operating Voo | DYDD, AVDD 0.98 us < tCYC 45 55] Vv supply tCYC < 1.02 us voltage range Hold voltage Vio | DVDD, AVDD. RAMs and the 2.0 55 registers hold data at HOLD mode. Input high-level Vin(t) | Port 0 (Schmitt) Output disable 45t055| 0.6Voo| | _Voo| voltage Vin(2) | Port 1 (Schmitt) Output disable 4505.5 | 0.75Voo Voo + P72,73 -HSVS Vi(3) | ¢ P70 Output N-channel — [4.5 t0 5.5 | 0.75Vo0 Voo portinput / interrupt | transistor OFF *P71 +RES (Schmitt) vi(4) | P70 Watchdog timer | Output N-channel [4.5 105.5 | Vo0-0.5 Voo input transistor OFF vis) [or eporinpt | ast] ovo] | voo| Input low-level vit) | Porto (Schmitt) _| Output disable 451055] ves} | _0.2V00| voltage V2) |*Port1 (Schmitt) | Output disable 4505.5 Vss 0.25Voo + P72,73 HS VS + Port 9 Vi(3)— | * P70 port input / N-channel transistor | 4.5 to 5.5 Ves 0.25Vo0 interrupt OFF + P71 + RES (Schmitt ViL(4) P70 N-channel transistor | 4.5 to 5.5 Vss 0.6Voo Watchdog timer input | OFF vid) | Porto 4.51055 Vss 0.3Vo0 port input CVIN input Vein CVIN 5.0 0.7 2.3] Vp-p |x amplitude ti me wvo@) [| except ospiunation [astoss[oeef [20] * Vp-p : Peak-to-peak voltage No. 5550-9/19
[vem [on [op [na | Oscillation FmcF | CF1, CF2 12MHz (ceramic 451055 | 11.76 12 | 12.24 frequency range resonator oscillation) (Note 1) Refer to Figure 1 FmL¢ | Let, Lc2 14.11MHz 45 105.5 14.44 (LC oscillation) Refer to Figure 2. Oscillation tmsCF | CF1, CF2 12 MHz (ceramic 45 to5.5 0.02 02 | ms stable time resonator oscillation) period (Note 2 Refer to Figure 3. (Note 1) The oscillation constant is shown on Table 1 and Table 2. (Note 2) The oscillation stable time period means the time to oscillate stably after the following conditions. 1. Supplying voltage. 2. Release the HOLD mode. 3. Release stopping the main-clock oscillation. Refer to Figure 3 for details. No. 5550-10/19
- Electrical Characteristics at Ta =-30°C to +70°C, Vss = 0V Parameter | Symbol Unit [ves [ mim [ye [max | Input high-level tut) fe Portt * Output disable 45055 +] pa current + Port 0 without + Pull-up MOS pull-up MOS transistor OFF transistor * Vin = Vop (including the off-leak current of the output transistor) Ii(2)— |* Port 7 without Vin = Voo 451055 1 pull-up MOS transistor + Port 9 > RES _ + HS,VS Input low-level Wa) fe Port4 * Output disable 451055 -1 current + Port 0 without + Pull-up MOS pull-up MOS transistor OFF transistor * Vin = Vss (including the off-leak current of the output transistor) 1(2)— |* Port7 without Vin= Vss 451055 4 pull-up MOS transistor + Port 9 1.3) + RES Vin = Ves 451055 -1 | HS,VS Output high-level Vou(t) [CMOS output of low =-1.0 mA 45055] Voo-t Vv voltage Ports 0,1 we — “sees et || Output oweve fou = 10™mA [astoss] [| 8 | voltage Vou(2) [Ports 0, 1 *lo= 1.6 mA 45055 04 * The total current of the ports 0,1 is not over 40 mA Vo(3) f* RGB, BL! lo = 30 mA 45to55 04 + PWMO to PWM9 | « The current of any unmesurement pin is not over 3 mA Pull-up MOS + Ports 0,1 Vou = 0.9 Voo 45055 13 38 ka transistor + Port 7 resistance Output off- lore |PWMO to PWM9 Vour = 13.6 V 451055 5] pA leakage current Hysteresis Vist Ports 0.1 Output disable 45055 0.1 Voo v voltage > Port 7 > RES _ + HS,VS No. 5550-11/19
Parameter | Symbol Pins Unit [voor [min [ye | max _| Input clamp Veume CVIN 5.0] 23 | 25 27 v voltage Pin capacitance cP All pins *f=1MHz 4505.5 10 pF + Unmeasured input pins are set to Vss level *Ta= 25°C 4. Serial Input/Output Characteristics at Ta = -30°C to +70°C , Vss =0V Parameter | Synba Pins [Range] une [oot [min | yp | max | teKcy (1) |* SCKO Refer to Figure 5 ast55 | 2] |_| tcve * SCLKO Low- | tCKCY (1) 45t055 | 1 ye | level ‘3 | pulse 3 [T 3 [width £ | High- | tcKcy (1) 450055 | 4 level pulse y width 3 Cycle | tcKCY (2) Sonno Use é rt ne 45to5.5 | 2 z Low- | tcKCY (2) resistor (1k2) 4.51055 /2tCKCY B| ~ reve during open drain 8 output B | use + Refer to Figure 5. 5 [watn efer to Figure 5. 8 | High] tcKcy @) 4505.5 [2tCKCY level pulse width _ | Data set-up tick | Slo + Data set-up to SCKO | 4.5t05.5 | 0.4 bs a time rising Ba + Data hold from Data hold 5 lan tCKI SCKO rising 4505.5 | 04 a * Refer to Figure 5. Output delay} —tcKo(1) | SOO + Use a pull-up 451055 TAM2tCYC| ps time resistor (1 kQ) 40.2 5 | (External during open drain B| serial clock) output. | Output delay] — tcKoy2) + Data set-up to SCKO | 4.5 05.5 1/3tCYC § | time falling 402 (intemal + Data hold from serial clock) SCKO falling + Refer to Figure 5. No. 5550-12/19
- Pulse Input Conditions at Ta = -30°C to +70°C, Vss=0V Highiow level tPIH(1) * INTOINT1 | * Interrupt acceptable | 4.5 to 5.5 tcYc pulse width 4PIL(1) * INT2/TOIN | Timer0-countable tPIH(2) INTS/TOIN + Interrupt acceptable | 4.5 to 5.5 tPIL(2) (The noise + Timer0-countable rejection clock is selected to 1/1) tPIH(3) INTS/TOIN + Interrupt acceptable | 4.5t05.5 | 32 tPIL(3) (The noise + Timer0-countable rejection clock is. selected to 1/16) PIL) Reset acceptable [aswoss | 200 | | | as _| tPIH(5) HS, VS Display position 451055 10 tCYC controllable Each active edge of tPIL(S) HS, VS must be more than 1tCYC. Refer to Figure 7. Rising/alling time tTHL AS Refer to Figure 7. 4505.5 500 | ns tTLH pull-in range Figure 10 is 1/2 Von. 6. A/D Converter Characteristics at Ta = -30°C to +70°C, Vss=0V veut) | min [yp | max _| Conversion time tCAD From selecting | 1 bit conversion time | 4.51055 196 | us Vref to resulting | = 2tCYC Reference current nee (Regulate the ladder [4 5t055 10 20 | ma resistor) Analog input Vain ‘ANO to AN3 451055 | Vss Voo v voltage range current Vinzv. (Note 3) Absolute precision excepts quantizing error (+1/2 LSB). No. 5550-13/19
- Current Dissipation Characteristics at Ta = -30°C to +70°C , Vss=0V. Parameter | Symbol Unit [vem [mm | op | ma] Current dissipation] Iooor(1)_ |DVDD, AVDD + FmCF = 12 MHz 4505.5 24 32 | ma during basic Ceramic resonator operation oscillation (Note 4) + FmLC = 14.11 MHz LC oscillation + System clock CF oscillation + Intemal RC oscillation stops Current dissipation] lopvacr(1) |DVDD, AVDD * HALT mode 45 to5.5 5 10 | ma in HALT mode + FmCF = 12 MHz (Note 4) Ceramic resonator oscillation + FmLC = 0 Hz (oscillation stops) + System clock : CF oscillation * Intemal RC oscillation stops. lopHacr(2). |DVDD, AVDD * HALT mode 451055 400 800 HA + FmCF = 0 MHz (oscillation stops) * FmLC = 0 Hz (oscillation stops) + System clock : Internal RC Current dissipation] IppHo.0 | DVDD, AVDD * HOLD mode 45055 0.05 20 BA in HOLD mode + All oscillation stops. (Note 4) (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. No. 5550-14/19
- Both Cl and C2 must use an K rank (+10%) and an SL characteristics.
Table 1. Ceramic Resonator Oscillation Guaranteed Constant (main-clock)
14.11 MHz LC oscillation 27 pE 30 pF (Trimmer)
Table 2. LC Oscillation Guaranteed Constant (OSD clock) the oscillation pins as possible with the shortest possible pattern length.
- If you use other oscillators than those shown above, we provide no guarantee for the characteristics.
Requirements Prior to Mounting Notes on Handling * The construction of one-time microcontrollers in which the PROM is not programmed precludes Sanyo from fully testing them before they are shipped. The screening procedure described below is recommended in order to attain higher reliability after programming the PROM. * The nature of one-time microcontrollers in which the PROM is not programmed precludes us from fully testing them by writing all of the bits. Therefore, it is not possible for us to guarantee a write yield of 100%. * — Storage in moisture-proof packaging (unopened) While they are still in the moisture-proof packaging, these devices should be stored at a temperature of 30°C and a humidity of no more than 70%. * After opening the moisture-proof packaging These devices should be mounted and soldered as soon as possible after the moisture-proof packaging is opened. Once the moisture-proof packaging is opened, the devices should be stored at a temperature of 30°C and a humidity of no more than 70% for no more than 96 hours. a. Inthe case of models that are programmed by the user (models that are shipped with the PROM not programmed) DIP model Programming/verification Recommended screening procedure Exposure to high temperature without power| 150 +5°C, 24%) hours Confirmation that program can be read b. Requirements prior to mounting for models that are programmed by Sanyo (models that are shipped with the PROM already programmed) DIP model Il No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. I Anyone purchasing any products described or contained herein for an above-mentioned use shall: @ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD.,|, its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use @® Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. I Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5550-19/19