LC86104A

LC86104A SANYO | Alldatasheet

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Nh Liquid Crystal Display Controller/ SANYO Driver, On-chip 4K bytes ROM and On-chip 168 bytes RAM 8-BIT SINGLE CHIP MICROCOMPUTER LC86104A The LC86104A microcomputer is an 8-bit single chip microcomputer with the following On- chip functional blocks: ~ CPU: Operable at a minimum cycle time of 1 microsecond. - On-chip ROM: Capacity = 4K bytes - On-chip RAM: Capacity = 168 bytes - Dot matrix Liquid Crystal automatic display controller/driver - Two 16-bit timers/counters - Seven-source 5-level vectored interrupt system All of the above functions are fabricated on a single chip, General purpose applications: (1) Data bank control (2) Remote controlling for VCR, Tuner, and the like. (3) Controlling for CD, Tuner, and the like. (4) Controlling for small-sized measuring instruments Features: (1) Read-Only Memory (ROM): 4096 x 8 bits (2) Random Access Memory (RAM): 168 bytes. 128 x 8 bits for computation (general purpose RAM) and 40 x 8 bits for data display (display RAM) (3) Cycle time: Cycle time varies depending on system clock sources. The selectable system clock sources are shown in the table below. Oscillation fe) ti Ceramic(CF) oscillation| ~ lus specification 12MHz|4. 5~6. 0V Ceramic(CF)oscillation ~ 4us specification 3MHz | 2. 5~6. 0V SANYO Electric Co.,Ltd. Semiconductor Business Headquarters . TOKYO OFFICE Tokyo Bidg.,1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 6228TA,TS No.2967-1/61

(4) Current dissipation a. Basic system operation mode Current System clock Oscillation vltegee Remarks dissipation source frequency range 9.5mA TYP Soaciflcation oscillation) 1 omit z Display segments OFF ill 1.4mA TYP aera ston aMHz|2. ev] Display segments OFF Crystal (X'tal} oscillation Displ ments OFF and CF/RC b. HALT operation mode Current System clock Oscillation | Operating dissipation source frequency woikege Remarks 3mA TYP orem CAC oscillation 12MHz Display segments OFF 440uA TYP peaiicaton Hh] amHz | 2. 9v| Display segments OFF 1504A TYP 800KHz Display segments OFF Crystal (X'tal) oscillati Display segments OFF and CF/RC (5) Ports - Input/output ports: 5 ports (37 port pins) Input/output port software programmable in 8-bit unit: 1 port (8 port pins) Input/output port software programmable in single-bit unit: 4 ports (29 port pins) (6) Liquid Crystal Display Drivers - Common driver pins: 8 - Segment driver pins: 40 (Extendable to 200 segments with LC7930 x 4) - Display signal duty mode: Static duty cycle to 1/8 duty cycle - Display biasing mode: Static bias to 1/5 bias (7) On-chip character generator ROM - ROM capacity: 5600 bits - Character font: 5 x 7 dots (Max.) - Number of characters: 160 (8) Liquid Crystal Display control instruction - Cursor display ON/OFF/blinking . ~ Display character blinking - Display ON/OFF (9) Timer - Two 16-bit timers/counters software programmable Mode 0: 13-bit timers/counters Mode 1: 16-bit timers/counters Mode 2: 8-bit automatic reloadable timers/counters — No.2967-2/61

(10) Interrupt mechanism: - 7 sources and 5 vectored interrupts: External interrupt INTO External interrupt INT Timer/counter interrupt TO Timer/counter interrupt T1, and Divider/port 1/port 3 interrupt (11) Stack levels - 128 levels (Max.): Stack area included in the RAM area (12) Two oscillation circuits . - One for CF or RC oscillation: Generate the system clocks and Liquid Crystal Display clocks, Note that the CF oscillation or the RC oscillation can be selected by the mask option. - One for X'tal oscillation: Generate time base clock, Liquid Crystal Display clocks and the system clocks. (13) Liquid Crystal Display display data transfer rates - 2/Fef, 4/Fef, 8/Fef --- 256/Fef 2/Fxt, 4/Fxt, 8/Fxt --- 256/Fxt One of the display data transfer rates can be selected by the mask option, Note: The Fef indicates the oscillation frequency output by the CF oscillation circuit or the RC oscillation circuit. Note: The Fxt indicates the oscillation frequency output by the crystal (X'tal) oscillation circuit, Note: The frame frequency Ffrm for Liquid Crystal display can be gained in the following manner: Ffrm = 1/(display data transfer rate x total display dot number) (14) Standby function - HALT mode function The HALT mode is used to reduce power dissipation, In this operation mode, program execution is stopped. This operation mode can be released by interrupt request signals or the initial system reset request signal. - HOLD mode function The HOLD mode is used to freeze both of the CF/RC oscillation and crystal (X'tal) oscillation, It can be released by the system reset request signal or the "L" level input signal to the external interrupt pin (INTO). Program execution is started again after the HOLD mode is released by the input signal to the INTO pin. However, in this release operation, it should be kept in mind that program execution may enter abnormal state due to unstable oscillation. In order to prevent it, you can set a desired data in timer/counter 0 to generate a wait time period. The oscillation will become stable for this wait time period. (15) Factory shipment - Chip delivery form - QIP 100 delivery form No.2967-3/61

Development Support system The development support system for the LC86104A applications consists of the following support tools: (1) User's Manual LC86104A user's manual (2) Development support tool manual LC86104A development support too! manual (3) Development support tools (a) Tools for developing the LC86104A application programs - MS-DOS machine ~ Macro assemblers (M86104.EXE and L86104,EXE) - Mask option selections program (SU86104,EXE) (b) Tools for evaluating the LC86104A application systems - Evaluation (EVA) chip: LC86999 - Evaluation (EVA) chip board: TB86104 ~ Evaluation (EVA) kit: EVA510 Note: MS-DOS is a trademark of Microsoft Corporation. Note: The EVA510 board has the same function as the EVA410 board except for the monitor ROM. Outline of the development support system MS-DOS machine Vi a Pe a k ” / User application EVA chip board system board (EVA510-TB86104) EVA510 board No.2967-4/61

a Pin assignment TPONKONODTMNKONGMNANHKOnONTOANHO NAA AA AOD 090009 OD OO HH Ht tt AOD . OO DOA OOO OOO OO AA OO OO OOO OO OA OOOO DOONAN IRON APA OH ARN OANA HAA DOO OO SPF STHAH-OCHHROHCHA- OH BbPODT OA orrrrrrrPPrPr Pr OCHOKSLC SCHR ESTH KH HOR HH RH P1s5cyje s0I4C5 P 1 6cjee «mC6 P 1 7oes asc C7 RS Tose 67508 T lcgss ss™VDD T Qcj86 asV5 T 3cje7 ava XT Icjee asinv3 XT aces a2>ve2 VS Scqjps0 amvi CF icde: aoS40 CF ace 39839 PO Omes 38863538 PO Icdss 3798S 37 PO 2c)s 38S 36 PO 3cds6 sxn$35 PO 4ce7 sa$ 34 PO 5cjee 33™$ 33 PO 6c3ss s2imn$32 PO 7oh00 315831 HAM eH oho BOHA NH EDOKnROMOHNH TE EHRB AS Pee re ae ea UUUTUUCUUT UU UU TOU UU ANMPNONDHDOAANTNONDHOAAMNTNON OHO NNNANNNRNNY at ase QAAANAN AAA AOD NNNNNNNNNNNNNNVNNNNNNN Package Dimensions 3089-Q100ALSI (unit: mm ) 0.15 I

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O00000 OOOOOO0ROOOOOOCARooOO OOOO oO) Fp size Xx ¥) 868584 82 80 78 76 74 72 70 68 66 64 62 60 59 58 57 56 . fromm O87 83 81 79 77 75 73 71 69 67 65 83 61 Chip height 480um (88(s31) (?07)550) O89 540.)| Pad size Oso 530)| 1202mx 120¢m Os. 520 Qg2 510 (33 500] O94 490] O35 481] Oss O37 470 Oss Y Os9 (0,0) 460 Doo —-— Xx O101 (vss)451) D102 Hl (vpD) “a0 Oe 30) O33 42D O4 10 (5(c5) 400 390 380 (P16)3709 11 13°15 17 19 21 23 25 27 29 31 33 367 6 7 8 910 12 14 16 18 20 22 24 26 28 30 32 30 0 000 QOOOOOROOOoORoRoOORooOooOnDoO #0 Pad coordinate values Pin Pad Pin value Pad Pin value number|number] name number] name 46 1 VDD|—-2676/— 781] 56 11 )P41)-1697/-2011 47 2 C8 t - 941] 57 12 |P42|-1537 t 48 3 C7 t -1101] 58 13 |P43|-1377 J 49 4 cé J —-1261] 59 14 |P44|/-1217 i 50 5 cs J -1421) 60 15 |P45|-1057 J 51 6 C4 |~2676/-2011] 61 16 |P46/—- 897 q 52 7 C3 {|-2429 t 62 17 |P47|/- 737 t 53 8 C2 {|-2249 J 63 18 |P30|/- 577 1 54 9 C1 |-2068 { 64 19 |P31|/- 417 1 ee No.2967-6/61

Pad Pin value Pin Pad value number] name number | number} 66 21 |P33)- 97|-2011 7 62 S7 1425 2150 : 67 23 | P34 62 1 8 63 $8 1265 J 68 23 |P35 222 { 9 64 $9 1105 i 69 24 |P20 382 { 10 65 |S$10 945 J 70 25 | P21 542 { 11 66 |S11 785 4 71 26 | P22 702 st 12 67 |$12 625 J 72 | 27 | P23 862 J 13 | 68 |S$13 465 { 73 28 | P24 1022 { 14 69 |S14 305 { 74 29 | P26 1182 s) 15 70 |S$15 145 { 75 30 | P27 1342 { 16 71 |S16/— 15 { 76 31 |P10 1502 J 17 72 |}S17};- 175 { 77 32 |P1il 1662 1 18 73° |S18/- 335 1 78 33 | P12 1822 J 19 74 |S19/- 495 J . 79 34 | P13 2530/-2011] 20 75 |S20;- 655 1 80 35 | P14 J —-1838] 21 76 |S21}/- 815 t 81 36 | P15 t ~-1672)] 22 77 |S22)- 975 4 82 37 |P16 { -1505] 23 78 |}S231/-1135 { 83 38 | P17 4 -1339] 24 79 |S$24/-1295 t 84 39 | RST { -1160] 25 80 |S$25;-1455 i 85 40 Ti 4 —-1000] 26 81 |S$26}-1773 t 86 41 T2 t —- 840] 27 82 |}S$27/-1954 t 87 42 T3 t — 680] 28 83 |}S28);-2134 { 88 43 |XT1 t - 503] 29 84 |S$29/-2315 4 89 44 |XT2 { —- 343] 30 85 |S$301}-2495 t 90 45 |VSs { - 104 ~ 86 - —2676 2150 91 46 |CF1 t 128 - 87 - J 1838 92 47 |CF2 1 288); 31 88 |S31 t 1618 93 48 | P00 J 487} 32 89 |S$32 1 1458 94 49 |POl 1 647] 33 90 |S33 1 1298 95 50 | P02 { 807] 34 91 |S34 s 1138 96 51 | P03 t 967] 35 92 |S35 J 978 97 52 PO4 1 1127 36 93 $36 J 818 98 53 |P05 t 1287] 37 94 |S37 J 658 99 54 |P06 J 1447] 38 95 |S$38 J 498 100] 55 | P07 { 1607] 39 96 |S$39 at 338 1 56 $1 2530 2150; 40 97 1S$40 J 178 2 57 $2 2350 1 41 98 vil J 18 3 58 $3 2170 1 42 99 v2 { - 141 4 59 $4 1989 { 43 100] V3 1 - 301 5 60 $5 1809 J 44 1/101] V4 1 - 461 6 61 $6 1585 2150) 45 |102!/ V5 .|/-2676/— 621 Note: Test pins Tl and T2 should be left unconnected. Note: Test pin T3 should be connected with the Vpp pin. Note: The chip substrate should be connected with the Vsg pin or be left unconnect- ed, Note: Pin-to-pin soldering connection should be adopted in mounting the QIP 100 package onto the printed circuit board (PCB), Entire package dipping should be avoided for this purpose, No.2967-7/61

| vss | 90 [ourpue Should be connected with the negative supply voltage pin. | von | 46 | input | Should be connected with the positive supply voltage pin. POO 93 Input/ Eight-bit input/output port with internal pull-up transistors. | i output Data can be input/output from/to the port in 8 bits unit. P07 100 P10 76 Eight-bit input/output port with internal pull-up transistors. { | Input/ | Data can be input/output from/to the port in a single bit output| unit, P17 83 Port pins 76 to 79 can be also used as the external signal P10 76 Input | input pins: Pll 17 Input | TO: External signal input pin to timer/counter 0, P12 78 | Input T1: External signal input pin to timer/counter 1. P13 79 | Input INTO: External interrupt 0 input pin PI INTI: External interrupt 1 input pin P20 69 Input/ Seven-bit input/output port with internal pull-up transistors, J 1 P Data can be input/output from/to the port in a single bit p24 | 73 | Pt unit P26 74 P27 75 P30 63 Input/ Six-bit input/output port with internal pull-up transistors. J J npul Data can be input/output from/to the port in a single bit p35 | 6g | MPU) unit. P40 55 Eight-bit input/output port with internal pull-up transistors, | Hl Input/ | Data can be input/output from/to the port in a single bit output} unit. P47 62 Port pins 55 to 60 can be also used as the special output pins: P40 55 |Output] CLI: Latch signal output to external Liquid Crystal Display driver circuit P41 5 6 |Output| CL2: Shift signal output to external Liquid Crystal Display driver circuit P42 5 7 |Output} Do: Data signal.output to external Liquid Crystal Display driver circuit P43 5 8 |Output] M: Synchronization signal output to external Liquid Crystal Display driver circuit P44 5 9 | Output] ALM: Alarm signal output to the ALM output pin P45 60 [Output] PLS: Pulse signal output to the pulse output pin v1 41 1 | Enpet! | vot 1 i i V's 45 output | VO tage supply pins to Liquid Crystal Display drivers. cl 54 | i Output) Common driver pins to Liquid Crystal Display drivers. c8 47 Continued on next page. No.2967-8/61

—— eee Continued from preceding page. Pin name {Pin Vo Functional Description number $1 1 ! 1 Output} Segment driver pins to Liquid Crystal Display. $40 40 Reset signal input pin with an internal pull-up transistor. Output} Should be left unconnected, | tz | 86 | Output} Should be left unconnected, Should be connected with the Vpp pin. Crystal oscillation input pin. Should be connected with the Crystal XT1 88 Input (X'tal) resonator with a 32.768kHz frequency. Crystal oscillation output pin, Should be connected with the Crystal XT2 {X'tal) resonator with a 32.768kHz frequency. The internal 20pF capacitor is provided between the XT2 pin and the Vss pin. Ceramic oscillation input pin. Or RC (Resistor and Capacitor) oscillation CFl 91 in i put pin, | cre | 92 | Output Ceramic oscillation output pin, Or RC (Resistor and Capacitor) oscillation output pin, No.2967-9/61

a Functional block diagram Piz [] Pow =|] Pa Ce pie (} Ll poe P13 Q DDR {] pos = | Po[p pio HINT fran Hi poo rao thre Peau ie] [eS Hs r27 res cees ||| feeeolreon etre ppt ps2 Epon frou [ror | [Jee rat Blea] | fram Ira tH P28 pso Hint Anterrupt control ral pee [ees [re | pert P2t P20 eri 0

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cre 1 Yy? circult mire ha byte, Pa Ho Pae {) pas pa [pe Ts FE eB xT2 QQ) Pa Ho Pag SCR rh Pa. Ta 4 Divider ree OR Leer | a ee — Hy M2 |5 yoo d c— poh 34 iL °° ve DO 28 38 i i [] sz sei va Ch #& {] sao nF va T| 2% vs TH 38 vss (1) Acc ACCUMULATOR IE INTERRUPT ENABLE REGISTER B B REGISTER THOD —-TIKER/COUNTER MODE CONTROL REGISTER PS¥ PROGRAM STATUS WORD TCON ‘TIMER/COUNTER CONTROL REGISTER SP STACK POINTER TOH TIMER/COUNTERO HIGH BYTE TRL TABLE REFERENCE REGISTER LOW BYTE © TOL ——‘TIMER/COUNTERO LOW BYTE TRH TABLE REFERENCE REGISTER HIGH BYTE T1H TIMER/COUNTERI HIGH BYTE PO PORTO LATCH TIL ——‘TIMBR/COUNTERI LOW BYTE PODDR PORTO DATA DIRECTION REGISTER PCON PORER CONTROL REGISTER Pl PORT1 LATCH PC PROGRAM COUNTER PIDDR PORT DATA DIRECTION REGISTER IR INSTRUCTION REGISTER PLINT PORT INTERRUPT REGISTER NCR MODE CONTROL REGISTER P2 PORT2 LATCH CPR CHARACTER PITCH REGISTER P2DDR — PORT2 DATA DIRECTION REGISTER CNR CHARACTER NUMBER REGISTER P3 PORT LATCH TDR ‘TIME DIVISION REGISTER PSDDR PORTS DATA DIRECTION REGISTER CAR CURSOR ADDRESS REGISTER PSINT PORTI INTERRUPT REGISTER DR DISPLAY RAK Pd PORT LATCH CGROM CHARACTER GENERATOR ROM P4DDR PORT DATA DIRECTION REGISTER ACR ALARM CONTROL REGISTER P4SCR PORT4 SIGNAL CHANGE REGISTER DCR —DIVIDER CONTROL REGISTER No.2967-10/61

1) Program memory (ROM) space The LC86000 series microcomputers have a program memory (ROM) space of 64K bytes. | (2) Data memory (RAM) space | The LC86000 serles microcomputers have a data memory (RAM) space of 512 bytes. The 512-byte RAM area can be functionally divided into the two areas: 256-byte data memory (RAM: 000H to OFFH)) and 256-byte specal function register (SFR) area (100H to 1FFH). The 256-byte RAM area includes the stack area and the SFR area contains the accumulator (ACC), the program status word (PSW), timers, ports and the like. The SFR area allows the LC86000 serles microcomputers to employ the full memory mapped 1/O architecture, The first 4 address areas (00H to 03H) in the data memory (RAM) can be used as the four 8-bit indirect address registers for allowing the user to make an access to the RAM tn the thdirect address mode. Of the above 4 indirect address registers, the first two registers with addresses 00H and 01H are used when the RAM area between address 00H and FFH is indirectly accessed. The remaining two Index registers are used when the SFR area between address 100H and address IFFH is indirectly accessed, Bits 3 and 4 of the program status word (PSW) can be used with the indirect address registers to select 4 RAM banks. The relattonship between the Indirect address registers, bits 3 and 4 of the PSW and the RAM addresses is shown in the table below. Indirect Bes os address RAM is Function register | ro | oon | Indirect RAM addressing Indirect RAM addressing | re | oem | Indirect SFR addressing Indirect SFR addressing | ro | oan | Indirect RAM addressing Rl 05H Indirect RAM addressing | ro | sn | Indirect RAM addressing port [| osm | Indirect RAM addressing OBH Indirect SFR addressing | ro | ocu | Indirect RAM addressing Indirect RAM addressing 1 1 | rz | oew | Indirect SFR addressing Indirect SFR addressing No.2967-11/61

———eeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSssSssSsSsSsSMMMSsFFMFMMeeee value The program counter (PC) is a 16-bit register. It is used to point to the address in the program memory (ROM), which stores the next instruction to be executed. Normally, the content of the program counter (PC) is incremented by 1 each time one instruction is ' executed. However, the PC register will be loaded with predefined address data when branch instruction or subroutine instruction is executed in your application program. In addition to this, the PC content will change according to interrupt requests and the initial reset request. The table below shows the contents of the program counter (PC) when the above mentioned operations are performed. External interrupt 0 0003H Timer/counter 0 interrupt O00OBH External interrupt 1 0013H Timer/counter 1 interrupt 001BH Divider circuit/port 1/ port 3 interrupt 0023H JMP al2]{PC15~12=Current page, PC11\\00=a12 Unconditional | J MP F al6|]PC15~00=a16 branching CALL al2}PC15~12=Current page, PC11~00=a12 Subroutine all _ operation CALLF a1l6|]PC15~00=al16 CALLR r16]} (PC+2) + (0~+65536) Note: The current page indicates the page area storing the instruction to be executed next. i Initial reset The program memory is a 4K-byte ROM (4096 x 8 bits). It stores a user application program to be executed on the LC86104A microcomputer. The whole content of the program memory (ROM) can be referenced by using the LDC instruction. No.2967-12/61

=) SSS value OOH |: RAM 1 Read/Write Data memory Unpredictable . 7FH The data memory is a 128-byte static RAM (128 x 8 bits). The first four bytes . (00H to 03H) of the RAM are used as the indirect address registers for indirect addressing, The first two indirect address registers (00H and 01H) of the four are used for indirect RAM addressing and the remaining two registers (02H and 03H) for indirect special function register (SFR) addressing. In addition, these indirect address registers can be used with bits 3 and 4 of the program status word (PSW) to select 4 banks, value MSB LSB ACC7 ACC6 ACCS ACC4 ACC3 ACC2 ACC1 ACCO . The accumulator (ACC) is a register used for calculation (logical or arithmetic), data transfer and data input/output. Note: If the current content of the accumulator (ACC) is transferred to the ACC itself, the data in the accumulator (ACC) will be destroyed, For example, this may happen if you use the LD ACD instruction in your application program. SSS No.2967-13/61

cy: Carry flag The carry flag (CY) is a flag which is set or reset when arithmetic operation is carried out, The carry flag (CY) will be set when an addition type instruction is executed in your application program and then a carry from the most significant bit (MSB) occurs. it will be | reset when an addition type instruction Is executed in your application program but a carry from the most significant bit (MSB) does not occur. The carry flag (CY) will be set when a subtraction type or comparison type instruction is executed in your application program and a borrow to the most significant bit (MSB) occurs.! It will be reset when a subtraction type or comparison type instruction is executed in your application program and a borrow to the most significant bit (MSB) does not occur. In addition, the carry flag (CY) will be affected when a carry-through rotation type instruction is executed in your application program. It will be reset when an ~ multiplication/division type instruction is executed in your application program. ' AC: Auxiliary Carry Flag The auxiliary carry flag (AC) is a flag which is set or reset when arithmetic operation instruction is executed in your application program. The auxiliary carry flag (AC) will be set when an- addition type instructiois executed in your application program and a carry from the third bit occurs. It will be reset when an addition type instruction is executed in your application program but a carry from the third bit does not occur, The auxillary carry flag (AC) will be set when a subtraction type instruction is executed in your application program and a borrow to the third bit occurs. It will be reset when a subtraction type instruction is executed in your application program but a borrow to the third bit does not occur, IRBK1: Indirect address register bank 1 IRBKO: Indirect address register bank 0 These two bits (IRBKO and IRBK1) of the program status word (PSW) are used to select 4 bank values for the Indirect address registers, As previously stated, the first 4 bytes of the RAM are used as the four indirect address registers for indirect addressing. Bits IRBKO and IRBK1 can be jointly used with these four indirect address registers to make an indirect access to an address In a selected RAM bank area, For detailed information, please refer to Memory Space, OV: Overflow flag The overflow flag (OV) is a flag which is set or reset when an addition type or subtraction type instruction with signed variables is executed in your application program. The overflow flag (OV) will be set when an addition type or subtraction type instruction with signed variables is executed In your application program and an overflow error then occurs. Otherwise it will be reset. The overflow flag (OV) will be set when a multiplication type instruction is executed in your application program and the resulted product exceeds 256, It will be reset if the resulted product is less than 256, In addition, the overflow flag (OV) will be set when a division type instruction is executed in your application program and the divisor is "0", Otherwise, it will not affected. No.2967-14/61

MSB LSB : Per [se [es [os [os | [i] | The B register is paired with the accumulator (ACC) and then used when a multiplication type or division type instruction is executed in your application program. In other operations, this register can be used as a general purpose register. reset_value ; Table reference register MSB LSB TRL7 TRL6 TRLS TRL4 TRL3 TRL2 TRL1 TRLO The table reference register low-order byte is used to hold the low-order byte of a ROM address specified by the LDC instruction, This 8-bit register can be used as a general purpose register when any instruction other than the LDC instruction is executed in your application program, Initial reset . Table reference register MSB LSB TRH7 TRH6 TRHS TRH4 TRH3 TRH2 TRH1 TRHO The table reference register high-order byte is used to hold the high-order byte of a ROM address specified by the LDC instruction. This 8-bit register can be used as a general purpose register when any instruction other than the LDC instruction is executed in your application program. No.2967-15/61

MSB ; LSB The stack pointer (SP) is incremented by 1 when the PUSH instruction is executed in your application program. It is decremented by 1 when the POP instruction is executed in your application program, The stack pointer (SP) is incremented by 2 when the CALL instruction is used in your application program. It is decremented by 2 when the RET instruction is executed in your application program, The stack pointer (SP) will be incremented by 2 when an interrupt request is accepted by the system, and will be decremented by 2 when the RETI instruction is executed at the end of the interrupt servicing routine. Note that the RETI instruction is used to transfer program execution back to the main routine from the interrupt service routine. The stack pointer value will become unpredictable at power on, Therefore, you should set an appropriate value in the stack pointer within the initial routine after power is applied. No.2967-16/61

= = = = Preene [reo recon] PCON2: Power control register bit 2 a 0: Disable the INTO HOLD mode release request. Note that the INTO request signal becomes active when the L level voltage is applied to the P12 pin. 1: Enable the INTO HOLD mode release request. Note that the INTO request signal becomes active when the L level voltage is applied to the P12 pin. In this case, program execution will start when timer/counter 0 outputs an overflow signal. As stated in the preceding paragraph, the overflow signal from timer/counter 0 will start the program execution. Therefore, timer/counter 0 can be used to prevent program execution from entering abnormal state when it is restarted immediately after the HOLD mode is released. For this purpose, you have to set an appropriate data in timer/counter 0 in advance, As a result, program execution will be restarted after the wait time period defined by the data in timer/counter 0 elapses. Note that the oscillation stabilization time period requires such wait time period. PCONI: Power control register bit 1 0: Disable the HOLD mode request. 1: Enable the HOLD mode request. The HOLD mode stops both of the CF/RC oscillation circuit and the X'tal oscillation circuit. The microcomputer is allowed to operate in the low current dissipation mode. That is, only the leakage current operates the LSI. The HOLD mode can be released by the reset request signal or by applying L level voltage to the INTO (P12) pin with PCON2 = 1. In this case, the HOLD mode should be selected after all the interrupt requests are disabled. If you fail to follow this procedure, program may enter abnormal run state. Please keep it in mind. PCONO: Power control register bit 0 0: Disable the HALT mode request. 1: Enable the HALT mode request. The HALT mode stops the program execution. This mode can be released by the reset request. It can be also released when an interrupt request is accepted by the system. eee No.2967-17/61

. Initial Pree = [= Dee Does [ier [aes [ee IE7: Interrupt enable control register bit 7 0: Disable all the interrupt requests. 1: Enable all the interrupt requests selected by bits IE4 to IEO. IE4: Interrupt enable control register bit 4 0: Disable an interrupt request from the divider circuit, port 1 or port 3. 1: Enable an interrupt request from the divider circuit, port 1 or port 3, --- Vectored address 23H IE3: Interrupt enable control register bit 3 . 0: Disable the interrupt request from timer/counter 1. 1: Enable the interrupt request from timer/counter 1. --- Vectored address 1BH IE2: Interrupt enable control register bit 2 0: Disable the external interrupt 1 request. 1: Enable the external interrupt 1 request. --- Vectored address 13H IEi: Interrupt enable control register bit 1 0: Disable the interrupt request from timer/counter 0. 1; Enable the interrupt request from timer/counter 0. --- Vectored address 0BH IEO: Interrupt enable control register bit 0 0: Disable the external interrupt 0 request. 1: Enable the external interrupt 1 request. --- Vectored address 03H Note: Some interrupt request flags are automatically reset or others are not automatically reset when interrupt requests are accepted by the system. These flags are as follows: Interrupt flags to be automatically reset: Timer/counter control register bit 7 (interrupt request by timer/counter 1) Timer/counter control register bit 5 (interrupt request by timer/counter 0) Timer/counter control register bit 3 (external interrupt 1) --- Falling edge detection mode Timer/counter contro! register bit 1 (external interrupt 0) --- Falling edge detection mode Interrupt request flags not to be automatically reset: Timer/counter control register bit 3 (external interrupt 1) --- L level detection mode Timer/counter control register bit 1 (external interrupt 0) --- L level detection mode Divider circuit control register bit 1 (interrupt from the divider circuit) Port 1 interrupt register bit 1 (interrupt from port 1) Port 3 interrupt register bit 1 (interrupt from port 3) Note: Timer/counter interrupt detection mode from the falling edge detection and L level signal detection modes is selected by software. No.2967-18/61

—SSSSSSSSSSSSSSSSSSSsssSS Initial TCON7: Timer/counter control register bit 7 Timer/counter control register bit 7 is set when timer/counter 1 outputs an overflow signal and then automatically reset when an interrupt servicing routine is started, TCON6: Timer/counter control register bit 6 0: Stop the timer/counter 1 operation. 1: Start the timer/counter 1 operation, TCONS: Timer/counter control register bit 5” | Timer/counter control register bit 5 is set when timer/counter 0 outputs an : overflow signal and then automatically reset when an interrupt servicing routine is . started, TCON4: Timer/counter control register bit 4 0: Stops the timer/counter 0 operation. 1: Start the timer/counter 0 operation, TCONS: Timer/counter control register bit 3 Timer/counter control register bit 3 is set when an external interrupt request signal from the INTI pin is generated and then automatically reset when the interrupt servicing routine is started. Please note keep it in mind that this bit is automatically reset only when the falling edge detection mode has been se- lected, TCON2: Timer/counter control register bit 2 Timer/counter control register bit 2 is used to select a desired INTI interrupt detection mode from the falling edge detection and L level signal detection modes. 0: Select the L level signal detection mode. 1: Select the falling edge detection mode. The H level signa! before the interrupt request and the L level signal for triggering an interrupt should remain active for more than one machine cycles. TCONI: Timer/counter control register bit 1 Timer/counter control register bit 1 is set when an external request signal from the INTO pin is generated and then automatically reset when the interrupt servicing routine is started. Please note this bit is automatically reset only if the falling edge detection mode has been selected. TCONO: Timer/counter contro! register bit 0 Timer/counter control register bit 0 is used to select a desired INTO interrupt detection mode from the falling edge detection and L level signal detection modes. 0: Select the L level signal detection mode. 1: Select the falling edge detection mode. The H level signal before the interrupt request and the L level signal for triggering an interrupt should remain active for more than one machine cycles. No.2967-19/61"

TMOD7: Timer/counter mode control register bit 7 ! Timer/counter mode control register bit 7 is used to specify a desired input pulse to the timer/counter 1 gate. 0: Select the unconditional pulse input to the timer/counter 1 gate, 1: Select the conditional pulse input to the timer/counter 1 gate. In this case, pulses are input to timer/counter 1 only if the INTI (P13) = H level. Otherwise, they are not input to the timer/counter 1 gate. TMOD6: Timer/counter mode control register bit 6 Timer/counter mode control register bit 6 is used to select the operation mode of timer/counter 1 from the timer operation and counter operation. 0: Select the timer operation mode. In this operation mode, timer/counter 1 will increment its value by 1 each machine cycle. 1: Select the event counter operation mode, In this operation mode, timer/counter 1 will count up the input clocks from the T1 (P11) pin. TMODS: Timer/counter mode control bit 5 TMOD4: Timer counter mode register bit 4 [ws [Tons [rmon4 [rien tae | 0 0 0 13-bit timer/counter 1 0 1 16-bit timer/counter 2 1 0 8-bit reload timer/counter TMOD3: Timer/counter mode control register bit 3 Timer/counter mode control register bit 3 is used to specify a desired input pulse to the timer/counter 0 gate. 0: Select the unconditional pulse input to the timer/counter 0 gate. 1; Select the conditional pulse input to the timer/counter 0 gate. In this case, pulses are input to timer/counter 0 only if the INTO (P12) = H level. Otherwise, they are not input to the timer/counter 0 gate. TMOD2: Timer/counter mode control register bit 2 Timer/counter mode control register bit 2 is used to select the operation mode of timer/counter 0 from the timer operation and counter operation. 0: Select the timer operation mode, In this operation mode, timer/counter 0 will increment its value by 1 each machine cycle, 1; Select the event counter operation mode. In this operation mode, timer/counter 0 will count up the input clocks from the TO (P10) pin. TMODI: Timer/counter mode control bit 1 TMODO: Timer counter mode register bit 0 0 0 13-bit timer/counter 1 0 16-bit timer/counter 2 1 8-bit reload timer/counter No.2967-20/61

Pron [rien] Reanie [Reromer sumaceroe [vow | Operation modes (selectable by bits TMODO and TMOD1) (1) Mode 0 (13-bit timer/counter) MSB LSB ron [se [ni [vo [oo [ee [or [oe] on t (2) Mode 1 (16-bit timer/counter) MSB LSB row [as [os fas [oe [a] ie [os [oe t rou [or] os] os] e+] os [oz | or | 00 | (3) Mode 2 (8-bit reload timer/counter) MSB LSB 1 { t I 1 { t t No.2967-21/61

[ome [eee nasties [rie [rian reare [aeronme visas foot] se ee [rin [itsn] aaa [nmwrommer annie me [oo Pe [roe [rine [sins [rine [ome [ina [vans | ron | Operation modes (selectable by bits TMOD4 and TMOD5) (1) Mode 0 (13-bit timer/counter) MSB LSB vin [ie [ar [oe [oe [oe [or [oe [os | , 1 me (TD Teter Teer [oe] (2) Mode 1 (16-bit timer/counter) MSB LSB na Gspe pele [ape] : T nu [or [ooo [ols fo [ai] oe] (3) Mode 2 (8-bit reload timer/counter) MSB LSB vin [or [oo [os [os [os [oe Dor] oo] 4 1 t { t 4 t 1 vu [or [ooTos[oe[os [oe] or] v0] 9 2967-22161

Symbol Read/Write | Name Initial | reset value | po | 140H]| Read/Write Port 0 latch : MSB LSB [ror [roe [res | roe] ros | roe [vi | roe | Initial PODDR]141H Port 0 data direction register MSB LSB The port 0 data direction register is used to select a desired port 0 operation mode from the input and output modes in a byte unit. PODDR 0: Input mode 1; Output mode Note: This register cannot be accessed by a bit manipulation instruction. [vf Q n a n PDP Oo °O wv °o n . ao mm ou a “BR & * VDD f 5 . ly Option ryt s d ] ca 0° R ° |_| L Q ai > | c_Q re CHT IBUS: Internal bus fe IRES: Initial reset pulse bs PLS; Port latch select RPO: Port 0 Read WPODDR: Port 0 DDR Write No.2967-23/61

| pi [isan Read/Write Port 1 latch MSB LSB pet [ee Dre [ee [es [re Den [rie The following port 1 pins can be used for special signal input. Port Special signal input P13 External interrupt signal input (INT1) P12 External interrupt signal input (INTO) Pil External clock input to Timer/counter 1 (T1) P10 External clock input to Timer/counter 0 (TO) Initial . Port 1 data direction MSB LSB P17 P16 P15 P14 P13 P12 Pll P10 DDR DDR DDR DDR DDR DDR DDR DDR The port 1 data direction register is used to select a desired port 1 operation mode from the input and output modes in a single bit unit, P1IXDDR (X: 0 to 7) 0: Input mode 1: Output mode Note: This register cannot be accessed by a bit manipulation instruction. reset_value . Port 1 interrupt control MSB LSB PIF: Port 1 interrupt flag The port 1 interrupt flag is set when an L level signal is applied to an input port pin of port 1. In this case, the input port pin of port 1 should be set to the input mode in advance. In addition, the port output latch, and port 1 interrupt control bit PIC should be also set beforehand, PIC: Port 1 interrupt control bit 0: Disable the interrupt from port 1. 1: Enable the interrupt from port 1, No.2967-24/61

o (a) na n Daag” ~ n aa wa ow a 4 4 m [re A. = VDD ff Ss ly -Option _ | fie d ol c_Q O R s L Q ai > | c_Q O TS RO MW e & e) a: U au a. T ] a TL] rt LQ Interrupt request signal | c R Q IBUS : Internal bus IRES : Initial reset pulse <] PLS : Port latch select re] WP1 : Port 1 Write Ss WPIDDR : Port 1 DDR Write WPIINT : PIINT Write LQ RPI : Port 1 Read rit —_ RPIINT : PIINT Read i C_Q cs ee No.2967-25/61

LC86104A ; A Initial | p2 | 148H]| Read/Write Port 2 latch 11x11111B MSB LSB Pear [eve [= [ree [ees [ pee [en] ree | Initial P2DDR{149H] Write only Port 2 data direction register 00x00000B MSB LSB P27 P26 P24 P23 P22 P21 P20 DDR DDR DDR DDR DDR DDR DDR The port 2 data direction register is used to select a desired port 2 operation mode from the input and output modes in a single bit unit. P2XDDR (X: 0 to 4,6,7) 0: Input mode 1; Output mode Note: This register cannot be accessed by a bit manipulation instruction, om [a} n a n :

2 N AN A nN n

aan ou ro) "= B- « ra VDD fi S ly Option O ri. s | ] _ q c_Q O R ; |_| L Q Sai Ta) | c_Q © CNT ey IBUS : Internal bus fai IRES : Initial reset pulse PST] | PLS : Port latch select RP2 : Port 2 Read WP2 : Port 2 Write WP2DDR : Port 2 DDR Write ' ; No.2967-26/61

symbol | Address } Read/Write Initial reset value MSB LSB Initial P3DDR]14DH] Write only Port 3 data direction register xXx000000B MSB LSB | P35 P34 P33 P32 P31 P30 | DDR DDR DDR DDR DDR DDR | The port 3 data direction register is used to select a desired port 3 operation mode from the input and output modes in a single bit unit. P3XDDR (X: 0 to 5) 0: Input mode 1: Output mode Note: This register cannot be accessed by a bit manipulation instruction. Symbol | Address | Read/Write | Name Initial reset value P3INT|14EH Port 3 interrupt control register MSB LSB ee ee P3F: Port 3 interrupt flag The port 3 interrupt flag is set when an L level signal is applied to an input port pin of port 1. In this case, the input port pin of port 3 should be set to the input mode in advance. In addition, the port output latch, and port 3 interrupt control bit P3C should be also set beforehand, P3C: Port 3 interrupt control bit 0: Disable the interrupt from port 3. 1; Enable the interrupt from port 3, : No.2967-27/61

[29] na n Do mM is) n oan aw foe) i) “ [va a = VDD || Ss LY Option Pi. = |» 5] _ e c_Q 0 R Ss ane ct TY) TAT aw TT & & O - J i) o ou ou i a TL rT L Q Interrupt request signal c Oo | R IBUS : Internal bus IRES : Initial reset pulse PLS : Port latch select Ty WP3 : Port 3 Write Ss WP3DDR : Port 3 DDR Write LQ WP3INT : P3INT Write mi RP3 : Port 3 Read Cc Qa RP3INT : P3INT Read || pe q No.2967-28/61

MSB LSB | pear | ras | ras | res | eee | rae | ores | peo | The following port 4 pins can be used for special output function. Port pin Special output function P45 Pulse output pin P44 Alarm output pin P43 External Liquid Crystal Display driver output pin (synchronization signal output M) P42 External Liquid Crystal Display driver output pin (data signal output DO) P4i External Liquid Crystal Display driver output pin (shift signa! output CL2) P40 External Liquid Crystal Display driver output pin (latch signal output CL1) Initial P4DDR]151H] Write only Port 4 data direction register MSB LSB P47 P46 P45 P44 P43 P42 P41 P40 DDR DDR DDR DDR DDR DDR DDR DDR The port 4 data direction register is used to select a desired port 4 operation mode from the input and output modes in a single bit unit. P4XDDR (X: 0 to 7) 0: Input mode 1: Output mode Note: This register cannot be accessed b;y a bit manipulation instruction, ” _ No.2967-29/61

Port 4 output signal selecti MSB LSB P45 P44 P40 SCR SCR SCR P45SCR: P45 output signal selection bit : 0: Select the P45 port latch output. 1: Select the pulse signal output. P44SCR: P44 output signal selection bit 0: Select the P44 port latch output. 1; Select the alarm signal output. P40SCR: P40 -P43 output signal selection bit P40~P43 P40SCR] Output signal P43 0 Select the P43 port latch output.

1 Select the external Liquid Crystal Display driver output

(synchronization signal output M). P42 0 Select the P42 port latch output. (data signal output DO), P41 0 Select the P41 port latch output. {shift signal output CL2). P40 0 Select the P40 port latch output. (latch signal output CL1). Note: If you are to select the external Liquid Crystal Display driver output, please reset bit 0 of the mode control register to activate the character display mode. Note: This register cannot be accessed by a bit manipulation instruction, No.2967-30/61

[sj Qa Co na n Lo) aa ¢ a ¢ nn aa & a t A . - FE Bs om om A VDD i s ly LY Option ><J So O Se sit | cle pg | 0 R s Pes g AL a ri) PJ CHER IBUS : Internal bus p<] IRES : Initial reset pulse BT] PLS : Port latch select RP4 : Port 4 Read wPp4 : Port 4 Write Port 4 structure WP4DDR : Port 4 DDR Write P4SCR__: Port 4 output signal select Symbol | Address | Read/Write Name Initial reset value 180H a Read/Write | Display RAM Unpredictable LA7H The display RAM ts a static RAM with a capacity of 40 bytes (40 x 8 bits). The liquid Crystal Display driver clrcult receives the display data from the display RAM and then generates dot matrix Liquid Crystal Display driver signals. There are two types of Liguld Crystal Display modes available on the LC86104A microcomputer: Graphic display mode and | Character display mode. In the graphic display mode, every single bit of the display RAM can be used to turn on/off a single Liquid Crystal Display dot, In the character display mode, the Internal character generator ROM Is used to output @ predefined dot character pattern to the Liquid Crystal Display driver circuit after recelving a character code already stored In the display RAM from the Liquid Crystal Display control circuit. A Initial Symbol | Address | Read/Write Name reset value CG Character generator ROM ROM The character generator ROM (CGROM) {s a 5600-bit ROM used in the character display mode. The Liquid Crystal Display control circult receives a character code already stored in the display RAM and then transfers it to the character generator ROM. The character generator ROM generates the corresponding dot pattern according to the character code output by the control circuit. Finally, the Liquid Crystal Display driver circult generates a dot matrix Liquid Crystal Display driver signals to display a desired character on the panel, The character generator ROM (CGROM) contents can be defined by the user, That 1s, you can set up to 160 types of character patterns in the character generator ROM (CGROM). Please note that each character pattern should have a character font of 5 x 7 dots (Max.). No.2967-31/61

Symbol | Address| Read/Write | Name Initial reset value 1E0H| Write Only | Mode control register Xxxx0000B , MSB LSB | MCR3: Mode control register bit 3 0: Place the Liquid Crystal Display in the OFF state. In this case, the supply voltage pins (V1 to V5) for Liquid Crystal Display are electronically connected with the Vpp pin. The common driver pins (C1 to C8) and segment driver pins (S1 to S40) are also electronically connected with the Vpp pin. 1; Place the Liquid Crystal Display in the ON state. In this case, you can output a desired signal to the common driver pins (C1 to C8) and the segment driver pins (S1 to S40) by electronically connecting the V5 supply voltage pin to the Vss pin, To control display brightness, add a resistor between the V5 pin and the VsSpin. MCR2: Mode control register bit 2 MCRI: Mode control register bit 1 Mode control register bits 1 and 2 (MCRI and MCR2) are used to control cursor display operation. The cursor display operations are shown in the table below. Note that these two bits can be effective only in the character display mode (MCRO = 0). MCR2|mMcR1| Cursor Blink Descripti display tn escription (0 | o | or | - | Place the cursor display operation in the OFF state, Place the cursor display operation in the ON 1 ON state. The cursor is displayed under the display character specified by the cursor address register (CAR). The display character specified by the cursor

1 OFF ‘Character address register (CAR) will blink, Black-White

blinking mode. The cursor is displayed under the display 1 1 ON Cursor | character specified by the cursor address register {CAR) and then blinks, MCRO: Mode control register bit 0 0: Character display mode The character display mode uses an internal character generator ROM to generate a desired dot pattern. The dot pattern is generated according to a character code . stored in the display RAM. 1: Graphic display mode Each bit of the display RAM is used to turn on or off a single dot of the Liquid Crystal Display panel. Note: This register cannot be accessed by a bit manipulation instruction. No.2967-32/61

Symbol | Address ad/Write Initial . v1 . Read/W. reset value < 1E1H] Write Only | Character pitch register x000xX000B MSB : LSB | = | CPR6 CPRS CPR4 | - | CPR2 CPR1 CPRO CPR6: Character pitch register bit 6 CPRS: Character pitch register bit 5 CPR4: Character pitch register bit 4 Character display mode: These character pitch register bits are used to specify the number of bits per character in the vertical direction (Vp). Graphic display mode: These character pitch register bits have no significance, The table below shows the relationship between the combinations of these bits and the vertical number of bits per character, poe pope tT Po fo fa foe | Po fa fof os | pepe taf os Po fa fo fot | CPR2: Character pitch register bit 2 CPRI: Character pitch register bit 1 CPRO: Character pitch register bit 0 Character display mode: These character pitch register bits are used to specify the number of bits per character In the horlzontal direction (Hp). Graphic display mode; These character pitch register bits are used to specify the effective number of display bits of each display RAM address, The table below shows the relatlonship between the combinations of these bits and the number of bits (Hp). po [ o | o | Not assigned, Fo [a | o | Not assigned. Po feta fos peta taf | Note: Hp values 1 through 3 cannot be specified. Please keep it in mind, Note: This register cannot be accessed by a bit manipulation instruction, No.2967-33/61

1E3H{ Write Only | Character number register Xx000000B MSB LSB |= [~ [ewes [ones | ewes | onra | cnmi | enee CNRS: Character number register bit 5 q | CNRO: Character number register bit 0 Character display mode: These character number register bits are used to specify the number of characters in the horizontal direction... Graphic display mode: These character count register bits are used to specify the number of bytes in the horizontal direction (Hn), The total number of dots in the horizontal direction can be calculated by (Hp x Hn). The table below shows the relationship between the combinations of these bits and Hn, CNRS |CNR4}CNR3]CNR2/CNR1]|CNRO pepe tote totota| pe fe foe foto fate pete Peto tite e | po fe |e fa fe Pe se | po fe Pepe ta fo fee | Pete toe Pet Ts fee | Note: This register cannot be accessed by a bit manipulation instruction. No.2967-34/61

1E4H] Write Only Time division register xXXXxXx000B MSB LSB TDR2: Time division register bit 2 TDRI: Time division, register bit 1 TDRO: Time division register bit 0 These time division register bits are used to specify the number of character lines in the vertical direction (Nx). Note that these vertical character lines are controlled by time division technique. The reciprocal of Nx indicates a display duty cycle, The total number of display dots on the Liquid Crystal Display panel can be calculated by (Hp x Hn x Nx). The table below shows the relationship between the combinations of these bits and the number of vertical character lines (Nx). Vertical character} TDR2}TDR1|TDRO fine count (Nx) pe fete} | pe tefpe | oe | po fafa pete fet os | po fe fat os | pete te to | peta tats | Note: This register cannot be accessed by a bit manipulation instruction. No.2967-35/61

[sm [osieo[ reams [one _| = [= [esns [cans [cana [ cnne Ponti [ enro | CARS: Cursor address register bit 5 . t t CARO: Cursor address register bit 0 Character display mode: These cursor address register bits are used to specify a display RAM address whose content will be displayed on the Liquid Crystal Display panel marked by a cursor. Note that the cursor is displayed under the display character and thet the cursor display Is controlled by the mode control register Graphic display mode: These cursor address register blts have no significance. The table below shows the relationship between the combinations of these bits and the display RAM addresses, Specifiable display po fo fe fe foe fo feo pe |e foe fe fo ft fem ee pe fee fo Ps feo Tt fiase pepe fe Pet fe five po fee Po Pe Pe Pt a Common driver pins, segment driver pins and character display ° or On OO -aAmMOdtnNn OR DAD = oo Mm OM + nNnnunnn NNNnNNN nNnNnNNnNnNN ¢1 OOBOO O89 BBO OM mmo ce OOMBOO SOCOM BOOOM c3 DOGOO OOOO gUOOO8 c4 OOOO OOOO Om mmO cs OOMOO OOBDO BOOOS c6é OOMOD ODO BUOCOM c?7 ON NEO SRE OED cs QOOO0O OOOOD ONOOOO No.2967-36/61

Graphic display mode ° oraono =a“ aot 10 one*ana om 0 0d OD et nuunaaxnaN nnnaANnN NAnRNnNNN Kontent of display, Content of display RAM address 184H a P =a LSB MSB ci-qDOOOO OOOO OOOO c2} 00000 OOOOO OOOO cs |} OOODOO OOOOO OOOO c4 SO0000 OOOO0 OOOO0O c5 FOOROO OOOOO OOO800 cs} OOOOO OOOO DOOOO c7/QOOOOO OOOOH OOOO ces “JOODOOOD OOOO OOOO Content of display Content of display RAM RAM_address_1A3H address 1A7H Character display mode K— wp ORB] eee EERE BOOO8 BOUOG OOOO || BMOOOS BOU08 OOOO 2> BOOOS SEBO OOgOO BEER BOO OmgO0O0 BUOOOSG BOOUOG BOOO00 BOOOS See aa | DNOOOO ee or | LU Display character Character display The cursor is Character display dot pattern gene- dot pattern gene- displayed because dot pattern gene- rated by the rated by the OlHandOAHhave rated by the CGROMaccording CGROMaccording been set in the CGROMaccording to the content of to the content of cursor address to the content of display RAM ad- display RAM ad- register and the display RAM ad- dress 180H. dress 181H. mode control dress 187H. . register, respec- tively. No.2967-37/61

Hp, Hn, Vp, Nx and Liquid Crystal display Horizontal Character pitch in horizontal (Character display mode: Character count per line Horizontal (or in horizontal direction). 1 to 40 characters character count |Graphic display mode: Byte count per line (or_in horizontal_direction). | vp [Vertical pitch Character pitch in vertical direction 1 to 8 bits ertical character] p, ; Bias modes 1/5 ~ 174 1/3 1/2 Static VDD pi poy po ite eck bok ieske dost Note: Set port pin PXX to the L level when you are to turn on the Liquid Crystal Display panel. In this case, set bit 3 of the mode contro! register (MCR) first and then set the PXX pin to the L level. Set port pin PXX to the H level and then reset bit 3 of the mode control register (MCR) when you are to turn off the Liquid Crystal Display panel. If you do not follow the above procedures, excessive current at about 1mA will be dissipated by the LSI when the display panel is turned on/off. No.2967-38/61

Pscnr [acne | - [sens | sens [acne [ acm | acre ACR7: Alarm control register bit 7 0: Disable the pulse output to sound an alarm tone. 1: Enable the pulse output to sound an alarm tone, Note: The pulse output reverses its polarity by an overflow signal from timer/ counter 0 if alarm control register bit 6 (ACR6) has been set to "1". ACR6: Alarm control register bit 6 0: Fix the pulse output at the "H" level. 1: Allow the pulse output to reverse its polarity by an overflow signal from timer/counter 0. ACR4: Alarm control register bit 4 0: Select the fundamental frequency of 4kHz for the alarm tone specified by bits ACRO to ACR3, i: Select the fundamental frequency of 2kHz for the alarm tone specified by bits ACRO to ACR3, ACR3: Alarm control register bit 3 . 0: Disable the fundamental frequency selected by ACR4 to generate the alarm tone signal. 1; Enable the fundamental frequency selected by ACR4 to generate the alarm tone signal, * | ACR2: Alarm control bit 2 0: Disable the combination of the signal frequencies of 32Hz, 4Hz, and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone. 1: Enable the combination of the signal frequencies of 32Hz, 4Hz, and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone, ACRI: Alarm control register bit 1 0: Disable the combination of the signal frequencies of 4Hz, 1Hz and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone. 1; Enable the combination of the signal frequencies of 4Hz, 1Hz, and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone, ACRO: Alarm control register bit 0 0: Disable the combination of the signal frequencies of 32Hz, 4Hz, IHz and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone. 1: Enable the combination of the signal frequencies of 32Hz, 4Hz, 1Hz, and 4kHz or 2kHz (fundamental frequency selected by ACR4) to sound an alarm tone. Note: To enable an alarm tone signal to be output to port pin P44, you have to set pin P44 to the output mode, In addition, bit 4 of the port 4 output signal selection . register (P4SCR) should be set to "1", Note: This register cannot be accessed by a bit manipulation instruction, Please keep it in mind, No.2967-39/61

Symbol | Address} Read/Write | Name Initial reset value The CF/RC oscillation circuit is composed of the CF1 and CF2 pins, and ceramic oscillator or RC oscillator, The ceramic oscillator or the RC oscillator can be selected by the mask option. The CF/RC oscillation signal can be as the system clock signal and the Liquid Crystal Display timing control signals. The figures below show the example CF and RC oscillation circuits, co ~ CF oscillation ~ RC oscillation . circuit circuit Symbol | Address | Read/Write | Name Initial reset value The XTAL oscillation circuit is composed of the XT! and XT2 pins, and the Crystal (XTAL) resonator. The capacitor of 20pF is provided between the XT2 pin and the VSS pin. The XTAL 7 oscillation signal can be used as the timer base clock signal, system clock signal, and the Liquid Crystal Display timing control signals. The Liquid Crystal Display timing control signal source can be selected from the CF/RC oscillation circuit and the XTAL oscillation circuit by the mask option. The figure below shows the example XTAL resonator oscillation circuit. = i) XTAL resonator oscillation circuit No.2967-40/61

DIVR | - | - | Divider circuit 0000H The divider circuit receives the signal frequency output from the 32kHz XTAL resonator oscillation circuit and then divides its input signal. This divider circuit is a up- counter with 15 output taps. The outputs from the divider circuit can be used to supply time base clock and alarm tone signals to the system. . i Initial 1FDH Divider circuit contro! register xXxXxx000B MSB LSB DCR2: Divider circuit control register bit 2 0: Reset the divider circuit. 1: Enable the divider circuit to divide the inpyt signal frequency from the 32kHz XTAL resonator oscillation circuit. DCRI: Divider circuit control register bit 1 The DCR is used to generate an interrupt request. This bit is set by an overflow signal from the divider circuit every 500 milliseconds with the DCRO = 1, Please note that the DCRI1 is not reset when the interrupt request is accepted by the system and thereby must be reset within the interrupt servicing routine. DCRO: Divider circuit control register bit 0 0: Disable the DCRI to be set by an overflow signal from the divider circuit every 500 milliseconds, 1: Enable the DCR1 to be set by an overflow signal from the divider circuit every 500 milliseconds, Symbol | Address | Read/Write | Name Initial y! reset value 1FEH]| Write Only Oscillation control register MSB LSB OCRO: Oscillation control register bit 0 0: Start the CF/RC oscillation circuit. 1: Stop the CF/RC oscillation circuit, Note: Set bit 0 of the system clock control register (SCR) to "1" when you write a data to the oscillation control register (OCR). That is, start or stop the CF/RC oscil- lation circuit after switching the system clock source to the XTAL resonator oscillation circuit. If you do not follow this advice, the system may enter the abnormal run state, Please keep it in mind. Note: This register cannot be accessed by a bit manipulation instruction. No.2967-41/61

1FFH] Write Only System clock control register MSB LSB SCRO: System clock control register bit 0 0: Select the CF/RC oscillation circuit as the system clock source. 1: Select the XTAL oscillation circuit as the system clock source. Note: Set bit 0 of the system clock control register (SCR) to "1" when you write a data to the oscillation control register (OCR). That is, start or stop the CF/RC oscil- lation: circuit after switching the system clock source to the XTAL resonator oscillation circuit. If you do not follow this advice, the system may enter the abnormal run state. Please keep it in mind, Note: This register cannot be accessed by a bit manipulation instruction. No 2967-42161

The following user mask options are available on the LC86104A microcomputer. User mask option Optional items Description CF/RC oscillation - CF oscillation Select the CF oscillation circuit with the CFI and circult selection circuit CF2 pins or the RC oscillation circuit with the - RC oscillation CFI and CF2 pins circult Liquid Crystal Display - XTAL oscillation Select elther the XTAL oscillation circuit or the controller clock source circult . CF/RC osclllation circult as the Liquid Crystal selection - CF/RC oscillation Display controller clock source. clrcult Liquid Crystal Display ~T/1 Select the division rate of the Liquid Crystal controller clock divi- - 1/2 Display controller clock. This user mask option sion rate selection - 1/4 allows the divider to output the clock with a - 1/8 desired Liquid Crystal Display frame frequency - 1/16 (Ffrm: 40Hz to 80Hz) to the display control ~ 1/32 circuit, - 1/64 - 1/128 Port 0 pull-up transistor - Pull-up circuit Select the port 0 input circult type from the (resistor) selection selection pull-up input circuit configuration and the open - Non pull-up circuit input circult configuration, selection Port 1 pull-up transistor - Pull-up circuit Select the port 1 input circuit type from the (resistor) selection selection pull-up input circult conflguration and the open - Non pull-up circuit input circult configuration, selection Port 2 pull-up transistor - Pull-up circuit Select the port 2 Input circult type from the (resistor) selection selection pull-up input circuit conflguration and the open ~ Non pull-up circuit | input circuit configuration, . selection Port 3 pull-up transistor - Pull-up circuit Select the port 3 input circuit type from the (resistor) selection selection pull-up input circuit configuration and the open - Non pull-up circuit input circuit configuration. selection Port 4 pull-up transistor - Pull-up circuit Select the port 4 Input circuit type from the (resistor) selection selection pull-up input circuit configuration and the open - Non pull-up circuit input circuit configuration, selection Note: The Liquid Crystal Display frame frequency can be calculated by the following formula: Ffrm = (Fosc x Ndiv)/(2 x Ndot) Fose: Oscillation frequency from a Liquid Crystal Display controller clock source Ndiv: Division rate for Liquid Crystal Display controller clock Ndot: Total number of Liquid Crystal Display dots (Ndot = Hp x Hn x Nx) Note: Pull-up transistor (resistor) can be selected in port unit by the user mask option. Please note that the pull-up resistor cannot be selected in a port bit unit by the option. No.2967-43/61

Parameter Symbol Pins and Conditions Supply _ voltage VDD 0. 3 +7 Vv Input VIN -0. 3] VDD Vv voltage +0. 3 Peak output Input/output ports, Output current | top | current per pin, +20 mA Average output} Input/output port. Average output current TOA current per pin for 100 milliseconds, +20 mA Output E1OA1 | Port 0. Total output current, Output Ports 1, 2, 3, and 4. Total output current 2 EIOA2 | crrent. —-23 |+110 |mA Power dissipa- _ on ° Fower S| pamax|ta=-a00~ 470%, @i100 | | 400 [mw Operating tem-| ° prone rang] TOP# | to | tro Storage tem- °, No.2967-44/61

Wi Recommended operating voltage range/Ta range = -30°C to +70 °C. ° VDD range = 2.5V to 6.0V. Vss = OV. Parameter Symbol Pins and Conditions Unit voltage range RAM and register All input port pins_ 0. 7 VIH1 | except for the RST pin VDD VDD Vv Input high voltage 0.75 VIH2 | RST VDD VDD Vv All input_port pins except 0. 3 V1IL1 | for the RST port pin VDD Vv Input low voltage 0. 25 VIL2 |RST VDD Vv FOSC1]|CF1, 2(Ceramic oscillation) 12 13 MHz VDD=4. 5~6. 0V FOSC2|CF1, 2(Ceramic oscillation) 2. 5 3.5 |MHz Oscillation fre- VDD=2. 5~6. OV juency range quency rang! FOSC3]|CF1, 2 (RC oscillation) 0.4 MHz VDD=2. 5~6. 0V R=15KQ. C=100pF FOSC4|XT1, 2 (Crystal oscillation) 32 34 KHz VDD=2. 5~6. 0V _ No,2967-45/61

W@ Electrical Characteristics/Ta = -30°C to +70 °C. VSS = 0V Parameter Symbol pins sand VOH1 All output pins VDD=4. 5V]0. 9 Vv Output high IOH=—-1. OmA}| VDD | voltage VOH2 All output pins VDD=2. 5V/0. 9 Vv IOH=-—0. 3mA] VDD VOL1 All output pins VDD=4. 5V 0. 1] V 1OL=+4. OmA VDD Output low voltage VOL2 | att output pins VDD=2. 5V oily 1OL=+1. OmA VDD All input/output pins RP1 | vpp=5v, VOH=0.9VDD 38 | 73 | ka All input/output pins . Pull-up [Rea | VDD=2.9V, VOH=0,9VDD KQ transistor Hysteresis VHYS |RST . 0.1 Vv voltage VDD Input leak _ _ Pin IDD1 Liquid Crystal Display OFF mA VDD=5V, FXT=32KHz FCF=12MHz . Liquid Crystal Display OFF 0.7 mA VDD=5V, FXT=32KHz FRC=800KHz Current IDD3 Liquid Crystal Display OFF 35 HA dissipation VDD=5V, FXT=32KHz during basic FCF=FRC=0Hz operation IDD4 Liquid Crystal Display OFF ,\\VDD=2.9V 2.2/1mA FXT=32KHz, FCF=3MHz IDDS Liquid Crystal Display OFF 615/u4A VDD=2. 9V. FXT=32KHz FRC=800KHz Liquid Crystal Display OFF 42 )uHA VDD=2. 9V, FXT=32KHz FCF=FRC=0Hz No.2967-46/61

Parameter Symbol Pins and Conditions Unit . IDD7 Liquid Crystal Display OFF, VDD=5V mA FXT=32KHz FCF=12MHz IDD8 Liquid Crystal Display OFF, VDD=5V 435] 4A FXT=32KHz FRC=800KHz Liquid Crystal Display OFF, VDD=5V 15 40 | uA Sissipation EXT=32KHz during HALT FCF=FRC=0Hz ation oper 1DD10 | Liquid Crystal Display OFF, VDD=2.9V 705|2A FXT=32KHz, FCF=3MHz 1DD1 1 } Liquid Crystal Display OFF, VDD=2.9V 150/240/4A FXT=32KHz FRC=800KHz I1DD1 2 | Liquid Crystal Display OFF, VDD=2.9V HA FXT=32KHz FCF=FRC=0Hz Current dissi- IDD1 8 | Liquid Crystal Display OFF, VDD=5V | | | 10 [eal pation during | HOLD operation! | DD 1 4 | Liquid Crystal Display OFF, VDD=2.9V Pt ft faa] ILcl Liquid Crystal Display ON, VDD=5V HA Liquid Crystal V5=0V, 1/5 Bias mode Display current 1 LC29 | Liquid Crystal Display ON, VDD=2.9V | 2.9 | 5. 8 12 HA V5=0V, 1/5 Bias mode Note: During the Liquid Crystal Display OFF, you have to reset bit 3 (MCR3) of the mode control register without fail. If you do not follow this procedure, the IDD12 current value will be increased twice or three times. . No.2967-47/61

= SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS Parameter Symbol Pins and Conditions Unit cain [ree [ax | VDD-Ci | ¥D1 | |-15 micro Ampere per C pin 120 |mv voltage drop VDD=2.9V (i: 1~8) VX-Ci | VD2 | |-15 micro Ampere per C pin 120 |mv voltage drop VDD=2.9V (Xi 1, 4) (it 1~8) VDD-Si |VD3 | -15 micro Ampere per S pin 120 |mV voltage drop VDD=2.9V (i :1~40) VDD=2.9V, V5=0V va ePut vvl Liquid Crystal Display clock % DD % a % aA Vv ortags frequency = 0Hz VDD=2.9V, V5=0V v2 output Vv2 Liquid Crystal Display clock % Bo. % as % A M voltage frequency = 0Hz VDD=2.9V, V5=0V V3 output Yv3 Liquid Crystal Display clock 0. 35 % ve % . v oltage frequency = 0Hz VDD D V4 output | vVv4 Liquid Crystal Display clock | 9 15[0- 20/0. 25] v voltage frequency = 0Hz VDD | VDD | vDD VDD=4,5 to 6.0V Tsttl 12-MHz ceramic mS . oscillation Oscillation start time Tstt2 | VDD=2,5 to 6,0V 30 mS period 3-MHz ceramic oscillation VDD=2.5 to 6.0V Tstt3| 39 kHz crystal (XTAL) 10 | Ss oscillation " No.2967-48/61

oe SSSSSSSSSSSSeSSSSSSSSSsSsSSSSssssSeSSSSSSSSSSSSSSSSSSSee Abbreviations ACC(A) : Accumulator B : B register cx(C) : Carry flag AC : Auxiliary carry flag ov + Overflow flag PC : Program counter ROM : Program memory RAM : Data memory SFR + Special function register PSW : Program status word TRL : Table read register low-order byte TRH : Table read register high-order byte sP : Stack pointer . PL : Port 1 P2 + Port 2 P3 : Port 3 Pa : Port 4 Ri : Indirect address register within the current bank (part of the internal RAM) Rj i Indirect address register within the current bank (part of the internal RAM) do : Direct addressing data Hi8 : Immediate data b3 : Bit addressing data rs : Relative addressing data rl6 : Relative addressing data al2 : Absolute addressing data ; al6 : Absolute addressing data ©) : Indicates the contents. - : Data transfer and its direction “Aw : Logical AND Vv : Logical OR v : Exclusive OR + + Addition - 3 Subtraction Set : Sete a bit to l. Reset : Sets a bit to 0. Bit : Binary digit contents (0 or 1) Clear : Sets all bits to 0. Carry : Carry for upper digits Borrow ; Borrow from upper digits Number of bytes (BYTES) : One byte has 8 bits. Indicates the number of units of an instruction. Number of cycles (CYCLES) : Indicates the number of CPU basic instruction cycles required by the execution of an instruction. No.2967-51/61

WArithmetic operations instruction MNEWONIC INSTRUCTION CODE | BYTES | CYCLES | DESCRIPTION PSE cy AC ov i7i6i5i4i3i2ilid d7d6d5d4d3d2d1d0 . ADD @Ri 10000 1ili0 1 (A)—(AD+CRI)) i:0,1,2.3 ADDC #18 10010001 1 CAY—CA)H(C) FFB. i7i6i5i4i3i2i1i0 ; d7d6d5d4d3d2d1d0 ADDC @Ri 10010 1ili0 1 1 (A)—(A)H(C)+C(RID) i:0.1,2,3 i7i6i5i4i3i2iliod SUB d9 101000 148 1 (A)—(A)-(d9) d7d6d5d4d3d2d1d0 SUB @Ri 10100 1ili0 1 (A)—-(A)-((RL)) i:0,1,2,3 iTiBi5i4i3i2i1id d7d6d5d4d3d2d1d0 SUBC @Ri 10110 1i1i0 1 1 CA)—(A)-(C)-CCRL)) i:0,1,2,3 INC a9 011000 148 2 1 (d9)+-(d9)+1 % | d7d6d5d4d3d2d1d0 DEC d9 011100 148 1 (d9)=-(d9)-1 % | d7d6d5d4d3d2d1d0 DEC @Ri *} 011-1 0 1i1i0 Pa [a | (CRE) CRI) )-1 420,123 | [ ms amon 1O[ 19 neve) [+ lowmave fol 10] ‘ No.2967-52/61

WLogical operations instruction MNEMONIC INSTRUCTION CODE | BYTES | CYCLES | DESCRIPTION PSY cy AC ov AND #i8 11100001 1 CA) CAA HIB iTi6i5i4i3i2i1i0 AND 49 111000 148 1 (A) (AAC) d7d6d5d4d3d2d1d0 OR #i8 11010001 2 1 (A)—CA)HI8 i7i6i5i4i3i2i1i0 OR d9 110100 148 1 (AY—(A(E8) d7d6d5d4d3d2d1d0 XOR #i8 11110001 1 (A) (A) #18 i7i16i5i4i3i2i1i0 XOR d9 111100 1d8) 2 1 CAY— CA) (09) d7d6d5d4d3d2d1d0 ROL 11100000 1 1 AT—AB AS AS 4 1 AVA A293 ROLC 11110000 1 CAT AB AS AA t 1 — AO AL A2 AB ROR 11000000 AT AB ASA t 4 AD—AL—A2—AB— RORC 11010000 1 1 CAT ABABA 1 t — AVAL ALAS : , No.2967-53/61

MData transfer instruction MNEWONIC INSTRUCTION CODE | BYTES | CYCLES | DESCRIPTION Pst cy | ac | ov LD a9 000000 148 1 (A)—-(d9) d7d6d5d4d3d2d1d0 LD @Ri 00000 1ili0 Pata | (A)—((Ri)) i:0,1,2,3 | tt ST 9 000100 148 1 (d9)—(A) d7d6d5d4d3d2d1d0 HOV #18, d9 001000 148 (d9)—-#i8 d7d6d5d4d3d2d1d0 i7i6i5i4i3i2i1i0 MOV #18, Ri 00100 1j1j0 1 ((R§) #18 i7i6i5i4i3i2i1i0 j:0,1,2.3 PUSH 9 011000 048 2 (SP)—(SP)+1, (CSP) )—(d9) d7d6d5d4d3d2d1d0 POP d9 011100 048 (d9)—((SP)), (SP)—(SP)-1 d7d6d5d4d3d2d1d0 XCH d9 110000 148 1 (d9 (A) d7d6d5d4d3d2d1d0 XCH @Ri 11000 1ili0d ba fo] (CRI) (A) 1:0,1,2,3 | | of] No.2967-54/61

MNEWONIC INSTRUCTION CODE | BYTES | CYCLES DESCRIPTION PS¥ cy AC ov JMP al2 0 oO tall (PC)(PC) +2: 1al0 a9 a8 (PC11-00)-al2 a7ababad4aza2alad JMPF al6 00100001 (PC)—al6 alS al4 al3 al2 : all al0 a9 a8 aTabadada3a2ala0 BR r8 o0000001 2 (PC)=-(PC) #2: r7r6rSr4r3r2rir0 (PC)—(PC)tr8 BRF r16 00010001 (PC)—(PC)#3: rir6r5r4r3r2r1r0 (PC)—(PC)-14r16 . r15 rl4 r13 rl2 rll rl0 r$ r8 BZ r8 10000000 (PC)—(PC)+2: r7r6r5r4r3r2rlr0 if (A)=0, then (PC)—(PC)+r8 BNZ r8 10010000 (PC)—(PC)+2: rir6r5r4r3rér.r0 if (A)#*0, then (PC)+-(PC)+r8 BP d9, b3, r8 0 1 1d8 1b2b1b0 (PC)+~(PC) +3: d7d6d5d4d3d2d1d0 if (49, b3)=1, r?r6ror4r3r2r1r0 then (PC)—(PC)+r8 BN d9, b3. r8 1 0 0d8 1b2b1b0 (PC)~-(PC)+3: d7d6d5d4d3d2d1d0 if (d9, b3)41, rirbrbr4r3r2rl1r0 then (PC)—(PC)+r8 DBNZ d9,r8 010100 148 (PC)—(PC) +3: d7d6d5d4d3d2d1d0 (d8)=(d9)-1: * | r7r6ror4r3r2r)r0 if (d9)0, then (PC)+-(PC)+r8 DBNZ @Ri. r8 01010 1ili0 2 (PC)—(PC) +2: rir6rbr4r3r2ri1r0 (CRi))=(CRi))-1 i=0, 1,2, 3: if (d9)=40, * then (PC)—(PC)+r8 Continued on next page. NG. 2967-55761

Continued from preceding page. MNEMONIC INSTRUCTION CODE | BYTES | CYCLES | DESCRIPTION PST cy AC ov BE #18, r8 oor10001 (PC)—(PC)+3: i7i1615i4i3i2i1i0 if (A)=#i8, rir6r5r4r3r2rlr0 then (PC)=~(PC)tr8: if (A)<#i8, then C1 else C0: d7d6d5d4d3d2d1d0 if (A=(d), r7r6rSr4r3r2r1r0 then (PC)+-(PC)+r8: if (AV<(d), then C—1 else C0: i7iGi5i4i3i2ilid if ((Rj))=Fi8, r?r6r5r4r3r2r1r0 then (PC)-(PC)+tr8: if ((Rj))<#i8, then C—1 else C—0: i7i16i5i4i3i2i1i0 if (A)##i8, rir6rSr4r3r2r1r0 then (PC)—(PC)tr8: if (A)<#i8, then C--1 else C0: BNE 43, r8 010000 1a8 | 3 (PC)—-(PC) +3: d7d6d5d4d3d2d1d0 if (A)#(4), r7r6r5r4r3r2rir0 then (PC)+(PC)tr8: if (A)<(d), then C+-1 else C0: BNE @Rj, i8. r8 01000 1j1j0 3 (PC)—(PC)+3: i7i6i5i4i3i2ilio if ((Rj))##i8, r7r6rSr4rdr2r.r0 then (PC)—(PC)+r8: if C(Rj))<#i8, then C1 else C0: No.2967-56/61

W@W Subroutine instruction MNEMONIC INSTRUCTION CODE | BYTES | CYCLES | DESCRIPTION PS¥ cy AC ov CALL al2 0 0 Oall (PC)—(PC) +2: 1al0 a9 a8 (SP)+-(SP)+H1: aTabaSa4a3a2ala0 ((SP))<—-PC7-0: (SP)—(SP) #1: ((SP))<~PC15-8: (PC11-0)+-al2 CALLF al6 00100000 (PC)+-(PC) +3: al5 al4 al3 al2 (SP)—(SP)+1: all al0 a9 a8 ((SP))—PCT-0: a7abaSa4a3a2ala0 (SP)—(SP)+1: (CSP) )<-PC15-8: (PC)—alb CALLR al6 00010000 4 (PC)—(PC) +3: j a?abada4a3a2ala0 (SP)—(SP)+1: | al5 al4 al3 al2 ((SP))—PCT-0: | all al0 a9 a8 (SP)—(SP)+1: | ((SP))<—PC15-8: | | (PC)—-(PC)-1 tr 16 | (SP)—(SP)-1: | | (PC7-0)—C(SP)): (SP)-(SP)-1 RETI 10110000 (PC15-8)<-((SP)): (SP)—-(SP)-1: (PC7-0)<—-(C(SP)): (SP)-(SP)-1 ME Bit manipulation instruction MNEXONIC INSTRUCTION CODE BYTES | CYCLES | DESCRIPTION PS¥ cy AC ov CLR1 49, b3 1 1 0d8 1b2b1b0 1 (d9, b3)+<-0 * | d7d6d5d4d3d2d1d0 SET! d9, b3 1 1 1d8 1b2b1b0 (d8, b3)—1 % | d7d6d5d4d3d2d1d0 NOT1 d9, b3 1 0 1d8 1b2b1b0 1 (d9, b3)—(d9, b3) * | d7d6d5d4d3d2d1d0 - No.2967-57/61

@ Other instructions MNEMONIC INSTRUCTION CODE | BYTES | CYCLES; DESCRIPTION PSE cy AC ov Note: If ports are addressed by the instructions marked with asterisks in byte units or bit units, their port latches will be selected. If ports are addressed by other instructions, external input signals to them will be selected. _ No.2967-58/61

Instruction map for the LC86104A microcomputer LOW BYTE 4-7 HIGH BYTE CALL al2 : Poa | CALLE r16 BRF r16 ST d9 ST @Ri fo | CALLF al6 JUPF alé _ MOV #18, do MOV #i8, @Ri JHP al2 Poe | lm BE #18, r8 BE d9, r8 BE @Ri, #18, r8 ee ee BNE #18, r8 BNE #d9,r8 | BNE @Ri. #18, r8 BP d9, b3, r8 POP 48 DEC 49 DEC @Ri BN d9, b3, r8 | 8 | BNZ r8 ADDC #i8 ADDC a9 ADDC @Ri NOT] 49, b3 } 3s | RETI SUBC #i8 SUBC d9 SUBC @Ri CLR1 9, b3 SETI d9, b3 ROLC XOR #i8 XOR a9 XOR @Ri HENo products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. W@ Anyone purchasing any products described or contained herein for an above-mentioned use shall: @® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD,, its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. Wi information (including circuit diagrams and circuit parameters) herein is for example only; it is not guarant- . eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees | are made or implied regarding its use or any infringements of intellectual property rights or other rights of | third parties. | No.2967-59/61 |

Example application circuit (1) +5V Voo CFI C1 Liquid Crystal Display i panel with 320-dot [ CI ce specification cF2 +5V $1 xT1 | $40 CI xT2 vt : v2 1/4 Bias mode RST ‘3 100k 0.1 V5 po Epo P00 T2 POI P02

1 PO3

+5V Pa2 P22 P43 P23 P44 P24 P45 P46 P26 ) O P47 P27 Vss Unit (resistance: 0, capacitance: F) No.2967-60/61

Example application circuit (2) +5V Voo CFI C1 Liquid Crystal Display Cc | panel with 640-dot cs specification OF2 XxT1 | co S40 xT2 V2 ty O.1uX3 ast v3 01 v4 le oe on] P00

12 POL Ot

n pos | ® P04 POS P06 LC7930N P07 +5V Note: You have to set the T Liquid Crystal Display P30 P10 Vop v1 operation mode to the P31 Pu character display mode If P32 P12 v2 you are planning to em- ploy several LC7930N(as| —] P33 bla vad the slave display panel) Psa Ps ‘a [I to expand digit display. —_ PIG +5V vat v6 PI7 Tl tyre " P20 P40 CLKia P22 P42 RDATA2 P24 P44 Ly] LOATAz P45 RDATA1 P26 P46 P27 par CH2-BP Vss | Lyvss Vee a Unit (resistance: Q, capacitance: F) ee No.2967-61/61